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ipq807x: rename target to qualcommax

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This commit is contained in:
coolsnowwolf 2024-01-30 11:00:16 +08:00
parent cabbb92abd
commit 8fcf7f0915
252 changed files with 25634 additions and 37520 deletions
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26
target/linux/ipq807x/Makefile
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@ -1,26 +0,0 @@
include $(TOPDIR)/rules.mk
ARCH:=aarch64
BOARD:=ipq807x
BOARDNAME:=Qualcomm Atheros IPQ807x
FEATURES:=squashfs ramdisk fpu nand rtc emmc
KERNELNAME:=Image dtbs
CPU_TYPE:=cortex-a53
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.10
KERNEL_TESTING_PATCHVER:=5.15
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \
kmod-leds-gpio kmod-gpio-button-hotplug \
ath11k-firmware-ipq8074 kmod-ath11k-ahb \
autocore-arm htop wpad-openssl uboot-envtools \
kmod-qca-nss-dp kmod-qca-nss-drv-64 \
kmod-qca-nss-drv-pppoe-64 kmod-qca-nss-ecm-64 \
kmod-qca-nss-drv-bridge-mgr-64 kmod-qca-nss-drv-vlan-mgr-64 \
nss-firmware-ipq8074 luci-app-ipsec-vpnd \
luci-app-unblockmusic luci-app-zerotier
$(eval $(call BuildTarget))

30
target/linux/ipq807x/base-files/etc/board.d/01_leds
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@ -1,30 +0,0 @@
. /lib/functions/leds.sh
. /lib/functions/uci-defaults.sh
board=$(board_name)
board_config_update
case $board in
xiaomi,ax3600|\
redmi,ax6)
ucidef_set_led_netdev "wan" "WAN" "blue:network" "eth0"
;;
tplink,tl-er2260t)
ucidef_set_led_netdev "SFP1_active" "SFP1_ACTIVE" "green:sfp1" "eth5"
ucidef_set_led_netdev "SFP2_active" "SFP2_ACTIVE" "green:sfp2" "eth4"
;;
qnap,301w)
ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth0"
ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth1"
ucidef_set_led_netdev "lan3" "LAN3" "green:lan3" "eth2"
ucidef_set_led_netdev "lan4" "LAN4" "green:lan4" "eth3"
ucidef_set_led_netdev "10G_1" "10G_1" "green:10g_1" "eth4"
ucidef_set_led_netdev "10G_2" "10G_2" "green:10g_2" "eth5"
;;
esac
board_config_flush
exit 0

63
target/linux/ipq807x/base-files/etc/board.d/02_network
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@ -1,63 +0,0 @@
#
# Copyright (c) 2015 The Linux Foundation. All rights reserved.
# Copyright (c) 2011-2015 OpenWrt.org
#
. /lib/functions/uci-defaults.sh
. /lib/functions/system.sh
ipq807x_setup_interfaces()
{
local board="$1"
case "$board" in
zyxel,nbg7815|\
qnap,301w)
ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3 eth4" "eth5"
;;
redmi,ax6|\
xiaomi,ax3600)
ucidef_set_interfaces_lan_wan "eth1 eth2 eth3" "eth0"
;;
zte,mf269)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
tplink,tl-er2260t)
ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3 eth5" "eth4"
;;
tplink,xtr10890)
ucidef_set_interfaces_lan_wan "eth0 eth1 eth2 eth3 eth4" "eth5"
;;
*)
echo "Unsupported hardware. Network interfaces not initialized"
;;
esac
}
ipq807x_setup_macs()
{
local board="$1"
local lan_mac=""
local wan_mac=""
local label_mac=""
case "$board" in
zte,mf269)
wan_mac=$(mtd_get_mac_binary mac 0x0)
lan_mac=$(macaddr_add "$wan_mac" 1)
label_mac=$wan_mac
;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
}
board_config_update
board=$(board_name)
ipq807x_setup_interfaces $board
ipq807x_setup_macs $board
board_config_flush
exit 0

20
target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
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@ -1,20 +0,0 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:01:00.0.bin")
case "$board" in
xiaomi,ax3600)
caldata_extract "0:art" 0x33000 0x844
;;
esac
;;
*)
exit 1
;;
esac

30
target/linux/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata
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@ -1,30 +0,0 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath11k/IPQ8074/hw2.0/cal-ahb-c000000.wifi.bin")
case "$board" in
qnap,301w|\
redmi,ax6|\
xiaomi,ax3600|\
xiaomi,ax9000|\
zyxel,nbg7815)
caldata_extract "0:art" 0x1000 0x20000
;;
zte,mf269)
caldata_extract "0:ART" 0x1000 0x20000
;;
tplink,xtr10890)
caldata_extract "0:ART" 0x1000 0x20000
;;
esac
;;
*)
exit 1
;;
esac

34
target/linux/ipq807x/base-files/etc/init.d/bootcount
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@ -1,34 +0,0 @@
#!/bin/sh /etc/rc.common
START=99
. /lib/functions/system.sh
boot() {
case $(board_name) in
redmi,ax6|\
xiaomi,ax3600)
# OTA handling should not be used. Reset it just in case.
fw_setenv flag_ota_reboot 0
# Not strictly needed but useful to handle partition crash condition
fw_setenv flag_boot_success 1
;;
zte,mf269)
mac_addr=$(mtd_get_mac_binary mac 0x0)
macaddr_add $mac_addr 2 > /sys/devices/platform/soc/c000000.wifi/ieee80211/phy0/macaddress
macaddr_add $mac_addr 3 > /sys/devices/platform/soc/c000000.wifi/ieee80211/phy1/macaddress
wifi
;;
qnap,301w)
ssdk_sh debug phy set 0 0x4004c441 0x8 1> /dev/kmsg 2>&1
ssdk_sh debug phy set 0 0x40070000 0x3200 1> /dev/kmsg 2>&1
ssdk_sh debug phy set 8 0x4004c441 0x8 1> /dev/kmsg 2>&1
ssdk_sh debug phy set 8 0x40070000 0x3200 1> /dev/kmsg 2>&1
;;
esac
for q in $(ls /sys/class/net/eth*/queues/rx-*/rps_cpus); do echo f > $q; done
for q in $(ls /sys/class/net/eth*/queues/rx-*/rps_flow_cnt); do echo 4096 > $q; done
for q in $(ls /sys/class/net/eth*/queues/tx-*/xps_cpus); do echo f > $q; done
echo 32768 > /proc/sys/net/core/rps_sock_flow_entries
}

6
target/linux/ipq807x/base-files/etc/sysctl.d/99-bridge-nf-call.conf
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@ -1,6 +0,0 @@
# disable bridge netfilter module
net.bridge.bridge-nf-call-arptables=0
net.bridge.bridge-nf-call-iptables=0
net.bridge.bridge-nf-call-ip6tables=0

58
target/linux/ipq807x/base-files/lib/upgrade/platform.sh
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@ -1,58 +0,0 @@
PART_NAME=firmware
REQUIRE_IMAGE_METADATA=1
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_check_image() {
return 0;
}
platform_do_upgrade() {
case "$(board_name)" in
zyxel,nbg7815|\
qnap,301w)
kernelname="0:HLOS"
rootfsname="rootfs"
mmc_do_upgrade "$1"
;;
redmi,ax6|\
xiaomi,ax3600|\
xiaomi,ax9000)
part_num="$(fw_printenv -n flag_boot_rootfs)"
if [ "$part_num" -eq "1" ]; then
CI_UBIPART="rootfs_1"
target_num=1
# Reset fail flag for the current partition
# With both partition set to fail, the partition 2 (bit 1)
# is loaded
fw_setenv flag_try_sys2_failed 0
else
CI_UBIPART="rootfs"
target_num=0
# Reset fail flag for the current partition
# or uboot will skip the loading of this partition
fw_setenv flag_try_sys1_failed 0
fi
# Tell uboot to switch partition
fw_setenv flag_boot_rootfs $target_num
fw_setenv flag_last_success $target_num
# Reset success flag
fw_setenv flag_boot_success 0
nand_do_upgrade "$1"
;;
zte,mf269)
nand_do_upgrade "$1"
;;
tplink,tl-er2260t|\
tplink,xtr10890)
nand_do_upgrade "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}

518
target/linux/ipq807x/config-5.10
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@ -1,518 +0,0 @@
CONFIG_64BIT=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AQUANTIA_PHY=y
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MMAP_RND_BITS=18
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
CONFIG_ARCH_PROC_KCORE_TEXT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_RANDOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y
CONFIG_ARM64=y
CONFIG_ARM64_4K_PAGES=y
CONFIG_ARM64_AMU_EXTN=y
CONFIG_ARM64_BTI=y
CONFIG_ARM64_CNP=y
CONFIG_ARM64_CRYPTO=y
CONFIG_ARM64_E0PD=y
CONFIG_ARM64_ERRATUM_1165522=y
CONFIG_ARM64_ERRATUM_1286807=y
CONFIG_ARM64_ERRATUM_1418040=y
CONFIG_ARM64_HW_AFDBM=y
CONFIG_ARM64_MODULE_PLTS=y
CONFIG_ARM64_MTE=y
CONFIG_ARM64_PAGE_SHIFT=12
CONFIG_ARM64_PAN=y
CONFIG_ARM64_PA_BITS=48
CONFIG_ARM64_PA_BITS_48=y
CONFIG_ARM64_PTR_AUTH=y
CONFIG_ARM64_RAS_EXTN=y
CONFIG_ARM64_SVE=y
CONFIG_ARM64_TAGGED_ADDR_ABI=y
CONFIG_ARM64_TLB_RANGE=y
CONFIG_ARM64_VA_BITS=39
CONFIG_ARM64_VA_BITS_39=y
CONFIG_ARM64_VHE=y
CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
# CONFIG_ARMV8_DEPRECATED is not set
CONFIG_ARM_AMBA=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_GIC=y
CONFIG_ARM_GIC_V2M=y
CONFIG_ARM_GIC_V3=y
CONFIG_ARM_GIC_V3_ITS=y
CONFIG_ARM_GIC_V3_ITS_PCI=y
CONFIG_ARM_PSCI_CPUIDLE=y
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_SCMI_PROTOCOL is not set
CONFIG_ARM_SMCCC_SOC_ID=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BLK_MQ_VIRTIO=y
CONFIG_BLK_PM=y
CONFIG_BLOCK_COMPAT=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT=y
# CONFIG_COMPAT_32BIT_TIME is not set
CONFIG_COMPAT_BINFMT_ELF=y
CONFIG_COMPAT_NETLINK_MESSAGES=y
CONFIG_COMPAT_OLD_SIGACTION=y
CONFIG_COREDUMP=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
# CONFIG_CPU_FREQ_STAT is not set
CONFIG_CPU_FREQ_THERMAL=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_THERMAL=y
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_QCE=y
CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set
CONFIG_CRYPTO_DEV_QCE_SHA=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEV_COREDUMP=y
CONFIG_DMADEVICES=y
CONFIG_DMA_DIRECT_REMAP=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_EDAC_SUPPORT=y
CONFIG_ETHTOOL_NETLINK=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FRAME_POINTER=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GLOB=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HOLES_IN_ZONE=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HZ=250
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
CONFIG_HZ_PERIODIC=y
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IPQ_APSS_6018 is not set
CONFIG_IPQ_APSS_8074=y
# CONFIG_IPQ_APSS_PLL is not set
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
CONFIG_IPQ_GCC_8074=y
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
CONFIG_LEDS_TLC591XX=y
CONFIG_LIBFDT=y
CONFIG_LLD_VERSION=0
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAILBOX=y
# CONFIG_MAILBOX_TEST is not set
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
CONFIG_MFD_SPMI_PMIC=y
CONFIG_MFD_SYSCON=y
CONFIG_MHI_BUS=y
CONFIG_MHI_BUS_DEBUG=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_RELA=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SG_DMA_LENGTH=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_SWITCHDEV=y
CONFIG_NLS=y
CONFIG_NR_CPUS=256
CONFIG_NVMEM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PARTITION_PERCPU=y
CONFIG_PCI=y
CONFIG_PCIEASPM=y
CONFIG_PCIEASPM_DEFAULT=y
# CONFIG_PCIEASPM_PERFORMANCE is not set
# CONFIG_PCIEASPM_POWERSAVE is not set
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_PME=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
CONFIG_PHYS_ADDR_T_64BIT=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
CONFIG_PHY_QCOM_QMP=y
CONFIG_PHY_QCOM_QUSB2=y
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
# CONFIG_PINCTRL_IPQ4019 is not set
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
CONFIG_PINCTRL_IPQ8074=y
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM=y
# CONFIG_PM8916_WATCHDOG is not set
CONFIG_PM_CLK=y
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
# CONFIG_POWER_RESET_QCOM_PON is not set
CONFIG_POWER_SUPPLY=y
CONFIG_PRINTK_TIME=y
# CONFIG_QCOM_A53PLL is not set
# CONFIG_QCOM_AOSS_QMP is not set
CONFIG_QCOM_APCS_IPC=y
# CONFIG_QCOM_APR is not set
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_CLK_APCC_MSM8996 is not set
# CONFIG_QCOM_CLK_APCS_MSM8916 is not set
# CONFIG_QCOM_COINCELL is not set
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
CONFIG_QCOM_EBI2=y
# CONFIG_QCOM_FASTRPC is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IPCC is not set
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_MDT_LOADER=y
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_PIL_INFO=y
# CONFIG_QCOM_Q6V5_ADSP is not set
CONFIG_QCOM_Q6V5_COMMON=y
# CONFIG_QCOM_Q6V5_MSS is not set
# CONFIG_QCOM_Q6V5_PAS is not set
CONFIG_QCOM_Q6V5_WCSS=y
CONFIG_QCOM_QFPROM=y
CONFIG_QCOM_QMI_HELPERS=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_RPROC_COMMON=y
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
# CONFIG_QCOM_SMD_RPM is not set
CONFIG_QCOM_SMEM=y
CONFIG_QCOM_SMEM_STATE=y
CONFIG_QCOM_SMP2P=y
# CONFIG_QCOM_SMSM is not set
CONFIG_QCOM_SOCINFO=y
# CONFIG_QCOM_SYSMON is not set
CONFIG_QCOM_TSENS=y
# CONFIG_QCOM_WCNSS_CTRL is not set
# CONFIG_QCOM_WCNSS_PIL is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_QRTR=y
CONFIG_QRTR_MHI=y
CONFIG_QRTR_SMD=y
CONFIG_QRTR_TUN=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDOMIZE_BASE=y
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
CONFIG_RATIONAL=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_SPMI=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_REGULATOR_QCOM_SPMI=y
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
CONFIG_RELOCATABLE=y
CONFIG_REMOTEPROC=y
CONFIG_REMOTEPROC_CDEV=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
CONFIG_RPMSG=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_QCOM_GLINK=y
CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_QCOM_GLINK_SMEM=y
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_RPS=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_THERMAL_PRESSURE=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
# CONFIG_SENSORS_EMC2305 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SOC_BUS=y
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWIOTLB=y
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSVIPC_COMPAT=y
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_NETLINK=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
# CONFIG_UACCE is not set
CONFIG_UBIFS_FS=y
CONFIG_UNMAP_KERNEL_AT_EL0=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_VIRTIO=y
# CONFIG_VIRTIO_BLK is not set
# CONFIG_VIRTIO_NET is not set
CONFIG_VMAP_STACK=y
CONFIG_WANT_DEV_COREDUMP=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZONE_DMA32=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

665
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8070-tl-er2260t.dts
View File

@ -1,665 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "TP-Link TL-ER2260T";
compatible = "tplink,tl-er2260t", "qcom,ipq8074";
qcom,msm-id = <0x143 0x0>;
interrupt-parent = <&intc>;
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
serial0 = &blsp1_uart5;
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
ethernet2 = "/soc/dp3";
ethernet3 = "/soc/dp4";
ethernet4 = "/soc/dp5";
ethernet5 = "/soc/dp6";
};
chosen {
stdout-path = "serial0";
bootargs-append = " root=/dev/ubiblock0_1";
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_sys: sys {
label = "green:sys";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
usb {
label = "green:usb";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "usbport";
};
sfp1-green {
label = "green:sfp1";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
};
sfp2-green {
label = "green:sfp2";
gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
};
};
spi@78b5000 {
status = "ok";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
m25p80@0 {
compatible = "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_0 {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
mux_2 {
pins = "gpio44";
function = "gpio";
bias-pull-up;
};
};
i2c_1_pins: i2c_1_pins {
pins = "gpio46", "gpio47";
function = "blsp2_i2c";
drive-strength = <8>;
bias-disable;
};
button_pins: button_pins {
reset {
pins = "gpio50";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
uniphy_pins: uniphy_pinmux {
mux {
pins = "gpio60";
function = "rx2";
bias-disable;
};
sfp_tx {
pins = "gpio59";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-high;
};
};
leds_pins: leds_pinmux {
mux {
pins = "gpio21", "gpio22", "gpio65";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_sfp1_active {
pins = "gpio51";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_sfp2_active {
pins = "gpio55";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
phy0:ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
phy1:ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
phy2:ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
phy3:ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
phy4: ethernet-phy@29 {
reg = <29>;
};
phy5: ethernet-phy@30 {
reg = <30>;
};
};
&ess_switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/ //use 10g_baser mode for default
switch_mac_mode2 = <0xe>; /* mac mode for uniphy instance2*/ //use 10g_baser mode for default
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
cmnblk_clk = "external_50MHz";
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <29>;//29
phy_i2c_address = <29>;//29
phy-i2c-mode; /*i2c access phy */
media-type = "sfp"; /* fiber mode */
};
port@5 {
port_id = <6>;
phy_address = <30>;//30
phy_i2c_address = <30>;//30
phy-i2c-mode; /*i2c access phy */
media-type = "sfp"; /* fiber mode */
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&soc {
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <0>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <1>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <2>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <3>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <29>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <30>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
nss-macsec1 {
compatible = "qcom,nss-macsec";
phy_addr = <0x1c>;
phy_access_mode = <0x00>;
mdiobus = <&mdio>;
};
watchdog@b017000 {
compatible = "qcom,kpss-wdt-ipq807x";
reg = <0xb017000 0x1000>;
reg-names = "kpss_wdt";
interrupt-names = "bark_irq";
interrupts = <0x00 0x03 0x00>;
clocks = <&sleep_clk>;
timeout-sec = <0x0a>;
wdt-max-timeout = <0x20>;
};
};
&blsp1_i2c2 {
status = "okay";
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};

498
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
View File

@ -1,498 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
#include "ipq8074.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ac-nss.dtsi"
#include "ipq8074-memory-512m.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_yellow;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
led-upgrade = &led_system_yellow;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
label-mac-device = &dp2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
reserved-memory {
/delete-node/ tzapp@4a400000;
/delete-node/ q6_etr_dump@50f00000;
/delete-node/ m3_dump@51000000;
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
/*
* Disable the reset GPIO temporarely as it
* resets the 100Mbit LED configuration which
* the bootloader writes.
*/
//reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
ethernet-phy@4 {
reg = <4>;
};
};
&ess_switch {
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x20>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <4>;
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&soc {
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <1>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <2>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <3>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <4>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
&wifi {
status = "okay";
qcom,board_id = <658>;
};

539
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts
View File

@ -1,539 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, ZhiPing */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ac-nss.dtsi"
#include "ipq8074-memory-512m.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "ZTE MF269";
compatible = "zte,mf269", "qcom,ipq8074";
interrupt-parent = <&intc>;
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
serial0 = &blsp1_uart5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
reserved-memory {
/delete-node/ tzapp@4a400000;
/delete-node/ q6_etr_dump@50f00000;
/delete-node/ m3_dump@51000000;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "white:power";
gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
};
};
soc {
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a003000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <24>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <28>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
flash@0 {
compatible = "jedec,spi-nor", "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&ess_switch {
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@4 {
port_id = <5>;
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@5 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
//reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@4 {
reg = <24>;
//reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
ethernet-phy@5 {
reg = <28>;
//reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
};
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&tlmm {
i2c_4_pins: i2c-4-pinmux {
pins = "gpio21", "gpio22";
function = "blsp4_i2c1";
drive-strength = <8>;
bias-disable;
};
slic_ctl_pins: slic_ctl_pins {
mux {
pins = "gpio59";
function = "gpio";
bias-pull-up;
};
};
spi_5_pins: spi-5-pins {
pins = "gpio0", "gpio2", "gpio9", "gpio16";
function = "blsp5_spi";
drive-strength = <8>;
bias-disable;
};
mdio_pins: mdio_pinmux {
mux_0 {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
mux_2 {
pins = "gpio25";
function = "gpio";
bias-pull-up;
};
mux_3 {
pins = "gpio44";
function = "gpio";
bias-pull-up;
};
};
usb_vbus_pins: usb_vbus_pins {
mux {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
};
};
&usb_0 {
pinctrl-0 = <&usb_vbus_pins>;
pinctrl-names = "default";
status = "okay";
};
&wifi {
status = "okay";
qcom,board_id = <658>;
qcom,ath11k-calibration-variant = "ZTE-MF269";
};

819
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
View File

@ -1,819 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ac-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "QNAP 301w";
compatible = "qnap,301w", "qcom,ipq8074";
interrupt-parent = <&intc>;
aliases {
serial0 = &blsp1_uart5;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_pwr_green;
led-upgrade = &led_system_red;
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
ethernet5 = &dp6;
label-mac-device = &dp1;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_system_green: system-green {
label = "green:system";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_system_red: system-red {
label = "red:system";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
};
led_pwr_green: pwr-green {
label = "green:pwr";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_wifi_green: wifi-green {
label = "green:wifi";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan1_green: lan1-green {
label = "green:lan1";
gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan1_amber: lan1-amber {
label = "amber:lan1";
gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_lan2_green: lan2-green {
label = "green:lan2";
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan2_amber: lan2-amber {
label = "amber:lan2";
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_lan3_green: lan3-green {
label = "green:lan3";
gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan3_amber: lan3-amber {
label = "amber:lan3";
gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_lan4_green: lan4-green {
label = "green:lan4";
gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan4_amber: lan4-amber {
label = "amber:lan4";
gpios = <&tlmm 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_10g_1_green: 10g_1-green {
label = "green:10g_1";
gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_10g_1_amber: 10g_1-amber {
label = "amber:10g_1";
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_10g_2_green: 10g_2-green {
label = "green:10g_2";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_10g_2_amber: 10g_2-amber {
label = "amber:10g_2";
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button_pins {
wps_button {
pins = "gpio57";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
rst_button {
pins = "gpio67";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
qpic_pins: qpic-pins {
status = "disabled";
/*disabling qpic-pins due to the leds are using all of the gpios*/
};
leds_pins: leds_pinmux {
led_pwr_green {
pins = "gpio4";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_system_green {
pins = "gpio1";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_system_red {
pins = "gpio3";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan1_green {
pins = "gpio6";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan1_amber {
pins = "gpio7";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan2_green {
pins = "gpio8";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan2_amber {
pins = "gpio11";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan3_green {
pins = "gpio12";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan3_amber {
pins = "gpio13";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan4_green {
pins = "gpio14";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan4_amber {
pins = "gpio15";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_1_green {
pins = "gpio54";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_1_amber {
pins = "gpio56";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_2_green {
pins = "gpio51";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_2_amber {
pins = "gpio52";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_wifi_green {
pins = "gpio42";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@0 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <0>;
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
};
ethernet-phy@8 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <8>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
ethernet-phy@16 {
reg = <16>;
};
ethernet-phy@17 {
reg = <17>;
};
ethernet-phy@18 {
reg = <18>;
};
ethernet-phy@19 {
reg = <19>;
};
};
&sdhc_1 {
/* According to the stock dts from the QNAP gpl drop
* the emmc has a problem with the hs400 > hs200 speed switch.
* But at the momment it doesn't seems possible to run that card in hs200 mode,
* it doesn't get recognized without the hs400 mode.
* Unfortunately it's not stable in hs400 mode so reduce the speed to mmc highspeed.
*/
no-1-8-v;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <5000000>;
vqmmc-supply = <&ldo11>;
status = "okay";
};
&ess_switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0xc0>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <16>;
};
port@1 {
port_id = <2>;
phy_address = <17>;
};
port@2 {
port_id = <3>;
phy_address = <18>;
};
port@3 {
port_id = <4>;
phy_address = <19>;
};
port@4 {
port_id = <5>;
phy_address = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
port@5 {
port_id = <6>;
phy_address = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&soc {
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <16>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <17>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <18>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <19>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <8>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <0>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
&wifi {
status = "okay";
/* using board_id 0xff is intentionally
* as the stock firmware is also using this default board_id
*/
qcom,board_id = <0xff>;
qcom,ath11k-calibration-variant = "QNAP-301w";
};

173
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8074-ac-cpu.dtsi
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@ -1,173 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
&CPU0 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu0-supply = <&s3>;
};
&CPU1 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu-supply = <&s3>;
};
&CPU2 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu-supply = <&s3>;
};
&CPU3 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu-supply = <&s3>;
};
&cpus {
cpu_opp_table: cpu_opp_table {
compatible = "operating-points-v2";
opp-shared;
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-microvolt = <704000>;
clock-latency-ns = <200000>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-microvolt = <824000>;
clock-latency-ns = <200000>;
};
};
};
&cpu0_thermal {
trips {
cpu0_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu1_thermal {
trips {
cpu1_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu2_thermal {
trips {
cpu2_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu3_thermal {
trips {
cpu3_passive: cpu-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cluster_thermal {
trips {
cluster_passive: cluster-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cluster_crit: cluster_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cluster_passive>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

256
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8074-ac-nss.dtsi
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@ -1,256 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
&soc {
dummy_reg: dummy-regulator@0 {
compatible = "regulator-fixed";
regulator-name = "dummy-reg";
regulator-min-microvolt = <848000>;
regulator-max-microvolt = <848000>;
regulator-always-on;
regulator-boot-on;
};
nss-common {
compatible = "qcom,nss-common";
reg = <0x01868010 0x1000>;
reg-names = "nss-misc-reset";
};
nss0: nss@40000000 {
compatible = "qcom,nss";
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 385 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 386 IRQ_TYPE_EDGE_RISING>;
reg = <0x39000000 0x1000>,
<0x38000000 0x30000>,
<0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_MPT_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>;
clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-mpt-clk",
"nss-nc-axi-clk";
qcom,id = <0>;
qcom,num-queue = <4>;
qcom,num-irq = <10>;
qcom,num-pri = <4>;
qcom,load-addr = <0x40000000>;
qcom,low-frequency = <187200000>;
qcom,mid-frequency = <748800000>;
qcom,max-frequency = <1689600000>;
npu-supply = <&dummy_reg>;
mx-supply = <&dummy_reg>;
qcom,bridge-enabled;
qcom,ipv4-enabled;
qcom,ipv4-reasm-enabled;
qcom,ipv6-enabled;
qcom,ipv6-reasm-enabled;
qcom,wlanredirect-enabled;
qcom,tun6rd-enabled;
qcom,l2tpv2-enabled;
qcom,gre-enabled;
qcom,gre-redir-enabled;
qcom,gre-redir-mark-enabled;
qcom,map-t-enabled;
qcom,portid-enabled;
qcom,ppe-enabled;
qcom,pppoe-enabled;
qcom,pptp-enabled;
qcom,tunipip6-enabled;
qcom,shaping-enabled;
qcom,wlan-dataplane-offload-enabled;
qcom,vlan-enabled;
qcom,igs-enabled;
qcom,vxlan-enabled;
qcom,match-enabled;
qcom,mirror-enabled;
qcom,udp-st-enabled;
};
nss1: nss@40800000 {
compatible = "qcom,nss";
interrupts = <GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 391 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 392 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 393 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 394 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 395 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 396 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 397 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 398 IRQ_TYPE_EDGE_RISING>;
reg = <0x39400000 0x1000>,
<0x38030000 0x30000>,
<0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_CORE_CLK>,
<&gcc GCC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_AXI_CLK>,
<&gcc GCC_UBI1_MPT_CLK>,
<&gcc GCC_UBI1_NC_AXI_CLK>;
clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-mpt-clk",
"nss-nc-axi-clk";
qcom,id = <1>;
qcom,num-queue = <4>;
qcom,num-irq = <9>;
qcom,num-pri = <4>;
qcom,load-addr = <0x40800000>;
qcom,capwap-enabled;
qcom,dtls-enabled;
qcom,tls-enabled;
qcom,crypto-enabled;
qcom,ipsec-enabled;
qcom,qvpn-enabled;
qcom,pvxlan-enabled;
qcom,clmap-enabled;
qcom,rmnet_rx-enabled;
};
nss_crypto: qcom,nss_crypto {
compatible = "qcom,nss-crypto";
#address-cells = <1>;
#size-cells = <1>;
qcom,max-contexts = <64>;
qcom,max-context-size = <32>;
ranges;
eip197_node {
compatible = "qcom,eip197";
reg-names = "crypto_pbase";
reg = <0x39800000 0x7ffff>;
clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSSNOC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_PPE_CLK>;
clock-names = "crypto_clk",
"crypto_nocclk",
"crypto_ppeclk";
clock-frequency = /bits/ 64 <600000000 600000000 300000000>;
qcom,dma-mask = <0xff>;
qcom,transform-enabled;
qcom,aes128-cbc;
qcom,aes192-cbc;
qcom,aes256-cbc;
qcom,aes128-ctr;
qcom,aes192-ctr;
qcom,aes256-ctr;
qcom,aes128-ecb;
qcom,aes192-ecb;
qcom,aes256-ecb;
qcom,3des-cbc;
qcom,md5-hash;
qcom,sha160-hash;
qcom,sha224-hash;
qcom,sha384-hash;
qcom,sha512-hash;
qcom,sha256-hash;
qcom,md5-hmac;
qcom,sha160-hmac;
qcom,sha224-hmac;
qcom,sha256-hmac;
qcom,sha384-hmac;
qcom,sha512-hmac;
qcom,aes128-gcm-gmac;
qcom,aes192-gcm-gmac;
qcom,aes256-gcm-gmac;
qcom,aes128-cbc-md5-hmac;
qcom,aes128-cbc-sha160-hmac;
qcom,aes192-cbc-md5-hmac;
qcom,aes192-cbc-sha160-hmac;
qcom,aes256-cbc-md5-hmac;
qcom,aes256-cbc-sha160-hmac;
qcom,aes128-ctr-sha160-hmac;
qcom,aes192-ctr-sha160-hmac;
qcom,aes256-ctr-sha160-hmac;
qcom,aes128-ctr-md5-hmac;
qcom,aes192-ctr-md5-hmac;
qcom,aes256-ctr-md5-hmac;
qcom,3des-cbc-md5-hmac;
qcom,3des-cbc-sha160-hmac;
qcom,aes128-cbc-sha256-hmac;
qcom,aes192-cbc-sha256-hmac;
qcom,aes256-cbc-sha256-hmac;
qcom,aes128-ctr-sha256-hmac;
qcom,aes192-ctr-sha256-hmac;
qcom,aes256-ctr-sha256-hmac;
qcom,3des-cbc-sha256-hmac;
qcom,aes128-cbc-sha384-hmac;
qcom,aes192-cbc-sha384-hmac;
qcom,aes256-cbc-sha384-hmac;
qcom,aes128-ctr-sha384-hmac;
qcom,aes192-ctr-sha384-hmac;
qcom,aes256-ctr-sha384-hmac;
qcom,aes128-cbc-sha512-hmac;
qcom,aes192-cbc-sha512-hmac;
qcom,aes256-cbc-sha512-hmac;
qcom,aes128-ctr-sha512-hmac;
qcom,aes192-ctr-sha512-hmac;
qcom,aes256-ctr-sha512-hmac;
engine0 {
reg_offset = <0x80000>;
qcom,ifpp-enabled;
qcom,ipue-enabled;
qcom,ofpp-enabled;
qcom,opue-enabled;
};
};
};
};

258
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8074-hk-cpu.dtsi
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@ -1,258 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
&CPU0 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu0-supply = <&s3>;
};
&CPU1 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu-supply = <&s3>;
};
&CPU2 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu-supply = <&s3>;
};
&CPU3 {
operating-points-v2 = <&cpu_opp_table>;
voltage-tolerance = <1>;
cpu-supply = <&s3>;
};
&cpus {
cpu_opp_table: cpu_opp_table {
compatible = "operating-points-v2";
opp-shared;
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-microvolt = <704000>;
clock-latency-ns = <200000>;
};
opp-1382400000 {
opp-hz = /bits/ 64 <1382400000>;
opp-microvolt = <784000>;
clock-latency-ns = <200000>;
};
opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-microvolt = <832000>;
clock-latency-ns = <200000>;
};
opp-1843200000 {
opp-hz = /bits/ 64 <1843200000>;
opp-microvolt = <880000>;
clock-latency-ns = <200000>;
};
opp-1920000000 {
opp-hz = /bits/ 64 <1920000000>;
opp-microvolt = <904000>;
clock-latency-ns = <200000>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <984000>;
clock-latency-ns = <200000>;
};
};
};
&cpu0_thermal {
trips {
cpu0_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu1_thermal {
trips {
cpu1_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu2_thermal {
trips {
cpu2_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cpu3_thermal {
trips {
cpu3_passive_low: cpu-passive-low {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_passive_high: cpu-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
&cluster_thermal {
trips {
cluster_passive_low: cluster-passive {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cluster_passive_high: cluster-passive-high {
temperature = <100000>;
hysteresis = <2000>;
type = "passive";
};
cluster_crit: cluster_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cluster_passive_low>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cluster_passive_high>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

51
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8074-memory-512m.dtsi
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@ -1,51 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2020 The Linux Foundation. All rights reserved.
*/
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
nss@40000000 {
no-map;
reg = <0x0 0x40000000 0x0 0x01000000>;
};
uboot@4a600000 {
no-map;
reg = <0x0 0x4a600000 0x0 0x00400000>;
};
sbl@4aa00000 {
no-map;
reg = <0x0 0x4aa00000 0x0 0x00100000>;
};
smem_region: smem@4ab00000 {
no-map;
reg = <0x0 0x4ab00000 0x0 0x00100000>;
};
tz@4ac00000 {
no-map;
reg = <0x0 0x4ac00000 0x0 0x00400000>;
};
q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x03700000>;
};
q6_etr_region: q6_etr_dump@4e700000 {
no-map;
reg = <0x0 0x4e700000 0x0 0x100000>;
};
wifi_dump@50500000 {
no-map;
reg = <0x0 0x50500000 0x0 0x200000>;
};
};
};

741
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8074-nbg7815.dts
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@ -1,741 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
* Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
*/
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ac-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Zyxel NBG7815";
compatible = "zyxel,nbg7815", "qcom,ipq8074";
aliases {
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
/* Alias as required by u-boot to patch MAC addresses */
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
ethernet5 = &dp6;
label-mac-device = &dp1;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart3 {
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <0>;
status = "okay";
/*
* Bootloader will find the NAND DT node by the compatible and
* then "fixup" it by adding the partitions from the SMEM table
* using the legacy bindings thus making it impossible for us
* to change the partition table or utilize NVMEM for calibration.
* So add a dummy partitions node that bootloader will populate
* and set it as disabled so the kernel ignores it instead of
* printing warnings due to the broken way bootloader adds the
* partitions.
*/
partitions {
status = "disabled";
};
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0 0x50000>;
read-only;
};
partition@50000 {
label = "0:mibib";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "0:bootconfig";
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:bootconfig1";
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:qsee";
reg = <0xa0000 0x180000>;
read-only;
};
partition@220000 {
label = "0:qsee_1";
reg = <0x220000 0x180000>;
read-only;
};
partition@3a0000 {
label = "0:devcfg";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "0:devcfg_1";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3c0000 {
label = "0:apdp";
reg = <0x3c0000 0x10000>;
read-only;
};
partition@3d0000 {
label = "0:apdp_1";
reg = <0x3d0000 0x10000>;
read-only;
};
partition@3e0000 {
label = "0:rpm";
reg = <0x3e0000 0x40000>;
read-only;
};
partition@420000 {
label = "0:rpm_1";
reg = <0x420000 0x40000>;
read-only;
};
partition@460000 {
label = "0:cdt";
reg = <0x460000 0x10000>;
read-only;
};
partition@470000 {
label = "0:cdt_1";
reg = <0x470000 0x10000>;
read-only;
};
partition@480000 {
label = "0:appsbl";
reg = <0x480000 0xc0000>;
read-only;
};
partition@540000 {
label = "0:appsbl_1";
reg = <0x540000 0xc0000>;
read-only;
};
partition@600000 {
compatible = "u-boot,env";
label = "0:appsblenv";
reg = <0x600000 0x10000>;
macaddr_lan: ethaddr {
};
};
partition@610000 {
label = "0:art";
reg = <0x610000 0x40000>;
read-only;
};
partition@650000 {
label = "0:ethphyfw";
reg = <0x650000 0x80000>;
read-only;
};
partition@6d0000 {
label = "0:crt";
reg = <0x6d0000 0x10000>;
read-only;
};
partition@6e0000 {
label = "dual_flag";
reg = <0x6e0000 0x10000>;
};
partition@6f0000 {
label = "reserved";
reg = <0x6f0000 0x110000>;
read-only;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@0 {
reg = <0>;
};
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
ethernet-phy@28 {
reg = <28>;
};
ethernet-phy@8 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <8>;
};
};
&ess_switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
port@5 {
port_id = <6>;
ethernet-phy-ieee802.3-c45;
phy_address = <8>;
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&soc {
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <0>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <1>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <2>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <3>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <28>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <8>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
&blsp1_i2c2 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tmp103@70 {
compatible = "ti,tmp103";
reg = <0x70>;
};
};
&sdhc_1 {
qcom,clk-rates = <400000 25000000 50000000 100000000 \
192000000 384000000>;
qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
qcom,nonremovable;
status = "ok";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
};

969
target/linux/ipq807x/files-5.10/arch/arm64/boot/dts/qcom/ipq8078-xtr10890.dts
View File

@ -1,969 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
/* Copyright (c) 2017, 2020-2021, The Linux Foundation. All rights reserved.
*/
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ac-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "TP-LINK XTR10890";
compatible = "tplink,xtr10890", "qcom,ipq8074";
interrupt-parent = <&intc>;
//qcom,msm-id = <0x143 0x0>, <0x186 0x0>, <0x158 0x0>, <0x188 0x0>;
aliases {
serial0 = &blsp1_uart5;
serial1 = &blsp1_uart3;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
led-boot = &led_system_red;
led-failsafe = &led_system_green;
led-running = &led_system_red;
led-upgrade = &led_system_green;
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
ethernet5 = &dp6;
};
chosen {
stdout-path = "serial0";
bootargs-append = " root=/dev/ubiblock0_1 rootfstype=squashfs";
};
reserved-memory {
/delete-node/ wifi_dump@51100000;
/delete-node/ wigig_dump@51300000;
qcn9000_pcie0: qcn9000_pcie0@51100000 {
no-map;
reg = <0x0 0x51100000 0x0 0x03500000>;
};
mhi_region0: dma_pool0@54600000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x54600000 0x0 0x00900000>;
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
status = "okay";
button@1 {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
led_system_green: system-green {
label = "green:system";
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
led_system_red: system-red {
label = "red:system";
gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
};
10g-green {
label = "green:10g";
gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
};
sfp_green {
label = "green:sfp";
gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
};
};
};
&sdhc_1 {
status = "okay";
};
&qpic_nand {
pinctrl-0 = <&qpic_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partition0@0 {
label = "0:SBL1";
reg = <0x0 0x80000>;
read-only;
};
partition1@80000 {
label = "0:MIBIB";
reg = <0x80000 0x40000>;
};
partition2@c0000 {
label = "0:BOOTCONFIG";
reg = <0xc0000 0x20000>;
read-only;
};
partition3@e0000 {
label = "0:BOOTCONFIG1";
reg = <0xe0000 0x20000>;
read-only;
};
partition4@100000 {
label = "0:QSEE";
reg = <0x100000 0x280000>;
read-only;
};
partition4@380000 {
label = "0:DEVCFG";
reg = <0x380000 0x20000>;
read-only;
};
partition4@3a0000 {
label = "0:RPM";
reg = <0x3a0000 0x40000>;
read-only;
};
partition5@3e0000 {
label = "0:CDT";
reg = <0x3e0000 0x20000>;
read-only;
};
partition6@400000 {
label = "0:APPSBLENV";
reg = <0x400000 0x40000>;
};
partition7@440000 {
label = "0:APPSBL";
reg = <0x440000 0x100000>;
};
partition8@540000 {
label = "0:ART";
reg = <0x540000 0x80000>;
};
partition12@5c0000 {
label = "rootfs";
reg = <0x5c0000 0x7000000>;
};
partition13@75c0000 {
label = "0:WIFIFW";
reg = <0x75c0000 0x900000>;
};
partition15@7ec0000 {
label = "0:ETHPHYFW";
reg = <0x7ec0000 0x80000>;
};
};
};
&mdio{
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 37 0>;
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
phy4: ethernet-phy@4 {
reg = <30>;
};
phy5: ethernet-phy@5 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <0>;
};
};
&tlmm {
sd_pins: sd-pinmux {
pins = "gpio63";
function = "sd_card";
drive-strength = <8>;
bias-pull-up;
};
button_pins: button_pins {
wps_button {
pins = "gpio50";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
leds_pins: leds_pinmux {
led_pwr_green {
pins = "gpio31";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_pwr_red {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_sfp_green {
pins = "gpio30";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_green {
pins = "gpio32";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_0 {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
qpic_pins: qpic-pins {
pins = "gpio1", "gpio3", "gpio4",
"gpio5", "gpio6", "gpio7",
"gpio8", "gpio10", "gpio11",
"gpio12", "gpio13", "gpio14",
"gpio15", "gpio17";
function = "qpic";
drive-strength = <8>;
bias-disable;
};
uniphy_pins: uniphy_pinmux {
mux {
pins = "gpio60";
function = "rx2";
bias-disable;
};
sfp_tx {
pins = "gpio52";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-low;
};
};
i2c_0_pins: i2c-0-pinmux {
pins = "gpio46", "gpio47";
function = "blsp1_i2c";
drive-strength = <8>;
bias-disable;
};
pwm_pins: pwm_pinmux {
mux_1 {
pins = "gpio25";
function = "pwm02";
drive-strength = <8>;
};
};
pcie0_pins: pcie_pins {
pcie0_rst {
pins = "gpio58";
function = "pcie0_rst";
drive-strength = <8>;
bias-pull-down;
};
pcie0_wake {
pins = "gpio59";
function = "pcie0_wake";
drive-strength = <8>;
bias-pull-down;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
m25p80@0 {
compatible = "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&blsp1_i2c2 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
perst-gpio = <&tlmm 58 1>;
status = "okay";
pcie0_rp {
status = "ok";
mhi_0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
qrtr_instance_id = <0x20>;
#address-cells = <0x2>;
#size-cells = <0x2>;
memory-region = <&mhi_region0>;
// base-addr = <0x51100000>;
// m3-dump-addr = <0x53400000>;
// etr-addr = <0x53500000>;
// qcom,caldb-addr = <0x53600000>;
// mhi,max-channels = <30>;
// mhi,timeout = <10000>;
// qcom,board_id= <0xa4>;
// pcie0_mhi: pcie0_mhi {
// status = "ok";
// };
};
};
};
&pcie_qmp1 {
//status = "okay";
status = "disabled";
};
&pcie1 {
perst-gpio = <&tlmm 61 0x1>;
status = "disabled";
};
&ess_switch {
status = "okay";
pinctrl-0 = <&uniphy_pins>;
pinctrl-names = "default";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0x0b>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0x0e>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0x0d>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <16>;
};
port@1 {
port_id = <2>;
phy_address = <17>;
};
port@2 {
port_id = <3>;
phy_address = <18>;
};
port@3 {
port_id = <4>;
phy_address = <19>;
};
port@4 {
port_id = <5>;
phy_address = <30>;
phy_i2c_address = <30>;
phy-i2c-mode; /*i2c access phy */
media-type = "sfp"; /* fiber mode */
};
port@5 {
port_id = <6>;
phy_address = <0>;
ethernet-phy-ieee802.3-c45;
};
};
port_scheduler_resource {
port@0 {
port_id = < 0x00 >;
ucast_queue = < 0x00 0x8f >;
mcast_queue = < 0x100 0x10f >;
l0sp = < 0x00 0x23 >;
l0cdrr = < 0x00 0x2f >;
l0edrr = < 0x00 0x2f >;
l1cdrr = < 0x00 0x07 >;
l1edrr = < 0x00 0x07 >;
};
port@1 {
port_id = < 0x01 >;
ucast_queue = < 0x90 0x9f >;
mcast_queue = < 0x110 0x113 >;
l0sp = < 0x24 0x27 >;
l0cdrr = < 0x30 0x3f >;
l0edrr = < 0x30 0x3f >;
l1cdrr = < 0x08 0x0b >;
l1edrr = < 0x08 0x0b >;
};
port@2 {
port_id = < 0x02 >;
ucast_queue = < 0xa0 0xaf >;
mcast_queue = < 0x114 0x117 >;
l0sp = < 0x28 0x2b >;
l0cdrr = < 0x40 0x4f >;
l0edrr = < 0x40 0x4f >;
l1cdrr = < 0x0c 0x0f >;
l1edrr = < 0x0c 0x0f >;
};
port@3 {
port_id = < 0x03 >;
ucast_queue = < 0xb0 0xbf >;
mcast_queue = < 0x118 0x11b >;
l0sp = < 0x2c 0x2f >;
l0cdrr = < 0x50 0x5f >;
l0edrr = < 0x50 0x5f >;
l1cdrr = < 0x10 0x13 >;
l1edrr = < 0x10 0x13 >;
};
port@4 {
port_id = < 0x04 >;
ucast_queue = < 0xc0 0xcf >;
mcast_queue = < 0x11c 0x11f >;
l0sp = < 0x30 0x33 >;
l0cdrr = < 0x60 0x6f >;
l0edrr = < 0x60 0x6f >;
l1cdrr = < 0x14 0x17 >;
l1edrr = < 0x14 0x17 >;
};
port@5 {
port_id = < 0x05 >;
ucast_queue = < 0xd0 0xdf >;
mcast_queue = < 0x120 0x123 >;
l0sp = < 0x34 0x37 >;
l0cdrr = < 0x70 0x7f >;
l0edrr = < 0x70 0x7f >;
l1cdrr = < 0x18 0x1b >;
l1edrr = < 0x18 0x1b >;
};
port@6 {
port_id = < 0x06 >;
ucast_queue = < 0xe0 0xef >;
mcast_queue = < 0x124 0x127 >;
l0sp = < 0x38 0x3b >;
l0cdrr = < 0x80 0x8f >;
l0edrr = < 0x80 0x8f >;
l1cdrr = < 0x1c 0x1f >;
l1edrr = < 0x1c 0x1f >;
};
port@7 {
port_id = < 0x07 >;
ucast_queue = < 0xf0 0xff >;
mcast_queue = < 0x128 0x12b >;
l0sp = < 0x3c 0x3f >;
l0cdrr = < 0x90 0x9f >;
l0edrr = < 0x90 0x9f >;
l1cdrr = < 0x20 0x23 >;
l1edrr = < 0x20 0x23 >;
};
};
port_scheduler_config {
port@0 {
port_id = < 0x00 >;
l1scheduler {
group@0 {
sp = < 0x00 0x01 >;
cfg = < 0x00 0x00 0x00 0x00 >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0x00 0x04 0x08 >;
mcast_queue = < 0x100 0x104 >;
cfg = < 0x00 0x00 0x00 0x00 0x00 >;
};
group@1 {
ucast_queue = < 0x01 0x05 0x09 >;
mcast_queue = < 0x101 0x105 >;
cfg = < 0x00 0x01 0x01 0x01 0x01 >;
};
group@2 {
ucast_queue = < 0x02 0x06 0x0a >;
mcast_queue = < 0x102 0x106 >;
cfg = < 0x00 0x02 0x02 0x02 0x02 >;
};
group@3 {
ucast_queue = < 0x03 0x07 0x0b >;
mcast_queue = < 0x103 0x107 >;
cfg = < 0x00 0x03 0x03 0x03 0x03 >;
};
};
};
port@1 {
port_id = < 0x01 >;
l1scheduler {
group@0 {
sp = < 0x24 >;
cfg = < 0x00 0x08 0x00 0x08 >;
};
group@1 {
sp = < 0x25 >;
cfg = < 0x01 0x09 0x01 0x09 >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0x90 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x110 >;
mcast_loop_pri = < 0x04 >;
cfg = < 0x24 0x00 0x30 0x00 0x30 >;
};
};
};
port@2 {
port_id = < 0x02 >;
l1scheduler {
group@0 {
sp = < 0x28 >;
cfg = < 0x00 0x0c 0x00 0x0c >;
};
group@1 {
sp = < 0x29 >;
cfg = < 0x01 0x0d 0x01 0x0d >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0xa0 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x114 >;
mcast_loop_pri = < 0x04 >;
cfg = < 0x28 0x00 0x40 0x00 0x40 >;
};
};
};
port@3 {
port_id = < 0x03 >;
l1scheduler {
group@0 {
sp = < 0x2c >;
cfg = < 0x00 0x10 0x00 0x10 >;
};
group@1 {
sp = < 0x2d >;
cfg = < 0x01 0x11 0x01 0x11 >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0xb0 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x118 >;
mcast_loop_pri = < 0x04 >;
cfg = < 0x2c 0x00 0x50 0x00 0x50 >;
};
};
};
port@4 {
port_id = < 0x04 >;
l1scheduler {
group@0 {
sp = < 0x30 >;
cfg = < 0x00 0x14 0x00 0x14 >;
};
group@1 {
sp = < 0x31 >;
cfg = < 0x01 0x15 0x01 0x15 >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0xc0 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x11c >;
mcast_loop_pri = < 0x04 >;
cfg = < 0x30 0x00 0x60 0x00 0x60 >;
};
};
};
port@5 {
port_id = < 0x05 >;
l1scheduler {
group@0 {
sp = < 0x34 >;
cfg = < 0x00 0x18 0x00 0x18 >;
};
group@1 {
sp = < 0x35 >;
cfg = < 0x01 0x19 0x01 0x19 >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0xd0 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x120 >;
mcast_loop_pri = < 0x04 >;
cfg = < 0x34 0x00 0x70 0x00 0x70 >;
};
};
};
port@6 {
port_id = < 0x06 >;
l1scheduler {
group@0 {
sp = < 0x38 >;
cfg = < 0x00 0x1c 0x00 0x1c >;
};
group@1 {
sp = < 0x39 >;
cfg = < 0x01 0x1d 0x01 0x1d >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0xe0 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x124 >;
mcast_loop_pri = < 0x04 >;
cfg = < 0x38 0x00 0x80 0x00 0x80 >;
};
};
};
port@7 {
port_id = < 0x07 >;
l1scheduler {
group@0 {
sp = < 0x3c >;
cfg = < 0x00 0x20 0x00 0x20 >;
};
group@1 {
sp = < 0x3d >;
cfg = < 0x01 0x21 0x01 0x21 >;
};
};
l0scheduler {
group@0 {
ucast_queue = < 0xf0 >;
ucast_loop_pri = < 0x10 >;
mcast_queue = < 0x128 >;
cfg = < 0x3c 0x00 0x90 0x00 0x90 >;
};
};
};
};
};
&soc {
phy@86000 {
status = "okay";
};
sd-pwrseq {
status = "okay";
};
sdhci@7864900 {
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
status = "okay";
};
pwm {
pinctrl-0 = <&pwm_pins>;
pinctrl-names = "default";
used-pwm-indices = <1>, <0>, <0>, <0>;
status = "disabled";
};
// qcom,test@0 {
// status = "okay";
// };
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <16>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <17>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <18>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <19>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a003000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <30>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <0>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
// qcn9000_pcie0: qcn9000_pcie0@51100000 {
// no-map;
// reg = <0x0 0x51100000 0x0 0x02D00000>;
// };
wifi1: wifi1@f00000 {
compatible = "qcom,cnss-qcn9000";
qcom,wlan-ramdump-dynamic = <0x400000>;
mhi,max-channels = <30>;
mhi,timeout = <10000>;
qrtr_node_id = <0x20>;
qca,auto-restart;
pcie0_mhi: pcie0_mhi {
status = "ok";
};
};
};
&wifi {
status = "okay";
qcom,board_id = <528>;
qcom,ath11k-calibration-variant = "TL-XTR10890";
};
&wifi1 {
base-addr = <0x51100000>;
m3-dump-addr = <0x53400000>;
etr-addr = <0x53500000>;
caldb-addr = <0x53600000>;
hremote-size = <0x2300000>;
tgt-mem-mode = <0x0>;
caldb-size = <0x800000>;
hremote_node = <&qcn9000_pcie0>;
pageable-size = <0x800000>;
board_id = <171>;
qcom,ath11k-calibration-variant = "TL-XTR10890";
status = "ok";
};

376
target/linux/ipq807x/files-5.10/drivers/hwmon/emc2305.c
View File

@ -1,376 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2021 Sartura Ltd.
*
* Driver for the SMSC/Microchip EMC2301/2/3/5 fan controller.
*
* Author: Robert Marko <robert.marko@sartura.hr>
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/hwmon-sysfs.h>
#include <linux/hwmon.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#define MANUFACTURER_ID_REG 0xfe
#define SMSC_MANUFACTURER_ID 0x5d
#define PRODUCT_ID_REG 0xfd
#define EMC2305_PRODUCT_ID 0x34
#define EMC2303_PRODUCT_ID 0x35
#define EMC2302_PRODUCT_ID 0x36
#define EMC2301_PRODUCT_ID 0x37
#define TACH1_HIGH_BYTE 0x3e
#define TACH1_LOW_BYTE 0x3f
#define FAN1_CONFIG 0x32
#define FAN_TACH_RANGE_MASK GENMASK(6, 5)
#define FAN_TACH_MULTIPLIER_8 3
#define FAN_TACH_MULTIPLIER_4 2
#define FAN_TACH_MULTIPLIER_2 1
#define FAN_TACH_MULTIPLIER_1 0
#define FAN_TACH_CONSTANT 3932160
#define FAN_TACH_READING_MASK GENMASK(15,3)
#define TACH1_TARGET_LOW_BYTE 0x3c
#define TACH1_TARGET_HIGH_BYTE 0x3d
#define TACH_HIGH_MASK GENMASK(12,5)
#define TACH_LOW_MASK GENMASK(4,0)
#define FANX_OFFSET 0x10
#define FAN_NUM_MAX 5
struct emc2305_fan_data {
u32 min_rpm;
u32 max_rpm;
u32 target_rpm;
};
struct emc2305_data {
struct regmap *regmap;
struct i2c_client *client;
struct emc2305_fan_data fan_data[FAN_NUM_MAX];
};
static struct regmap_config emc2305_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = 0xff,
};
static int emc2305_read_fan(struct emc2305_data *data, int channel,
long *val)
{
unsigned int regval, high_byte, low_byte;
u8 range, multiplier;
int ret;
ret = regmap_read(data->regmap,
FAN1_CONFIG + channel * FANX_OFFSET,
&regval);
if (ret < 0)
return ret;
range = FIELD_GET(FAN_TACH_RANGE_MASK, regval);
switch (range) {
case FAN_TACH_MULTIPLIER_8:
multiplier = 8;
break;
case FAN_TACH_MULTIPLIER_4:
multiplier = 4;
break;
case FAN_TACH_MULTIPLIER_2:
multiplier = 2;
break;
case FAN_TACH_MULTIPLIER_1:
multiplier = 1;
break;
default:
return -EINVAL;
}
ret = regmap_read(data->regmap,
TACH1_HIGH_BYTE + channel * FANX_OFFSET,
&high_byte);
if (ret < 0)
return ret;
ret = regmap_read(data->regmap,
TACH1_LOW_BYTE + channel * FANX_OFFSET,
&low_byte);
if (ret < 0)
return ret;
regval = (u8) high_byte << 8 | (u8) low_byte;
*val = (FAN_TACH_CONSTANT * multiplier) / FIELD_GET(FAN_TACH_READING_MASK, regval);
return 0;
}
static int emc2305_read_fan_target(struct emc2305_data *data, int channel,
long *val)
{
unsigned int regval;
int ret;
ret = regmap_bulk_read(data->regmap,
TACH1_TARGET_LOW_BYTE + channel * FANX_OFFSET,
&regval,
2);
if (ret < 0)
return ret;
*val = regval;
return 0;
}
static int emc2305_set_fan_target(struct emc2305_data *data, int channel,
long val)
{
int ret;
ret = regmap_write(data->regmap,
TACH1_TARGET_LOW_BYTE + channel * FANX_OFFSET,
val & TACH_LOW_MASK);
if (ret < 0)
return ret;
ret = regmap_write(data->regmap,
TACH1_TARGET_HIGH_BYTE + channel * FANX_OFFSET,
(val & TACH_HIGH_MASK) >> 5);
if (ret < 0)
return ret;
return 0;
}
static int emc2305_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct emc2305_data *data = dev_get_drvdata(dev);
int err;
switch (type) {
case hwmon_fan:
switch (attr) {
case hwmon_fan_target:
err = emc2305_set_fan_target(data, channel, val);
break;
default:
return -EOPNOTSUPP;
}
break;
default:
return -EOPNOTSUPP;
}
return err;
}
static int emc2305_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct emc2305_data *data = dev_get_drvdata(dev);
int err;
switch (type) {
case hwmon_fan:
switch (attr) {
case hwmon_fan_input:
err = emc2305_read_fan(data, channel, val);
break;
case hwmon_fan_target:
err = emc2305_read_fan_target(data, channel, val);
break;
default:
return -EOPNOTSUPP;
}
break;
default:
return -EOPNOTSUPP;
}
return err;
}
static const char * const emc2305_fan_label[] = {
"Fan1",
"Fan2",
"Fan3",
"Fan4",
"Fan5",
};
static int emc2305_read_string(struct device *dev,
enum hwmon_sensor_types type,
u32 attr, int channel, const char **str)
{
switch (type) {
case hwmon_fan:
*str = emc2305_fan_label[channel];
break;
default:
return -EOPNOTSUPP;
}
return 0;
}
static umode_t emc2305_is_visible(const void *data, enum hwmon_sensor_types type,
u32 attr, int channel)
{
switch (type) {
case hwmon_fan:
switch (attr) {
case hwmon_fan_input:
case hwmon_fan_label:
return 0444;
case hwmon_fan_target:
return 0644;
default:
return 0;
}
default:
return 0;
}
}
static const struct hwmon_channel_info *emc2301_info[] = {
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL),
NULL
};
static const struct hwmon_channel_info *emc2302_info[] = {
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL),
NULL
};
static const struct hwmon_channel_info *emc2303_info[] = {
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL),
NULL
};
static const struct hwmon_channel_info *emc2305_info[] = {
HWMON_CHANNEL_INFO(fan,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL,
HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_LABEL),
NULL
};
static const struct hwmon_ops emc2305_hwmon_ops = {
.is_visible = emc2305_is_visible,
.write = emc2305_write,
.read = emc2305_read,
.read_string = emc2305_read_string,
};
static struct hwmon_chip_info emc2305_chip_info = {
.ops = &emc2305_hwmon_ops,
};
static int emc2305_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct emc2305_data *data;
struct device *hwmon_dev;
const char *model_name;
unsigned int regval;
int ret;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->client = client;
i2c_set_clientdata(client, data);
data->regmap = devm_regmap_init_i2c(client, &emc2305_regmap_config);
if (IS_ERR(data->regmap)) {
dev_err(dev, "failed to allocate register map\n");
return PTR_ERR(data->regmap);
}
ret = regmap_read(data->regmap, MANUFACTURER_ID_REG, &regval);
if (ret < 0)
return ret;
if (regval != SMSC_MANUFACTURER_ID) {
dev_err(dev, "Invalid manufacturer id: 0x%x\n", regval);
return -ENODEV;
}
ret = regmap_read(data->regmap, PRODUCT_ID_REG, &regval);
if (ret < 0)
return ret;
switch (regval) {
case EMC2305_PRODUCT_ID:
model_name = "emc2305";
emc2305_chip_info.info = emc2305_info;
break;
case EMC2303_PRODUCT_ID:
model_name = "emc2303";
emc2305_chip_info.info = emc2303_info;
break;
case EMC2302_PRODUCT_ID:
model_name = "emc2302";
emc2305_chip_info.info = emc2302_info;
break;
case EMC2301_PRODUCT_ID:
model_name = "emc2301";
emc2305_chip_info.info = emc2301_info;
break;
default:
dev_err(dev, "Unknown ID detected: 0x%x\n", regval);
return -ENODEV;
}
dev_info(dev, "%s detected\n", model_name);
hwmon_dev = devm_hwmon_device_register_with_info(dev, model_name,
data, &emc2305_chip_info,
NULL);
if (IS_ERR(hwmon_dev))
return PTR_ERR(hwmon_dev);
return 0;
}
static const struct of_device_id emc2305_of_match[] = {
{ .compatible = "smsc,emc2301", },
{ .compatible = "smsc,emc2302", },
{ .compatible = "smsc,emc2303", },
{ .compatible = "smsc,emc2305", },
{ },
};
MODULE_DEVICE_TABLE(of, emc2305_of_match);
static struct i2c_driver emc2305_driver = {
.probe_new = emc2305_probe,
.driver = {
.name = "emc2305",
.of_match_table = of_match_ptr(emc2305_of_match),
},
};
module_i2c_driver(emc2305_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Robert Marko <robert.marko@sartura.hr>");
MODULE_DESCRIPTION("SMSC EMC2301/2/3/5 fan controller");

666
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8070-tl-er2260t.dts
View File

@ -1,666 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "TP-Link TL-ER2260T";
compatible = "tplink,tl-er2260t", "qcom,ipq8074";
qcom,msm-id = <0x143 0x0>;
interrupt-parent = <&intc>;
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
serial0 = &blsp1_uart5;
ethernet0 = "/soc/dp1";
ethernet1 = "/soc/dp2";
ethernet2 = "/soc/dp3";
ethernet3 = "/soc/dp4";
ethernet4 = "/soc/dp5";
ethernet5 = "/soc/dp6";
};
chosen {
stdout-path = "serial0";
bootargs-append = " root=/dev/ubiblock0_1";
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_sys: sys {
label = "green:sys";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
usb {
label = "green:usb";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "usbport";
};
sfp1-green {
label = "green:sfp1";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
};
sfp2-green {
label = "green:sfp2";
gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>;
};
};
spi@78b5000 {
status = "ok";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
m25p80@0 {
compatible = "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_0 {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
mux_2 {
pins = "gpio44";
function = "gpio";
bias-pull-up;
};
};
i2c_1_pins: i2c_1_pins {
pins = "gpio46", "gpio47";
function = "blsp2_i2c";
drive-strength = <8>;
bias-disable;
};
button_pins: button_pins {
reset {
pins = "gpio50";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
uniphy_pins: uniphy_pinmux {
mux {
pins = "gpio60";
function = "rx2";
bias-disable;
};
sfp_tx {
pins = "gpio59";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
output-high;
};
};
leds_pins: leds_pinmux {
mux {
pins = "gpio21", "gpio22", "gpio65";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_sfp1_active {
pins = "gpio51";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_sfp2_active {
pins = "gpio55";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
phy0:ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
phy1:ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
phy2:ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
phy3:ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
phy4: ethernet-phy@29 {
reg = <29>;
};
phy5: ethernet-phy@30 {
reg = <30>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/ //use 10g_baser mode for default
switch_mac_mode2 = <0xe>; /* mac mode for uniphy instance2*/ //use 10g_baser mode for default
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
cmnblk_clk = "external_50MHz";
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <29>;//29
phy_i2c_address = <29>;//29
phy-i2c-mode; /*i2c access phy */
media-type = "sfp"; /* fiber mode */
};
port@5 {
port_id = <6>;
phy_address = <30>;//30
phy_i2c_address = <30>;//30
phy-i2c-mode; /*i2c access phy */
media-type = "sfp"; /* fiber mode */
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&soc {
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <0>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <1>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <2>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <3>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <29>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <30>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
nss-macsec1 {
compatible = "qcom,nss-macsec";
phy_addr = <0x1c>;
phy_access_mode = <0x00>;
mdiobus = <&mdio>;
};
watchdog@b017000 {
compatible = "qcom,kpss-wdt-ipq807x";
reg = <0xb017000 0x1000>;
reg-names = "kpss_wdt";
interrupt-names = "bark_irq";
interrupts = <0x00 0x03 0x00>;
clocks = <&sleep_clk>;
timeout-sec = <0x0a>;
wdt-max-timeout = <0x20>;
};
};
&blsp1_i2c2 {
status = "okay";
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};

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target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dts
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@ -1,71 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8071-ax3600.dtsi"
/ {
model = "Xiaomi AX3600";
compatible = "xiaomi,ax3600", "qcom,ipq8074";
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
};
led_system_yellow: system-yellow {
label = "yellow:system";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
network-yellow {
label = "yellow:network";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
network-blue {
label = "blue:network";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
aiot {
label = "blue:aiot";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
};
};
&pcie_qmp0 {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 52 GPIO_ACTIVE_HIGH>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi0: wifi@1,0 {
status = "okay";
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Xiaomi-AX3600";
};
};
};
&wifi {
qcom,ath11k-calibration-variant = "Xiaomi-AX3600";
};

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target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax3600.dtsi
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
aliases {
serial0 = &blsp1_uart5;
led-boot = &led_system_yellow;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
led-upgrade = &led_system_yellow;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
label-mac-device = &dp2;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@1 {
reg = <1>;
};
ethernet-phy@2 {
reg = <2>;
};
ethernet-phy@3 {
reg = <3>;
};
ethernet-phy@4 {
reg = <4>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x1e>; /* lan port bitmap */
switch_wan_bmp = <0x20>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@4 {
port_id = <5>;
phy_address = <4>;
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&edma {
status = "okay";
};
&soc {
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <1>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <2>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <3>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <4>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
&wifi {
status = "okay";
qcom,board_id = <658>;
};

39
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-ax6.dts
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@ -1,39 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Zhijun You <hujy652@gmail.com> */
/dts-v1/;
#include "ipq8071-ax3600.dtsi"
/ {
model = "Redmi AX6";
compatible = "redmi,ax6", "qcom,ipq8074";
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
};
led_system_yellow: system-yellow {
label = "yellow:system";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
network-blue {
label = "blue:network";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
};
network-yellow {
label = "yellow:network";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
};
};
&wifi {
qcom,ath11k-calibration-variant = "Redmi-AX6";
};

587
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8071-mf269.dts
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@ -1,587 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, ZhiPing */
/dts-v1/;
#include "ipq8074-512m.dtsi"
#include "ipq8074-ac-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include "ipq8074-ac-nss.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "ZTE MF269";
compatible = "zte,mf269", "qcom,ipq8074";
interrupt-parent = <&intc>;
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
serial0 = &blsp1_uart5;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "white:power";
gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>;
};
};
soc {
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a003000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <24>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <28>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-select = <0>;
flash@0 {
compatible = "jedec,spi-nor", "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
/*
&blsp1_spi6 {
status = "okay";
pinctrl-0 = <&spi_5_pins>;
pinctrl-names = "default";
cs-select = <0>;
si3217x@0 {
compatible = "si3217x";
num_slic = <1>;
reg = <0>;
spi-cpha;
spi-cpol;
spi-max-frequency = <960000>;
pinctrl-0 = <&slic_ctl_pins>;
pinctrl-names = "default";
ctl-gpio = <&tlmm 57 0>;
rst-gpio = <&tlmm 58 0>;
irq-gpio = <&tlmm 59 0>;
};
};
&blsp1_i2c5 {
status = "okay";
pinctrl-0 = <&i2c_4_pins>;
pinctrl-names = "default";
aw9106b@5b {
compatible = "aw9106b";
reg = <0x5b>;
reset-gpio = <&tlmm 54 0>;
};
};
*/
&blsp1_uart5 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&edma {
status = "okay";
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@4 {
port_id = <5>;
phy_address = <24>;
port_mac_sel = "QGMAC_PORT";
};
port@5 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
//reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@4 {
reg = <24>;
//reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
ethernet-phy@5 {
reg = <28>;
//reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
};
};
&prng {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&tlmm {
i2c_4_pins: i2c-4-pinmux {
pins = "gpio21", "gpio22";
function = "blsp4_i2c1";
drive-strength = <8>;
bias-disable;
};
slic_ctl_pins: slic_ctl_pins {
mux {
pins = "gpio59";
function = "gpio";
bias-pull-up;
};
};
spi_5_pins: spi-5-pins {
pins = "gpio0", "gpio2", "gpio9", "gpio16";
function = "blsp5_spi";
drive-strength = <8>;
bias-disable;
};
mdio_pins: mdio_pinmux {
mux_0 {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mux_1 {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
mux_2 {
pins = "gpio25";
function = "gpio";
bias-pull-up;
};
mux_3 {
pins = "gpio44";
function = "gpio";
bias-pull-up;
};
};
usb_vbus_pins: usb_vbus_pins {
mux {
pins = "gpio29";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
};
usb_cc_pins: usb_cc_pins {
mux {
pins = "gpio47", "gpio48";
function = "gpio";
drive-strength = <8>;
bias-disable;
output-high;
};
};
};
&usb_0 {
pinctrl-0 = <&usb_vbus_pins &usb_cc_pins>;
pinctrl-names = "default";
status = "okay";
};
&wifi {
status = "okay";
qcom,board_id = <658>;
qcom,ath11k-calibration-variant = "ZTE-MF269";
};

820
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8072-301w.dts
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@ -1,820 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Dirk Buchwalder <buchwalder@posteo.de> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "QNAP 301w";
compatible = "qnap,301w", "qcom,ipq8074";
interrupt-parent = <&intc>;
aliases {
serial0 = &blsp1_uart5;
/*
* Aliases as required by u-boot
* to patch MAC addresses
*/
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_pwr_green;
led-upgrade = &led_system_red;
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
ethernet5 = &dp6;
label-mac-device = &dp1;
};
chosen {
stdout-path = "serial0:115200n8";
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_system_green: system-green {
label = "green:system";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_system_red: system-red {
label = "red:system";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_RED>;
};
led_pwr_green: pwr-green {
label = "green:pwr";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_wifi_green: wifi-green {
label = "green:wifi";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan1_green: lan1-green {
label = "green:lan1";
gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan1_amber: lan1-amber {
label = "amber:lan1";
gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_lan2_green: lan2-green {
label = "green:lan2";
gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan2_amber: lan2-amber {
label = "amber:lan2";
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_lan3_green: lan3-green {
label = "green:lan3";
gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan3_amber: lan3-amber {
label = "amber:lan3";
gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_lan4_green: lan4-green {
label = "green:lan4";
gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_lan4_amber: lan4-amber {
label = "amber:lan4";
gpios = <&tlmm 15 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_10g_1_green: 10g_1-green {
label = "green:10g_1";
gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_10g_1_amber: 10g_1-amber {
label = "amber:10g_1";
gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
led_10g_2_green: 10g_2-green {
label = "green:10g_2";
gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_GREEN>;
};
led_10g_2_amber: 10g_2-amber {
label = "amber:10g_2";
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_AMBER>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
button_pins: button_pins {
wps_button {
pins = "gpio57";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
rst_button {
pins = "gpio67";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
};
qpic_pins: qpic-pins {
status = "disabled";
/*disabling qpic-pins due to the leds are using all of the gpios*/
};
leds_pins: leds_pinmux {
led_pwr_green {
pins = "gpio4";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_system_green {
pins = "gpio1";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_system_red {
pins = "gpio3";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan1_green {
pins = "gpio6";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan1_amber {
pins = "gpio7";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan2_green {
pins = "gpio8";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan2_amber {
pins = "gpio11";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan3_green {
pins = "gpio12";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan3_amber {
pins = "gpio13";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan4_green {
pins = "gpio14";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_lan4_amber {
pins = "gpio15";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_1_green {
pins = "gpio54";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_1_amber {
pins = "gpio56";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_2_green {
pins = "gpio51";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_10g_2_amber {
pins = "gpio52";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
led_wifi_green {
pins = "gpio42";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_1 {
status = "okay";
};
&qusb_phy_1 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <0>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
ethernet-phy@0 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <0>;
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
};
ethernet-phy@8 {
compatible ="ethernet-phy-ieee802.3-c45";
reg = <8>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
ethernet-phy@16 {
reg = <16>;
};
ethernet-phy@17 {
reg = <17>;
};
ethernet-phy@18 {
reg = <18>;
};
ethernet-phy@19 {
reg = <19>;
};
};
&sdhc_1 {
/* According to the stock dts from the QNAP gpl drop
* the emmc has a problem with the hs400 > hs200 speed switch.
* Therefore remove the mmc-hs400-1_8v property
*/
/delete-property/ mmc-hs400-1_8v;
mmc-hs200-1_8v;
mmc-ddr-1_8v;
vqmmc-supply = <&ldo11>;
status = "okay";
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0xc0>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xd>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <16>;
};
port@1 {
port_id = <2>;
phy_address = <17>;
};
port@2 {
port_id = <3>;
phy_address = <18>;
};
port@3 {
port_id = <4>;
phy_address = <19>;
};
port@4 {
port_id = <5>;
phy_address = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
port@5 {
port_id = <6>;
phy_address = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
ethernet-phy-ieee802.3-c45;
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&edma {
status = "okay";
};
&soc {
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <16>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <17>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <18>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <19>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <5>;
reg = <0x3a001800 0x200>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <8>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
dp6: dp6 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
qcom,link-poll = <1>;
qcom,phy-mdio-addr = <0>;
phy-mode = "sgmii";
mdio-bus = <&mdio>;
};
};
&wifi {
status = "okay";
/* using board_id 0xff is intentionally
* as the stock firmware is also using this default board_id
*/
qcom,board_id = <0xff>;
qcom,ath11k-calibration-variant = "QNAP-301w";
};

256
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-ac-nss.dtsi
View File

@ -1,256 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
&soc {
dummy_reg: dummy-regulator@0 {
compatible = "regulator-fixed";
regulator-name = "dummy-reg";
regulator-min-microvolt = <848000>;
regulator-max-microvolt = <848000>;
regulator-always-on;
regulator-boot-on;
};
nss-common {
compatible = "qcom,nss-common";
reg = <0x01868010 0x1000>;
reg-names = "nss-misc-reset";
};
nss0: nss@40000000 {
compatible = "qcom,nss";
interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 385 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 386 IRQ_TYPE_EDGE_RISING>;
reg = <0x39000000 0x1000>,
<0x38000000 0x30000>,
<0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_MPT_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>;
clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-mpt-clk",
"nss-nc-axi-clk";
qcom,id = <0>;
qcom,num-queue = <4>;
qcom,num-irq = <10>;
qcom,num-pri = <4>;
qcom,load-addr = <0x40000000>;
qcom,low-frequency = <187200000>;
qcom,mid-frequency = <748800000>;
qcom,max-frequency = <1689600000>;
npu-supply = <&dummy_reg>;
mx-supply = <&dummy_reg>;
qcom,bridge-enabled;
qcom,ipv4-enabled;
qcom,ipv4-reasm-enabled;
qcom,ipv6-enabled;
qcom,ipv6-reasm-enabled;
qcom,wlanredirect-enabled;
qcom,tun6rd-enabled;
qcom,l2tpv2-enabled;
qcom,gre-enabled;
qcom,gre-redir-enabled;
qcom,gre-redir-mark-enabled;
qcom,map-t-enabled;
qcom,portid-enabled;
qcom,ppe-enabled;
qcom,pppoe-enabled;
qcom,pptp-enabled;
qcom,tunipip6-enabled;
qcom,shaping-enabled;
qcom,wlan-dataplane-offload-enabled;
qcom,vlan-enabled;
qcom,igs-enabled;
qcom,vxlan-enabled;
qcom,match-enabled;
qcom,mirror-enabled;
qcom,udp-st-enabled;
};
nss1: nss@40800000 {
compatible = "qcom,nss";
interrupts = <GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 391 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 392 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 393 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 394 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 395 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 396 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 397 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 398 IRQ_TYPE_EDGE_RISING>;
reg = <0x39400000 0x1000>,
<0x38030000 0x30000>,
<0x0b111000 0x1000>;
reg-names = "nphys", "vphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_CORE_CLK>,
<&gcc GCC_UBI1_AHB_CLK>,
<&gcc GCC_UBI1_AXI_CLK>,
<&gcc GCC_UBI1_MPT_CLK>,
<&gcc GCC_UBI1_NC_AXI_CLK>;
clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-cfg-clk",
"nss-imem-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-mem-noc-nss-axi-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-ce-axi-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-mpt-clk",
"nss-nc-axi-clk";
qcom,id = <1>;
qcom,num-queue = <4>;
qcom,num-irq = <9>;
qcom,num-pri = <4>;
qcom,load-addr = <0x40800000>;
qcom,capwap-enabled;
qcom,dtls-enabled;
qcom,tls-enabled;
qcom,crypto-enabled;
qcom,ipsec-enabled;
qcom,qvpn-enabled;
qcom,pvxlan-enabled;
qcom,clmap-enabled;
qcom,rmnet_rx-enabled;
};
nss_crypto: qcom,nss_crypto {
compatible = "qcom,nss-crypto";
#address-cells = <1>;
#size-cells = <1>;
qcom,max-contexts = <64>;
qcom,max-context-size = <32>;
ranges;
eip197_node {
compatible = "qcom,eip197";
reg-names = "crypto_pbase";
reg = <0x39800000 0x7ffff>;
clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSSNOC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_PPE_CLK>;
clock-names = "crypto_clk",
"crypto_nocclk",
"crypto_ppeclk";
clock-frequency = /bits/ 64 <600000000 600000000 300000000>;
qcom,dma-mask = <0xff>;
qcom,transform-enabled;
qcom,aes128-cbc;
qcom,aes192-cbc;
qcom,aes256-cbc;
qcom,aes128-ctr;
qcom,aes192-ctr;
qcom,aes256-ctr;
qcom,aes128-ecb;
qcom,aes192-ecb;
qcom,aes256-ecb;
qcom,3des-cbc;
qcom,md5-hash;
qcom,sha160-hash;
qcom,sha224-hash;
qcom,sha384-hash;
qcom,sha512-hash;
qcom,sha256-hash;
qcom,md5-hmac;
qcom,sha160-hmac;
qcom,sha224-hmac;
qcom,sha256-hmac;
qcom,sha384-hmac;
qcom,sha512-hmac;
qcom,aes128-gcm-gmac;
qcom,aes192-gcm-gmac;
qcom,aes256-gcm-gmac;
qcom,aes128-cbc-md5-hmac;
qcom,aes128-cbc-sha160-hmac;
qcom,aes192-cbc-md5-hmac;
qcom,aes192-cbc-sha160-hmac;
qcom,aes256-cbc-md5-hmac;
qcom,aes256-cbc-sha160-hmac;
qcom,aes128-ctr-sha160-hmac;
qcom,aes192-ctr-sha160-hmac;
qcom,aes256-ctr-sha160-hmac;
qcom,aes128-ctr-md5-hmac;
qcom,aes192-ctr-md5-hmac;
qcom,aes256-ctr-md5-hmac;
qcom,3des-cbc-md5-hmac;
qcom,3des-cbc-sha160-hmac;
qcom,aes128-cbc-sha256-hmac;
qcom,aes192-cbc-sha256-hmac;
qcom,aes256-cbc-sha256-hmac;
qcom,aes128-ctr-sha256-hmac;
qcom,aes192-ctr-sha256-hmac;
qcom,aes256-ctr-sha256-hmac;
qcom,3des-cbc-sha256-hmac;
qcom,aes128-cbc-sha384-hmac;
qcom,aes192-cbc-sha384-hmac;
qcom,aes256-cbc-sha384-hmac;
qcom,aes128-ctr-sha384-hmac;
qcom,aes192-ctr-sha384-hmac;
qcom,aes256-ctr-sha384-hmac;
qcom,aes128-cbc-sha512-hmac;
qcom,aes192-cbc-sha512-hmac;
qcom,aes256-cbc-sha512-hmac;
qcom,aes128-ctr-sha512-hmac;
qcom,aes192-ctr-sha512-hmac;
qcom,aes256-ctr-sha512-hmac;
engine0 {
reg_offset = <0x80000>;
qcom,ifpp-enabled;
qcom,ipue-enabled;
qcom,ofpp-enabled;
qcom,opue-enabled;
};
};
};
};

170
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi
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@ -1,170 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
&clocks {
bias_pll_cc_clk {
compatible = "fixed-clock";
clock-frequency = <300000000>;
#clock-cells = <0>;
};
bias_pll_nss_noc_clk {
compatible = "fixed-clock";
clock-frequency = <416500000>;
#clock-cells = <0>;
};
};
&soc {
switch: ess-switch@3a000000 {
compatible = "qcom,ess-switch-ipq807x";
reg = <0x3a000000 0x1000000>;
switch_access_mode = "local bus";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_inner_bmp = <0x80>; /*inner port bitmap*/
clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
<&gcc GCC_CMN_12GPLL_SYS_CLK>,
<&gcc GCC_UNIPHY0_AHB_CLK>,
<&gcc GCC_UNIPHY0_SYS_CLK>,
<&gcc GCC_UNIPHY1_AHB_CLK>,
<&gcc GCC_UNIPHY1_SYS_CLK>,
<&gcc GCC_UNIPHY2_AHB_CLK>,
<&gcc GCC_UNIPHY2_SYS_CLK>,
<&gcc GCC_PORT1_MAC_CLK>,
<&gcc GCC_PORT2_MAC_CLK>,
<&gcc GCC_PORT3_MAC_CLK>,
<&gcc GCC_PORT4_MAC_CLK>,
<&gcc GCC_PORT5_MAC_CLK>,
<&gcc GCC_PORT6_MAC_CLK>,
<&gcc GCC_NSS_PPE_CLK>,
<&gcc GCC_NSS_PPE_CFG_CLK>,
<&gcc GCC_NSSNOC_PPE_CLK>,
<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
<&gcc GCC_NSS_EDMA_CLK>,
<&gcc GCC_NSS_EDMA_CFG_CLK>,
<&gcc GCC_NSS_PPE_IPE_CLK>,
<&gcc GCC_NSS_PPE_BTQ_CLK>,
<&gcc GCC_MDIO_AHB_CLK>,
<&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
<&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSS_IMEM_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_PORT1_RX_CLK>,
<&gcc GCC_NSS_PORT1_TX_CLK>,
<&gcc GCC_NSS_PORT2_RX_CLK>,
<&gcc GCC_NSS_PORT2_TX_CLK>,
<&gcc GCC_NSS_PORT3_RX_CLK>,
<&gcc GCC_NSS_PORT3_TX_CLK>,
<&gcc GCC_NSS_PORT4_RX_CLK>,
<&gcc GCC_NSS_PORT4_TX_CLK>,
<&gcc GCC_NSS_PORT5_RX_CLK>,
<&gcc GCC_NSS_PORT5_TX_CLK>,
<&gcc GCC_NSS_PORT6_RX_CLK>,
<&gcc GCC_NSS_PORT6_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
<&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
<&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
<&gcc NSS_PORT5_RX_CLK_SRC>,
<&gcc NSS_PORT5_TX_CLK_SRC>;
clock-names = "cmn_ahb_clk", "cmn_sys_clk",
"uniphy0_ahb_clk", "uniphy0_sys_clk",
"uniphy1_ahb_clk", "uniphy1_sys_clk",
"uniphy2_ahb_clk", "uniphy2_sys_clk",
"port1_mac_clk", "port2_mac_clk",
"port3_mac_clk", "port4_mac_clk",
"port5_mac_clk", "port6_mac_clk",
"nss_ppe_clk", "nss_ppe_cfg_clk",
"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
"nss_edma_clk", "nss_edma_cfg_clk",
"nss_ppe_ipe_clk", "nss_ppe_btq_clk",
"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
"gcc_nssnoc_snoc_clk",
"gcc_mem_noc_nss_axi_clk",
"gcc_nss_crypto_clk",
"gcc_nss_imem_clk",
"gcc_nss_ptp_ref_clk",
"nss_port1_rx_clk", "nss_port1_tx_clk",
"nss_port2_rx_clk", "nss_port2_tx_clk",
"nss_port3_rx_clk", "nss_port3_tx_clk",
"nss_port4_rx_clk", "nss_port4_tx_clk",
"nss_port5_rx_clk", "nss_port5_tx_clk",
"nss_port6_rx_clk", "nss_port6_tx_clk",
"uniphy0_port1_rx_clk",
"uniphy0_port1_tx_clk",
"uniphy0_port2_rx_clk",
"uniphy0_port2_tx_clk",
"uniphy0_port3_rx_clk",
"uniphy0_port3_tx_clk",
"uniphy0_port4_rx_clk",
"uniphy0_port4_tx_clk",
"uniphy0_port5_rx_clk",
"uniphy0_port5_tx_clk",
"uniphy1_port5_rx_clk",
"uniphy1_port5_tx_clk",
"uniphy2_port6_rx_clk",
"uniphy2_port6_tx_clk",
"nss_port5_rx_clk_src",
"nss_port5_tx_clk_src";
resets = <&gcc GCC_PPE_FULL_RESET>,
<&gcc GCC_UNIPHY0_SOFT_RESET>,
<&gcc GCC_UNIPHY0_XPCS_RESET>,
<&gcc GCC_UNIPHY1_SOFT_RESET>,
<&gcc GCC_UNIPHY1_XPCS_RESET>,
<&gcc GCC_UNIPHY2_SOFT_RESET>,
<&gcc GCC_UNIPHY2_XPCS_RESET>,
<&gcc GCC_NSSPORT1_RESET>,
<&gcc GCC_NSSPORT2_RESET>,
<&gcc GCC_NSSPORT3_RESET>,
<&gcc GCC_NSSPORT4_RESET>,
<&gcc GCC_NSSPORT5_RESET>,
<&gcc GCC_NSSPORT6_RESET>;
reset-names = "ppe_rst", "uniphy0_soft_rst",
"uniphy0_xpcs_rst", "uniphy1_soft_rst",
"uniphy1_xpcs_rst", "uniphy2_soft_rst",
"uniphy2_xpcs_rst", "nss_port1_rst",
"nss_port2_rst", "nss_port3_rst",
"nss_port4_rst", "nss_port5_rst",
"nss_port6_rst";
mdio-bus = <&mdio>;
status = "disabled";
};
ess-uniphy@7a00000 {
compatible = "qcom,ess-uniphy";
reg = <0x7a00000 0x30000>;
uniphy_access_mode = "local bus";
};
edma: edma@3ab00000 {
compatible = "qcom,edma";
reg = <0x3ab00000 0x76900>;
reg-names = "edma-reg-base";
qcom,txdesc-ring-start = <23>;
qcom,txdesc-rings = <1>;
qcom,txcmpl-ring-start = <7>;
qcom,txcmpl-rings = <1>;
qcom,rxfill-ring-start = <7>;
qcom,rxfill-rings = <1>;
qcom,rxdesc-ring-start = <15>;
qcom,rxdesc-rings = <1>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
resets = <&gcc GCC_EDMA_HW_RESET>;
reset-names = "edma_rst";
status = "disabled";
};
};

543
target/linux/ipq807x/files-5.15/arch/arm64/boot/dts/qcom/ipq8078-xtr10890.dts
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@ -1,543 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2022, Robert Marko <robimarko@gmail.com> */
/dts-v1/;
#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "TP-LINK XTR10890";
compatible = "tplink,xtr10890", "qcom,ipq8074";
aliases {
led-boot = &led_system_red;
led-failsafe = &led_system_red;
led-running = &led_system_blue;
led-upgrade = &led_system_red;
serial0 = &blsp1_uart5;
/* Aliases as required by u-boot to patch MAC addresses */
ethernet0 = &dp1;
ethernet1 = &dp2;
ethernet2 = &dp3;
ethernet3 = &dp4;
ethernet4 = &dp5;
label-mac-device = &dp1;
};
chosen {
stdout-path = "serial0:115200n8";
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_system_blue: system-blue {
label = "blue:system";
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
};
led_system_red: system-red {
label = "yellow:system";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_YELLOW>;
};
};
};
&tlmm {
mdio_pins: mdio-pins {
mdc {
pins = "gpio68";
function = "mdc";
drive-strength = <8>;
bias-pull-up;
};
mdio {
pins = "gpio69";
function = "mdio";
drive-strength = <8>;
bias-pull-up;
};
};
};
&blsp1_uart5 {
status = "okay";
};
&prng {
status = "okay";
};
&cryptobam {
status = "okay";
};
&crypto {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&qusb_phy_0 {
status = "okay";
};
&ssphy_0 {
status = "okay";
};
&usb_0 {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
qca8075_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
qca8075_1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
qca8075_2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
};
qca8075_3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
};
qca8081: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
};
&switch {
status = "okay";
switch_cpu_bmp = <0x1>; /* cpu port bitmap */
switch_lan_bmp = <0x3e>; /* lan port bitmap */
switch_wan_bmp = <0x40>; /* wan port bitmap */
switch_mac_mode = <0xb>; /* mac mode for uniphy instance0*/
switch_mac_mode1 = <0xff>; /* mac mode for uniphy instance1*/
switch_mac_mode2 = <0xc>; /* mac mode for uniphy instance2*/
bm_tick_mode = <0>; /* bm tick mode */
tm_tick_mode = <0>; /* tm tick mode */
qcom,port_phyinfo {
port@0 {
port_id = <1>;
phy_address = <0>;
};
port@1 {
port_id = <2>;
phy_address = <1>;
};
port@2 {
port_id = <3>;
phy_address = <2>;
};
port@3 {
port_id = <4>;
phy_address = <3>;
};
port@5 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
port_scheduler_resource {
port@0 {
port_id = <0>;
ucast_queue = <0 143>;
mcast_queue = <256 271>;
l0sp = <0 35>;
l0cdrr = <0 47>;
l0edrr = <0 47>;
l1cdrr = <0 7>;
l1edrr = <0 7>;
};
port@1 {
port_id = <1>;
ucast_queue = <144 159>;
mcast_queue = <272 275>;
l0sp = <36 39>;
l0cdrr = <48 63>;
l0edrr = <48 63>;
l1cdrr = <8 11>;
l1edrr = <8 11>;
};
port@2 {
port_id = <2>;
ucast_queue = <160 175>;
mcast_queue = <276 279>;
l0sp = <40 43>;
l0cdrr = <64 79>;
l0edrr = <64 79>;
l1cdrr = <12 15>;
l1edrr = <12 15>;
};
port@3 {
port_id = <3>;
ucast_queue = <176 191>;
mcast_queue = <280 283>;
l0sp = <44 47>;
l0cdrr = <80 95>;
l0edrr = <80 95>;
l1cdrr = <16 19>;
l1edrr = <16 19>;
};
port@4 {
port_id = <4>;
ucast_queue = <192 207>;
mcast_queue = <284 287>;
l0sp = <48 51>;
l0cdrr = <96 111>;
l0edrr = <96 111>;
l1cdrr = <20 23>;
l1edrr = <20 23>;
};
port@5 {
port_id = <5>;
ucast_queue = <208 223>;
mcast_queue = <288 291>;
l0sp = <52 55>;
l0cdrr = <112 127>;
l0edrr = <112 127>;
l1cdrr = <24 27>;
l1edrr = <24 27>;
};
port@6 {
port_id = <6>;
ucast_queue = <224 239>;
mcast_queue = <292 295>;
l0sp = <56 59>;
l0cdrr = <128 143>;
l0edrr = <128 143>;
l1cdrr = <28 31>;
l1edrr = <28 31>;
};
port@7 {
port_id = <7>;
ucast_queue = <240 255>;
mcast_queue = <296 299>;
l0sp = <60 63>;
l0cdrr = <144 159>;
l0edrr = <144 159>;
l1cdrr = <32 35>;
l1edrr = <32 35>;
};
};
port_scheduler_config {
port@0 {
port_id = <0>;
l1scheduler {
group@0 {
sp = <0 1>; /*L0 SPs*/
/*cpri cdrr epri edrr*/
cfg = <0 0 0 0>;
};
};
l0scheduler {
group@0 {
/*unicast queues*/
ucast_queue = <0 4 8>;
/*multicast queues*/
mcast_queue = <256 260>;
/*sp cpri cdrr epri edrr*/
cfg = <0 0 0 0 0>;
};
group@1 {
ucast_queue = <1 5 9>;
mcast_queue = <257 261>;
cfg = <0 1 1 1 1>;
};
group@2 {
ucast_queue = <2 6 10>;
mcast_queue = <258 262>;
cfg = <0 2 2 2 2>;
};
group@3 {
ucast_queue = <3 7 11>;
mcast_queue = <259 263>;
cfg = <0 3 3 3 3>;
};
};
};
port@1 {
port_id = <1>;
l1scheduler {
group@0 {
sp = <36>;
cfg = <0 8 0 8>;
};
group@1 {
sp = <37>;
cfg = <1 9 1 9>;
};
};
l0scheduler {
group@0 {
ucast_queue = <144>;
ucast_loop_pri = <16>;
mcast_queue = <272>;
mcast_loop_pri = <4>;
cfg = <36 0 48 0 48>;
};
};
};
port@2 {
port_id = <2>;
l1scheduler {
group@0 {
sp = <40>;
cfg = <0 12 0 12>;
};
group@1 {
sp = <41>;
cfg = <1 13 1 13>;
};
};
l0scheduler {
group@0 {
ucast_queue = <160>;
ucast_loop_pri = <16>;
mcast_queue = <276>;
mcast_loop_pri = <4>;
cfg = <40 0 64 0 64>;
};
};
};
port@3 {
port_id = <3>;
l1scheduler {
group@0 {
sp = <44>;
cfg = <0 16 0 16>;
};
group@1 {
sp = <45>;
cfg = <1 17 1 17>;
};
};
l0scheduler {
group@0 {
ucast_queue = <176>;
ucast_loop_pri = <16>;
mcast_queue = <280>;
mcast_loop_pri = <4>;
cfg = <44 0 80 0 80>;
};
};
};
port@4 {
port_id = <4>;
l1scheduler {
group@0 {
sp = <48>;
cfg = <0 20 0 20>;
};
group@1 {
sp = <49>;
cfg = <1 21 1 21>;
};
};
l0scheduler {
group@0 {
ucast_queue = <192>;
ucast_loop_pri = <16>;
mcast_queue = <284>;
mcast_loop_pri = <4>;
cfg = <48 0 96 0 96>;
};
};
};
port@5 {
port_id = <5>;
l1scheduler {
group@0 {
sp = <52>;
cfg = <0 24 0 24>;
};
group@1 {
sp = <53>;
cfg = <1 25 1 25>;
};
};
l0scheduler {
group@0 {
ucast_queue = <208>;
ucast_loop_pri = <16>;
mcast_queue = <288>;
mcast_loop_pri = <4>;
cfg = <52 0 112 0 112>;
};
};
};
port@6 {
port_id = <6>;
l1scheduler {
group@0 {
sp = <56>;
cfg = <0 28 0 28>;
};
group@1 {
sp = <57>;
cfg = <1 29 1 29>;
};
};
l0scheduler {
group@0 {
ucast_queue = <224>;
ucast_loop_pri = <16>;
mcast_queue = <292>;
mcast_loop_pri = <4>;
cfg = <56 0 128 0 128>;
};
};
};
port@7 {
port_id = <7>;
l1scheduler {
group@0 {
sp = <60>;
cfg = <0 32 0 32>;
};
group@1 {
sp = <61>;
cfg = <1 33 1 33>;
};
};
l0scheduler {
group@0 {
ucast_queue = <240>;
ucast_loop_pri = <16>;
mcast_queue = <296>;
cfg = <60 0 144 0 144>;
};
};
};
};
};
&edma {
status = "okay";
};
&soc {
dp1: dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <6>;
reg = <0x3a007000 0x3fff>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-handle = <&qca8081>;
phy-mode = "sgmii";
};
dp2: dp2 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <4>;
reg = <0x3a001600 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-handle = <&qca8075_3>;
phy-mode = "sgmii";
};
dp3: dp3 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <3>;
reg = <0x3a001400 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-handle = <&qca8075_2>;
phy-mode = "sgmii";
};
dp4: dp4 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <2>;
reg = <0x3a001200 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
phy-handle = <&qca8075_1>;
phy-mode = "sgmii";
};
dp5: dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <1>;
local-mac-address = [000000000000];
phy-handle = <&qca8075_0>;
phy-mode = "sgmii";
};
};
&wifi {
status = "okay";
qcom,ath11k-calibration-variant = "TP-LINK-XTR10890";
};

7
target/linux/ipq807x/files-5.15/drivers/power/qcom/Kconfig
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@ -1,7 +0,0 @@
config QCOM_APM
bool "Qualcomm Technologies Inc platform specific APM driver"
help
Platform specific driver to manage the power source of
memory arrays. Interfaces with regulator drivers to ensure
SRAM Vmin requirements are met across different performance
levels.

1
target/linux/ipq807x/files-5.15/drivers/power/qcom/Makefile
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obj-$(CONFIG_QCOM_APM) += apm.o

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target/linux/ipq807x/files-5.15/drivers/power/qcom/apm.c
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/*
* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/of_device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/power/qcom/apm.h>
/*
* VDD_APCC
* =============================================================
* | VDD_MX | |
* | ==========================|============= |
* ___|___ ___|___ ___|___ ___|___ ___|___ ___|___
* | | | | | | | | | | | |
* | APCC | | MX HS | | MX HS | | APCC | | MX HS | | APCC |
* | HS | | | | | | HS | | | | HS |
* |_______| |_______| |_______| |_______| |_______| |_______|
* |_________| |_________| |__________|
* | | |
* ______|_____ ______|_____ _______|_____
* | | | | | |
* | | | | | |
* | CPU MEM | | L2 MEM | | L3 MEM |
* | Arrays | | Arrays | | Arrays |
* | | | | | |
* |____________| |____________| |_____________|
*
*/
/* Register value definitions */
#define APCS_GFMUXA_SEL_VAL 0x13
#define APCS_GFMUXA_DESEL_VAL 0x03
#define MSM_APM_MX_MODE_VAL 0x00
#define MSM_APM_APCC_MODE_VAL 0x10
#define MSM_APM_MX_DONE_VAL 0x00
#define MSM_APM_APCC_DONE_VAL 0x03
#define MSM_APM_OVERRIDE_SEL_VAL 0xb0
#define MSM_APM_SEC_CLK_SEL_VAL 0x30
#define SPM_EVENT_SET_VAL 0x01
#define SPM_EVENT_CLEAR_VAL 0x00
/* Register bit mask definitions */
#define MSM_APM_CTL_STS_MASK 0x0f
/* Register offset definitions */
#define APCC_APM_MODE 0x00000098
#define APCC_APM_CTL_STS 0x000000a8
#define APCS_SPARE 0x00000068
#define APCS_VERSION 0x00000fd0
#define HMSS_VERSION_1P2 0x10020000
#define MSM_APM_SWITCH_TIMEOUT_US 10
#define SPM_WAKEUP_DELAY_US 2
#define SPM_EVENT_NUM 6
#define MSM_APM_DRIVER_NAME "qcom,msm-apm"
enum {
MSM8996_ID,
MSM8953_ID,
IPQ807x_ID,
};
struct msm_apm_ctrl_dev {
struct list_head list;
struct device *dev;
enum msm_apm_supply supply;
spinlock_t lock;
void __iomem *reg_base;
void __iomem *apcs_csr_base;
void __iomem **apcs_spm_events_addr;
void __iomem *apc0_pll_ctl_addr;
void __iomem *apc1_pll_ctl_addr;
u32 version;
struct dentry *debugfs;
u32 msm_id;
};
#if defined(CONFIG_DEBUG_FS)
static struct dentry *apm_debugfs_base;
#endif
static DEFINE_MUTEX(apm_ctrl_list_mutex);
static LIST_HEAD(apm_ctrl_list);
/*
* Get the resources associated with the APM controller from device tree
* and remap all I/O addresses that are relevant to this HW revision.
*/
static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev,
struct msm_apm_ctrl_dev *ctrl)
{
struct device *dev = &pdev->dev;
struct resource *res;
static const char *res_name[SPM_EVENT_NUM] = {
"apc0-l2-spm",
"apc1-l2-spm",
"apc0-cpu0-spm",
"apc0-cpu1-spm",
"apc1-cpu0-spm",
"apc1-cpu1-spm"
};
int i, ret = 0;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
if (!res) {
dev_err(dev, "Missing PM APCC Global register physical address");
return -EINVAL;
}
ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
if (!ctrl->reg_base) {
dev_err(dev, "Failed to map PM APCC Global registers\n");
return -ENOMEM;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr");
if (!res) {
dev_err(dev, "Missing APCS CSR physical base address");
return -EINVAL;
}
ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res));
if (!ctrl->apcs_csr_base) {
dev_err(dev, "Failed to map APCS CSR registers\n");
return -ENOMEM;
}
ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION);
if (ctrl->version >= HMSS_VERSION_1P2)
return ret;
ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev,
SPM_EVENT_NUM
* sizeof(void __iomem *),
GFP_KERNEL);
if (!ctrl->apcs_spm_events_addr) {
dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n");
return -ENOMEM;
}
for (i = 0; i < SPM_EVENT_NUM; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
res_name[i]);
if (!res) {
dev_err(dev, "Missing address for %s\n", res_name[i]);
ret = -EINVAL;
goto free_events;
}
ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start,
resource_size(res));
if (!ctrl->apcs_spm_events_addr[i]) {
dev_err(dev, "Failed to map %s\n", res_name[i]);
ret = -ENOMEM;
goto free_events;
}
dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i],
&res->start, ctrl->apcs_spm_events_addr[i]);
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"apc0-pll-ctl");
if (!res) {
dev_err(dev, "Missing APC0 PLL CTL physical address\n");
ret = -EINVAL;
goto free_events;
}
ctrl->apc0_pll_ctl_addr = devm_ioremap(dev,
res->start,
resource_size(res));
if (!ctrl->apc0_pll_ctl_addr) {
dev_err(dev, "Failed to map APC0 PLL CTL register\n");
ret = -ENOMEM;
goto free_events;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"apc1-pll-ctl");
if (!res) {
dev_err(dev, "Missing APC1 PLL CTL physical address\n");
ret = -EINVAL;
goto free_events;
}
ctrl->apc1_pll_ctl_addr = devm_ioremap(dev,
res->start,
resource_size(res));
if (!ctrl->apc1_pll_ctl_addr) {
dev_err(dev, "Failed to map APC1 PLL CTL register\n");
ret = -ENOMEM;
goto free_events;
}
return ret;
free_events:
devm_kfree(dev, ctrl->apcs_spm_events_addr);
return ret;
}
/* 8953 register offset definition */
#define MSM8953_APM_DLY_CNTR 0x2ac
/* Register field shift definitions */
#define APM_CTL_SEL_SWITCH_DLY_SHIFT 0
#define APM_CTL_RESUME_CLK_DLY_SHIFT 8
#define APM_CTL_HALT_CLK_DLY_SHIFT 16
#define APM_CTL_POST_HALT_DLY_SHIFT 24
/* Register field mask definitions */
#define APM_CTL_SEL_SWITCH_DLY_MASK GENMASK(7, 0)
#define APM_CTL_RESUME_CLK_DLY_MASK GENMASK(15, 8)
#define APM_CTL_HALT_CLK_DLY_MASK GENMASK(23, 16)
#define APM_CTL_POST_HALT_DLY_MASK GENMASK(31, 24)
/*
* Get the resources associated with the msm8953 APM controller from
* device tree, remap all I/O addresses, and program the initial
* register configuration required for the 8953 APM controller device.
*/
static int msm8953_apm_ctrl_init(struct platform_device *pdev,
struct msm_apm_ctrl_dev *ctrl)
{
struct device *dev = &pdev->dev;
struct resource *res;
u32 delay_counter, val = 0, regval = 0;
int rc = 0;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
if (!res) {
dev_err(dev, "Missing PM APCC Global register physical address\n");
return -ENODEV;
}
ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
if (!ctrl->reg_base) {
dev_err(dev, "Failed to map PM APCC Global registers\n");
return -ENOMEM;
}
/*
* Initial APM register configuration required before starting
* APM HW controller.
*/
regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR);
val = regval;
if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) {
rc = of_property_read_u32(dev->of_node,
"qcom,apm-post-halt-delay", &delay_counter);
if (rc < 0) {
dev_err(dev, "apm-post-halt-delay read failed, rc = %d",
rc);
return rc;
}
val &= ~APM_CTL_POST_HALT_DLY_MASK;
val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT)
& APM_CTL_POST_HALT_DLY_MASK;
}
if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) {
rc = of_property_read_u32(dev->of_node,
"qcom,apm-halt-clk-delay", &delay_counter);
if (rc < 0) {
dev_err(dev, "apm-halt-clk-delay read failed, rc = %d",
rc);
return rc;
}
val &= ~APM_CTL_HALT_CLK_DLY_MASK;
val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT)
& APM_CTL_HALT_CLK_DLY_MASK;
}
if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) {
rc = of_property_read_u32(dev->of_node,
"qcom,apm-resume-clk-delay", &delay_counter);
if (rc < 0) {
dev_err(dev, "apm-resume-clk-delay read failed, rc = %d",
rc);
return rc;
}
val &= ~APM_CTL_RESUME_CLK_DLY_MASK;
val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT)
& APM_CTL_RESUME_CLK_DLY_MASK;
}
if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) {
rc = of_property_read_u32(dev->of_node,
"qcom,apm-sel-switch-delay", &delay_counter);
if (rc < 0) {
dev_err(dev, "apm-sel-switch-delay read failed, rc = %d",
rc);
return rc;
}
val &= ~APM_CTL_SEL_SWITCH_DLY_MASK;
val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT)
& APM_CTL_SEL_SWITCH_DLY_MASK;
}
if (val != regval) {
writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR);
/* make sure write completes before return */
mb();
}
return rc;
}
static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
{
int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
u32 regval;
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&ctrl_dev->lock, flags);
/* Perform revision-specific programming steps */
if (ctrl_dev->version < HMSS_VERSION_1P2) {
/* Clear SPM events */
for (i = 0; i < SPM_EVENT_NUM; i++)
writel_relaxed(SPM_EVENT_CLEAR_VAL,
ctrl_dev->apcs_spm_events_addr[i]);
udelay(SPM_WAKEUP_DELAY_US);
/* Switch APC/CBF to GPLL0 clock */
writel_relaxed(APCS_GFMUXA_SEL_VAL,
ctrl_dev->apcs_csr_base + APCS_SPARE);
ndelay(200);
writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
ctrl_dev->apc0_pll_ctl_addr);
ndelay(200);
writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
ctrl_dev->apc1_pll_ctl_addr);
/* Ensure writes complete before proceeding */
mb();
}
/* Switch arrays to MX supply and wait for its completion */
writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base +
APCC_APM_MODE);
/* Ensure write above completes before delaying */
mb();
while (timeout > 0) {
regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
if ((regval & MSM_APM_CTL_STS_MASK) ==
MSM_APM_MX_DONE_VAL)
break;
udelay(1);
timeout--;
}
if (timeout == 0) {
ret = -ETIMEDOUT;
dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
regval);
}
/* Perform revision-specific programming steps */
if (ctrl_dev->version < HMSS_VERSION_1P2) {
/* Switch APC/CBF clocks to original source */
writel_relaxed(APCS_GFMUXA_DESEL_VAL,
ctrl_dev->apcs_csr_base + APCS_SPARE);
ndelay(200);
writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
ctrl_dev->apc0_pll_ctl_addr);
ndelay(200);
writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
ctrl_dev->apc1_pll_ctl_addr);
/* Complete clock source switch before SPM event sequence */
mb();
/* Set SPM events */
for (i = 0; i < SPM_EVENT_NUM; i++)
writel_relaxed(SPM_EVENT_SET_VAL,
ctrl_dev->apcs_spm_events_addr[i]);
}
if (!ret) {
ctrl_dev->supply = MSM_APM_SUPPLY_MX;
dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
}
spin_unlock_irqrestore(&ctrl_dev->lock, flags);
return ret;
}
static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
{
int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
u32 regval;
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&ctrl_dev->lock, flags);
/* Perform revision-specific programming steps */
if (ctrl_dev->version < HMSS_VERSION_1P2) {
/* Clear SPM events */
for (i = 0; i < SPM_EVENT_NUM; i++)
writel_relaxed(SPM_EVENT_CLEAR_VAL,
ctrl_dev->apcs_spm_events_addr[i]);
udelay(SPM_WAKEUP_DELAY_US);
/* Switch APC/CBF to GPLL0 clock */
writel_relaxed(APCS_GFMUXA_SEL_VAL,
ctrl_dev->apcs_csr_base + APCS_SPARE);
ndelay(200);
writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
ctrl_dev->apc0_pll_ctl_addr);
ndelay(200);
writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
ctrl_dev->apc1_pll_ctl_addr);
/* Ensure previous writes complete before proceeding */
mb();
}
/* Switch arrays to APCC supply and wait for its completion */
writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
APCC_APM_MODE);
/* Ensure write above completes before delaying */
mb();
while (timeout > 0) {
regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
if ((regval & MSM_APM_CTL_STS_MASK) ==
MSM_APM_APCC_DONE_VAL)
break;
udelay(1);
timeout--;
}
if (timeout == 0) {
ret = -ETIMEDOUT;
dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
regval);
}
/* Perform revision-specific programming steps */
if (ctrl_dev->version < HMSS_VERSION_1P2) {
/* Set SPM events */
for (i = 0; i < SPM_EVENT_NUM; i++)
writel_relaxed(SPM_EVENT_SET_VAL,
ctrl_dev->apcs_spm_events_addr[i]);
/* Complete SPM event sequence before clock source switch */
mb();
/* Switch APC/CBF clocks to original source */
writel_relaxed(APCS_GFMUXA_DESEL_VAL,
ctrl_dev->apcs_csr_base + APCS_SPARE);
ndelay(200);
writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
ctrl_dev->apc0_pll_ctl_addr);
ndelay(200);
writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
ctrl_dev->apc1_pll_ctl_addr);
}
if (!ret) {
ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
}
spin_unlock_irqrestore(&ctrl_dev->lock, flags);
return ret;
}
/* 8953 register value definitions */
#define MSM8953_APM_MX_MODE_VAL 0x00
#define MSM8953_APM_APCC_MODE_VAL 0x02
#define MSM8953_APM_MX_DONE_VAL 0x00
#define MSM8953_APM_APCC_DONE_VAL 0x03
/* 8953 register offset definitions */
#define MSM8953_APCC_APM_MODE 0x000002a8
#define MSM8953_APCC_APM_CTL_STS 0x000002b0
/* 8953 constants */
#define MSM8953_APM_SWITCH_TIMEOUT_US 500
/* Register bit mask definitions */
#define MSM8953_APM_CTL_STS_MASK 0x1f
static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
{
int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
u32 regval;
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&ctrl_dev->lock, flags);
/* Switch arrays to MX supply and wait for its completion */
writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base +
MSM8953_APCC_APM_MODE);
/* Ensure write above completes before delaying */
mb();
while (timeout > 0) {
regval = readl_relaxed(ctrl_dev->reg_base +
MSM8953_APCC_APM_CTL_STS);
if ((regval & MSM8953_APM_CTL_STS_MASK) ==
MSM8953_APM_MX_DONE_VAL)
break;
udelay(1);
timeout--;
}
if (timeout == 0) {
ret = -ETIMEDOUT;
dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
regval);
} else {
ctrl_dev->supply = MSM_APM_SUPPLY_MX;
dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
}
spin_unlock_irqrestore(&ctrl_dev->lock, flags);
return ret;
}
static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
{
int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
u32 regval;
int ret = 0;
unsigned long flags;
spin_lock_irqsave(&ctrl_dev->lock, flags);
/* Switch arrays to APCC supply and wait for its completion */
writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
MSM8953_APCC_APM_MODE);
/* Ensure write above completes before delaying */
mb();
while (timeout > 0) {
regval = readl_relaxed(ctrl_dev->reg_base +
MSM8953_APCC_APM_CTL_STS);
if ((regval & MSM8953_APM_CTL_STS_MASK) ==
MSM8953_APM_APCC_DONE_VAL)
break;
udelay(1);
timeout--;
}
if (timeout == 0) {
ret = -ETIMEDOUT;
dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
regval);
} else {
ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
}
spin_unlock_irqrestore(&ctrl_dev->lock, flags);
return ret;
}
static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
{
int ret = 0;
switch (ctrl_dev->msm_id) {
case MSM8996_ID:
ret = msm8996_apm_switch_to_mx(ctrl_dev);
break;
case MSM8953_ID:
case IPQ807x_ID:
ret = msm8953_apm_switch_to_mx(ctrl_dev);
break;
}
return ret;
}
static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
{
int ret = 0;
switch (ctrl_dev->msm_id) {
case MSM8996_ID:
ret = msm8996_apm_switch_to_apcc(ctrl_dev);
break;
case MSM8953_ID:
case IPQ807x_ID:
ret = msm8953_apm_switch_to_apcc(ctrl_dev);
break;
}
return ret;
}
/**
* msm_apm_get_supply() - Returns the supply that is currently
* powering the memory arrays
* @ctrl_dev: Pointer to an MSM APM controller device
*
* Returns the supply currently selected by the APM.
*/
int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
{
return ctrl_dev->supply;
}
EXPORT_SYMBOL(msm_apm_get_supply);
/**
* msm_apm_set_supply() - Perform the necessary steps to switch the voltage
* source of the memory arrays to a given supply
* @ctrl_dev: Pointer to an MSM APM controller device
* @supply: Power rail to use as supply for the memory
* arrays
*
* Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if
* the supply is not supported.
*/
int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
enum msm_apm_supply supply)
{
int ret;
switch (supply) {
case MSM_APM_SUPPLY_APCC:
ret = msm_apm_switch_to_apcc(ctrl_dev);
break;
case MSM_APM_SUPPLY_MX:
ret = msm_apm_switch_to_mx(ctrl_dev);
break;
default:
ret = -EPERM;
break;
}
return ret;
}
EXPORT_SYMBOL(msm_apm_set_supply);
/**
* msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to
* the device in device tree
* @dev: Pointer to the device
*
* The device must specify "qcom,apm-ctrl" property in its device tree
* node which points to an MSM APM controller device node.
*
* Returns an MSM APM controller handle if successful or ERR_PTR on any error.
* If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is
* returned.
*/
struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
{
struct msm_apm_ctrl_dev *ctrl_dev = NULL;
struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER);
struct device_node *ctrl_node;
if (!dev || !dev->of_node) {
pr_err("Invalid device node\n");
return ERR_PTR(-EINVAL);
}
ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0);
if (!ctrl_node) {
pr_err("Could not find qcom,apm-ctrl property in %s\n",
dev->of_node->full_name);
return ERR_PTR(-ENXIO);
}
mutex_lock(&apm_ctrl_list_mutex);
list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) {
if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) {
dev_found = ctrl_dev;
break;
}
}
mutex_unlock(&apm_ctrl_list_mutex);
of_node_put(ctrl_node);
return dev_found;
}
EXPORT_SYMBOL(msm_apm_ctrl_dev_get);
#if defined(CONFIG_DEBUG_FS)
static int apm_supply_dbg_open(struct inode *inode, struct file *filep)
{
filep->private_data = inode->i_private;
return 0;
}
static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf,
size_t count, loff_t *ppos)
{
struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data;
char buf[10];
int len;
if (!ctrl_dev) {
pr_err("invalid apm ctrl handle\n");
return -ENODEV;
}
if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC)
len = snprintf(buf, sizeof(buf), "APCC\n");
else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX)
len = snprintf(buf, sizeof(buf), "MX\n");
else
len = snprintf(buf, sizeof(buf), "ERR\n");
return simple_read_from_buffer(ubuf, count, ppos, buf, len);
}
static const struct file_operations apm_supply_fops = {
.open = apm_supply_dbg_open,
.read = apm_supply_dbg_read,
};
static void apm_debugfs_base_init(void)
{
apm_debugfs_base = debugfs_create_dir("msm-apm", NULL);
if (IS_ERR_OR_NULL(apm_debugfs_base))
pr_err("msm-apm debugfs base directory creation failed\n");
}
static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
{
struct dentry *temp;
if (IS_ERR_OR_NULL(apm_debugfs_base)) {
pr_err("Base directory missing, cannot create apm debugfs nodes\n");
return;
}
ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev),
apm_debugfs_base);
if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) {
pr_err("%s debugfs directory creation failed\n",
dev_name(ctrl_dev->dev));
return;
}
temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs,
ctrl_dev, &apm_supply_fops);
if (IS_ERR_OR_NULL(temp)) {
pr_err("supply mode creation failed\n");
return;
}
}
static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
{
if (!IS_ERR_OR_NULL(ctrl_dev->debugfs))
debugfs_remove_recursive(ctrl_dev->debugfs);
}
static void apm_debugfs_base_remove(void)
{
debugfs_remove_recursive(apm_debugfs_base);
}
#else
static void apm_debugfs_base_init(void)
{}
static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
{}
static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
{}
static void apm_debugfs_base_remove(void)
{}
#endif
static struct of_device_id msm_apm_match_table[] = {
{
.compatible = "qcom,msm-apm",
.data = (void *)(uintptr_t)MSM8996_ID,
},
{
.compatible = "qcom,msm8953-apm",
.data = (void *)(uintptr_t)MSM8953_ID,
},
{
.compatible = "qcom,ipq807x-apm",
.data = (void *)(uintptr_t)IPQ807x_ID,
},
{}
};
static int msm_apm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct msm_apm_ctrl_dev *ctrl;
const struct of_device_id *match;
int ret = 0;
dev_dbg(dev, "probing MSM Array Power Mux driver\n");
if (!dev->of_node) {
dev_err(dev, "Device tree node is missing\n");
return -ENODEV;
}
match = of_match_device(msm_apm_match_table, dev);
if (!match)
return -ENODEV;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl) {
dev_err(dev, "MSM APM controller memory allocation failed\n");
return -ENOMEM;
}
INIT_LIST_HEAD(&ctrl->list);
spin_lock_init(&ctrl->lock);
ctrl->dev = dev;
ctrl->msm_id = (uintptr_t)match->data;
platform_set_drvdata(pdev, ctrl);
switch (ctrl->msm_id) {
case MSM8996_ID:
ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl);
if (ret) {
dev_err(dev, "Failed to add APM controller device\n");
return ret;
}
break;
case MSM8953_ID:
case IPQ807x_ID:
ret = msm8953_apm_ctrl_init(pdev, ctrl);
if (ret) {
dev_err(dev, "Failed to initialize APM controller device: ret=%d\n",
ret);
return ret;
}
break;
default:
dev_err(dev, "unable to add APM controller device for msm_id:%d\n",
ctrl->msm_id);
return -ENODEV;
}
apm_debugfs_init(ctrl);
mutex_lock(&apm_ctrl_list_mutex);
list_add_tail(&ctrl->list, &apm_ctrl_list);
mutex_unlock(&apm_ctrl_list_mutex);
dev_dbg(dev, "MSM Array Power Mux driver probe successful");
return ret;
}
static int msm_apm_remove(struct platform_device *pdev)
{
struct msm_apm_ctrl_dev *ctrl_dev;
ctrl_dev = platform_get_drvdata(pdev);
if (ctrl_dev) {
mutex_lock(&apm_ctrl_list_mutex);
list_del(&ctrl_dev->list);
mutex_unlock(&apm_ctrl_list_mutex);
apm_debugfs_deinit(ctrl_dev);
}
return 0;
}
static struct platform_driver msm_apm_driver = {
.driver = {
.name = MSM_APM_DRIVER_NAME,
.of_match_table = msm_apm_match_table,
.owner = THIS_MODULE,
},
.probe = msm_apm_probe,
.remove = msm_apm_remove,
};
static int __init msm_apm_init(void)
{
apm_debugfs_base_init();
return platform_driver_register(&msm_apm_driver);
}
static void __exit msm_apm_exit(void)
{
platform_driver_unregister(&msm_apm_driver);
apm_debugfs_base_remove();
}
arch_initcall(msm_apm_init);
module_exit(msm_apm_exit);
MODULE_DESCRIPTION("MSM Array Power Mux driver");
MODULE_LICENSE("GPL v2");

695
target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-npu-regulator.c
View File

@ -1,695 +0,0 @@
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/thermal.h>
#include "cpr3-regulator.h"
#define IPQ807x_NPU_FUSE_CORNERS 2
#define IPQ817x_NPU_FUSE_CORNERS 1
#define IPQ807x_NPU_FUSE_STEP_VOLT 8000
#define IPQ807x_NPU_VOLTAGE_FUSE_SIZE 6
#define IPQ807x_NPU_CPR_CLOCK_RATE 19200000
#define IPQ807x_NPU_CPR_TCSR_START 6
#define IPQ807x_NPU_CPR_TCSR_END 7
#define NPU_TSENS 5
u32 g_valid_npu_fuse_count = IPQ807x_NPU_FUSE_CORNERS;
/**
* struct cpr3_ipq807x_npu_fuses - NPU specific fuse data for IPQ807x
* @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value
* for each fuse corner (raw, not converted to a voltage)
* This struct holds the values for all of the fuses read from memory.
*/
struct cpr3_ipq807x_npu_fuses {
u64 init_voltage[IPQ807x_NPU_FUSE_CORNERS];
};
/*
* Constants which define the name of each fuse corner.
*/
enum cpr3_ipq807x_npu_fuse_corner {
CPR3_IPQ807x_NPU_FUSE_CORNER_NOM = 0,
CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO = 1,
};
static const char * const cpr3_ipq807x_npu_fuse_corner_name[] = {
[CPR3_IPQ807x_NPU_FUSE_CORNER_NOM] = "NOM",
[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO] = "TURBO",
};
/*
* IPQ807x NPU fuse parameter locations:
*
* Structs are organized with the following dimensions:
* Outer: 0 to 1 for fuse corners from lowest to highest corner
* Inner: large enough to hold the longest set of parameter segments which
* fully defines a fuse parameter, +1 (for NULL termination).
* Each segment corresponds to a contiguous group of bits from a
* single fuse row. These segments are concatentated together in
* order to form the full fuse parameter value. The segments for
* a given parameter may correspond to different fuse rows.
*/
static struct cpr3_fuse_param
ipq807x_npu_init_voltage_param[IPQ807x_NPU_FUSE_CORNERS][2] = {
{{73, 22, 27}, {} },
{{73, 16, 21}, {} },
};
/*
* Open loop voltage fuse reference voltages in microvolts for IPQ807x
*/
static int
ipq807x_npu_fuse_ref_volt [IPQ807x_NPU_FUSE_CORNERS] = {
912000,
992000,
};
/*
* IPQ9574 (Few parameters are changed, remaining are same as IPQ807x)
*/
#define IPQ9574_NPU_FUSE_CORNERS 2
#define IPQ9574_NPU_FUSE_STEP_VOLT 10000
#define IPQ9574_NPU_CPR_CLOCK_RATE 24000000
/*
* fues parameters for IPQ9574
*/
static struct cpr3_fuse_param
ipq9574_npu_init_voltage_param[IPQ9574_NPU_FUSE_CORNERS][2] = {
{{105, 12, 17}, {} },
{{105, 6, 11}, {} },
};
/*
* Open loop voltage fuse reference voltages in microvolts for IPQ9574
*/
static int
ipq9574_npu_fuse_ref_volt [IPQ9574_NPU_FUSE_CORNERS] = {
862500,
987500,
};
struct cpr3_controller *g_ctrl;
void cpr3_npu_temp_notify(int sensor, int temp, int low_notif)
{
u32 prev_sensor_state;
if (sensor != NPU_TSENS)
return;
prev_sensor_state = g_ctrl->cur_sensor_state;
if (low_notif)
g_ctrl->cur_sensor_state |= BIT(sensor);
else
g_ctrl->cur_sensor_state &= ~BIT(sensor);
if (!prev_sensor_state && g_ctrl->cur_sensor_state)
cpr3_handle_temp_open_loop_adjustment(g_ctrl, true);
else if (prev_sensor_state && !g_ctrl->cur_sensor_state)
cpr3_handle_temp_open_loop_adjustment(g_ctrl, false);
}
/**
* cpr3_ipq807x_npu_read_fuse_data() - load NPU specific fuse parameter values
* @vreg: Pointer to the CPR3 regulator
*
* This function allocates a cpr3_ipq807x_npu_fuses struct, fills it with
* values read out of hardware fuses, and finally copies common fuse values
* into the CPR3 regulator struct.
*
* Return: 0 on success, errno on failure
*/
static int cpr3_ipq807x_npu_read_fuse_data(struct cpr3_regulator *vreg)
{
void __iomem *base = vreg->thread->ctrl->fuse_base;
struct cpr3_ipq807x_npu_fuses *fuse;
int i, rc;
fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
if (!fuse)
return -ENOMEM;
for (i = 0; i < g_valid_npu_fuse_count; i++) {
rc = cpr3_read_fuse_param(base,
vreg->cpr3_regulator_data->init_voltage_param[i],
&fuse->init_voltage[i]);
if (rc) {
cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
i, rc);
return rc;
}
}
vreg->fuse_corner_count = g_valid_npu_fuse_count;
vreg->platform_fuses = fuse;
return 0;
}
/**
* cpr3_npu_parse_corner_data() - parse NPU corner data from device tree
* properties of the CPR3 regulator's device node
* @vreg: Pointer to the CPR3 regulator
*
* Return: 0 on success, errno on failure
*/
static int cpr3_npu_parse_corner_data(struct cpr3_regulator *vreg)
{
int rc;
rc = cpr3_parse_common_corner_data(vreg);
if (rc) {
cpr3_err(vreg, "error reading corner data, rc=%d\n", rc);
return rc;
}
return rc;
}
/**
* cpr3_ipq807x_npu_calculate_open_loop_voltages() - calculate the open-loop
* voltage for each corner of a CPR3 regulator
* @vreg: Pointer to the CPR3 regulator
* @temp_correction: Temperature based correction
*
* If open-loop voltage interpolation is allowed in device tree, then
* this function calculates the open-loop voltage for a given corner using
* linear interpolation. This interpolation is performed using the processor
* frequencies of the lower and higher Fmax corners along with their fused
* open-loop voltages.
*
* If open-loop voltage interpolation is not allowed, then this function uses
* the Fmax fused open-loop voltage for all of the corners associated with a
* given fuse corner.
*
* Return: 0 on success, errno on failure
*/
static int cpr3_ipq807x_npu_calculate_open_loop_voltages(
struct cpr3_regulator *vreg, bool temp_correction)
{
struct cpr3_ipq807x_npu_fuses *fuse = vreg->platform_fuses;
struct cpr3_controller *ctrl = vreg->thread->ctrl;
int i, j, rc = 0;
u64 freq_low, volt_low, freq_high, volt_high;
int *fuse_volt;
int *fmax_corner;
fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt),
GFP_KERNEL);
fmax_corner = kcalloc(vreg->fuse_corner_count, sizeof(*fmax_corner),
GFP_KERNEL);
if (!fuse_volt || !fmax_corner) {
rc = -ENOMEM;
goto done;
}
for (i = 0; i < vreg->fuse_corner_count; i++) {
if (ctrl->cpr_global_setting == CPR_DISABLED)
fuse_volt[i] = vreg->cpr3_regulator_data->fuse_ref_volt[i];
else
fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(
vreg->cpr3_regulator_data->fuse_ref_volt[i],
vreg->cpr3_regulator_data->fuse_step_volt,
fuse->init_voltage[i],
IPQ807x_NPU_VOLTAGE_FUSE_SIZE);
/* Log fused open-loop voltage values for debugging purposes. */
cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n",
cpr3_ipq807x_npu_fuse_corner_name[i],
fuse_volt[i]);
}
rc = cpr3_determine_part_type(vreg,
fuse_volt[CPR3_IPQ807x_NPU_FUSE_CORNER_TURBO]);
if (rc) {
cpr3_err(vreg,
"fused part type detection failed failed, rc=%d\n", rc);
goto done;
}
rc = cpr3_adjust_fused_open_loop_voltages(vreg, fuse_volt);
if (rc) {
cpr3_err(vreg,
"fused open-loop voltage adjustment failed, rc=%d\n",
rc);
goto done;
}
if (temp_correction) {
rc = cpr3_determine_temp_base_open_loop_correction(vreg,
fuse_volt);
if (rc) {
cpr3_err(vreg,
"temp open-loop voltage adj. failed, rc=%d\n",
rc);
goto done;
}
}
for (i = 1; i < vreg->fuse_corner_count; i++) {
if (fuse_volt[i] < fuse_volt[i - 1]) {
cpr3_info(vreg,
"fuse corner %d voltage=%d uV < fuse corner %d \
voltage=%d uV; overriding: fuse corner %d \
voltage=%d\n",
i, fuse_volt[i], i - 1, fuse_volt[i - 1],
i, fuse_volt[i - 1]);
fuse_volt[i] = fuse_volt[i - 1];
}
}
/* Determine highest corner mapped to each fuse corner */
j = vreg->fuse_corner_count - 1;
for (i = vreg->corner_count - 1; i >= 0; i--) {
if (vreg->corner[i].cpr_fuse_corner == j) {
fmax_corner[j] = i;
j--;
}
}
if (j >= 0) {
cpr3_err(vreg, "invalid fuse corner mapping\n");
rc = -EINVAL;
goto done;
}
/*
* Interpolation is not possible for corners mapped to the lowest fuse
* corner so use the fuse corner value directly.
*/
for (i = 0; i <= fmax_corner[0]; i++)
vreg->corner[i].open_loop_volt = fuse_volt[0];
/* Interpolate voltages for the higher fuse corners. */
for (i = 1; i < vreg->fuse_corner_count; i++) {
freq_low = vreg->corner[fmax_corner[i - 1]].proc_freq;
volt_low = fuse_volt[i - 1];
freq_high = vreg->corner[fmax_corner[i]].proc_freq;
volt_high = fuse_volt[i];
for (j = fmax_corner[i - 1] + 1; j <= fmax_corner[i]; j++)
vreg->corner[j].open_loop_volt = cpr3_interpolate(
freq_low, volt_low, freq_high, volt_high,
vreg->corner[j].proc_freq);
}
done:
if (rc == 0) {
cpr3_debug(vreg, "unadjusted per-corner open-loop voltages:\n");
for (i = 0; i < vreg->corner_count; i++)
cpr3_debug(vreg, "open-loop[%2d] = %d uV\n", i,
vreg->corner[i].open_loop_volt);
rc = cpr3_adjust_open_loop_voltages(vreg);
if (rc)
cpr3_err(vreg,
"open-loop voltage adjustment failed, rc=%d\n",
rc);
}
kfree(fuse_volt);
kfree(fmax_corner);
return rc;
}
/**
* cpr3_npu_print_settings() - print out NPU CPR configuration settings into
* the kernel log for debugging purposes
* @vreg: Pointer to the CPR3 regulator
*/
static void cpr3_npu_print_settings(struct cpr3_regulator *vreg)
{
struct cpr3_corner *corner;
int i;
cpr3_debug(vreg,
"Corner: Frequency (Hz), Fuse Corner, Floor (uV), \
Open-Loop (uV), Ceiling (uV)\n");
for (i = 0; i < vreg->corner_count; i++) {
corner = &vreg->corner[i];
cpr3_debug(vreg, "%3d: %10u, %2d, %7d, %7d, %7d\n",
i, corner->proc_freq, corner->cpr_fuse_corner,
corner->floor_volt, corner->open_loop_volt,
corner->ceiling_volt);
}
if (vreg->thread->ctrl->apm)
cpr3_debug(vreg, "APM threshold = %d uV, APM adjust = %d uV\n",
vreg->thread->ctrl->apm_threshold_volt,
vreg->thread->ctrl->apm_adj_volt);
}
/**
* cpr3_ipq807x_npu_calc_temp_based_ol_voltages() - Calculate the open loop
* voltages based on temperature based correction margins
* @vreg: Pointer to the CPR3 regulator
*/
static int
cpr3_ipq807x_npu_calc_temp_based_ol_voltages(struct cpr3_regulator *vreg,
bool temp_correction)
{
int rc, i;
rc = cpr3_ipq807x_npu_calculate_open_loop_voltages(vreg,
temp_correction);
if (rc) {
cpr3_err(vreg,
"unable to calculate open-loop voltages, rc=%d\n", rc);
return rc;
}
rc = cpr3_limit_open_loop_voltages(vreg);
if (rc) {
cpr3_err(vreg, "unable to limit open-loop voltages, rc=%d\n",
rc);
return rc;
}
cpr3_open_loop_voltage_as_ceiling(vreg);
rc = cpr3_limit_floor_voltages(vreg);
if (rc) {
cpr3_err(vreg, "unable to limit floor voltages, rc=%d\n", rc);
return rc;
}
for (i = 0; i < vreg->corner_count; i++) {
if (temp_correction)
vreg->corner[i].cold_temp_open_loop_volt =
vreg->corner[i].open_loop_volt;
else
vreg->corner[i].normal_temp_open_loop_volt =
vreg->corner[i].open_loop_volt;
}
cpr3_npu_print_settings(vreg);
return rc;
}
/**
* cpr3_npu_init_thread() - perform steps necessary to initialize the
* configuration data for a CPR3 thread
* @thread: Pointer to the CPR3 thread
*
* Return: 0 on success, errno on failure
*/
static int cpr3_npu_init_thread(struct cpr3_thread *thread)
{
int rc;
rc = cpr3_parse_common_thread_data(thread);
if (rc) {
cpr3_err(thread->ctrl,
"thread %u CPR thread data from DT- failed, rc=%d\n",
thread->thread_id, rc);
return rc;
}
return 0;
}
/**
* cpr3_npu_init_regulator() - perform all steps necessary to initialize the
* configuration data for a CPR3 regulator
* @vreg: Pointer to the CPR3 regulator
*
* Return: 0 on success, errno on failure
*/
static int cpr3_npu_init_regulator(struct cpr3_regulator *vreg)
{
struct cpr3_ipq807x_npu_fuses *fuse;
int rc, cold_temp = 0;
bool can_adj_cold_temp = cpr3_can_adjust_cold_temp(vreg);
rc = cpr3_ipq807x_npu_read_fuse_data(vreg);
if (rc) {
cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
return rc;
}
fuse = vreg->platform_fuses;
rc = cpr3_npu_parse_corner_data(vreg);
if (rc) {
cpr3_err(vreg,
"Cannot read CPR corner data from DT, rc=%d\n", rc);
return rc;
}
rc = cpr3_mem_acc_init(vreg);
if (rc) {
if (rc != -EPROBE_DEFER)
cpr3_err(vreg,
"Cannot initialize mem-acc regulator settings, rc=%d\n",
rc);
return rc;
}
if (can_adj_cold_temp) {
rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, true);
if (rc) {
cpr3_err(vreg,
"unable to calculate open-loop voltages, rc=%d\n", rc);
return rc;
}
}
rc = cpr3_ipq807x_npu_calc_temp_based_ol_voltages(vreg, false);
if (rc) {
cpr3_err(vreg,
"unable to calculate open-loop voltages, rc=%d\n", rc);
return rc;
}
if (can_adj_cold_temp) {
cpr3_info(vreg,
"Normal and Cold condition init done. Default to normal.\n");
rc = cpr3_get_cold_temp_threshold(vreg, &cold_temp);
if (rc) {
cpr3_err(vreg,
"Get cold temperature threshold failed, rc=%d\n", rc);
return rc;
}
register_low_temp_notif(NPU_TSENS, cold_temp,
cpr3_npu_temp_notify);
}
return rc;
}
/**
* cpr3_npu_init_controller() - perform NPU CPR3 controller specific
* initializations
* @ctrl: Pointer to the CPR3 controller
*
* Return: 0 on success, errno on failure
*/
static int cpr3_npu_init_controller(struct cpr3_controller *ctrl)
{
int rc;
rc = cpr3_parse_open_loop_common_ctrl_data(ctrl);
if (rc) {
if (rc != -EPROBE_DEFER)
cpr3_err(ctrl, "unable to parse common controller data, rc=%d\n",
rc);
return rc;
}
ctrl->ctrl_type = CPR_CTRL_TYPE_CPR3;
ctrl->supports_hw_closed_loop = false;
return 0;
}
static const struct cpr3_reg_data ipq807x_cpr_npu = {
.cpr_valid_fuse_count = IPQ807x_NPU_FUSE_CORNERS,
.init_voltage_param = ipq807x_npu_init_voltage_param,
.fuse_ref_volt = ipq807x_npu_fuse_ref_volt,
.fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT,
.cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE,
};
static const struct cpr3_reg_data ipq817x_cpr_npu = {
.cpr_valid_fuse_count = IPQ817x_NPU_FUSE_CORNERS,
.init_voltage_param = ipq807x_npu_init_voltage_param,
.fuse_ref_volt = ipq807x_npu_fuse_ref_volt,
.fuse_step_volt = IPQ807x_NPU_FUSE_STEP_VOLT,
.cpr_clk_rate = IPQ807x_NPU_CPR_CLOCK_RATE,
};
static const struct cpr3_reg_data ipq9574_cpr_npu = {
.cpr_valid_fuse_count = IPQ9574_NPU_FUSE_CORNERS,
.init_voltage_param = ipq9574_npu_init_voltage_param,
.fuse_ref_volt = ipq9574_npu_fuse_ref_volt,
.fuse_step_volt = IPQ9574_NPU_FUSE_STEP_VOLT,
.cpr_clk_rate = IPQ9574_NPU_CPR_CLOCK_RATE,
};
static struct of_device_id cpr3_regulator_match_table[] = {
{
.compatible = "qcom,cpr3-ipq807x-npu-regulator",
.data = &ipq807x_cpr_npu
},
{
.compatible = "qcom,cpr3-ipq817x-npu-regulator",
.data = &ipq817x_cpr_npu
},
{
.compatible = "qcom,cpr3-ipq9574-npu-regulator",
.data = &ipq9574_cpr_npu
},
{}
};
static int cpr3_npu_regulator_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cpr3_controller *ctrl;
int i, rc;
const struct of_device_id *match;
struct cpr3_reg_data *cpr_data;
if (!dev->of_node) {
dev_err(dev, "Device tree node is missing\n");
return -EINVAL;
}
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
if (!ctrl)
return -ENOMEM;
g_ctrl = ctrl;
match = of_match_device(cpr3_regulator_match_table, &pdev->dev);
if (!match)
return -ENODEV;
cpr_data = (struct cpr3_reg_data *)match->data;
g_valid_npu_fuse_count = cpr_data->cpr_valid_fuse_count;
dev_info(dev, "NPU CPR valid fuse count: %d\n", g_valid_npu_fuse_count);
ctrl->cpr_clock_rate = cpr_data->cpr_clk_rate;
ctrl->dev = dev;
/* Set to false later if anything precludes CPR operation. */
ctrl->cpr_allowed_hw = true;
rc = of_property_read_string(dev->of_node, "qcom,cpr-ctrl-name",
&ctrl->name);
if (rc) {
cpr3_err(ctrl, "unable to read qcom,cpr-ctrl-name, rc=%d\n",
rc);
return rc;
}
rc = cpr3_map_fuse_base(ctrl, pdev);
if (rc) {
cpr3_err(ctrl, "could not map fuse base address\n");
return rc;
}
rc = cpr3_read_tcsr_setting(ctrl, pdev, IPQ807x_NPU_CPR_TCSR_START,
IPQ807x_NPU_CPR_TCSR_END);
if (rc) {
cpr3_err(ctrl, "could not read CPR tcsr rsetting\n");
return rc;
}
rc = cpr3_allocate_threads(ctrl, 0, 0);
if (rc) {
cpr3_err(ctrl, "failed to allocate CPR thread array, rc=%d\n",
rc);
return rc;
}
if (ctrl->thread_count != 1) {
cpr3_err(ctrl, "expected 1 thread but found %d\n",
ctrl->thread_count);
return -EINVAL;
}
rc = cpr3_npu_init_controller(ctrl);
if (rc) {
if (rc != -EPROBE_DEFER)
cpr3_err(ctrl, "failed to initialize CPR controller parameters, rc=%d\n",
rc);
return rc;
}
rc = cpr3_npu_init_thread(&ctrl->thread[0]);
if (rc) {
cpr3_err(ctrl, "thread initialization failed, rc=%d\n", rc);
return rc;
}
for (i = 0; i < ctrl->thread[0].vreg_count; i++) {
ctrl->thread[0].vreg[i].cpr3_regulator_data = cpr_data;
rc = cpr3_npu_init_regulator(&ctrl->thread[0].vreg[i]);
if (rc) {
cpr3_err(&ctrl->thread[0].vreg[i], "regulator initialization failed, rc=%d\n",
rc);
return rc;
}
}
platform_set_drvdata(pdev, ctrl);
return cpr3_open_loop_regulator_register(pdev, ctrl);
}
static int cpr3_npu_regulator_remove(struct platform_device *pdev)
{
struct cpr3_controller *ctrl = platform_get_drvdata(pdev);
return cpr3_open_loop_regulator_unregister(ctrl);
}
static struct platform_driver cpr3_npu_regulator_driver = {
.driver = {
.name = "qcom,cpr3-npu-regulator",
.of_match_table = cpr3_regulator_match_table,
.owner = THIS_MODULE,
},
.probe = cpr3_npu_regulator_probe,
.remove = cpr3_npu_regulator_remove,
};
static int cpr3_regulator_init(void)
{
return platform_driver_register(&cpr3_npu_regulator_driver);
}
arch_initcall(cpr3_regulator_init);
static void cpr3_regulator_exit(void)
{
platform_driver_unregister(&cpr3_npu_regulator_driver);
}
module_exit(cpr3_regulator_exit);
MODULE_DESCRIPTION("QCOM CPR3 NPU regulator driver");
MODULE_LICENSE("Dual BSD/GPLv2");
MODULE_ALIAS("platform:npu-ipq807x");

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target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.c
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target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-regulator.h
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target/linux/ipq807x/files-5.15/drivers/regulator/cpr3-util.c
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target/linux/ipq807x/files-5.15/drivers/regulator/cpr4-apss-regulator.c
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target/linux/ipq807x/files-5.15/include/linux/power/qcom/apm.h
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/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_POWER_QCOM_APM_H__
#define __LINUX_POWER_QCOM_APM_H__
#include <linux/device.h>
#include <linux/err.h>
/**
* enum msm_apm_supply - supported power rails to supply memory arrays
* %MSM_APM_SUPPLY_APCC: to enable selection of VDD_APCC rail as supply
* %MSM_APM_SUPPLY_MX: to enable selection of VDD_MX rail as supply
*/
enum msm_apm_supply {
MSM_APM_SUPPLY_APCC,
MSM_APM_SUPPLY_MX,
};
/* Handle used to identify an APM controller device */
struct msm_apm_ctrl_dev;
#ifdef CONFIG_QCOM_APM
struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev);
int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
enum msm_apm_supply supply);
int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev);
#else
static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
{ return ERR_PTR(-EPERM); }
static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
enum msm_apm_supply supply)
{ return -EPERM; }
static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
{ return -EPERM; }
#endif
#endif

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target/linux/ipq807x/files-5.15/include/soc/qcom/socinfo.h
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/* Copyright (c) 2009-2014, 2016, 2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_
#define _ARCH_ARM_MACH_MSM_SOCINFO_H_
#include <linux/of.h>
#define CPU_IPQ8074 323
#define CPU_IPQ8072 342
#define CPU_IPQ8076 343
#define CPU_IPQ8078 344
#define CPU_IPQ8070 375
#define CPU_IPQ8071 376
#define CPU_IPQ8072A 389
#define CPU_IPQ8074A 390
#define CPU_IPQ8076A 391
#define CPU_IPQ8078A 392
#define CPU_IPQ8070A 395
#define CPU_IPQ8071A 396
#define CPU_IPQ8172 397
#define CPU_IPQ8173 398
#define CPU_IPQ8174 399
#define CPU_IPQ6018 402
#define CPU_IPQ6028 403
#define CPU_IPQ6000 421
#define CPU_IPQ6010 422
#define CPU_IPQ6005 453
#define CPU_IPQ5010 446
#define CPU_IPQ5018 447
#define CPU_IPQ5028 448
#define CPU_IPQ5000 503
#define CPU_IPQ0509 504
#define CPU_IPQ0518 505
#define CPU_IPQ9514 510
#define CPU_IPQ9554 512
#define CPU_IPQ9570 513
#define CPU_IPQ9574 514
#define CPU_IPQ9550 511
#define CPU_IPQ9510 521
static inline int read_ipq_soc_version_major(void)
{
const int *prop;
prop = of_get_property(of_find_node_by_path("/"), "soc_version_major",
NULL);
if (!prop)
return -EINVAL;
return le32_to_cpu(*prop);
}
static inline int read_ipq_cpu_type(void)
{
const int *prop;
prop = of_get_property(of_find_node_by_path("/"), "cpu_type", NULL);
/*
* Return Default CPU type if "cpu_type" property is not found in DTSI
*/
if (!prop)
return CPU_IPQ8074;
return le32_to_cpu(*prop);
}
static inline int cpu_is_ipq8070(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8070;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8071(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8071;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8072(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8072;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8074(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8074;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8076(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8076;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8078(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8078;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8072a(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8072A;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8074a(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8074A;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8076a(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8076A;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8078a(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8078A;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8070a(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8070A;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8071a(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8071A;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8172(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8172;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8173(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8173;
#else
return 0;
#endif
}
static inline int cpu_is_ipq8174(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ8174;
#else
return 0;
#endif
}
static inline int cpu_is_ipq6018(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ6018;
#else
return 0;
#endif
}
static inline int cpu_is_ipq6028(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ6028;
#else
return 0;
#endif
}
static inline int cpu_is_ipq6000(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ6000;
#else
return 0;
#endif
}
static inline int cpu_is_ipq6010(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ6010;
#else
return 0;
#endif
}
static inline int cpu_is_ipq6005(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ6005;
#else
return 0;
#endif
}
static inline int cpu_is_ipq5010(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ5010;
#else
return 0;
#endif
}
static inline int cpu_is_ipq5018(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ5018;
#else
return 0;
#endif
}
static inline int cpu_is_ipq5028(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ5028;
#else
return 0;
#endif
}
static inline int cpu_is_ipq5000(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ5000;
#else
return 0;
#endif
}
static inline int cpu_is_ipq0509(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ0509;
#else
return 0;
#endif
}
static inline int cpu_is_ipq0518(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ0518;
#else
return 0;
#endif
}
static inline int cpu_is_ipq9514(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ9514;
#else
return 0;
#endif
}
static inline int cpu_is_ipq9554(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ9554;
#else
return 0;
#endif
}
static inline int cpu_is_ipq9570(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ9570;
#else
return 0;
#endif
}
static inline int cpu_is_ipq9574(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ9574;
#else
return 0;
#endif
}
static inline int cpu_is_ipq9550(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ9550;
#else
return 0;
#endif
}
static inline int cpu_is_ipq9510(void)
{
#ifdef CONFIG_ARCH_QCOM
return read_ipq_cpu_type() == CPU_IPQ9510;
#else
return 0;
#endif
}
static inline int cpu_is_ipq807x(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq8072() || cpu_is_ipq8074() ||
cpu_is_ipq8076() || cpu_is_ipq8078() ||
cpu_is_ipq8070() || cpu_is_ipq8071() ||
cpu_is_ipq8072a() || cpu_is_ipq8074a() ||
cpu_is_ipq8076a() || cpu_is_ipq8078a() ||
cpu_is_ipq8070a() || cpu_is_ipq8071a() ||
cpu_is_ipq8172() || cpu_is_ipq8173() ||
cpu_is_ipq8174();
#else
return 0;
#endif
}
static inline int cpu_is_ipq60xx(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq6018() || cpu_is_ipq6028() ||
cpu_is_ipq6000() || cpu_is_ipq6010() ||
cpu_is_ipq6005();
#else
return 0;
#endif
}
static inline int cpu_is_ipq50xx(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq5010() || cpu_is_ipq5018() ||
cpu_is_ipq5028() || cpu_is_ipq5000() ||
cpu_is_ipq0509() || cpu_is_ipq0518();
#else
return 0;
#endif
}
static inline int cpu_is_ipq95xx(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq9514() || cpu_is_ipq9554() ||
cpu_is_ipq9570() || cpu_is_ipq9574() ||
cpu_is_ipq9550() || cpu_is_ipq9510();
#else
return 0;
#endif
}
static inline int cpu_is_nss_crypto_enabled(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq807x() || cpu_is_ipq60xx() ||
cpu_is_ipq50xx() || cpu_is_ipq9570() ||
cpu_is_ipq9550() || cpu_is_ipq9574() ||
cpu_is_ipq9554();
#else
return 0;
#endif
}
static inline int cpu_is_internal_wifi_enabled(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq807x() || cpu_is_ipq60xx() ||
cpu_is_ipq50xx() || cpu_is_ipq9514() ||
cpu_is_ipq9554() || cpu_is_ipq9574();
#else
return 0;
#endif
}
static inline int cpu_is_uniphy1_enabled(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq807x() || cpu_is_ipq60xx() ||
cpu_is_ipq9554() || cpu_is_ipq9570() ||
cpu_is_ipq9574() || cpu_is_ipq9550();
#else
return 0;
#endif
}
static inline int cpu_is_uniphy2_enabled(void)
{
#ifdef CONFIG_ARCH_QCOM
return cpu_is_ipq807x() || cpu_is_ipq9570() ||
cpu_is_ipq9574();
#else
return 0;
#endif
}
#endif /* _ARCH_ARM_MACH_MSM_SOCINFO_H_ */

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target/linux/ipq807x/generic/target.mk
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BOARDNAME:=Generic

111
target/linux/ipq807x/image/generic.mk
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@ -1,111 +0,0 @@
define Device/FitImage
KERNEL_SUFFIX := -fit-uImage.itb
KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_NAME := Image
endef
define Device/FitImageLzma
KERNEL_SUFFIX := -fit-uImage.itb
KERNEL = kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_NAME := Image
endef
define Device/UbiFit
KERNEL_IN_UBI := 1
IMAGES := nand-factory.ubi nand-sysupgrade.bin
IMAGE/nand-factory.ubi := append-ubi
IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
endef
define Device/qnap_301w
$(call Device/FitImage)
DEVICE_VENDOR := QNAP
DEVICE_MODEL := 301w
DEVICE_DTS_CONFIG := config@hk01
KERNEL_SIZE := 16384k
BLOCKSIZE := 512k
SOC := ipq8072
IMAGES += factory.bin sysupgrade.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ipq-wifi-qnap_301w e2fsprogs kmod-fs-ext4 losetup
endef
TARGET_DEVICES += qnap_301w
define Device/redmi_ax6
$(call Device/xiaomi_ax3600)
DEVICE_VENDOR := Redmi
DEVICE_MODEL := AX6
DEVICE_PACKAGES := ipq-wifi-redmi_ax6
endef
TARGET_DEVICES += redmi_ax6
define Device/tplink_xtr10890
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := TPLINK
DEVICE_MODEL := XTR10890
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@hk01.c6
SOC := ipq8078
DEVICE_PACKAGES := ipq-wifi-tplink_xtr10890 uboot-envtools
endef
TARGET_DEVICES += tplink_xtr10890
define Device/xiaomi_ax3600
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Xiaomi
DEVICE_MODEL := AX3600
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@ac04
SOC := ipq8071
DEVICE_PACKAGES := ipq-wifi-xiaomi_ax3600 kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct
endef
TARGET_DEVICES += xiaomi_ax3600
define Device/xiaomi_ax9000
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Xiaomi
DEVICE_MODEL := AX9000
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@hk14
SOC := ipq8072
DEVICE_PACKAGES := ipq-wifi-xiaomi_ax9000 kmod-ath11k-pci ath11k-firmware-qcn9074 \
kmod-ath10k-ct ath10k-firmware-qca9887-ct
endef
TARGET_DEVICES += xiaomi_ax9000
define Device/zte_mf269
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := ZTE
DEVICE_MODEL := MF269
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@ac04
SOC := ipq8071
DEVICE_PACKAGES := ipq-wifi-zte_mf269 uboot-envtools
endef
TARGET_DEVICES += zte_mf269
define Device/zyxel_nbg7815
$(call Device/FitImage)
DEVICE_VENDOR := ZYXEL
DEVICE_MODEL := NBG7815
DEVICE_TITLE := Zyxel Armor G5 (NBG7815)
DEVICE_DTS_CONFIG := config@nbg7815
BLOCKSIZE := 128k
PAGESIZE := 2048
SOC := ipq8074
IMAGES += factory.bin sysupgrade.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ipq-wifi-zyxel_nbg7815 kmod-ath11k-pci e2fsprogs kmod-fs-ext4 losetup kmod-hwmon-tmp103
endef
TARGET_DEVICES += zyxel_nbg7815

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target/linux/ipq807x/patches-5.10/001-v5.11-remoteproc-sysmon-Expose-the-shutdown-result.patch
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@ -1,222 +0,0 @@
From c47b1e60f043925ecce585f8c5340c049deda25e Mon Sep 17 00:00:00 2001
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Date: Sat, 21 Nov 2020 21:41:33 -0800
Subject: [PATCH] remoteproc: sysmon: Expose the shutdown result
A graceful shutdown of the Qualcomm remote processors where
traditionally performed by invoking a shared memory state signal and
waiting for the associated ack.
This was later superseded by the "sysmon" mechanism, where some form of
shared memory bus is used to send a "graceful shutdown request" message
and one of more signals comes back to indicate its success.
But when this newer mechanism is in effect the firmware is shut down by
the time the older mechanism, implemented in the remoteproc drivers,
attempts to perform a graceful shutdown - and as such it will never
receive an ack back.
This patch therefor track the success of the latest shutdown attempt in
sysmon and exposes a new function in the API that the remoteproc driver
can use to query the success and the necessity of invoking the older
mechanism.
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Link: https://lore.kernel.org/r/20201122054135.802935-3-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_common.h | 6 +++
drivers/remoteproc/qcom_sysmon.c | 82 ++++++++++++++++++++++++--------
2 files changed, 69 insertions(+), 19 deletions(-)
--- a/drivers/remoteproc/qcom_common.h
+++ b/drivers/remoteproc/qcom_common.h
@@ -51,6 +51,7 @@ struct qcom_sysmon *qcom_add_sysmon_subd
const char *name,
int ssctl_instance);
void qcom_remove_sysmon_subdev(struct qcom_sysmon *sysmon);
+bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon);
#else
static inline struct qcom_sysmon *qcom_add_sysmon_subdev(struct rproc *rproc,
const char *name,
@@ -62,6 +63,11 @@ static inline struct qcom_sysmon *qcom_a
static inline void qcom_remove_sysmon_subdev(struct qcom_sysmon *sysmon)
{
}
+
+static inline bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon)
+{
+ return false;
+}
#endif
#endif
--- a/drivers/remoteproc/qcom_sysmon.c
+++ b/drivers/remoteproc/qcom_sysmon.c
@@ -45,6 +45,7 @@ struct qcom_sysmon {
struct mutex lock;
bool ssr_ack;
+ bool shutdown_acked;
struct qmi_handle qmi;
struct sockaddr_qrtr ssctl;
@@ -116,10 +117,13 @@ out_unlock:
/**
* sysmon_request_shutdown() - request graceful shutdown of remote
* @sysmon: sysmon context
+ *
+ * Return: boolean indicator of the remote processor acking the request
*/
-static void sysmon_request_shutdown(struct qcom_sysmon *sysmon)
+static bool sysmon_request_shutdown(struct qcom_sysmon *sysmon)
{
char *req = "ssr:shutdown";
+ bool acked = false;
int ret;
mutex_lock(&sysmon->lock);
@@ -142,9 +146,13 @@ static void sysmon_request_shutdown(stru
if (!sysmon->ssr_ack)
dev_err(sysmon->dev,
"unexpected response to sysmon shutdown request\n");
+ else
+ acked = true;
out_unlock:
mutex_unlock(&sysmon->lock);
+
+ return acked;
}
static int sysmon_callback(struct rpmsg_device *rpdev, void *data, int count,
@@ -298,14 +306,33 @@ static struct qmi_msg_handler qmi_indica
{}
};
+static bool ssctl_request_shutdown_wait(struct qcom_sysmon *sysmon)
+{
+ int ret;
+
+ ret = wait_for_completion_timeout(&sysmon->shutdown_comp, 10 * HZ);
+ if (ret)
+ return true;
+
+ ret = try_wait_for_completion(&sysmon->ind_comp);
+ if (ret)
+ return true;
+
+ dev_err(sysmon->dev, "timeout waiting for shutdown ack\n");
+ return false;
+}
+
/**
* ssctl_request_shutdown() - request shutdown via SSCTL QMI service
* @sysmon: sysmon context
+ *
+ * Return: boolean indicator of the remote processor acking the request
*/
-static void ssctl_request_shutdown(struct qcom_sysmon *sysmon)
+static bool ssctl_request_shutdown(struct qcom_sysmon *sysmon)
{
struct ssctl_shutdown_resp resp;
struct qmi_txn txn;
+ bool acked = false;
int ret;
reinit_completion(&sysmon->ind_comp);
@@ -313,7 +340,7 @@ static void ssctl_request_shutdown(struc
ret = qmi_txn_init(&sysmon->qmi, &txn, ssctl_shutdown_resp_ei, &resp);
if (ret < 0) {
dev_err(sysmon->dev, "failed to allocate QMI txn\n");
- return;
+ return false;
}
ret = qmi_send_request(&sysmon->qmi, &sysmon->ssctl, &txn,
@@ -321,27 +348,23 @@ static void ssctl_request_shutdown(struc
if (ret < 0) {
dev_err(sysmon->dev, "failed to send shutdown request\n");
qmi_txn_cancel(&txn);
- return;
+ return false;
}
ret = qmi_txn_wait(&txn, 5 * HZ);
- if (ret < 0)
+ if (ret < 0) {
dev_err(sysmon->dev, "failed receiving QMI response\n");
- else if (resp.resp.result)
+ } else if (resp.resp.result) {
dev_err(sysmon->dev, "shutdown request failed\n");
- else
+ } else {
dev_dbg(sysmon->dev, "shutdown request completed\n");
-
- if (sysmon->shutdown_irq > 0) {
- ret = wait_for_completion_timeout(&sysmon->shutdown_comp,
- 10 * HZ);
- if (!ret) {
- ret = try_wait_for_completion(&sysmon->ind_comp);
- if (!ret)
- dev_err(sysmon->dev,
- "timeout waiting for shutdown ack\n");
- }
+ acked = true;
}
+
+ if (sysmon->shutdown_irq > 0)
+ return ssctl_request_shutdown_wait(sysmon);
+
+ return acked;
}
/**
@@ -514,6 +537,9 @@ static void sysmon_stop(struct rproc_sub
.subsys_name = sysmon->name,
.ssr_event = SSCTL_SSR_EVENT_BEFORE_SHUTDOWN
};
+ bool acked;
+
+ sysmon->shutdown_acked = false;
mutex_lock(&sysmon->state_lock);
sysmon->state = SSCTL_SSR_EVENT_BEFORE_SHUTDOWN;
@@ -530,9 +556,11 @@ static void sysmon_stop(struct rproc_sub
}
if (sysmon->ssctl_version)
- ssctl_request_shutdown(sysmon);
+ acked = ssctl_request_shutdown(sysmon);
else if (sysmon->ept)
- sysmon_request_shutdown(sysmon);
+ acked = sysmon_request_shutdown(sysmon);
+
+ sysmon->shutdown_acked = acked;
}
static void sysmon_unprepare(struct rproc_subdev *subdev)
@@ -695,6 +723,22 @@ void qcom_remove_sysmon_subdev(struct qc
EXPORT_SYMBOL_GPL(qcom_remove_sysmon_subdev);
/**
+ * qcom_sysmon_shutdown_acked() - query the success of the last shutdown
+ * @sysmon: sysmon context
+ *
+ * When sysmon is used to request a graceful shutdown of the remote processor
+ * this can be used by the remoteproc driver to query the success, in order to
+ * know if it should fall back to other means of requesting a shutdown.
+ *
+ * Return: boolean indicator of the success of the last shutdown request
+ */
+bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon)
+{
+ return sysmon && sysmon->shutdown_acked;
+}
+EXPORT_SYMBOL_GPL(qcom_sysmon_shutdown_acked);
+
+/**
* sysmon_probe() - probe sys_mon channel
* @rpdev: rpmsg device handle
*

120
target/linux/ipq807x/patches-5.10/002-v5.11-remoteproc-qcom-q6v5-Query-sysmon-before-graceful-sh.patch
View File

@ -1,120 +0,0 @@
From 47c815630294b6d2284fff10377d808f376de2b2 Mon Sep 17 00:00:00 2001
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Date: Sat, 21 Nov 2020 21:41:34 -0800
Subject: [PATCH 01/16] remoteproc: qcom: q6v5: Query sysmon before graceful
shutdown
Requesting a graceful shutdown through the shared memory state signals
will not be acked in the event that sysmon has already successfully shut
down the remote firmware. So extend the stop request API to optionally
take the remoteproc's sysmon instance and query if there's already been
a successful shutdown attempt, before doing the signal dance.
Tested-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Link: https://lore.kernel.org/r/20201122054135.802935-4-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5.c | 8 +++++++-
drivers/remoteproc/qcom_q6v5.h | 3 ++-
drivers/remoteproc/qcom_q6v5_adsp.c | 2 +-
drivers/remoteproc/qcom_q6v5_mss.c | 2 +-
drivers/remoteproc/qcom_q6v5_pas.c | 2 +-
drivers/remoteproc/qcom_q6v5_wcss.c | 2 +-
6 files changed, 13 insertions(+), 6 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5.c
+++ b/drivers/remoteproc/qcom_q6v5.c
@@ -13,6 +13,7 @@
#include <linux/soc/qcom/smem.h>
#include <linux/soc/qcom/smem_state.h>
#include <linux/remoteproc.h>
+#include "qcom_common.h"
#include "qcom_q6v5.h"
#define Q6V5_PANIC_DELAY_MS 200
@@ -146,15 +147,20 @@ static irqreturn_t q6v5_stop_interrupt(i
/**
* qcom_q6v5_request_stop() - request the remote processor to stop
* @q6v5: reference to qcom_q6v5 context
+ * @sysmon: reference to the remote's sysmon instance, or NULL
*
* Return: 0 on success, negative errno on failure
*/
-int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5)
+int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon)
{
int ret;
q6v5->running = false;
+ /* Don't perform SMP2P dance if sysmon already shut down the remote */
+ if (qcom_sysmon_shutdown_acked(sysmon))
+ return 0;
+
qcom_smem_state_update_bits(q6v5->state,
BIT(q6v5->stop_bit), BIT(q6v5->stop_bit));
--- a/drivers/remoteproc/qcom_q6v5.h
+++ b/drivers/remoteproc/qcom_q6v5.h
@@ -8,6 +8,7 @@
struct rproc;
struct qcom_smem_state;
+struct qcom_sysmon;
struct qcom_q6v5 {
struct device *dev;
@@ -40,7 +41,7 @@ int qcom_q6v5_init(struct qcom_q6v5 *q6v
int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5);
int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5);
-int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5);
+int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon);
int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout);
unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5);
--- a/drivers/remoteproc/qcom_q6v5_adsp.c
+++ b/drivers/remoteproc/qcom_q6v5_adsp.c
@@ -266,7 +266,7 @@ static int adsp_stop(struct rproc *rproc
int handover;
int ret;
- ret = qcom_q6v5_request_stop(&adsp->q6v5);
+ ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
if (ret == -ETIMEDOUT)
dev_err(adsp->dev, "timed out on wait\n");
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -1402,7 +1402,7 @@ static int q6v5_stop(struct rproc *rproc
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
int ret;
- ret = qcom_q6v5_request_stop(&qproc->q6v5);
+ ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
if (ret == -ETIMEDOUT)
dev_err(qproc->dev, "timed out on wait\n");
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -217,7 +217,7 @@ static int adsp_stop(struct rproc *rproc
int handover;
int ret;
- ret = qcom_q6v5_request_stop(&adsp->q6v5);
+ ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);
if (ret == -ETIMEDOUT)
dev_err(adsp->dev, "timed out on wait\n");
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -390,7 +390,7 @@ static int q6v5_wcss_stop(struct rproc *
int ret;
/* WCSS powerdown */
- ret = qcom_q6v5_request_stop(&wcss->q6v5);
+ ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
if (ret == -ETIMEDOUT) {
dev_err(wcss->dev, "timed out on wait\n");
return ret;

104
target/linux/ipq807x/patches-5.10/003-v5.13-remoteproc-qcom-wcss-populate-hardcoded-param-using-.patch
View File

@ -1,104 +0,0 @@
From 6a83f257a5a10b24c7311475f19d58399c475476 Mon Sep 17 00:00:00 2001
From: Govind Singh <govinds@codeaurora.org>
Date: Fri, 29 Jan 2021 00:18:12 +0530
Subject: [PATCH 02/16] remoteproc: qcom: wcss: populate hardcoded param using
driver data
Q6 based WiFi fw loading is supported across
different targets, ex: IPQ8074/QCS404. In order to
support different fw names/pas id etc, populate
hardcoded param using driver data.
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1611859695-11824-2-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 29 ++++++++++++++++++++++++-----
1 file changed, 24 insertions(+), 5 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -71,6 +71,11 @@
#define TCSR_WCSS_CLK_MASK 0x1F
#define TCSR_WCSS_CLK_ENABLE 0x14
+struct wcss_data {
+ const char *firmware_name;
+ unsigned int crash_reason_smem;
+};
+
struct q6v5_wcss {
struct device *dev;
@@ -93,6 +98,8 @@ struct q6v5_wcss {
void *mem_region;
size_t mem_size;
+ unsigned int crash_reason_smem;
+
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
};
@@ -438,7 +445,7 @@ static int q6v5_wcss_load(struct rproc *
return ret;
}
-static const struct rproc_ops q6v5_wcss_ops = {
+static const struct rproc_ops q6v5_wcss_ipq8074_ops = {
.start = q6v5_wcss_start,
.stop = q6v5_wcss_stop,
.da_to_va = q6v5_wcss_da_to_va,
@@ -538,12 +545,17 @@ static int q6v5_alloc_memory_region(stru
static int q6v5_wcss_probe(struct platform_device *pdev)
{
+ const struct wcss_data *desc;
struct q6v5_wcss *wcss;
struct rproc *rproc;
int ret;
- rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops,
- "IPQ8074/q6_fw.mdt", sizeof(*wcss));
+ desc = device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops,
+ desc->firmware_name, sizeof(*wcss));
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
return -ENOMEM;
@@ -551,6 +563,7 @@ static int q6v5_wcss_probe(struct platfo
wcss = rproc->priv;
wcss->dev = &pdev->dev;
+ wcss->crash_reason_smem = desc->crash_reason_smem;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -564,7 +577,8 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
- ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
+ ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
+ NULL);
if (ret)
goto free_rproc;
@@ -595,8 +609,13 @@ static int q6v5_wcss_remove(struct platf
return 0;
}
+static const struct wcss_data wcss_ipq8074_res_init = {
+ .firmware_name = "IPQ8074/q6_fw.mdt",
+ .crash_reason_smem = WCSS_CRASH_REASON,
+};
+
static const struct of_device_id q6v5_wcss_of_match[] = {
- { .compatible = "qcom,ipq8074-wcss-pil" },
+ { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);

764
target/linux/ipq807x/patches-5.10/004-v5.13-remoteproc-qcom-wcss-Add-non-pas-wcss-Q6-support-for.patch
View File

@ -1,764 +0,0 @@
From 155940892f022482c7e7a33c917fd766519d031b Mon Sep 17 00:00:00 2001
From: Govind Singh <govinds@codeaurora.org>
Date: Fri, 29 Jan 2021 00:18:14 +0530
Subject: [PATCH 03/16] remoteproc: qcom: wcss: Add non pas wcss Q6 support for
QCS404
Add non PAS WCSS remoteproc driver support for QCS404 SOC.
Add WCSS q6 bootup and shutdown sequence handled from
Application Processor SubSystem(APSS).
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1611859695-11824-4-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 566 ++++++++++++++++++++++++++--
1 file changed, 528 insertions(+), 38 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -4,13 +4,18 @@
* Copyright (C) 2014 Sony Mobile Communications AB
* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
*/
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
+#include <linux/of_address.h>
#include <linux/of_reserved_mem.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/soc/qcom/mdt_loader.h>
#include "qcom_common.h"
@@ -24,6 +29,9 @@
#define Q6SS_GFMUX_CTL_REG 0x020
#define Q6SS_PWR_CTL_REG 0x030
#define Q6SS_MEM_PWR_CTL 0x0B0
+#define Q6SS_STRAP_ACC 0x110
+#define Q6SS_CGC_OVERRIDE 0x034
+#define Q6SS_BCR_REG 0x6000
/* AXI Halt Register Offsets */
#define AXI_HALTREQ_REG 0x0
@@ -37,14 +45,19 @@
#define Q6SS_CORE_ARES BIT(1)
#define Q6SS_BUS_ARES_ENABLE BIT(2)
+/* Q6SS_BRC_RESET */
+#define Q6SS_BRC_BLK_ARES BIT(0)
+
/* Q6SS_GFMUX_CTL */
#define Q6SS_CLK_ENABLE BIT(1)
+#define Q6SS_SWITCH_CLK_SRC BIT(8)
/* Q6SS_PWR_CTL */
#define Q6SS_L2DATA_STBY_N BIT(18)
#define Q6SS_SLP_RET_N BIT(19)
#define Q6SS_CLAMP_IO BIT(20)
#define QDSS_BHS_ON BIT(21)
+#define QDSS_Q6_MEMORIES GENMASK(15, 0)
/* Q6SS parameters */
#define Q6SS_LDO_BYP BIT(25)
@@ -53,6 +66,7 @@
#define Q6SS_CLAMP_QMC_MEM BIT(22)
#define HALT_CHECK_MAX_LOOPS 200
#define Q6SS_XO_CBCR GENMASK(5, 3)
+#define Q6SS_SLEEP_CBCR GENMASK(5, 2)
/* Q6SS config/status registers */
#define TCSR_GLOBAL_CFG0 0x0
@@ -71,9 +85,23 @@
#define TCSR_WCSS_CLK_MASK 0x1F
#define TCSR_WCSS_CLK_ENABLE 0x14
+#define MAX_HALT_REG 3
+enum {
+ WCSS_IPQ8074,
+ WCSS_QCS404,
+};
+
struct wcss_data {
const char *firmware_name;
unsigned int crash_reason_smem;
+ u32 version;
+ bool aon_reset_required;
+ bool wcss_q6_reset_required;
+ const char *ssr_name;
+ const char *sysmon_name;
+ int ssctl_id;
+ const struct rproc_ops *ops;
+ bool requires_force_stop;
};
struct q6v5_wcss {
@@ -87,9 +115,26 @@ struct q6v5_wcss {
u32 halt_wcss;
u32 halt_nc;
+ struct clk *xo;
+ struct clk *ahbfabric_cbcr_clk;
+ struct clk *gcc_abhs_cbcr;
+ struct clk *gcc_axim_cbcr;
+ struct clk *lcc_csr_cbcr;
+ struct clk *ahbs_cbcr;
+ struct clk *tcm_slave_cbcr;
+ struct clk *qdsp6ss_abhm_cbcr;
+ struct clk *qdsp6ss_sleep_cbcr;
+ struct clk *qdsp6ss_axim_cbcr;
+ struct clk *qdsp6ss_xo_cbcr;
+ struct clk *qdsp6ss_core_gfmux;
+ struct clk *lcc_bcr_sleep;
+ struct regulator *cx_supply;
+ struct qcom_sysmon *sysmon;
+
struct reset_control *wcss_aon_reset;
struct reset_control *wcss_reset;
struct reset_control *wcss_q6_reset;
+ struct reset_control *wcss_q6_bcr_reset;
struct qcom_q6v5 q6v5;
@@ -99,6 +144,8 @@ struct q6v5_wcss {
size_t mem_size;
unsigned int crash_reason_smem;
+ u32 version;
+ bool requires_force_stop;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -244,6 +291,207 @@ wcss_reset:
return ret;
}
+static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss)
+{
+ unsigned long val;
+ int ret, idx;
+
+ /* Toggle the restart */
+ reset_control_assert(wcss->wcss_reset);
+ usleep_range(200, 300);
+ reset_control_deassert(wcss->wcss_reset);
+ usleep_range(200, 300);
+
+ /* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */
+ ret = clk_prepare_enable(wcss->gcc_abhs_cbcr);
+ if (ret)
+ return ret;
+
+ /* Remove reset to the WCNSS QDSP6SS */
+ reset_control_deassert(wcss->wcss_q6_bcr_reset);
+
+ /* Enable Q6SSTOP_AHBFABRIC_CBCR clock */
+ ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk);
+ if (ret)
+ goto disable_gcc_abhs_cbcr_clk;
+
+ /* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */
+ ret = clk_prepare_enable(wcss->lcc_csr_cbcr);
+ if (ret)
+ goto disable_ahbfabric_cbcr_clk;
+
+ /* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */
+ ret = clk_prepare_enable(wcss->ahbs_cbcr);
+ if (ret)
+ goto disable_csr_cbcr_clk;
+
+ /* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */
+ ret = clk_prepare_enable(wcss->tcm_slave_cbcr);
+ if (ret)
+ goto disable_ahbs_cbcr_clk;
+
+ /* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */
+ ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr);
+ if (ret)
+ goto disable_tcm_slave_cbcr_clk;
+
+ /* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */
+ ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr);
+ if (ret)
+ goto disable_abhm_cbcr_clk;
+
+ /* Enable the Q6SS XO CBC */
+ val = readl(wcss->reg_base + Q6SS_XO_CBCR);
+ val |= BIT(0);
+ writel(val, wcss->reg_base + Q6SS_XO_CBCR);
+ /* Read CLKOFF bit to go low indicating CLK is enabled */
+ ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
+ val, !(val & BIT(31)), 1,
+ HALT_CHECK_MAX_LOOPS);
+ if (ret) {
+ dev_err(wcss->dev,
+ "xo cbcr enabling timed out (rc:%d)\n", ret);
+ return ret;
+ }
+
+ writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);
+
+ /* Enable QDSP6 sleep clock clock */
+ val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
+ val |= BIT(0);
+ writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
+
+ /* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/
+ ret = clk_prepare_enable(wcss->gcc_axim_cbcr);
+ if (ret)
+ goto disable_sleep_cbcr_clk;
+
+ /* Assert resets, stop core */
+ val = readl(wcss->reg_base + Q6SS_RESET_REG);
+ val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+ writel(val, wcss->reg_base + Q6SS_RESET_REG);
+
+ /* Program the QDSP6SS PWR_CTL register */
+ writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ /*
+ * Enable memories by turning on the QDSP6 memory foot/head switch, one
+ * bank at a time to avoid in-rush current
+ */
+ for (idx = 28; idx >= 0; idx--) {
+ writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) |
+ (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL);
+ }
+
+ writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+ writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ val = readl(wcss->reg_base + Q6SS_RESET_REG);
+ val &= ~Q6SS_CORE_ARES;
+ writel(val, wcss->reg_base + Q6SS_RESET_REG);
+
+ /* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */
+ val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
+ val |= Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC;
+ writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
+
+ /* Enable sleep clock branch needed for BCR circuit */
+ ret = clk_prepare_enable(wcss->lcc_bcr_sleep);
+ if (ret)
+ goto disable_core_gfmux_clk;
+
+ return 0;
+
+disable_core_gfmux_clk:
+ val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
+ val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC);
+ writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
+ clk_disable_unprepare(wcss->gcc_axim_cbcr);
+disable_sleep_cbcr_clk:
+ val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
+ val &= ~Q6SS_CLK_ENABLE;
+ writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
+ val = readl(wcss->reg_base + Q6SS_XO_CBCR);
+ val &= ~Q6SS_CLK_ENABLE;
+ writel(val, wcss->reg_base + Q6SS_XO_CBCR);
+ clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr);
+disable_abhm_cbcr_clk:
+ clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr);
+disable_tcm_slave_cbcr_clk:
+ clk_disable_unprepare(wcss->tcm_slave_cbcr);
+disable_ahbs_cbcr_clk:
+ clk_disable_unprepare(wcss->ahbs_cbcr);
+disable_csr_cbcr_clk:
+ clk_disable_unprepare(wcss->lcc_csr_cbcr);
+disable_ahbfabric_cbcr_clk:
+ clk_disable_unprepare(wcss->ahbfabric_cbcr_clk);
+disable_gcc_abhs_cbcr_clk:
+ clk_disable_unprepare(wcss->gcc_abhs_cbcr);
+
+ return ret;
+}
+
+static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss)
+{
+ unsigned long val;
+
+ writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC);
+
+ /* Start core execution */
+ val = readl(wcss->reg_base + Q6SS_RESET_REG);
+ val &= ~Q6SS_STOP_CORE;
+ writel(val, wcss->reg_base + Q6SS_RESET_REG);
+
+ return 0;
+}
+
+static int q6v5_qcs404_wcss_start(struct rproc *rproc)
+{
+ struct q6v5_wcss *wcss = rproc->priv;
+ int ret;
+
+ ret = clk_prepare_enable(wcss->xo);
+ if (ret)
+ return ret;
+
+ ret = regulator_enable(wcss->cx_supply);
+ if (ret)
+ goto disable_xo_clk;
+
+ qcom_q6v5_prepare(&wcss->q6v5);
+
+ ret = q6v5_wcss_qcs404_power_on(wcss);
+ if (ret) {
+ dev_err(wcss->dev, "wcss clk_enable failed\n");
+ goto disable_cx_supply;
+ }
+
+ writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
+
+ q6v5_wcss_qcs404_reset(wcss);
+
+ ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
+ if (ret == -ETIMEDOUT) {
+ dev_err(wcss->dev, "start timed out\n");
+ goto disable_cx_supply;
+ }
+
+ return 0;
+
+disable_cx_supply:
+ regulator_disable(wcss->cx_supply);
+disable_xo_clk:
+ clk_disable_unprepare(wcss->xo);
+
+ return ret;
+}
+
static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
struct regmap *halt_map,
u32 offset)
@@ -278,6 +526,70 @@ static void q6v5_wcss_halt_axi_port(stru
regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
}
+static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss)
+{
+ unsigned long val;
+ int ret;
+
+ q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
+
+ /* assert clamps to avoid MX current inrush */
+ val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
+ val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM);
+ writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ /* Disable memories by turning off memory foot/headswitch */
+ writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) &
+ ~QDSS_Q6_MEMORIES),
+ wcss->reg_base + Q6SS_MEM_PWR_CTL);
+
+ /* Clear the BHS_ON bit */
+ val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
+ val &= ~Q6SS_BHS_ON;
+ writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+ clk_disable_unprepare(wcss->ahbfabric_cbcr_clk);
+ clk_disable_unprepare(wcss->lcc_csr_cbcr);
+ clk_disable_unprepare(wcss->tcm_slave_cbcr);
+ clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr);
+ clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr);
+
+ val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
+ val &= ~BIT(0);
+ writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
+
+ val = readl(wcss->reg_base + Q6SS_XO_CBCR);
+ val &= ~BIT(0);
+ writel(val, wcss->reg_base + Q6SS_XO_CBCR);
+
+ clk_disable_unprepare(wcss->ahbs_cbcr);
+ clk_disable_unprepare(wcss->lcc_bcr_sleep);
+
+ val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
+ val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC);
+ writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
+
+ clk_disable_unprepare(wcss->gcc_abhs_cbcr);
+
+ ret = reset_control_assert(wcss->wcss_reset);
+ if (ret) {
+ dev_err(wcss->dev, "wcss_reset failed\n");
+ return ret;
+ }
+ usleep_range(200, 300);
+
+ ret = reset_control_deassert(wcss->wcss_reset);
+ if (ret) {
+ dev_err(wcss->dev, "wcss_reset failed\n");
+ return ret;
+ }
+ usleep_range(200, 300);
+
+ clk_disable_unprepare(wcss->gcc_axim_cbcr);
+
+ return 0;
+}
+
static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
{
int ret;
@@ -397,20 +709,28 @@ static int q6v5_wcss_stop(struct rproc *
int ret;
/* WCSS powerdown */
- ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
- if (ret == -ETIMEDOUT) {
- dev_err(wcss->dev, "timed out on wait\n");
- return ret;
+ if (wcss->requires_force_stop) {
+ ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
+ if (ret == -ETIMEDOUT) {
+ dev_err(wcss->dev, "timed out on wait\n");
+ return ret;
+ }
}
- ret = q6v5_wcss_powerdown(wcss);
- if (ret)
- return ret;
-
- /* Q6 Power down */
- ret = q6v5_q6_powerdown(wcss);
- if (ret)
- return ret;
+ if (wcss->version == WCSS_QCS404) {
+ ret = q6v5_qcs404_wcss_shutdown(wcss);
+ if (ret)
+ return ret;
+ } else {
+ ret = q6v5_wcss_powerdown(wcss);
+ if (ret)
+ return ret;
+
+ /* Q6 Power down */
+ ret = q6v5_q6_powerdown(wcss);
+ if (ret)
+ return ret;
+ }
qcom_q6v5_unprepare(&wcss->q6v5);
@@ -453,14 +773,26 @@ static const struct rproc_ops q6v5_wcss_
.get_boot_addr = rproc_elf_get_boot_addr,
};
-static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
+static const struct rproc_ops q6v5_wcss_qcs404_ops = {
+ .start = q6v5_qcs404_wcss_start,
+ .stop = q6v5_wcss_stop,
+ .da_to_va = q6v5_wcss_da_to_va,
+ .load = q6v5_wcss_load,
+ .get_boot_addr = rproc_elf_get_boot_addr,
+ .parse_fw = qcom_register_dump_segments,
+};
+
+static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,
+ const struct wcss_data *desc)
{
struct device *dev = wcss->dev;
- wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
- if (IS_ERR(wcss->wcss_aon_reset)) {
- dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n");
- return PTR_ERR(wcss->wcss_aon_reset);
+ if (desc->aon_reset_required) {
+ wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
+ if (IS_ERR(wcss->wcss_aon_reset)) {
+ dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n");
+ return PTR_ERR(wcss->wcss_aon_reset);
+ }
}
wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
@@ -469,10 +801,18 @@ static int q6v5_wcss_init_reset(struct q
return PTR_ERR(wcss->wcss_reset);
}
- wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
- if (IS_ERR(wcss->wcss_q6_reset)) {
- dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
- return PTR_ERR(wcss->wcss_q6_reset);
+ if (desc->wcss_q6_reset_required) {
+ wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
+ if (IS_ERR(wcss->wcss_q6_reset)) {
+ dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
+ return PTR_ERR(wcss->wcss_q6_reset);
+ }
+ }
+
+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
}
return 0;
@@ -481,35 +821,48 @@ static int q6v5_wcss_init_reset(struct q
static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
struct platform_device *pdev)
{
- struct of_phandle_args args;
+ unsigned int halt_reg[MAX_HALT_REG] = {0};
+ struct device_node *syscon;
struct resource *res;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
- wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
if (IS_ERR(wcss->reg_base))
return PTR_ERR(wcss->reg_base);
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
- wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(wcss->rmb_base))
- return PTR_ERR(wcss->rmb_base);
+ if (wcss->version == WCSS_IPQ8074) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
+ wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(wcss->rmb_base))
+ return PTR_ERR(wcss->rmb_base);
+ }
- ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
- "qcom,halt-regs", 3, 0, &args);
- if (ret < 0) {
+ syscon = of_parse_phandle(pdev->dev.of_node,
+ "qcom,halt-regs", 0);
+ if (!syscon) {
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
return -EINVAL;
}
- wcss->halt_map = syscon_node_to_regmap(args.np);
- of_node_put(args.np);
+ wcss->halt_map = syscon_node_to_regmap(syscon);
+ of_node_put(syscon);
if (IS_ERR(wcss->halt_map))
return PTR_ERR(wcss->halt_map);
- wcss->halt_q6 = args.args[0];
- wcss->halt_wcss = args.args[1];
- wcss->halt_nc = args.args[2];
+ ret = of_property_read_variable_u32_array(pdev->dev.of_node,
+ "qcom,halt-regs",
+ halt_reg, 0,
+ MAX_HALT_REG);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
+ return -EINVAL;
+ }
+
+ wcss->halt_q6 = halt_reg[0];
+ wcss->halt_wcss = halt_reg[1];
+ wcss->halt_nc = halt_reg[2];
return 0;
}
@@ -543,6 +896,107 @@ static int q6v5_alloc_memory_region(stru
return 0;
}
+static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
+{
+ int ret;
+
+ wcss->xo = devm_clk_get(wcss->dev, "xo");
+ if (IS_ERR(wcss->xo)) {
+ ret = PTR_ERR(wcss->xo);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get xo clock");
+ return ret;
+ }
+
+ wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr");
+ if (IS_ERR(wcss->gcc_abhs_cbcr)) {
+ ret = PTR_ERR(wcss->gcc_abhs_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get gcc abhs clock");
+ return PTR_ERR(wcss->gcc_abhs_cbcr);
+ }
+
+ wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr");
+ if (IS_ERR(wcss->gcc_axim_cbcr)) {
+ ret = PTR_ERR(wcss->gcc_axim_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get gcc axim clock\n");
+ return PTR_ERR(wcss->gcc_axim_cbcr);
+ }
+
+ wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev,
+ "lcc_ahbfabric_cbc");
+ if (IS_ERR(wcss->ahbfabric_cbcr_clk)) {
+ ret = PTR_ERR(wcss->ahbfabric_cbcr_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get ahbfabric clock\n");
+ return PTR_ERR(wcss->ahbfabric_cbcr_clk);
+ }
+
+ wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc");
+ if (IS_ERR(wcss->lcc_csr_cbcr)) {
+ ret = PTR_ERR(wcss->lcc_csr_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get csr cbcr clk\n");
+ return PTR_ERR(wcss->lcc_csr_cbcr);
+ }
+
+ wcss->ahbs_cbcr = devm_clk_get(wcss->dev,
+ "lcc_abhs_cbc");
+ if (IS_ERR(wcss->ahbs_cbcr)) {
+ ret = PTR_ERR(wcss->ahbs_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n");
+ return PTR_ERR(wcss->ahbs_cbcr);
+ }
+
+ wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev,
+ "lcc_tcm_slave_cbc");
+ if (IS_ERR(wcss->tcm_slave_cbcr)) {
+ ret = PTR_ERR(wcss->tcm_slave_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get tcm cbcr clk\n");
+ return PTR_ERR(wcss->tcm_slave_cbcr);
+ }
+
+ wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc");
+ if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) {
+ ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get abhm cbcr clk\n");
+ return PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+ }
+
+ wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc");
+ if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) {
+ ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get axim cbcr clk\n");
+ return PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+ }
+
+ wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep");
+ if (IS_ERR(wcss->lcc_bcr_sleep)) {
+ ret = PTR_ERR(wcss->lcc_bcr_sleep);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "failed to get bcr cbcr clk\n");
+ return PTR_ERR(wcss->lcc_bcr_sleep);
+ }
+
+ return 0;
+}
+
+static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
+{
+ wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
+ if (IS_ERR(wcss->cx_supply))
+ return PTR_ERR(wcss->cx_supply);
+
+ regulator_set_load(wcss->cx_supply, 100000);
+
+ return 0;
+}
+
static int q6v5_wcss_probe(struct platform_device *pdev)
{
const struct wcss_data *desc;
@@ -554,7 +1008,7 @@ static int q6v5_wcss_probe(struct platfo
if (!desc)
return -EINVAL;
- rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops,
+ rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->firmware_name, sizeof(*wcss));
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
@@ -563,7 +1017,10 @@ static int q6v5_wcss_probe(struct platfo
wcss = rproc->priv;
wcss->dev = &pdev->dev;
- wcss->crash_reason_smem = desc->crash_reason_smem;
+ wcss->version = desc->version;
+
+ wcss->version = desc->version;
+ wcss->requires_force_stop = desc->requires_force_stop;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -573,7 +1030,17 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
- ret = q6v5_wcss_init_reset(wcss);
+ if (wcss->version == WCSS_QCS404) {
+ ret = q6v5_wcss_init_clock(wcss);
+ if (ret)
+ goto free_rproc;
+
+ ret = q6v5_wcss_init_regulator(wcss);
+ if (ret)
+ goto free_rproc;
+ }
+
+ ret = q6v5_wcss_init_reset(wcss, desc);
if (ret)
goto free_rproc;
@@ -585,6 +1052,11 @@ static int q6v5_wcss_probe(struct platfo
qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
+ if (desc->ssctl_id)
+ wcss->sysmon = qcom_add_sysmon_subdev(rproc,
+ desc->sysmon_name,
+ desc->ssctl_id);
+
ret = rproc_add(rproc);
if (ret)
goto free_rproc;
@@ -612,10 +1084,28 @@ static int q6v5_wcss_remove(struct platf
static const struct wcss_data wcss_ipq8074_res_init = {
.firmware_name = "IPQ8074/q6_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
+ .aon_reset_required = true,
+ .wcss_q6_reset_required = true,
+ .ops = &q6v5_wcss_ipq8074_ops,
+ .requires_force_stop = true,
+};
+
+static const struct wcss_data wcss_qcs404_res_init = {
+ .crash_reason_smem = WCSS_CRASH_REASON,
+ .firmware_name = "wcnss.mdt",
+ .version = WCSS_QCS404,
+ .aon_reset_required = false,
+ .wcss_q6_reset_required = false,
+ .ssr_name = "mpss",
+ .sysmon_name = "wcnss",
+ .ssctl_id = 0x12,
+ .ops = &q6v5_wcss_qcs404_ops,
+ .requires_force_stop = false,
};
static const struct of_device_id q6v5_wcss_of_match[] = {
{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
+ { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
{ },
};
MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);

43
target/linux/ipq807x/patches-5.10/005-v5.13-remoteproc-qcom-wcss-explicitly-request-exclusive-re.patch
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@ -1,43 +0,0 @@
From 7b230496f6b45e840bc7b13e7df2a8676bab9230 Mon Sep 17 00:00:00 2001
From: Govind Singh <govinds@codeaurora.org>
Date: Fri, 29 Jan 2021 00:18:15 +0530
Subject: [PATCH 04/16] remoteproc: qcom: wcss: explicitly request exclusive
reset control
Use request exclusive reset control for wcss reset controls.
Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1611859695-11824-5-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -788,21 +788,21 @@ static int q6v5_wcss_init_reset(struct q
struct device *dev = wcss->dev;
if (desc->aon_reset_required) {
- wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
+ wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset");
if (IS_ERR(wcss->wcss_aon_reset)) {
dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n");
return PTR_ERR(wcss->wcss_aon_reset);
}
}
- wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
+ wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset");
if (IS_ERR(wcss->wcss_reset)) {
dev_err(wcss->dev, "unable to acquire wcss_reset\n");
return PTR_ERR(wcss->wcss_reset);
}
if (desc->wcss_q6_reset_required) {
- wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
+ wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset");
if (IS_ERR(wcss->wcss_q6_reset)) {
dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
return PTR_ERR(wcss->wcss_q6_reset);

32
target/linux/ipq807x/patches-5.10/006-v5.13-remoteproc-qcom-wcss-Fix-return-value-check-in-q6v5_.patch
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@ -1,32 +0,0 @@
From 5b8b0967576f04d2ee3ea36310c078a3d50e7339 Mon Sep 17 00:00:00 2001
From: Wei Yongjun <weiyongjun1@huawei.com>
Date: Fri, 19 Mar 2021 09:41:00 +0000
Subject: [PATCH 05/16] remoteproc: qcom: wcss: Fix return value check in
q6v5_wcss_init_mmio()
In case of error, the function devm_ioremap() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20210319094100.4185044-1-weiyongjun1@huawei.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -829,8 +829,8 @@ static int q6v5_wcss_init_mmio(struct q6
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
- if (IS_ERR(wcss->reg_base))
- return PTR_ERR(wcss->reg_base);
+ if (!wcss->reg_base)
+ return -ENOMEM;
if (wcss->version == WCSS_IPQ8074) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");

32
target/linux/ipq807x/patches-5.10/007-v5.13-remoteproc-qcom-wcss-Fix-wrong-pointer-passed-to-PTR.patch
View File

@ -1,32 +0,0 @@
From 6a52dbbde0e741e84f217cf762233589cc3efd13 Mon Sep 17 00:00:00 2001
From: Wei Yongjun <weiyongjun1@huawei.com>
Date: Fri, 26 Mar 2021 02:47:41 +0000
Subject: [PATCH 06/16] remoteproc: qcom: wcss: Fix wrong pointer passed to
PTR_ERR()
PTR_ERR should access the value just tested by IS_ERR, otherwise
the wrong error code will be returned.
This commit fix it by return 'ret' directly.
Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: 0af65b9b915e ("remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Link: https://lore.kernel.org/r/20210326024741.841267-1-weiyongjun1@huawei.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -972,7 +972,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get axim cbcr clk\n");
- return PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+ return ret;
}
wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep");

89
target/linux/ipq807x/patches-5.10/008-v5.13-remoteproc-qcom-wcss-Remove-unnecessary-PTR_ERR.patch
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@ -1,89 +0,0 @@
From 00f24490f498db0ea67715a4dfe6c4a6ca11c6a0 Mon Sep 17 00:00:00 2001
From: Junlin Yang <yangjunlin@yulong.com>
Date: Thu, 8 Apr 2021 22:33:22 +0800
Subject: [PATCH 07/16] remoteproc: qcom: wcss: Remove unnecessary PTR_ERR()
Remove unnecessary PTR_ERR(), it has been assigned to ret before,
so return ret directly.
Signed-off-by: Junlin Yang <yangjunlin@yulong.com>
Link: https://lore.kernel.org/r/20210408143322.1647-1-angkery@163.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -913,7 +913,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->gcc_abhs_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get gcc abhs clock");
- return PTR_ERR(wcss->gcc_abhs_cbcr);
+ return ret;
}
wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr");
@@ -921,7 +921,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->gcc_axim_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get gcc axim clock\n");
- return PTR_ERR(wcss->gcc_axim_cbcr);
+ return ret;
}
wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev,
@@ -930,7 +930,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->ahbfabric_cbcr_clk);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get ahbfabric clock\n");
- return PTR_ERR(wcss->ahbfabric_cbcr_clk);
+ return ret;
}
wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc");
@@ -938,7 +938,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->lcc_csr_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get csr cbcr clk\n");
- return PTR_ERR(wcss->lcc_csr_cbcr);
+ return ret;
}
wcss->ahbs_cbcr = devm_clk_get(wcss->dev,
@@ -947,7 +947,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->ahbs_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n");
- return PTR_ERR(wcss->ahbs_cbcr);
+ return ret;
}
wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev,
@@ -956,7 +956,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->tcm_slave_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get tcm cbcr clk\n");
- return PTR_ERR(wcss->tcm_slave_cbcr);
+ return ret;
}
wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc");
@@ -964,7 +964,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get abhm cbcr clk\n");
- return PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+ return ret;
}
wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc");
@@ -980,7 +980,7 @@ static int q6v5_wcss_init_clock(struct q
ret = PTR_ERR(wcss->lcc_bcr_sleep);
if (ret != -EPROBE_DEFER)
dev_err(wcss->dev, "failed to get bcr cbcr clk\n");
- return PTR_ERR(wcss->lcc_bcr_sleep);
+ return ret;
}
return 0;

217
target/linux/ipq807x/patches-5.10/009-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch
View File

@ -1,217 +0,0 @@
From 803eb124e1a64e42888542c3444bfe6dac412c7f Mon Sep 17 00:00:00 2001
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Mon, 4 Jan 2021 09:41:35 +0530
Subject: mtd: parsers: Add Qcom SMEM parser
NAND based Qualcomm platforms have the partition table populated in the
Shared Memory (SMEM). Hence, add a parser for parsing the partitions
from it.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadhasivam@linaro.org
---
drivers/mtd/parsers/Kconfig | 8 ++
drivers/mtd/parsers/Makefile | 1 +
drivers/mtd/parsers/qcomsmempart.c | 170 +++++++++++++++++++++++++++++++++++++
3 files changed, 179 insertions(+)
create mode 100644 drivers/mtd/parsers/qcomsmempart.c
--- a/drivers/mtd/parsers/Kconfig
+++ b/drivers/mtd/parsers/Kconfig
@@ -205,6 +205,14 @@ config MTD_SERCOMM_PARTS
offsets, which may differ from device to device depending on the
number and location of bad blocks on NAND.
+config MTD_QCOMSMEM_PARTS
+ tristate "Qualcomm SMEM NAND flash partition parser"
+ depends on MTD_NAND_QCOM || COMPILE_TEST
+ depends on QCOM_SMEM
+ help
+ This provides support for parsing partitions from Shared Memory (SMEM)
+ for NAND flash on Qualcomm platforms.
+
config MTD_ROUTERBOOT_PARTS
tristate "RouterBoot flash partition parser"
depends on MTD && OF
--- a/drivers/mtd/parsers/Makefile
+++ b/drivers/mtd/parsers/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_MTD_PARSER_TRX) += parser_
obj-$(CONFIG_MTD_SERCOMM_PARTS) += scpart.o
obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o
obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
+obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o
obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o
--- /dev/null
+++ b/drivers/mtd/parsers/qcomsmempart.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm SMEM NAND flash partition parser
+ *
+ * Copyright (C) 2020, Linaro Ltd.
+ */
+
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/slab.h>
+#include <linux/soc/qcom/smem.h>
+
+#define SMEM_AARM_PARTITION_TABLE 9
+#define SMEM_APPS 0
+
+#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa
+#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb
+#define SMEM_FLASH_PTABLE_V3 3
+#define SMEM_FLASH_PTABLE_V4 4
+#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16
+#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48
+#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32))
+#define SMEM_FLASH_PTABLE_NAME_SIZE 16
+
+/**
+ * struct smem_flash_pentry - SMEM Flash partition entry
+ * @name: Name of the partition
+ * @offset: Offset in blocks
+ * @length: Length of the partition in blocks
+ * @attr: Flags for this partition
+ */
+struct smem_flash_pentry {
+ char name[SMEM_FLASH_PTABLE_NAME_SIZE];
+ __le32 offset;
+ __le32 length;
+ u8 attr;
+} __packed __aligned(4);
+
+/**
+ * struct smem_flash_ptable - SMEM Flash partition table
+ * @magic1: Partition table Magic 1
+ * @magic2: Partition table Magic 2
+ * @version: Partition table version
+ * @numparts: Number of partitions in this ptable
+ * @pentry: Flash partition entries belonging to this ptable
+ */
+struct smem_flash_ptable {
+ __le32 magic1;
+ __le32 magic2;
+ __le32 version;
+ __le32 numparts;
+ struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4];
+} __packed __aligned(4);
+
+static int parse_qcomsmem_part(struct mtd_info *mtd,
+ const struct mtd_partition **pparts,
+ struct mtd_part_parser_data *data)
+{
+ struct smem_flash_pentry *pentry;
+ struct smem_flash_ptable *ptable;
+ size_t len = SMEM_FLASH_PTABLE_HDR_LEN;
+ struct mtd_partition *parts;
+ int ret, i, numparts;
+ char *name, *c;
+
+ pr_debug("Parsing partition table info from SMEM\n");
+ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
+ if (IS_ERR(ptable)) {
+ pr_err("Error reading partition table header\n");
+ return PTR_ERR(ptable);
+ }
+
+ /* Verify ptable magic */
+ if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 ||
+ le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) {
+ pr_err("Partition table magic verification failed\n");
+ return -EINVAL;
+ }
+
+ /* Ensure that # of partitions is less than the max we have allocated */
+ numparts = le32_to_cpu(ptable->numparts);
+ if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) {
+ pr_err("Partition numbers exceed the max limit\n");
+ return -EINVAL;
+ }
+
+ /* Find out length of partition data based on table version */
+ if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) {
+ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 *
+ sizeof(struct smem_flash_pentry);
+ } else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) {
+ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 *
+ sizeof(struct smem_flash_pentry);
+ } else {
+ pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version));
+ return -EINVAL;
+ }
+
+ /*
+ * Now that the partition table header has been parsed, verified
+ * and the length of the partition table calculated, read the
+ * complete partition table
+ */
+ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);
+ if (IS_ERR_OR_NULL(ptable)) {
+ pr_err("Error reading partition table\n");
+ return PTR_ERR(ptable);
+ }
+
+ parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL);
+ if (!parts)
+ return -ENOMEM;
+
+ for (i = 0; i < numparts; i++) {
+ pentry = &ptable->pentry[i];
+ if (pentry->name[0] == '\0')
+ continue;
+
+ name = kstrdup(pentry->name, GFP_KERNEL);
+ if (!name) {
+ ret = -ENOMEM;
+ goto out_free_parts;
+ }
+
+ /* Convert name to lower case */
+ for (c = name; *c != '\0'; c++)
+ *c = tolower(*c);
+
+ parts[i].name = name;
+ parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize;
+ parts[i].mask_flags = pentry->attr;
+ parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize;
+ pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n",
+ i, pentry->name, le32_to_cpu(pentry->offset),
+ le32_to_cpu(pentry->length), pentry->attr);
+ }
+
+ pr_debug("SMEM partition table found: ver: %d len: %d\n",
+ le32_to_cpu(ptable->version), numparts);
+ *pparts = parts;
+
+ return numparts;
+
+out_free_parts:
+ while (--i >= 0)
+ kfree(parts[i].name);
+ kfree(parts);
+ *pparts = NULL;
+
+ return ret;
+}
+
+static const struct of_device_id qcomsmem_of_match_table[] = {
+ { .compatible = "qcom,smem-part" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table);
+
+static struct mtd_part_parser mtd_parser_qcomsmem = {
+ .parse_fn = parse_qcomsmem_part,
+ .name = "qcomsmem",
+ .of_match_table = qcomsmem_of_match_table,
+};
+module_mtd_part_parser(mtd_parser_qcomsmem);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
+MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser");

120
target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch
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@ -1,120 +0,0 @@
From 80b960829a85e555b96bfd4e31f31b3db3e8f5da Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Thu, 5 Nov 2020 15:11:50 -0600
Subject: [PATCH 1/5] PCI: dwc: Drop the .set_num_vectors() host op
There's no reason for the .set_num_vectors() host op. Drivers needing a
non-default value can just initialize pcie_port.num_vectors directly.
Link: https://lore.kernel.org/r/20201105211159.1814485-8-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org
---
.../pci/controller/dwc/pcie-designware-host.c | 19 ++++---------------
.../pci/controller/dwc/pcie-designware-plat.c | 7 +------
drivers/pci/controller/dwc/pcie-designware.h | 1 -
drivers/pci/controller/dwc/pcie-tegra194.c | 7 +------
4 files changed, 6 insertions(+), 28 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -358,22 +358,11 @@ int dw_pcie_host_init(struct pcie_port *
pci->link_gen = of_pci_get_max_link_speed(np);
if (pci_msi_enabled()) {
- /*
- * If a specific SoC driver needs to change the
- * default number of vectors, it needs to implement
- * the set_num_vectors callback.
- */
- if (!pp->ops->set_num_vectors) {
+ if (!pp->num_vectors) {
pp->num_vectors = MSI_DEF_NUM_VECTORS;
- } else {
- pp->ops->set_num_vectors(pp);
-
- if (pp->num_vectors > MAX_MSI_IRQS ||
- pp->num_vectors == 0) {
- dev_err(dev,
- "Invalid number of vectors\n");
- return -EINVAL;
- }
+ } else if (pp->num_vectors > MAX_MSI_IRQS) {
+ dev_err(dev, "Invalid number of vectors\n");
+ return -EINVAL;
}
if (!pp->ops->msi_host_init) {
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -44,14 +44,8 @@ static int dw_plat_pcie_host_init(struct
return 0;
}
-static void dw_plat_set_num_vectors(struct pcie_port *pp)
-{
- pp->num_vectors = MAX_MSI_IRQS;
-}
-
static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
.host_init = dw_plat_pcie_host_init,
- .set_num_vectors = dw_plat_set_num_vectors,
};
static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
@@ -128,6 +122,7 @@ static int dw_plat_add_pcie_port(struct
return pp->msi_irq;
}
+ pp->num_vectors = MAX_MSI_IRQS;
pp->ops = &dw_plat_pcie_host_ops;
ret = dw_pcie_host_init(pp);
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -174,7 +174,6 @@ enum dw_pcie_device_mode {
struct dw_pcie_host_ops {
int (*host_init)(struct pcie_port *pp);
- void (*set_num_vectors)(struct pcie_port *pp);
int (*msi_host_init)(struct pcie_port *pp);
};
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -996,11 +996,6 @@ static int tegra_pcie_dw_link_up(struct
return !!(val & PCI_EXP_LNKSTA_DLLLA);
}
-static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp)
-{
- pp->num_vectors = MAX_MSI_IRQS;
-}
-
static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
{
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
@@ -1025,7 +1020,6 @@ static const struct dw_pcie_ops tegra_dw
static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
.host_init = tegra_pcie_dw_host_init,
- .set_num_vectors = tegra_pcie_set_msi_vec_num,
};
static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
@@ -2010,6 +2004,7 @@ static int tegra_pcie_dw_probe(struct pl
pci->n_fts[1] = FTS_VAL;
pp = &pci->pp;
+ pp->num_vectors = MAX_MSI_IRQS;
pcie->dev = &pdev->dev;
pcie->mode = (enum dw_pcie_device_mode)data->mode;

288
target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch
View File

@ -1,288 +0,0 @@
From 264b6fd7baa53bfaef2a6d41067b9568dff7163a Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Thu, 5 Nov 2020 15:11:51 -0600
Subject: [PATCH 2/5] PCI: dwc: Move MSI interrupt setup into DWC common code
Platforms using the built-in DWC MSI controller all have a dedicated
interrupt with "msi" name or at index 0, so let's move setting up the
interrupt to the common DWC code.
spear13xx and dra7xx are the 2 oddballs with muxed interrupts, so
we need to prevent configuring the MSI interrupt by setting msi_irq
to negative.
Link: https://lore.kernel.org/r/20201105211159.1814485-9-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Yue Wang <yue.wang@Amlogic.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@axis.com
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
---
drivers/pci/controller/dwc/pci-dra7xx.c | 3 +++
drivers/pci/controller/dwc/pci-exynos.c | 6 -----
drivers/pci/controller/dwc/pci-imx6.c | 6 -----
drivers/pci/controller/dwc/pci-meson.c | 6 -----
drivers/pci/controller/dwc/pcie-artpec6.c | 6 -----
.../pci/controller/dwc/pcie-designware-host.c | 11 +++++++++-
.../pci/controller/dwc/pcie-designware-plat.c | 6 -----
drivers/pci/controller/dwc/pcie-histb.c | 6 -----
drivers/pci/controller/dwc/pcie-kirin.c | 22 -------------------
drivers/pci/controller/dwc/pcie-qcom.c | 8 -------
drivers/pci/controller/dwc/pcie-spear13xx.c | 1 +
drivers/pci/controller/dwc/pcie-tegra194.c | 8 -------
drivers/pci/controller/dwc/pcie-uniphier.c | 6 -----
13 files changed, 14 insertions(+), 81 deletions(-)
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -622,6 +622,9 @@ static int __init dra7xx_add_pcie_port(s
if (pp->irq < 0)
return pp->irq;
+ /* MSI IRQ is muxed */
+ pp->msi_irq = -ENODEV;
+
ret = dra7xx_pcie_init_irq_domain(pp);
if (ret < 0)
return ret;
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -415,12 +415,6 @@ static int __init exynos_add_pcie_port(s
return ret;
}
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq(pdev, 0);
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
pp->ops = &exynos_pcie_host_ops;
ret = dw_pcie_host_init(pp);
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -858,12 +858,6 @@ static int imx6_add_pcie_port(struct imx
struct device *dev = &pdev->dev;
int ret;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq_byname(pdev, "msi");
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
pp->ops = &imx6_pcie_host_ops;
ret = dw_pcie_host_init(pp);
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -405,12 +405,6 @@ static int meson_add_pcie_port(struct me
struct device *dev = &pdev->dev;
int ret;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq(pdev, 0);
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
pp->ops = &meson_pcie_host_ops;
ret = dw_pcie_host_init(pp);
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -348,12 +348,6 @@ static int artpec6_add_pcie_port(struct
struct device *dev = pci->dev;
int ret;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq_byname(pdev, "msi");
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
pp->ops = &artpec6_pcie_host_ops;
ret = dw_pcie_host_init(pp);
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -366,13 +366,22 @@ int dw_pcie_host_init(struct pcie_port *
}
if (!pp->ops->msi_host_init) {
+ if (!pp->msi_irq) {
+ pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
+ if (pp->msi_irq < 0) {
+ pp->msi_irq = platform_get_irq(pdev, 0);
+ if (pp->msi_irq < 0)
+ return pp->msi_irq;
+ }
+ }
+
pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
ret = dw_pcie_allocate_domains(pp);
if (ret)
return ret;
- if (pp->msi_irq)
+ if (pp->msi_irq > 0)
irq_set_chained_handler_and_data(pp->msi_irq,
dw_chained_msi_isr,
pp);
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -116,12 +116,6 @@ static int dw_plat_add_pcie_port(struct
if (pp->irq < 0)
return pp->irq;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq(pdev, 0);
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
pp->num_vectors = MAX_MSI_IRQS;
pp->ops = &dw_plat_pcie_host_ops;
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -400,12 +400,6 @@ static int histb_pcie_probe(struct platf
return PTR_ERR(hipcie->bus_reset);
}
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq_byname(pdev, "msi");
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
hipcie->phy = devm_phy_get(dev, "phy");
if (IS_ERR(hipcie->phy)) {
dev_info(dev, "no pcie-phy found\n");
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -444,31 +444,9 @@ static const struct dw_pcie_host_ops kir
.host_init = kirin_pcie_host_init,
};
-static int kirin_pcie_add_msi(struct dw_pcie *pci,
- struct platform_device *pdev)
-{
- int irq;
-
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
-
- pci->pp.msi_irq = irq;
- }
-
- return 0;
-}
-
static int kirin_add_pcie_port(struct dw_pcie *pci,
struct platform_device *pdev)
{
- int ret;
-
- ret = kirin_pcie_add_msi(pci, pdev);
- if (ret)
- return ret;
-
pci->pp.ops = &kirin_pcie_host_ops;
return dw_pcie_host_init(&pci->pp);
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1424,14 +1424,6 @@ static int qcom_pcie_probe(struct platfo
pp->ops = &qcom_pcie_dw_ops;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq_byname(pdev, "msi");
- if (pp->msi_irq < 0) {
- ret = pp->msi_irq;
- goto err_pm_runtime_put;
- }
- }
-
ret = phy_init(pcie->phy);
if (ret)
goto err_pm_runtime_put;
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -183,6 +183,7 @@ static int spear13xx_add_pcie_port(struc
}
pp->ops = &spear13xx_pcie_host_ops;
+ pp->msi_irq = -ENODEV;
ret = dw_pcie_host_init(pp);
if (ret) {
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1560,14 +1560,6 @@ static int tegra_pcie_config_rp(struct t
char *name;
int ret;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = of_irq_get_byname(dev->of_node, "msi");
- if (!pp->msi_irq) {
- dev_err(dev, "Failed to get MSI interrupt\n");
- return -ENODEV;
- }
- }
-
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -335,12 +335,6 @@ static int uniphier_add_pcie_port(struct
pp->ops = &uniphier_pcie_host_ops;
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- pp->msi_irq = platform_get_irq_byname(pdev, "msi");
- if (pp->msi_irq < 0)
- return pp->msi_irq;
- }
-
ret = dw_pcie_host_init(pp);
if (ret) {
dev_err(dev, "Failed to initialize host (%d)\n", ret);

199
target/linux/ipq807x/patches-5.10/012-v5.11-PCI-dwc-Rework-MSI-initialization.patch
View File

@ -1,199 +0,0 @@
From ed016f820e3f1b980dfe0ef6137069e008f99109 Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Thu, 5 Nov 2020 15:11:52 -0600
Subject: [PATCH 3/5] PCI: dwc: Rework MSI initialization
There are 3 possible MSI implementations for the DWC host. The first is
using the built-in DWC MSI controller. The 2nd is a custom MSI
controller as part of the PCI host (keystone only). The 3rd is an
external MSI controller (typically GICv3 ITS). Currently, the last 2
are distinguished with a .msi_host_init() hook with the 3rd option using
an empty function. However we can detect the 3rd case with the presence
of 'msi-parent' or 'msi-map' properties, so let's do that instead and
remove the empty functions.
Link: https://lore.kernel.org/r/20201105211159.1814485-10-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Minghuan Lian <minghuan.Lian@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: linuxppc-dev@lists.ozlabs.org
---
drivers/pci/controller/dwc/pci-keystone.c | 9 -------
drivers/pci/controller/dwc/pci-layerscape.c | 25 -------------------
.../pci/controller/dwc/pcie-designware-host.c | 20 +++++++++------
drivers/pci/controller/dwc/pcie-designware.h | 1 +
drivers/pci/controller/dwc/pcie-intel-gw.c | 9 -------
5 files changed, 13 insertions(+), 51 deletions(-)
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -272,14 +272,6 @@ static void ks_pcie_handle_legacy_irq(st
ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
}
-/*
- * Dummy function so that DW core doesn't configure MSI
- */
-static int ks_pcie_am654_msi_host_init(struct pcie_port *pp)
-{
- return 0;
-}
-
static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
{
ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
@@ -855,7 +847,6 @@ static const struct dw_pcie_host_ops ks_
static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = {
.host_init = ks_pcie_host_init,
- .msi_host_init = ks_pcie_am654_msi_host_init,
};
static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -182,37 +182,12 @@ static int ls1021_pcie_host_init(struct
return ls_pcie_host_init(pp);
}
-static int ls_pcie_msi_host_init(struct pcie_port *pp)
-{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct device *dev = pci->dev;
- struct device_node *np = dev->of_node;
- struct device_node *msi_node;
-
- /*
- * The MSI domain is set by the generic of_msi_configure(). This
- * .msi_host_init() function keeps us from doing the default MSI
- * domain setup in dw_pcie_host_init() and also enforces the
- * requirement that "msi-parent" exists.
- */
- msi_node = of_parse_phandle(np, "msi-parent", 0);
- if (!msi_node) {
- dev_err(dev, "failed to find msi-parent\n");
- return -EINVAL;
- }
-
- of_node_put(msi_node);
- return 0;
-}
-
static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
.host_init = ls1021_pcie_host_init,
- .msi_host_init = ls_pcie_msi_host_init,
};
static const struct dw_pcie_host_ops ls_pcie_host_ops = {
.host_init = ls_pcie_host_init,
- .msi_host_init = ls_pcie_msi_host_init,
};
static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -358,6 +358,10 @@ int dw_pcie_host_init(struct pcie_port *
pci->link_gen = of_pci_get_max_link_speed(np);
if (pci_msi_enabled()) {
+ pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
+ of_property_read_bool(np, "msi-parent") ||
+ of_property_read_bool(np, "msi-map"));
+
if (!pp->num_vectors) {
pp->num_vectors = MSI_DEF_NUM_VECTORS;
} else if (pp->num_vectors > MAX_MSI_IRQS) {
@@ -365,7 +369,11 @@ int dw_pcie_host_init(struct pcie_port *
return -EINVAL;
}
- if (!pp->ops->msi_host_init) {
+ if (pp->ops->msi_host_init) {
+ ret = pp->ops->msi_host_init(pp);
+ if (ret < 0)
+ return ret;
+ } else if (pp->has_msi_ctrl) {
if (!pp->msi_irq) {
pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
if (pp->msi_irq < 0) {
@@ -396,10 +404,6 @@ int dw_pcie_host_init(struct pcie_port *
pp->msi_data = 0;
goto err_free_msi;
}
- } else {
- ret = pp->ops->msi_host_init(pp);
- if (ret < 0)
- return ret;
}
}
@@ -420,7 +424,7 @@ int dw_pcie_host_init(struct pcie_port *
return 0;
err_free_msi:
- if (pci_msi_enabled() && !pp->ops->msi_host_init)
+ if (pp->has_msi_ctrl)
dw_pcie_free_msi(pp);
return ret;
}
@@ -430,7 +434,7 @@ void dw_pcie_host_deinit(struct pcie_por
{
pci_stop_root_bus(pp->bridge->bus);
pci_remove_root_bus(pp->bridge->bus);
- if (pci_msi_enabled() && !pp->ops->msi_host_init)
+ if (pp->has_msi_ctrl)
dw_pcie_free_msi(pp);
}
EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
@@ -541,7 +545,7 @@ void dw_pcie_setup_rc(struct pcie_port *
dw_pcie_setup(pci);
- if (pci_msi_enabled() && !pp->ops->msi_host_init) {
+ if (pp->has_msi_ctrl) {
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
/* Initialize IRQ Status array */
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -178,6 +178,7 @@ struct dw_pcie_host_ops {
};
struct pcie_port {
+ bool has_msi_ctrl:1;
u64 cfg0_base;
void __iomem *va_cfg0_base;
u32 cfg0_size;
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -403,14 +403,6 @@ static int intel_pcie_rc_init(struct pci
return intel_pcie_host_setup(lpp);
}
-/*
- * Dummy function so that DW core doesn't configure MSI
- */
-static int intel_pcie_msi_init(struct pcie_port *pp)
-{
- return 0;
-}
-
static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)
{
return cpu_addr + BUS_IATU_OFFSET;
@@ -422,7 +414,6 @@ static const struct dw_pcie_ops intel_pc
static const struct dw_pcie_host_ops intel_pcie_dw_ops = {
.host_init = intel_pcie_rc_init,
- .msi_host_init = intel_pcie_msi_init,
};
static const struct intel_pcie_soc pcie_data = {

603
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View File

@ -1,603 +0,0 @@
From 533bee2aeda70c212a3fb5547d5beb6406e3ccf7 Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Thu, 5 Nov 2020 15:11:53 -0600
Subject: [PATCH 4/5] PCI: dwc: Move link handling into common code
All the DWC drivers do link setup and checks at roughly the same time.
Let's use the existing .start_link() hook (currently only used in EP
mode) and move the link handling to the core code.
The behavior for a link down was inconsistent as some drivers would fail
probe in that case while others succeed. Let's standardize this to
succeed as there are usecases where devices (and the link) appear later
even without hotplug. For example, a reconfigured FPGA device.
Link: https://lore.kernel.org/r/20201105211159.1814485-11-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Yue Wang <yue.wang@Amlogic.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@axis.com
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 -
drivers/pci/controller/dwc/pci-exynos.c | 41 +++++++----------
drivers/pci/controller/dwc/pci-imx6.c | 9 ++--
drivers/pci/controller/dwc/pci-keystone.c | 9 ----
drivers/pci/controller/dwc/pci-meson.c | 24 ++++------
drivers/pci/controller/dwc/pcie-armada8k.c | 39 +++++++---------
drivers/pci/controller/dwc/pcie-artpec6.c | 2 -
.../pci/controller/dwc/pcie-designware-host.c | 9 ++++
.../pci/controller/dwc/pcie-designware-plat.c | 3 --
drivers/pci/controller/dwc/pcie-histb.c | 34 +++++++-------
drivers/pci/controller/dwc/pcie-kirin.c | 23 ++--------
drivers/pci/controller/dwc/pcie-qcom.c | 19 ++------
drivers/pci/controller/dwc/pcie-spear13xx.c | 46 ++++++++-----------
drivers/pci/controller/dwc/pcie-tegra194.c | 1 -
drivers/pci/controller/dwc/pcie-uniphier.c | 13 ++----
15 files changed, 103 insertions(+), 171 deletions(-)
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -183,8 +183,6 @@ static int dra7xx_pcie_host_init(struct
dw_pcie_setup_rc(pp);
- dra7xx_pcie_establish_link(pci);
- dw_pcie_wait_for_link(pci);
dw_pcie_msi_init(pp);
dra7xx_pcie_enable_interrupts(dra7xx);
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -229,30 +229,9 @@ static void exynos_pcie_assert_reset(str
GPIOF_OUT_INIT_HIGH, "RESET");
}
-static int exynos_pcie_establish_link(struct exynos_pcie *ep)
+static int exynos_pcie_start_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = ep->pci;
- struct pcie_port *pp = &pci->pp;
- struct device *dev = pci->dev;
-
- if (dw_pcie_link_up(pci)) {
- dev_err(dev, "Link already up\n");
- return 0;
- }
-
- exynos_pcie_assert_core_reset(ep);
-
- phy_reset(ep->phy);
-
- exynos_pcie_writel(ep->mem_res->elbi_base, 1,
- PCIE_PWR_RESET);
-
- phy_power_on(ep->phy);
- phy_init(ep->phy);
-
- exynos_pcie_deassert_core_reset(ep);
- dw_pcie_setup_rc(pp);
- exynos_pcie_assert_reset(ep);
+ struct exynos_pcie *ep = to_exynos_pcie(pci);
/* assert LTSSM enable */
exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
@@ -386,7 +365,20 @@ static int exynos_pcie_host_init(struct
pp->bridge->ops = &exynos_pci_ops;
- exynos_pcie_establish_link(ep);
+ exynos_pcie_assert_core_reset(ep);
+
+ phy_reset(ep->phy);
+
+ exynos_pcie_writel(ep->mem_res->elbi_base, 1,
+ PCIE_PWR_RESET);
+
+ phy_power_on(ep->phy);
+ phy_init(ep->phy);
+
+ exynos_pcie_deassert_core_reset(ep);
+ dw_pcie_setup_rc(pp);
+ exynos_pcie_assert_reset(ep);
+
exynos_pcie_enable_interrupts(ep);
return 0;
@@ -430,6 +422,7 @@ static const struct dw_pcie_ops dw_pcie_
.read_dbi = exynos_pcie_read_dbi,
.write_dbi = exynos_pcie_write_dbi,
.link_up = exynos_pcie_link_up,
+ .start_link = exynos_pcie_start_link,
};
static int __init exynos_pcie_probe(struct platform_device *pdev)
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -750,9 +750,9 @@ static void imx6_pcie_ltssm_enable(struc
}
}
-static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
+static int imx6_pcie_start_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = imx6_pcie->pci;
+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
struct device *dev = pci->dev;
u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
u32 tmp;
@@ -840,7 +840,6 @@ static int imx6_pcie_host_init(struct pc
imx6_pcie_deassert_core_reset(imx6_pcie);
imx6_setup_phy_mpll(imx6_pcie);
dw_pcie_setup_rc(pp);
- imx6_pcie_establish_link(imx6_pcie);
dw_pcie_msi_init(pp);
return 0;
@@ -870,7 +869,7 @@ static int imx6_add_pcie_port(struct imx
}
static const struct dw_pcie_ops dw_pcie_ops = {
- /* No special ops needed, but pcie-designware still expects this struct */
+ .start_link = imx6_pcie_start_link,
};
#ifdef CONFIG_PM_SLEEP
@@ -979,7 +978,7 @@ static int imx6_pcie_resume_noirq(struct
imx6_pcie_deassert_core_reset(imx6_pcie);
dw_pcie_setup_rc(pp);
- ret = imx6_pcie_establish_link(imx6_pcie);
+ ret = imx6_pcie_start_link(imx6_pcie->pci);
if (ret < 0)
dev_info(dev, "pcie link is down after resume.\n");
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -511,14 +511,8 @@ static void ks_pcie_stop_link(struct dw_
static int ks_pcie_start_link(struct dw_pcie *pci)
{
struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
- struct device *dev = pci->dev;
u32 val;
- if (dw_pcie_link_up(pci)) {
- dev_dbg(dev, "link is already up\n");
- return 0;
- }
-
/* Initiate Link Training */
val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
@@ -834,9 +828,6 @@ static int __init ks_pcie_host_init(stru
"Asynchronous external abort");
#endif
- ks_pcie_start_link(pci);
- dw_pcie_wait_for_link(pci);
-
return 0;
}
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -231,7 +231,7 @@ static void meson_pcie_assert_reset(stru
gpiod_set_value_cansleep(mp->reset_gpio, 0);
}
-static void meson_pcie_init_dw(struct meson_pcie *mp)
+static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
{
u32 val;
@@ -289,20 +289,14 @@ static void meson_set_max_rd_req_size(st
dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
}
-static int meson_pcie_establish_link(struct meson_pcie *mp)
+static int meson_pcie_start_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = &mp->pci;
- struct pcie_port *pp = &pci->pp;
-
- meson_pcie_init_dw(mp);
- meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
- meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
-
- dw_pcie_setup_rc(pp);
+ struct meson_pcie *mp = to_meson_pcie(pci);
+ meson_pcie_ltssm_enable(mp);
meson_pcie_assert_reset(mp);
- return dw_pcie_wait_for_link(pci);
+ return 0;
}
static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
@@ -380,14 +374,13 @@ static int meson_pcie_host_init(struct p
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct meson_pcie *mp = to_meson_pcie(pci);
- int ret;
pp->bridge->ops = &meson_pci_ops;
- ret = meson_pcie_establish_link(mp);
- if (ret)
- return ret;
+ meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
+ meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
+ dw_pcie_setup_rc(pp);
dw_pcie_msi_init(pp);
return 0;
@@ -418,6 +411,7 @@ static int meson_add_pcie_port(struct me
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = meson_pcie_link_up,
+ .start_link = meson_pcie_start_link,
};
static int meson_pcie_probe(struct platform_device *pdev)
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -154,10 +154,24 @@ static int armada8k_pcie_link_up(struct
return 0;
}
-static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
+static int armada8k_pcie_start_link(struct dw_pcie *pci)
+{
+ u32 reg;
+
+ /* Start LTSSM */
+ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
+ reg |= PCIE_APP_LTSSM_EN;
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
+
+ return 0;
+}
+
+static int armada8k_pcie_host_init(struct pcie_port *pp)
{
- struct dw_pcie *pci = pcie->pci;
u32 reg;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+
+ dw_pcie_setup_rc(pp);
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
@@ -193,26 +207,6 @@ static void armada8k_pcie_establish_link
PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
- if (!dw_pcie_link_up(pci)) {
- /* Configuration done. Start LTSSM */
- reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
- reg |= PCIE_APP_LTSSM_EN;
- dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
- }
-
- /* Wait until the link becomes active again */
- if (dw_pcie_wait_for_link(pci))
- dev_err(pci->dev, "Link not up after reconfiguration\n");
-}
-
-static int armada8k_pcie_host_init(struct pcie_port *pp)
-{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
-
- dw_pcie_setup_rc(pp);
- armada8k_pcie_establish_link(pcie);
-
return 0;
}
@@ -269,6 +263,7 @@ static int armada8k_add_pcie_port(struct
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = armada8k_pcie_link_up,
+ .start_link = armada8k_pcie_start_link,
};
static int armada8k_pcie_probe(struct platform_device *pdev)
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -329,8 +329,6 @@ static int artpec6_pcie_host_init(struct
artpec6_pcie_deassert_core_reset(artpec6_pcie);
artpec6_pcie_wait_for_phy(artpec6_pcie);
dw_pcie_setup_rc(pp);
- artpec6_pcie_establish_link(pci);
- dw_pcie_wait_for_link(pci);
dw_pcie_msi_init(pp);
return 0;
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -417,6 +417,15 @@ int dw_pcie_host_init(struct pcie_port *
goto err_free_msi;
}
+ if (!dw_pcie_link_up(pci) && pci->ops->start_link) {
+ ret = pci->ops->start_link(pci);
+ if (ret)
+ goto err_free_msi;
+ }
+
+ /* Ignore errors, the link may come up later */
+ dw_pcie_wait_for_link(pci);
+
bridge->sysdata = pp;
ret = pci_host_probe(bridge);
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -35,10 +35,7 @@ static const struct of_device_id dw_plat
static int dw_plat_pcie_host_init(struct pcie_port *pp)
{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-
dw_pcie_setup_rc(pp);
- dw_pcie_wait_for_link(pci);
dw_pcie_msi_init(pp);
return 0;
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -169,39 +169,36 @@ static int histb_pcie_link_up(struct dw_
return 0;
}
-static int histb_pcie_establish_link(struct pcie_port *pp)
+static int histb_pcie_start_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct histb_pcie *hipcie = to_histb_pcie(pci);
u32 regval;
- if (dw_pcie_link_up(pci)) {
- dev_info(pci->dev, "Link already up\n");
- return 0;
- }
-
- /* PCIe RC work mode */
- regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
- regval &= ~PCIE_DEVICE_TYPE_MASK;
- regval |= PCIE_WM_RC;
- histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
-
- /* setup root complex */
- dw_pcie_setup_rc(pp);
-
/* assert LTSSM enable */
regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7);
regval |= PCIE_APP_LTSSM_ENABLE;
histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval);
- return dw_pcie_wait_for_link(pci);
+ return 0;
}
static int histb_pcie_host_init(struct pcie_port *pp)
{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct histb_pcie *hipcie = to_histb_pcie(pci);
+ u32 regval;
+
pp->bridge->ops = &histb_pci_ops;
- histb_pcie_establish_link(pp);
+ /* PCIe RC work mode */
+ regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
+ regval &= ~PCIE_DEVICE_TYPE_MASK;
+ regval |= PCIE_WM_RC;
+ histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
+
+ /* setup root complex */
+ dw_pcie_setup_rc(pp);
+
dw_pcie_msi_init(pp);
return 0;
@@ -300,6 +297,7 @@ static const struct dw_pcie_ops dw_pcie_
.read_dbi = histb_pcie_read_dbi,
.write_dbi = histb_pcie_write_dbi,
.link_up = histb_pcie_link_up,
+ .start_link = histb_pcie_start_link,
};
static int histb_pcie_probe(struct platform_device *pdev)
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -395,32 +395,14 @@ static int kirin_pcie_link_up(struct dw_
return 0;
}
-static int kirin_pcie_establish_link(struct pcie_port *pp)
+static int kirin_pcie_start_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
- struct device *dev = kirin_pcie->pci->dev;
- int count = 0;
-
- if (kirin_pcie_link_up(pci))
- return 0;
-
- dw_pcie_setup_rc(pp);
/* assert LTSSM enable */
kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
PCIE_APP_LTSSM_ENABLE);
- /* check if the link is up or not */
- while (!kirin_pcie_link_up(pci)) {
- usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
- count++;
- if (count == 1000) {
- dev_err(dev, "Link Fail\n");
- return -EINVAL;
- }
- }
-
return 0;
}
@@ -428,7 +410,7 @@ static int kirin_pcie_host_init(struct p
{
pp->bridge->ops = &kirin_pci_ops;
- kirin_pcie_establish_link(pp);
+ dw_pcie_setup_rc(pp);
dw_pcie_msi_init(pp);
return 0;
@@ -438,6 +420,7 @@ static const struct dw_pcie_ops kirin_dw
.read_dbi = kirin_pcie_read_dbi,
.write_dbi = kirin_pcie_write_dbi,
.link_up = kirin_pcie_link_up,
+ .start_link = kirin_pcie_start_link,
};
static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -207,18 +207,15 @@ static void qcom_ep_reset_deassert(struc
usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
}
-static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
+static int qcom_pcie_start_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = pcie->pci;
-
- if (dw_pcie_link_up(pci))
- return 0;
+ struct qcom_pcie *pcie = to_qcom_pcie(pci);
/* Enable Link Training state machine */
if (pcie->ops->ltssm_enable)
pcie->ops->ltssm_enable(pcie);
- return dw_pcie_wait_for_link(pci);
+ return 0;
}
static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
@@ -1280,15 +1277,8 @@ static int qcom_pcie_host_init(struct pc
qcom_ep_reset_deassert(pcie);
- ret = qcom_pcie_establish_link(pcie);
- if (ret)
- goto err;
-
return 0;
-err:
- qcom_ep_reset_assert(pcie);
- if (pcie->ops->post_deinit)
- pcie->ops->post_deinit(pcie);
+
err_disable_phy:
phy_power_off(pcie->phy);
err_deinit:
@@ -1355,6 +1345,7 @@ static const struct qcom_pcie_ops ops_2_
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
+ .start_link = qcom_pcie_start_link,
};
static int qcom_pcie_probe(struct platform_device *pdev)
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1555,7 +1555,6 @@ static int tegra_pcie_deinit_controller(
static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
{
- struct pcie_port *pp = &pcie->pci.pp;
struct device *dev = pcie->dev;
char *name;
int ret;
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -146,16 +146,13 @@ static int uniphier_pcie_link_up(struct
return (val & mask) == mask;
}
-static int uniphier_pcie_establish_link(struct dw_pcie *pci)
+static int uniphier_pcie_start_link(struct dw_pcie *pci)
{
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
- if (dw_pcie_link_up(pci))
- return 0;
-
uniphier_pcie_ltssm_enable(priv, true);
- return dw_pcie_wait_for_link(pci);
+ return 0;
}
static void uniphier_pcie_stop_link(struct dw_pcie *pci)
@@ -312,10 +309,6 @@ static int uniphier_pcie_host_init(struc
uniphier_pcie_irq_enable(priv);
dw_pcie_setup_rc(pp);
- ret = uniphier_pcie_establish_link(pci);
- if (ret)
- return ret;
-
dw_pcie_msi_init(pp);
return 0;
@@ -379,7 +372,7 @@ out_clk_disable:
}
static const struct dw_pcie_ops dw_pcie_ops = {
- .start_link = uniphier_pcie_establish_link,
+ .start_link = uniphier_pcie_start_link,
.stop_link = uniphier_pcie_stop_link,
.link_up = uniphier_pcie_link_up,
};

272
target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch
View File

@ -1,272 +0,0 @@
From 02c98d70da854cd4d145afe800194768c5eefe1d Mon Sep 17 00:00:00 2001
From: Rob Herring <robh@kernel.org>
Date: Thu, 5 Nov 2020 15:11:54 -0600
Subject: [PATCH 5/5] PCI: dwc: Move dw_pcie_msi_init() into core
The host drivers which call dw_pcie_msi_init() are all the ones using
the built-in MSI controller, so let's move it into the common DWC code.
Link: https://lore.kernel.org/r/20201105211159.1814485-12-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Yue Wang <yue.wang@Amlogic.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@axis.com
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
---
drivers/pci/controller/dwc/pci-dra7xx.c | 2 --
drivers/pci/controller/dwc/pci-exynos.c | 4 ----
drivers/pci/controller/dwc/pci-imx6.c | 1 -
drivers/pci/controller/dwc/pci-meson.c | 1 -
drivers/pci/controller/dwc/pcie-artpec6.c | 1 -
drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++----
drivers/pci/controller/dwc/pcie-designware-plat.c | 1 -
drivers/pci/controller/dwc/pcie-designware.h | 10 ----------
drivers/pci/controller/dwc/pcie-histb.c | 2 --
drivers/pci/controller/dwc/pcie-kirin.c | 1 -
drivers/pci/controller/dwc/pcie-qcom.c | 2 --
drivers/pci/controller/dwc/pcie-spear13xx.c | 6 +-----
drivers/pci/controller/dwc/pcie-tegra194.c | 2 --
drivers/pci/controller/dwc/pcie-uniphier.c | 1 -
14 files changed, 6 insertions(+), 37 deletions(-)
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -182,8 +182,6 @@ static int dra7xx_pcie_host_init(struct
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
dw_pcie_setup_rc(pp);
-
- dw_pcie_msi_init(pp);
dra7xx_pcie_enable_interrupts(dra7xx);
return 0;
--- a/drivers/pci/controller/dwc/pci-exynos.c
+++ b/drivers/pci/controller/dwc/pci-exynos.c
@@ -273,12 +273,8 @@ static irqreturn_t exynos_pcie_irq_handl
static void exynos_pcie_msi_init(struct exynos_pcie *ep)
{
- struct dw_pcie *pci = ep->pci;
- struct pcie_port *pp = &pci->pp;
u32 val;
- dw_pcie_msi_init(pp);
-
/* enable MSI interrupt */
val = exynos_pcie_readl(ep->mem_res->elbi_base, PCIE_IRQ_EN_LEVEL);
val |= IRQ_MSI_ENABLE;
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -840,7 +840,6 @@ static int imx6_pcie_host_init(struct pc
imx6_pcie_deassert_core_reset(imx6_pcie);
imx6_setup_phy_mpll(imx6_pcie);
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
return 0;
}
--- a/drivers/pci/controller/dwc/pci-meson.c
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -381,7 +381,6 @@ static int meson_pcie_host_init(struct p
meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
return 0;
}
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -329,7 +329,6 @@ static int artpec6_pcie_host_init(struct
artpec6_pcie_deassert_core_reset(artpec6_pcie);
artpec6_pcie_wait_for_phy(artpec6_pcie);
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
return 0;
}
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -256,7 +256,7 @@ int dw_pcie_allocate_domains(struct pcie
return 0;
}
-void dw_pcie_free_msi(struct pcie_port *pp)
+static void dw_pcie_free_msi(struct pcie_port *pp)
{
if (pp->msi_irq) {
irq_set_chained_handler(pp->msi_irq, NULL);
@@ -275,19 +275,18 @@ void dw_pcie_free_msi(struct pcie_port *
}
}
-void dw_pcie_msi_init(struct pcie_port *pp)
+static void dw_pcie_msi_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
u64 msi_target = (u64)pp->msi_data;
- if (!IS_ENABLED(CONFIG_PCI_MSI))
+ if (!pci_msi_enabled() || !pp->has_msi_ctrl)
return;
/* Program the msi_data */
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
}
-EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
int dw_pcie_host_init(struct pcie_port *pp)
{
@@ -417,6 +416,8 @@ int dw_pcie_host_init(struct pcie_port *
goto err_free_msi;
}
+ dw_pcie_msi_init(pp);
+
if (!dw_pcie_link_up(pci) && pci->ops->start_link) {
ret = pci->ops->start_link(pci);
if (ret)
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -36,7 +36,6 @@ static const struct of_device_id dw_plat
static int dw_plat_pcie_host_init(struct pcie_port *pp)
{
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
return 0;
}
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -365,8 +365,6 @@ static inline void dw_pcie_dbi_ro_wr_dis
#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
-void dw_pcie_msi_init(struct pcie_port *pp);
-void dw_pcie_free_msi(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
void dw_pcie_host_deinit(struct pcie_port *pp);
@@ -379,14 +377,6 @@ static inline irqreturn_t dw_handle_msi_
return IRQ_NONE;
}
-static inline void dw_pcie_msi_init(struct pcie_port *pp)
-{
-}
-
-static inline void dw_pcie_free_msi(struct pcie_port *pp)
-{
-}
-
static inline void dw_pcie_setup_rc(struct pcie_port *pp)
{
}
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -199,8 +199,6 @@ static int histb_pcie_host_init(struct p
/* setup root complex */
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
-
return 0;
}
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -411,7 +411,6 @@ static int kirin_pcie_host_init(struct p
pp->bridge->ops = &kirin_pci_ops;
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
return 0;
}
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1273,8 +1273,6 @@ static int qcom_pcie_host_init(struct pc
}
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
-
qcom_ep_reset_deassert(pcie);
return 0;
--- a/drivers/pci/controller/dwc/pcie-spear13xx.c
+++ b/drivers/pci/controller/dwc/pcie-spear13xx.c
@@ -124,16 +124,12 @@ static irqreturn_t spear13xx_pcie_irq_ha
static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
{
- struct dw_pcie *pci = spear13xx_pcie->pci;
- struct pcie_port *pp = &pci->pp;
struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
/* Enable MSI interrupt */
- if (IS_ENABLED(CONFIG_PCI_MSI)) {
- dw_pcie_msi_init(pp);
+ if (IS_ENABLED(CONFIG_PCI_MSI))
writel(readl(&app_reg->int_mask) |
MSI_CTRL_INT, &app_reg->int_mask);
- }
}
static int spear13xx_pcie_link_up(struct dw_pcie *pci)
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -767,8 +767,6 @@ static void tegra_pcie_enable_msi_interr
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
- dw_pcie_msi_init(pp);
-
/* Enable MSI interrupt generation */
val = appl_readl(pcie, APPL_INTR_EN_L0_0);
val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -309,7 +309,6 @@ static int uniphier_pcie_host_init(struc
uniphier_pcie_irq_enable(priv);
dw_pcie_setup_rc(pp);
- dw_pcie_msi_init(pp);
return 0;
}

48
target/linux/ipq807x/patches-5.10/101-arm64-dts-ipq8074-add-crypto-nodes.patch
View File

@ -1,48 +0,0 @@
From 69581d91675df8c0d9b5f746de7c2f3d73344280 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 11 May 2021 15:10:37 +0200
Subject: [PATCH] arm64: dts: ipq8074: add crypto nodes
IPQ8074 uses Qualcom QCE crypto engine v5.1
which is already supported.
So simply add nodes for its DMA and QCE itself.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -224,6 +224,30 @@
};
};
+ cryptobam: dma@704000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x00704000 0x20000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <1>;
+ qcom,controlled-remotely = <1>;
+ status = "disabled";
+ };
+
+ crypto: crypto@73a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0x0073a000 0x6000>;
+ clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc GCC_CRYPTO_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x01000000 0x300000>;

30
target/linux/ipq807x/patches-5.10/102-arm64-dts-ipq8074-add-PRNG-node.patch
View File

@ -1,30 +0,0 @@
From ff46c62852e862ac360aeb1054180c8e715fbeb4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 11 May 2021 15:23:53 +0200
Subject: [PATCH] arm64: dts: ipq8074: add PRNG node
PRNG insinde of IPQ8074 is already supported,
so simply add the node for it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -224,6 +224,14 @@
};
};
+ prng: rng@e3000 {
+ compatible = "qcom,prng-ee";
+ reg = <0x000e3000 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
cryptobam: dma@704000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00704000 0x20000>;

155
target/linux/ipq807x/patches-5.10/103-remoteproc-qcom-Add-PRNG-proxy-clock.patch
View File

@ -1,155 +0,0 @@
From e0d3c4e232c2b29532f7b894485814782201fdd9 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:05 +0530
Subject: [PATCH 08/16] remoteproc: qcom: Add PRNG proxy clock
PRNG clock is needed by the secure PIL, support for the same
is added in subsequent patches.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 65 +++++++++++++++++++++--------
1 file changed, 47 insertions(+), 18 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -91,19 +91,6 @@ enum {
WCSS_QCS404,
};
-struct wcss_data {
- const char *firmware_name;
- unsigned int crash_reason_smem;
- u32 version;
- bool aon_reset_required;
- bool wcss_q6_reset_required;
- const char *ssr_name;
- const char *sysmon_name;
- int ssctl_id;
- const struct rproc_ops *ops;
- bool requires_force_stop;
-};
-
struct q6v5_wcss {
struct device *dev;
@@ -128,6 +115,7 @@ struct q6v5_wcss {
struct clk *qdsp6ss_xo_cbcr;
struct clk *qdsp6ss_core_gfmux;
struct clk *lcc_bcr_sleep;
+ struct clk *prng_clk;
struct regulator *cx_supply;
struct qcom_sysmon *sysmon;
@@ -151,6 +139,21 @@ struct q6v5_wcss {
struct qcom_rproc_ssr ssr_subdev;
};
+struct wcss_data {
+ int (*init_clock)(struct q6v5_wcss *wcss);
+ int (*init_regulator)(struct q6v5_wcss *wcss);
+ const char *firmware_name;
+ unsigned int crash_reason_smem;
+ u32 version;
+ bool aon_reset_required;
+ bool wcss_q6_reset_required;
+ const char *ssr_name;
+ const char *sysmon_name;
+ int ssctl_id;
+ const struct rproc_ops *ops;
+ bool requires_force_stop;
+};
+
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
{
int ret;
@@ -240,6 +243,12 @@ static int q6v5_wcss_start(struct rproc
struct q6v5_wcss *wcss = rproc->priv;
int ret;
+ ret = clk_prepare_enable(wcss->prng_clk);
+ if (ret) {
+ dev_err(wcss->dev, "prng clock enable failed\n");
+ return ret;
+ }
+
qcom_q6v5_prepare(&wcss->q6v5);
/* Release Q6 and WCSS reset */
@@ -732,6 +741,7 @@ static int q6v5_wcss_stop(struct rproc *
return ret;
}
+ clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
return 0;
@@ -896,7 +906,21 @@ static int q6v5_alloc_memory_region(stru
return 0;
}
-static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
+static int ipq8074_init_clock(struct q6v5_wcss *wcss)
+{
+ int ret;
+
+ wcss->prng_clk = devm_clk_get(wcss->dev, "prng");
+ if (IS_ERR(wcss->prng_clk)) {
+ ret = PTR_ERR(wcss->prng_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(wcss->dev, "Failed to get prng clock\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int qcs404_init_clock(struct q6v5_wcss *wcss)
{
int ret;
@@ -986,7 +1010,7 @@ static int q6v5_wcss_init_clock(struct q
return 0;
}
-static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
+static int qcs404_init_regulator(struct q6v5_wcss *wcss)
{
wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
if (IS_ERR(wcss->cx_supply))
@@ -1030,12 +1054,14 @@ static int q6v5_wcss_probe(struct platfo
if (ret)
goto free_rproc;
- if (wcss->version == WCSS_QCS404) {
- ret = q6v5_wcss_init_clock(wcss);
+ if (desc->init_clock) {
+ ret = desc->init_clock(wcss);
if (ret)
goto free_rproc;
+ }
- ret = q6v5_wcss_init_regulator(wcss);
+ if (desc->init_regulator) {
+ ret = desc->init_regulator(wcss);
if (ret)
goto free_rproc;
}
@@ -1082,6 +1108,7 @@ static int q6v5_wcss_remove(struct platf
}
static const struct wcss_data wcss_ipq8074_res_init = {
+ .init_clock = ipq8074_init_clock,
.firmware_name = "IPQ8074/q6_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
@@ -1091,6 +1118,8 @@ static const struct wcss_data wcss_ipq80
};
static const struct wcss_data wcss_qcs404_res_init = {
+ .init_clock = qcs404_init_clock,
+ .init_regulator = qcs404_init_regulator,
.crash_reason_smem = WCSS_CRASH_REASON,
.firmware_name = "wcnss.mdt",
.version = WCSS_QCS404,

143
target/linux/ipq807x/patches-5.10/104-remoteproc-qcom-Add-secure-PIL-support.patch
View File

@ -1,143 +0,0 @@
From a6256ebbd66f3457e4a285b72b362d452bc6854f Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:06 +0530
Subject: [PATCH 09/16] remoteproc: qcom: Add secure PIL support
IPQ8074 uses secure PIL. Hence, adding the support for the same.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 43 +++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 3 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -18,6 +18,7 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/soc/qcom/mdt_loader.h>
+#include <linux/qcom_scm.h>
#include "qcom_common.h"
#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
@@ -86,6 +87,9 @@
#define TCSR_WCSS_CLK_ENABLE 0x14
#define MAX_HALT_REG 3
+
+#define WCNSS_PAS_ID 6
+
enum {
WCSS_IPQ8074,
WCSS_QCS404,
@@ -134,6 +138,7 @@ struct q6v5_wcss {
unsigned int crash_reason_smem;
u32 version;
bool requires_force_stop;
+ bool need_mem_protection;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -152,6 +157,7 @@ struct wcss_data {
int ssctl_id;
const struct rproc_ops *ops;
bool requires_force_stop;
+ bool need_mem_protection;
};
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -251,6 +257,15 @@ static int q6v5_wcss_start(struct rproc
qcom_q6v5_prepare(&wcss->q6v5);
+ if (wcss->need_mem_protection) {
+ ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
+ if (ret) {
+ dev_err(wcss->dev, "wcss_reset failed\n");
+ return ret;
+ }
+ goto wait_for_reset;
+ }
+
/* Release Q6 and WCSS reset */
ret = reset_control_deassert(wcss->wcss_reset);
if (ret) {
@@ -285,6 +300,7 @@ static int q6v5_wcss_start(struct rproc
if (ret)
goto wcss_q6_reset;
+wait_for_reset:
ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
if (ret == -ETIMEDOUT)
dev_err(wcss->dev, "start timed out\n");
@@ -717,6 +733,15 @@ static int q6v5_wcss_stop(struct rproc *
struct q6v5_wcss *wcss = rproc->priv;
int ret;
+ if (wcss->need_mem_protection) {
+ ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
+ if (ret) {
+ dev_err(wcss->dev, "not able to shutdown\n");
+ return ret;
+ }
+ goto pas_done;
+ }
+
/* WCSS powerdown */
if (wcss->requires_force_stop) {
ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
@@ -741,6 +766,7 @@ static int q6v5_wcss_stop(struct rproc *
return ret;
}
+pas_done:
clk_disable_unprepare(wcss->prng_clk);
qcom_q6v5_unprepare(&wcss->q6v5);
@@ -764,9 +790,15 @@ static int q6v5_wcss_load(struct rproc *
struct q6v5_wcss *wcss = rproc->priv;
int ret;
- ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
- 0, wcss->mem_region, wcss->mem_phys,
- wcss->mem_size, &wcss->mem_reloc);
+ if (wcss->need_mem_protection)
+ ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
+ WCNSS_PAS_ID, wcss->mem_region,
+ wcss->mem_phys, wcss->mem_size,
+ &wcss->mem_reloc);
+ else
+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
+ 0, wcss->mem_region, wcss->mem_phys,
+ wcss->mem_size, &wcss->mem_reloc);
if (ret)
return ret;
@@ -1032,6 +1064,9 @@ static int q6v5_wcss_probe(struct platfo
if (!desc)
return -EINVAL;
+ if (desc->need_mem_protection && !qcom_scm_is_available())
+ return -EPROBE_DEFER;
+
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
desc->firmware_name, sizeof(*wcss));
if (!rproc) {
@@ -1045,6 +1080,7 @@ static int q6v5_wcss_probe(struct platfo
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
+ wcss->need_mem_protection = desc->need_mem_protection;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1115,6 +1151,7 @@ static const struct wcss_data wcss_ipq80
.wcss_q6_reset_required = true,
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
+ .need_mem_protection = true,
};
static const struct wcss_data wcss_qcs404_res_init = {

104
target/linux/ipq807x/patches-5.10/105-remoteproc-qcom-Add-support-for-split-q6-m3-wlan-fir.patch
View File

@ -1,104 +0,0 @@
From ea44aa0384fec6d6fcd5bf6bf52175628bad7319 Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:07 +0530
Subject: [PATCH 10/16] remoteproc: qcom: Add support for split q6 + m3 wlan
firmware
IPQ8074 supports split firmware for q6 and m3 as well.
So add support for loading the m3 firmware before q6.
Now the drivers works fine for both split and unified
firmwares.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 33 +++++++++++++++++++++++++----
1 file changed, 29 insertions(+), 4 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -139,6 +139,7 @@ struct q6v5_wcss {
u32 version;
bool requires_force_stop;
bool need_mem_protection;
+ const char *m3_firmware_name;
struct qcom_rproc_glink glink_subdev;
struct qcom_rproc_ssr ssr_subdev;
@@ -147,7 +148,8 @@ struct q6v5_wcss {
struct wcss_data {
int (*init_clock)(struct q6v5_wcss *wcss);
int (*init_regulator)(struct q6v5_wcss *wcss);
- const char *firmware_name;
+ const char *q6_firmware_name;
+ const char *m3_firmware_name;
unsigned int crash_reason_smem;
u32 version;
bool aon_reset_required;
@@ -788,8 +790,29 @@ static void *q6v5_wcss_da_to_va(struct r
static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
{
struct q6v5_wcss *wcss = rproc->priv;
+ const struct firmware *m3_fw;
int ret;
+ if (wcss->m3_firmware_name) {
+ ret = request_firmware(&m3_fw, wcss->m3_firmware_name,
+ wcss->dev);
+ if (ret)
+ goto skip_m3;
+
+ ret = qcom_mdt_load_no_init(wcss->dev, m3_fw,
+ wcss->m3_firmware_name, 0,
+ wcss->mem_region, wcss->mem_phys,
+ wcss->mem_size, &wcss->mem_reloc);
+
+ release_firmware(m3_fw);
+
+ if (ret) {
+ dev_err(wcss->dev, "can't load m3_fw.bXX\n");
+ return ret;
+ }
+ }
+
+skip_m3:
if (wcss->need_mem_protection)
ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware,
WCNSS_PAS_ID, wcss->mem_region,
@@ -1068,7 +1091,7 @@ static int q6v5_wcss_probe(struct platfo
return -EPROBE_DEFER;
rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
- desc->firmware_name, sizeof(*wcss));
+ desc->q6_firmware_name, sizeof(*wcss));
if (!rproc) {
dev_err(&pdev->dev, "failed to allocate rproc\n");
return -ENOMEM;
@@ -1081,6 +1104,7 @@ static int q6v5_wcss_probe(struct platfo
wcss->version = desc->version;
wcss->requires_force_stop = desc->requires_force_stop;
wcss->need_mem_protection = desc->need_mem_protection;
+ wcss->m3_firmware_name = desc->m3_firmware_name;
ret = q6v5_wcss_init_mmio(wcss, pdev);
if (ret)
@@ -1145,7 +1169,8 @@ static int q6v5_wcss_remove(struct platf
static const struct wcss_data wcss_ipq8074_res_init = {
.init_clock = ipq8074_init_clock,
- .firmware_name = "IPQ8074/q6_fw.mdt",
+ .q6_firmware_name = "IPQ8074/q6_fw.mdt",
+ .m3_firmware_name = "IPQ8074/m3_fw.mdt",
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
@@ -1158,7 +1183,7 @@ static const struct wcss_data wcss_qcs40
.init_clock = qcs404_init_clock,
.init_regulator = qcs404_init_regulator,
.crash_reason_smem = WCSS_CRASH_REASON,
- .firmware_name = "wcnss.mdt",
+ .q6_firmware_name = "wcnss.mdt",
.version = WCSS_QCS404,
.aon_reset_required = false,
.wcss_q6_reset_required = false,

24
target/linux/ipq807x/patches-5.10/106-remoteproc-qcom-Add-ssr-subdevice-identifier.patch
View File

@ -1,24 +0,0 @@
From dcfc2e3a3e346e0cad4c5b8707aaab96f4bbb59d Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:08 +0530
Subject: [PATCH 11/16] remoteproc: qcom: Add ssr subdevice identifier
Add name for ssr subdevice on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -1174,6 +1174,7 @@ static const struct wcss_data wcss_ipq80
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
+ .ssr_name = "q6wcss",
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
.need_mem_protection = true,

80
target/linux/ipq807x/patches-5.10/107-remoteproc-qcom-Update-regmap-offsets-for-halt-regis.patch
View File

@ -1,80 +0,0 @@
From 543a7093420b500a197fc64361084613f248f07a Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:09 +0530
Subject: [PATCH 12/16] remoteproc: qcom: Update regmap offsets for halt
register
Fixed issue in reading halt-regs parameter from device-tree.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -86,7 +86,7 @@
#define TCSR_WCSS_CLK_MASK 0x1F
#define TCSR_WCSS_CLK_ENABLE 0x14
-#define MAX_HALT_REG 3
+#define MAX_HALT_REG 4
#define WCNSS_PAS_ID 6
@@ -154,6 +154,7 @@ struct wcss_data {
u32 version;
bool aon_reset_required;
bool wcss_q6_reset_required;
+ bool bcr_reset_required;
const char *ssr_name;
const char *sysmon_name;
int ssctl_id;
@@ -874,10 +875,13 @@ static int q6v5_wcss_init_reset(struct q
}
}
- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
- if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
- return PTR_ERR(wcss->wcss_q6_bcr_reset);
+ if (desc->bcr_reset_required) {
+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
+ "wcss_q6_bcr_reset");
+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
+ }
}
return 0;
@@ -925,9 +929,9 @@ static int q6v5_wcss_init_mmio(struct q6
return -EINVAL;
}
- wcss->halt_q6 = halt_reg[0];
- wcss->halt_wcss = halt_reg[1];
- wcss->halt_nc = halt_reg[2];
+ wcss->halt_q6 = halt_reg[1];
+ wcss->halt_wcss = halt_reg[2];
+ wcss->halt_nc = halt_reg[3];
return 0;
}
@@ -1174,6 +1178,7 @@ static const struct wcss_data wcss_ipq80
.crash_reason_smem = WCSS_CRASH_REASON,
.aon_reset_required = true,
.wcss_q6_reset_required = true,
+ .bcr_reset_required = false,
.ssr_name = "q6wcss",
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
@@ -1188,6 +1193,7 @@ static const struct wcss_data wcss_qcs40
.version = WCSS_QCS404,
.aon_reset_required = false,
.wcss_q6_reset_required = false,
+ .bcr_reset_required = true,
.ssr_name = "mpss",
.sysmon_name = "wcnss",
.ssctl_id = 0x12,

25
target/linux/ipq807x/patches-5.10/108-dt-bindings-clock-qcom-Add-reset-for-WCSSAON.patch
View File

@ -1,25 +0,0 @@
From 12c7588316e1aceb3a4918896735e8bc3757815f Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:10 +0530
Subject: [PATCH 13/16] dt-bindings: clock: qcom: Add reset for WCSSAON
Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -366,5 +366,6 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
+#define GCC_WCSSAON_RESET 132
#endif

25
target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch
View File

@ -1,25 +0,0 @@
From 6de5e246382d6b15f297cadbf26bdd78ee7f9fea Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:11 +0530
Subject: [PATCH 14/16] clk: qcom: Add WCSSAON reset
Add WCSSAON reset required for Q6v5 on IPQ8074 SoC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4784,6 +4784,7 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
+ [GCC_WCSSAON_RESET] = { 0x59010, 0 },
};
static const struct of_device_id gcc_ipq8074_match_table[] = {

28
target/linux/ipq807x/patches-5.10/110-arm64-dts-Add-support-for-scm-on-IPQ8074-SoCs.patch
View File

@ -1,28 +0,0 @@
From b177148d326cac30723f5fe9c939db2919aab33a Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:12 +0530
Subject: [PATCH 15/16] arm64: dts: Add support for scm on IPQ8074 SoCs
Enables scm support, clock is not needed for enabling scm interface.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -76,6 +76,12 @@
method = "smc";
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq8074", "qcom,scm";
+ };
+ };
+
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;

158
target/linux/ipq807x/patches-5.10/111-arm64-dts-qcom-Enable-Q6v5-WCSS-for-ipq8074-SoC.patch
View File

@ -1,158 +0,0 @@
From 9428cd325c99212b25407df8035284012d65acdb Mon Sep 17 00:00:00 2001
From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Date: Sat, 30 Jan 2021 10:50:13 +0530
Subject: [PATCH 16/16] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
Enable remoteproc WCSS PIL driver with glink
and ssr subdevices. Also configures shared memory
and enables smp2p and mailboxes required for IPC.
Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 121 ++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -76,12 +76,66 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem_region: memory@4ab00000 {
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x00100000>;
+ };
+
+ q6_region: memory@4b000000 {
+ no-map;
+ reg = <0x0 0x4b000000 0x0 0x05f00000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
};
};
+ tcsr_mutex: hwlock@193d000 {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_regs 0 0x80>;
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_region>;
+ hwlocks = <&tcsr_mutex 0>;
+ };
+
+ wcss: smp2p-wcss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 322 1>;
+
+ mboxes = <&apcs_glb 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ wcss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ qcom,smp2p-feature-ssr-ack;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -754,5 +808,72 @@
"axi_s_sticky";
status = "disabled";
};
+
+ tcsr_q6: syscon@1945000 {
+ compatible = "syscon";
+ reg = <0x01945000 0xe000>;
+ };
+
+ tcsr_mutex_regs: syscon@193d000 {
+ compatible = "syscon";
+ reg = <0x01905000 0x8000>;
+ };
+
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq8074-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ q6v5_wcss: q6v5_wcss@cd00000 {
+ compatible = "qcom,ipq8074-wcss-pil";
+ reg = <0x0cd00000 0x4040>,
+ <0x004ab000 0x20>;
+ reg-names = "qdsp6",
+ "rmb";
+ qca,auto-restart;
+ qca,extended-intc;
+ interrupts-extended = <&intc 0 325 1>,
+ <&wcss_smp2p_in 0 0>,
+ <&wcss_smp2p_in 1 0>,
+ <&wcss_smp2p_in 2 0>,
+ <&wcss_smp2p_in 3 0>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ resets = <&gcc GCC_WCSSAON_RESET>,
+ <&gcc GCC_WCSS_BCR>,
+ <&gcc GCC_WCSS_Q6_BCR>;
+
+ reset-names = "wcss_aon_reset",
+ "wcss_reset",
+ "wcss_q6_reset";
+
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "prng";
+
+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
+
+ qcom,smem-states = <&wcss_smp2p_out 0>,
+ <&wcss_smp2p_out 1>;
+ qcom,smem-state-names = "shutdown",
+ "stop";
+
+ memory-region = <&q6_region>;
+
+ glink-edge {
+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
+ qcom,remote-pid = <1>;
+ mboxes = <&apcs_glb 8>;
+
+ rpm_requests {
+ qcom,glink-channels = "IPCRTR";
+ };
+ };
+ };
};
};

35
target/linux/ipq807x/patches-5.10/112-qcom-socinfo-Add-IPQ8074-SoC-family-ID-s.patch
View File

@ -1,35 +0,0 @@
From 5454294f432c0c095f3e2b54fd45491be779c545 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 11 May 2021 18:11:13 +0200
Subject: [PATCH] soc: qcom: socinfo: Add IPQ8074 SoC family ID-s
Add ID-s for the Qualcomm IPQ8074 SoC family.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/soc/qcom/socinfo.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -224,8 +224,20 @@ static const struct soc_id soc_id[] = {
{ 312, "APQ8096SG" },
{ 318, "SDM630" },
{ 321, "SDM845" },
+ { 323, "IPQ8074" },
{ 341, "SDA845" },
+ { 342, "IPQ8072" },
+ { 343, "IPQ8076" },
+ { 344, "IPQ8078" },
{ 356, "SM8250" },
+ { 375, "IPQ8070" },
+ { 376, "IPQ8071" },
+ { 389, "IPQ8072A" },
+ { 390, "IPQ8074A" },
+ { 391, "IPQ8076A" },
+ { 392, "IPQ8078A" },
+ { 395, "IPQ8070A" },
+ { 396, "IPQ8071A" },
{ 402, "IPQ6018" },
{ 425, "SC7180" },
};

49
target/linux/ipq807x/patches-5.10/113-net-mdio-ipq4019-add-clock-handling.patch
View File

@ -1,49 +0,0 @@
From d91c466ec19e5ced30631cec703164c79525b986 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Sun, 27 Dec 2020 18:55:56 +0100
Subject: [PATCH] net: mdio-ipq4019: add clock handling
Newer SoC-s like IPQ807x and IPQ60xx use the same MDIO controller,
but have separate MDIO clocks that need to be handled.
So lets add support for doing that.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/mdio/mdio-ipq4019.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/drivers/net/mdio/mdio-ipq4019.c
+++ b/drivers/net/mdio/mdio-ipq4019.c
@@ -2,6 +2,7 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved. */
/* Copyright (c) 2020 Sartura Ltd. */
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/iopoll.h>
@@ -33,6 +34,7 @@
struct ipq4019_mdio_data {
void __iomem *membase;
+ struct clk *clk;
};
static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
@@ -187,6 +189,16 @@ static int ipq4019_mdio_probe(struct pla
if (IS_ERR(priv->membase))
return PTR_ERR(priv->membase);
+ priv->clk = devm_clk_get_optional(&pdev->dev, "mdio_ahb");
+ if (IS_ERR(priv->clk)) {
+ dev_err(&pdev->dev, "Failed getting clock!\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return ret;
+
bus->name = "ipq4019_mdio";
bus->read = ipq4019_mdio_read;
bus->write = ipq4019_mdio_write;

34
target/linux/ipq807x/patches-5.10/114-arm64-dts-ipq8074-Add-MDIO-support.patch
View File

@ -1,34 +0,0 @@
From 67ba6e563928123fc65dab604592a60da2cce648 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 11 May 2021 18:24:35 +0200
Subject: [PATCH] arm64: dts: ipq8074: Add MDIO support
MDIO controller is the same one as in IPQ4019, so
lets add the node to support it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -284,6 +284,18 @@
};
};
+ mdio: mdio@90000 {
+ compatible = "qcom,ipq4019-mdio";
+ reg = <0x00090000 0x64>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ clock-names = "mdio_ahb";
+
+ status = "disabled";
+ };
+
prng: rng@e3000 {
compatible = "qcom,prng-ee";
reg = <0x000e3000 0x1000>;

369
target/linux/ipq807x/patches-5.10/115-phy-qcom-qmp-Add-IPQ8074-PCIe-Gen3-QMP-PHY-support.patch
View File

@ -1,369 +0,0 @@
From 57887b141d68224dcf4039a2f5215011f43dd9f4 Mon Sep 17 00:00:00 2001
From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Date: Wed, 29 Jul 2020 21:00:04 +0530
Subject: [PATCH] phy: qcom-qmp: Add IPQ8074 PCIe Gen3 QMP PHY support
IPQ8074 has two PCIe ports, One Gen2 and one Gen3 port.
Since support for Gen2 PHY is already available, add support for
PCIe Gen3 PHY.
Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 139 ++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qmp.c | 171 +++++++++++++++++++++-
2 files changed, 308 insertions(+), 2 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef PHY_QCOM_PCIE_H
+#define PHY_QCOM_PCIE_H
+
+/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES PLL registers */
+#define QSERDES_PLL_BG_TIMER 0x00c
+#define QSERDES_PLL_SSC_PER1 0x01c
+#define QSERDES_PLL_SSC_PER2 0x020
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
+#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c
+#define QSERDES_PLL_CLK_ENABLE1 0x040
+#define QSERDES_PLL_SYS_CLK_CTRL 0x044
+#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048
+#define QSERDES_PLL_PLL_IVCO 0x050
+#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054
+#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058
+#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060
+#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064
+#define QSERDES_PLL_BG_TRIM 0x074
+#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078
+#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c
+#define QSERDES_PLL_CP_CTRL_MODE0 0x080
+#define QSERDES_PLL_CP_CTRL_MODE1 0x084
+#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088
+#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C
+#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090
+#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094
+#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4
+#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8
+#define QSERDES_PLL_RESETSM_CNTRL 0x0b0
+#define QSERDES_PLL_LOCK_CMP_EN 0x0c4
+#define QSERDES_PLL_DEC_START_MODE0 0x0cc
+#define QSERDES_PLL_DEC_START_MODE1 0x0d0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8
+#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc
+#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0
+#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4
+#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8
+#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104
+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108
+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c
+#define QSERDES_PLL_VCO_TUNE_MAP 0x120
+#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124
+#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128
+#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c
+#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130
+#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c
+#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140
+#define QSERDES_PLL_CLK_SELECT 0x16c
+#define QSERDES_PLL_HSCLK_SEL 0x170
+#define QSERDES_PLL_CORECLK_DIV 0x17c
+#define QSERDES_PLL_CORE_CLK_EN 0x184
+#define QSERDES_PLL_CMN_CONFIG 0x18c
+#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194
+#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4
+
+/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - - QSERDES TX registers */
+#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c
+#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058
+#define QSERDES_TX0_LANE_MODE_1 0x084
+#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c
+
+/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES RX registers */
+#define QSERDES_RX0_UCDR_FO_GAIN 0x008
+#define QSERDES_RX0_UCDR_SO_GAIN 0x014
+#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034
+#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044
+#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec
+#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0
+#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4
+#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8
+#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc
+#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
+#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114
+#define QSERDES_RX0_SIGDET_ENABLES 0x118
+#define QSERDES_RX0_SIGDET_CNTRL 0x11c
+#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124
+#define QSERDES_RX0_RX_MODE_00_LOW 0x170
+#define QSERDES_RX0_RX_MODE_00_HIGH 0x174
+#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178
+#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c
+#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180
+#define QSERDES_RX0_RX_MODE_01_LOW 0x184
+#define QSERDES_RX0_RX_MODE_01_HIGH 0x188
+#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c
+#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190
+#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194
+#define QSERDES_RX0_RX_MODE_10_LOW 0x198
+#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c
+#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0
+#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4
+#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8
+#define QSERDES_RX0_DFE_EN_TIMER 0x1b4
+
+/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS registers */
+
+#define PCS_COM_FLL_CNTRL1 0x098
+#define PCS_COM_FLL_CNTRL2 0x09c
+#define PCS_COM_FLL_CNT_VAL_L 0x0a0
+#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4
+#define PCS_COM_FLL_MAN_CODE 0x0a8
+#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc
+#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c
+#define PCS_COM_RX_SIGDET_LVL 0x188
+#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
+#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
+#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8
+#define PCS_COM_EQ_CONFIG5 0x1ec
+
+/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - PCS Misc registers */
+
+#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
+#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
+#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
+#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
+#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
+#define PCS_PCIE_EQ_CONFIG1 0x4a0
+#define PCS_PCIE_EQ_CONFIG2 0x4a4
+#define PCS_PCIE_PRESET_P10_PRE 0x4bc
+#define PCS_PCIE_PRESET_P10_POST 0x4e0
+
+#endif
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -23,6 +23,7 @@
#include <dt-bindings/phy/phy.h>
#include "phy-qcom-qmp.h"
+#include "phy-qcom-pcie3-qmp.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
@@ -676,6 +677,132 @@ static const struct qmp_phy_init_tbl ipq
QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
};
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
+};
static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -2187,6 +2314,36 @@ static const struct qmp_phy_cfg ipq8074_
.pwrdn_delay_max = 1005, /* us */
};
+static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
+ .type = PHY_TYPE_PCIE,
+ .nlanes = 1,
+
+ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
+ .tx_tbl = ipq8074_pcie_gen3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
+ .rx_tbl = ipq8074_pcie_gen3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
+ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
+ .clk_list = ipq8074_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
+ .reset_list = ipq8074_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+ .vreg_list = NULL,
+ .num_vregs = 0,
+ .regs = qmp_v4_usb3phy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+
+ .has_phy_com_ctrl = false,
+ .has_lane_rst = false,
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = 995, /* us */
+ .pwrdn_delay_max = 1005, /* us */
+};
+
static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
.type = PHY_TYPE_PCIE,
.nlanes = 1,
@@ -3476,8 +3633,15 @@ static int phy_pipe_clk_register(struct
init.ops = &clk_fixed_rate_ops;
- /* controllers using QMP phys use 125MHz pipe clock interface */
- fixed->fixed_rate = 125000000;
+ /*
+ * controllers using QMP phys use 125MHz pipe clock interface unless
+ * other frequency is specified in dts
+ */
+ ret = of_property_read_u32(np, "clock-output-rate",
+ (u32 *)&fixed->fixed_rate);
+ if (ret)
+ fixed->fixed_rate = 125000000;
+
fixed->hw.init = &init;
ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
@@ -3868,6 +4032,9 @@ static const struct of_device_id qcom_qm
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
}, {
+ .compatible = "qcom,ipq8074-qmp-pcie-gen3-phy",
+ .data = &ipq8074_pciephy_gen3_cfg,
+ }, {
.compatible = "qcom,sc7180-qmp-usb3-phy",
.data = &sc7180_usb3phy_cfg,
}, {

44
target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch
View File

@ -1,44 +0,0 @@
From 35df745d335bd21094f522dc9dff7eaae92114d9 Mon Sep 17 00:00:00 2001
From: Baruch Siach <baruch@tkos.co.il>
Date: Wed, 5 May 2021 12:18:29 +0300
Subject: [PATCH] PCI: dwc: tegra: move GEN3_RELATED DBI register to common
header
These are common dwc macros that will be used for other platforms.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
2 files changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -74,6 +74,12 @@
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
+#define GEN3_RELATED_OFF 0x890
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
+
#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
#define PORT_MLTI_UPCFG_SUPPORT BIT(7)
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -194,12 +194,6 @@
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
#define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
-#define GEN3_RELATED_OFF 0x890
-#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
-#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
-#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
-
#define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
#define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
#define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)

230
target/linux/ipq807x/patches-5.10/117-PCI-qcom-add-support-for-IPQ60xx-PCIe-controller.patch
View File

@ -1,230 +0,0 @@
From 809a720946f720dca2009bac29294992375a31b9 Mon Sep 17 00:00:00 2001
From: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Date: Tue, 11 May 2021 21:53:08 +0200
Subject: [PATCH] PCI: qcom: add support for IPQ60xx PCIe controller
IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
platform.
The code is based on downstream Codeaurora kernel v5.4. Split out the
DBI registers access part from .init into .post_init. DBI registers are
only accessible after phy_power_on().
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
drivers/pci/controller/dwc/pcie-designware.h | 1 +
drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++
2 files changed, 151 insertions(+)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -76,6 +76,7 @@
#define GEN3_RELATED_OFF 0x890
#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -51,6 +51,10 @@
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
+#define AHB_CLK_EN BIT(0)
+#define MSTR_AXI_CLK_EN BIT(1)
+#define BYPASS BIT(4)
+
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
#define PCIE20_PARF_LTSSM 0x1B0
@@ -92,6 +96,12 @@
#define SLV_ADDR_SPACE_SZ 0x10000000
#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
+#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)
+#define SPEED_GEN1 0x1
+#define SPEED_GEN2 0x2
+#define SPEED_GEN3 0x3
+#define AXI_CLK_RATE 200000000
+#define RCHNG_CLK_RATE 100000000
#define DEVICE_TYPE_RC 0x4
@@ -161,6 +171,11 @@ struct qcom_pcie_resources_2_7_0 {
struct clk *pipe_clk;
};
+struct qcom_pcie_resources_2_9_0 {
+ struct clk_bulk_data clks[5];
+ struct reset_control *rst;
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -168,6 +183,7 @@ union qcom_pcie_resources {
struct qcom_pcie_resources_2_3_3 v2_3_3;
struct qcom_pcie_resources_2_4_0 v2_4_0;
struct qcom_pcie_resources_2_7_0 v2_7_0;
+ struct qcom_pcie_resources_2_9_0 v2_9_0;
};
struct qcom_pcie;
@@ -1242,6 +1258,130 @@ static void qcom_pcie_post_deinit_2_7_0(
clk_disable_unprepare(res->pipe_clk);
}
+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int ret;
+
+ res->clks[0].id = "iface";
+ res->clks[1].id = "axi_m";
+ res->clks[2].id = "axi_s";
+ res->clks[3].id = "axi_bridge";
+ res->clks[4].id = "rchng";
+
+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+ if (ret < 0)
+ return ret;
+
+ res->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(res->rst))
+ return PTR_ERR(res->rst);
+
+ return 0;
+}
+
+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
+ struct device *dev = pcie->pci->dev;
+ int ret;
+
+ ret = reset_control_assert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset assert failed (%d)\n", ret);
+ return ret;
+ }
+
+ usleep_range(2000, 2500);
+
+ ret = reset_control_deassert(res->rst);
+ if (ret) {
+ dev_err(dev, "reset deassert failed (%d)\n", ret);
+ return ret;
+ }
+
+ /*
+ * Don't have a way to see if the reset has completed.
+ * Wait for some time.
+ */
+ usleep_range(2000, 2500);
+
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+ if (ret)
+ goto err_reset;
+
+ return 0;
+
+ /*
+ * Not checking for failure, will anyway return
+ * the original failure in 'ret'.
+ */
+err_reset:
+ reset_control_assert(res->rst);
+
+ return ret;
+}
+
+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct dw_pcie *pci = pcie->pci;
+ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ u32 val;
+ int i;
+
+ writel(SLV_ADDR_SPACE_SZ,
+ pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
+
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
+
+ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
+ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
+ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
+ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS
+ | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
+ pci->dbi_base + GEN3_RELATED_OFF);
+
+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
+ | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
+ pcie->parf + PCIE20_PARF_SYS_CTRL);
+
+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
+
+ dw_pcie_dbi_ro_wr_en(pci);
+ writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+
+ /* Configure PCIe link capabilities for ASPM */
+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+ val &= ~PCI_EXP_LNKCAP_ASPMS;
+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
+
+ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+ PCI_EXP_DEVCTL2);
+
+ writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3,
+ pci->dbi_base + offset + PCI_EXP_DEVCTL2);
+
+ for (i = 0;i < 256;i++)
+ writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N
+ + (4 * i));
+
+ return 0;
+}
+
static int qcom_pcie_link_up(struct dw_pcie *pci)
{
u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
@@ -1341,6 +1481,15 @@ static const struct qcom_pcie_ops ops_2_
.post_deinit = qcom_pcie_post_deinit_2_7_0,
};
+/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
+static const struct qcom_pcie_ops ops_2_9_0 = {
+ .get_resources = qcom_pcie_get_resources_2_9_0,
+ .init = qcom_pcie_init_2_9_0,
+ .post_init = qcom_pcie_post_init_2_9_0,
+ .deinit = qcom_pcie_deinit_2_9_0,
+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
+};
+
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
@@ -1446,6 +1595,7 @@ static const struct of_device_id qcom_pc
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
+ { .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 },
{ }
};

26
target/linux/ipq807x/patches-5.10/119-qcom-backport-register-define.patch
View File

@ -1,26 +0,0 @@
From 5d3f9ed5a9eb305a2531015cc65200d48be5dbf4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 11 May 2021 22:21:57 +0200
Subject: [PATCH 1/2] PCI: qcom: backport register define
This is used by the pending IPQ6018 PCI support which
uses the same Gen3 IP and the one we are reusing for
IPQ8074.
Without it compilation will break.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -61,6 +61,7 @@
#define PCIE20_PARF_SID_OFFSET 0x234
#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
#define PCIE20_PARF_DEVICE_TYPE 0x1000
+#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000
#define PCIE20_ELBI_SYS_CTRL 0x04
#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)

48
target/linux/ipq807x/patches-5.10/120-PCI-qcom-Add-IPQ8074-PCIe-Gen3-support.patch
View File

@ -1,48 +0,0 @@
From 9467e9860e72d7351b24dc6d77f0e9fe141ce166 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 26 May 2021 16:06:32 +0200
Subject: [PATCH] PCI: qcom: Add IPQ8074 PCIe Gen3 support
IPQ6018 uses the same v2.9.0 IP for the Gen3 PCIe
controller.
So, lets reuse that and add clocks that the IPQ6018
patch missed.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -173,7 +173,7 @@ struct qcom_pcie_resources_2_7_0 {
};
struct qcom_pcie_resources_2_9_0 {
- struct clk_bulk_data clks[5];
+ struct clk_bulk_data clks[7];
struct reset_control *rst;
};
@@ -1269,8 +1269,10 @@ static int qcom_pcie_get_resources_2_9_0
res->clks[0].id = "iface";
res->clks[1].id = "axi_m";
res->clks[2].id = "axi_s";
- res->clks[3].id = "axi_bridge";
- res->clks[4].id = "rchng";
+ res->clks[3].id = "ahb";
+ res->clks[4].id = "aux";
+ res->clks[5].id = "axi_bridge";
+ res->clks[6].id = "rchng";
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
if (ret < 0)
@@ -1597,6 +1599,7 @@ static const struct of_device_id qcom_pc
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
{ .compatible = "qcom,pcie-ipq6018", .data = &ops_2_9_0 },
+ { .compatible = "qcom,pcie-ipq8074-gen3", .data = &ops_2_9_0 },
{ }
};

27
target/linux/ipq807x/patches-5.10/122-arm64-uaccess-include-scheduler.h.patch
View File

@ -1,27 +0,0 @@
From 5fcad0d86d985b068eb97e55b55f7be87cd1b008 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 12 May 2021 17:01:29 +0200
Subject: [PATCH] arm64: uaccess: include scheduler.h
Qualcomm SSDK exposed a bug in which the uaccess is
using a struct and header definition that are not
included.
So, simply: #include <linux/sched.h> to fix it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/include/asm/uaccess.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -24,6 +24,8 @@
#include <asm/memory.h>
#include <asm/extable.h>
+#include <linux/sched.h>
+
#define get_fs() (current_thread_info()->addr_limit)
static inline void set_fs(mm_segment_t fs)

170
target/linux/ipq807x/patches-5.10/123-arm64-dts-ipq8074-add-networking-nodes.patch
View File

@ -1,170 +0,0 @@
From f581e7b004d0d997acc1f0fa5b2c454f90f0b2de Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Wed, 12 May 2021 18:49:30 +0200
Subject: [PATCH] arm64: dts: ipq8074: add networking nodes
Add networking nodes required for SSDK and NSS-DP.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 150 ++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -887,5 +887,155 @@
};
};
};
+
+ ess_switch: ess-switch@3a000000 {
+ compatible = "qcom,ess-switch-ipq807x";
+ reg = <0x3a000000 0x1000000>;
+ switch_access_mode = "local bus";
+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
+ switch_inner_bmp = <0x80>; /*inner port bitmap*/
+ mdio-bus = <&mdio>;
+ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>,
+ <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>,
+ <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_UNIPHY2_AHB_CLK>,
+ <&gcc GCC_UNIPHY2_SYS_CLK>,
+ <&gcc GCC_PORT1_MAC_CLK>,
+ <&gcc GCC_PORT2_MAC_CLK>,
+ <&gcc GCC_PORT3_MAC_CLK>,
+ <&gcc GCC_PORT4_MAC_CLK>,
+ <&gcc GCC_PORT5_MAC_CLK>,
+ <&gcc GCC_PORT6_MAC_CLK>,
+ <&gcc GCC_NSS_PPE_CLK>,
+ <&gcc GCC_NSS_PPE_CFG_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
+ <&gcc GCC_NSS_EDMA_CLK>,
+ <&gcc GCC_NSS_EDMA_CFG_CLK>,
+ <&gcc GCC_NSS_PPE_IPE_CLK>,
+ <&gcc GCC_NSS_PPE_BTQ_CLK>,
+ <&gcc GCC_NSS_NOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
+ <&gcc GCC_NSS_CRYPTO_CLK>,
+ <&gcc GCC_NSS_IMEM_CLK>,
+ <&gcc GCC_NSS_PTP_REF_CLK>,
+ <&gcc GCC_NSS_PORT1_RX_CLK>,
+ <&gcc GCC_NSS_PORT1_TX_CLK>,
+ <&gcc GCC_NSS_PORT2_RX_CLK>,
+ <&gcc GCC_NSS_PORT2_TX_CLK>,
+ <&gcc GCC_NSS_PORT3_RX_CLK>,
+ <&gcc GCC_NSS_PORT3_TX_CLK>,
+ <&gcc GCC_NSS_PORT4_RX_CLK>,
+ <&gcc GCC_NSS_PORT4_TX_CLK>,
+ <&gcc GCC_NSS_PORT5_RX_CLK>,
+ <&gcc GCC_NSS_PORT5_TX_CLK>,
+ <&gcc GCC_NSS_PORT6_RX_CLK>,
+ <&gcc GCC_NSS_PORT6_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
+ <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
+ <&gcc NSS_PORT5_RX_CLK_SRC>,
+ <&gcc NSS_PORT5_TX_CLK_SRC>;
+ clock-names = "cmn_ahb_clk", "cmn_sys_clk",
+ "uniphy0_ahb_clk", "uniphy0_sys_clk",
+ "uniphy1_ahb_clk", "uniphy1_sys_clk",
+ "uniphy2_ahb_clk", "uniphy2_sys_clk",
+ "port1_mac_clk", "port2_mac_clk",
+ "port3_mac_clk", "port4_mac_clk",
+ "port5_mac_clk", "port6_mac_clk",
+ "nss_ppe_clk", "nss_ppe_cfg_clk",
+ "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
+ "nss_edma_clk", "nss_edma_cfg_clk",
+ "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
+ "gcc_nss_noc_clk",
+ "gcc_nssnoc_snoc_clk",
+ "gcc_mem_noc_nss_axi_clk",
+ "gcc_nss_crypto_clk",
+ "gcc_nss_imem_clk",
+ "gcc_nss_ptp_ref_clk",
+ "nss_port1_rx_clk", "nss_port1_tx_clk",
+ "nss_port2_rx_clk", "nss_port2_tx_clk",
+ "nss_port3_rx_clk", "nss_port3_tx_clk",
+ "nss_port4_rx_clk", "nss_port4_tx_clk",
+ "nss_port5_rx_clk", "nss_port5_tx_clk",
+ "nss_port6_rx_clk", "nss_port6_tx_clk",
+ "uniphy0_port1_rx_clk",
+ "uniphy0_port1_tx_clk",
+ "uniphy0_port2_rx_clk",
+ "uniphy0_port2_tx_clk",
+ "uniphy0_port3_rx_clk",
+ "uniphy0_port3_tx_clk",
+ "uniphy0_port4_rx_clk",
+ "uniphy0_port4_tx_clk",
+ "uniphy0_port5_rx_clk",
+ "uniphy0_port5_tx_clk",
+ "uniphy1_port5_rx_clk",
+ "uniphy1_port5_tx_clk",
+ "uniphy2_port6_rx_clk",
+ "uniphy2_port6_tx_clk",
+ "nss_port5_rx_clk_src",
+ "nss_port5_tx_clk_src";
+ resets = <&gcc GCC_PPE_FULL_RESET>,
+ <&gcc GCC_UNIPHY0_SOFT_RESET>,
+ <&gcc GCC_UNIPHY0_XPCS_RESET>,
+ <&gcc GCC_UNIPHY1_SOFT_RESET>,
+ <&gcc GCC_UNIPHY1_XPCS_RESET>,
+ <&gcc GCC_UNIPHY2_SOFT_RESET>,
+ <&gcc GCC_UNIPHY2_XPCS_RESET>,
+ <&gcc GCC_NSSPORT1_RESET>,
+ <&gcc GCC_NSSPORT2_RESET>,
+ <&gcc GCC_NSSPORT3_RESET>,
+ <&gcc GCC_NSSPORT4_RESET>,
+ <&gcc GCC_NSSPORT5_RESET>,
+ <&gcc GCC_NSSPORT6_RESET>;
+ reset-names = "ppe_rst", "uniphy0_soft_rst",
+ "uniphy0_xpcs_rst", "uniphy1_soft_rst",
+ "uniphy1_xpcs_rst", "uniphy2_soft_rst",
+ "uniphy2_xpcs_rst", "nss_port1_rst",
+ "nss_port2_rst", "nss_port3_rst",
+ "nss_port4_rst", "nss_port5_rst",
+ "nss_port6_rst";
+ };
+
+ ess-uniphy@7a00000 {
+ compatible = "qcom,ess-uniphy";
+ reg = <0x7a00000 0x30000>;
+ uniphy_access_mode = "local bus";
+ };
+
+ edma@3ab00000 {
+ compatible = "qcom,edma";
+ reg = <0x3ab00000 0x76900>;
+ reg-names = "edma-reg-base";
+ qcom,txdesc-ring-start = <23>;
+ qcom,txdesc-rings = <1>;
+ qcom,txcmpl-ring-start = <7>;
+ qcom,txcmpl-rings = <1>;
+ qcom,rxfill-ring-start = <7>;
+ qcom,rxfill-rings = <1>;
+ qcom,rxdesc-ring-start = <15>;
+ qcom,rxdesc-rings = <1>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&gcc GCC_EDMA_HW_RESET>;
+ reset-names = "edma_rst";
+ };
};
};

79
target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch
View File

@ -1,79 +0,0 @@
From 4f579facd45c39f8f8b9993570944f4d83a95955 Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Wed, 5 Feb 2020 10:13:01 +0530
Subject: [PATCH 2/8] ipq8074: gcc: Added support for NSS clocks
Change-Id: I446e84dbc3498618425677811a73124b99b5c0ad
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++
drivers/clk/qcom/gcc-ipq8074.c | 68 +++++++++++++++++++-
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
3 files changed, 80 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -1037,5 +1037,17 @@
resets = <&gcc GCC_EDMA_HW_RESET>;
reset-names = "edma_rst";
};
+
+ bias_pll_cc_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ #clock-cells = <0>;
+ };
+
+ bias_pll_nss_noc_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <416500000>;
+ #clock-cells = <0>;
+ };
};
};
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -3177,6 +3177,24 @@ static struct clk_branch gcc_nss_ptp_ref
},
};
+static struct clk_branch gcc_crypto_ppe_clk = {
+ .halt_reg = 0x68310,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x68310,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_ppe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
.halt_reg = 0x6830c,
.clkr = {
@@ -4602,6 +4620,7 @@ static struct clk_regmap *gcc_ipq8074_cl
[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -233,6 +233,7 @@
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
#define GCC_PCIE0_RCHNG_CLK_SRC 225
#define GCC_PCIE0_RCHNG_CLK 226
+#define GCC_CRYPTO_PPE_CLK 227
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1

352
target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch
View File

@ -1,352 +0,0 @@
From 6504bc9edeb1a2a54d813f4bb5d0267e7bf827f9 Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Thu, 6 Feb 2020 17:35:42 +0530
Subject: [PATCH 4/8] clk: ipq8074: Support added for necessary clocks and
reset
Change-Id: I21a76a44185f766e9b6dcba274392ea8e599718b
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 238 ++++++++++++++++++-
include/dt-bindings/clock/qcom,gcc-ipq8074.h | 35 ++-
2 files changed, 258 insertions(+), 15 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -391,6 +391,22 @@ static const struct parent_map gcc_xo_gp
{ P_SLEEP_CLK, 6 },
};
+static const char * const gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
+ "xo",
+ "gpll4",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL6, 3 },
+ { P_GPLL0_DIV2, 4 },
+};
+
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -957,6 +973,12 @@ static const struct freq_tbl ftbl_pcie_a
{ }
};
+struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ { }
+};
+
static struct clk_rcg2 pcie0_axi_clk_src = {
.cmd_rcgr = 0x75054,
.freq_tbl = ftbl_pcie_axi_clk_src,
@@ -2016,6 +2038,78 @@ static struct clk_rcg2 gp3_clk_src = {
},
};
+struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
+ F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
+ F(320000000, P_GPLL0, 2.5, 0, 0),
+ F(600000000, P_GPLL6, 2, 0, 0),
+ { }
+};
+
+struct clk_rcg2 qdss_tsctr_clk_src = {
+ .cmd_rcgr = 0x29064,
+ .freq_tbl = ftbl_qdss_tsctr_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qdss_tsctr_clk_src",
+ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor qdss_dap_sync_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "qdss_dap_sync_clk_src",
+ .parent_names = (const char *[]){
+ "qdss_tsctr_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+struct freq_tbl ftbl_qdss_at_clk_src[] = {
+ F(66670000, P_GPLL0_DIV2, 6, 0, 0),
+ F(240000000, P_GPLL6, 6, 0, 0),
+ { }
+};
+
+struct clk_rcg2 qdss_at_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .freq_tbl = ftbl_qdss_at_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qdss_at_clk_src",
+ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+
+struct freq_tbl ftbl_adss_pwm_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+struct clk_rcg2 adss_pwm_clk_src = {
+ .cmd_rcgr = 0x1c008,
+ .freq_tbl = ftbl_adss_pwm_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "adss_pwm_clk_src",
+ .parent_data = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.clkr = {
@@ -4347,13 +4441,7 @@ static struct clk_branch gcc_gp3_clk = {
},
};
-static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(100000000, P_GPLL0, 8, 0, 0),
- { }
-};
-
-static struct clk_rcg2 pcie0_rchng_clk_src = {
+struct clk_rcg2 pcie0_rchng_clk_src = {
.cmd_rcgr = 0x75070,
.freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5,
@@ -4429,6 +4517,114 @@ static const struct alpha_pll_config nss
.alpha_en_mask = BIT(24),
};
+static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
+ .halt_reg = 0x4700c,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x4700c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_snoc_bus_timeout2_ahb_clk",
+ .parent_names = (const char *[]){
+ "usb0_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = {
+ .halt_reg = 0x47014,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x47014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_snoc_bus_timeout3_ahb_clk",
+ .parent_names = (const char *[]){
+ "usb1_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_clk = {
+ .halt_reg = 0x77004,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x77004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_dcc_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_at_clk = {
+ .halt_reg = 0x29024,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x29024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_at_clk",
+ .parent_names = (const char *[]){
+ "qdss_at_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_clk = {
+ .halt_reg = 0x29084,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x29084,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_dap_clk",
+ .parent_names = (const char *[]){
+ "qdss_dap_sync_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_adss_pwm_clk = {
+ .halt_reg = 0x1c020,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x1c020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_adss_pwm_clk",
+ .parent_names = (const char *[]){
+ "adss_pwm_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_ipq8074_hws[] = {
&gpll0_out_main_div2.hw,
&gpll6_out_main_div2.hw,
@@ -4437,6 +4633,7 @@ static struct clk_hw *gcc_ipq8074_hws[]
&gcc_xo_div4_clk_src.hw,
&nss_noc_clk_src.hw,
&nss_ppe_cdiv_clk_src.hw,
+ &qdss_dap_sync_clk_src.hw,
};
static struct clk_regmap *gcc_ipq8074_clks[] = {
@@ -4668,6 +4865,15 @@ static struct clk_regmap *gcc_ipq8074_cl
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
+ [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
+ [GCC_SNOC_BUS_TIMEOUT3_AHB_CLK] = &gcc_snoc_bus_timeout3_ahb_clk.clkr,
+ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
+ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
+ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -4804,6 +5010,20 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
[GCC_WCSSAON_RESET] = { 0x59010, 0 },
+ [GCC_PPE_FULL_RESET] = { 0x68014, 0, 0xf0000},
+ [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0, 0x3ff2},
+ [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
+ [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0, 0x32},
+ [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
+ [GCC_UNIPHY2_SOFT_RESET] = { 0x56204, 0, 0x32},
+ [GCC_UNIPHY2_XPCS_RESET] = { 0x56204, 2 },
+ [GCC_EDMA_HW_RESET] = { 0x68014, 0, 0x300000},
+ [GCC_NSSPORT1_RESET] = { 0x68014, 0, 0x1000003},
+ [GCC_NSSPORT2_RESET] = { 0x68014, 0, 0x200000c},
+ [GCC_NSSPORT3_RESET] = { 0x68014, 0, 0x4000030},
+ [GCC_NSSPORT4_RESET] = { 0x68014, 0, 0x8000300},
+ [GCC_NSSPORT5_RESET] = { 0x68014, 0, 0x10000c00},
+ [GCC_NSSPORT6_RESET] = { 0x68014, 0, 0x20003000},
};
static const struct of_device_id gcc_ipq8074_match_table[] = {
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -230,10 +230,19 @@
#define GCC_GP1_CLK 221
#define GCC_GP2_CLK 222
#define GCC_GP3_CLK 223
-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
-#define GCC_PCIE0_RCHNG_CLK_SRC 225
-#define GCC_PCIE0_RCHNG_CLK 226
-#define GCC_CRYPTO_PPE_CLK 227
+#define GCC_CRYPTO_PPE_CLK 224
+#define GCC_PCIE0_RCHNG_CLK_SRC 225
+#define GCC_PCIE0_RCHNG_CLK 226
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 227
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 228
+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 229
+#define GCC_DCC_CLK 230
+#define ADSS_PWM_CLK_SRC 231
+#define GCC_ADSS_PWM_CLK 232
+#define QDSS_TSCTR_CLK_SRC 233
+#define QDSS_AT_CLK_SRC 234
+#define GCC_QDSS_AT_CLK 235
+#define GCC_QDSS_DAP_CLK 236
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@@ -368,5 +377,19 @@
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
#define GCC_WCSSAON_RESET 132
+#define GCC_PPE_FULL_RESET 133
+#define GCC_UNIPHY0_SOFT_RESET 134
+#define GCC_UNIPHY0_XPCS_RESET 135
+#define GCC_UNIPHY1_SOFT_RESET 136
+#define GCC_UNIPHY1_XPCS_RESET 137
+#define GCC_UNIPHY2_SOFT_RESET 138
+#define GCC_UNIPHY2_XPCS_RESET 139
+#define GCC_EDMA_HW_RESET 140
+#define GCC_NSSPORT1_RESET 141
+#define GCC_NSSPORT2_RESET 142
+#define GCC_NSSPORT3_RESET 143
+#define GCC_NSSPORT4_RESET 144
+#define GCC_NSSPORT5_RESET 145
+#define GCC_NSSPORT6_RESET 146
#endif

44
target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch
View File

@ -1,44 +0,0 @@
From 462aa0c53397ec5bf78e3e7f68aa8a3ca300f4ba Mon Sep 17 00:00:00 2001
From: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Date: Tue, 24 Mar 2020 19:09:38 +0530
Subject: [PATCH 5/8] clk: qcom: ipq8074: Fix gcc_snoc_bus_timeout_ahb_clk
offset
By default, the ipq8074 V2 clks are provided in the gcc driver.
Updating the gcc_snoc_bus_timeout_ahb_clk offsets also as needed
in ipq8074 V2.
Change-Id: I5a6e98d002f5c3354a804e55dd9ebb1f83f7f974
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4518,10 +4518,10 @@ static const struct alpha_pll_config nss
};
static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
- .halt_reg = 0x4700c,
+ .halt_reg = 0x47014,
.halt_bit = 31,
.clkr = {
- .enable_reg = 0x4700c,
+ .enable_reg = 0x47014,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_snoc_bus_timeout2_ahb_clk",
@@ -4536,10 +4536,10 @@ static struct clk_branch gcc_snoc_bus_ti
};
static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = {
- .halt_reg = 0x47014,
+ .halt_reg = 0x4701C,
.halt_bit = 31,
.clkr = {
- .enable_reg = 0x47014,
+ .enable_reg = 0x4701C,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_snoc_bus_timeout3_ahb_clk",

41
target/linux/ipq807x/patches-5.10/131-arm64-dts-ipq8074-add-SPMI-bus.patch
View File

@ -1,41 +0,0 @@
From 43d5a2b56802327a27a3acb30eb1e458959f5794 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 13 May 2021 11:14:02 +0200
Subject: [PATCH] arm64: dts: ipq8074: add SPMI bus
IPQ8074 has a SPMI v2 arbiter, so add the node
for it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -385,6 +385,25 @@
#reset-cells = <0x1>;
};
+ spmi_bus: qcom,spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x200f000 0x1000>,
+ <0x2400000 0x800000>,
+ <0x2c00000 0x800000>,
+ <0x3800000 0x200000>,
+ <0x200a000 0x000700>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
sdhc_1: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;

38
target/linux/ipq807x/patches-5.10/132-regulator-qcom_spmi-Add-PMD9655-SPMI-regulator.patch
View File

@ -1,38 +0,0 @@
From 43361c2201bc9b67ee42a6afab7a3a476eaf6156 Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Tue, 31 Mar 2020 22:00:27 +0530
Subject: [PATCH 1/6] regulator: qcom_spmi: Add PMD9655 SPMI regulator
PMD9655 is used in IPQ8074 and provides S3 for cores,
S4 for UBI core and LDO11 for SDIO/eMMC.
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/regulator/qcom_spmi-regulator.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -2082,6 +2082,13 @@ static const struct spmi_regulator_data
{ }
};
+static const struct spmi_regulator_data pmd9655_regulators[] = {
+ { "s3", 0x1a00, "vdd_s3",},
+ { "s4", 0x1d00, "vdd_s4",},
+ { "ldo11", 0x4a00, "vdd_ldo11",},
+ { }
+};
+
static const struct of_device_id qcom_spmi_regulator_match[] = {
{ .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators },
{ .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators },
@@ -2094,6 +2101,7 @@ static const struct of_device_id qcom_sp
{ .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
{ .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
{ .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
+ { .compatible = "qcom,pmd9655-regulators", .data = &pmd9655_regulators },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);

22
target/linux/ipq807x/patches-5.10/133-regulator-qcom_spmi-SMPS-range-is-added-to-support-P.patch
View File

@ -1,22 +0,0 @@
From 095567c1736af28ef6b472e2ab728a2222a425da Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Mon, 4 May 2020 19:31:00 +0530
Subject: [PATCH 2/6] regulator: qcom_spmi: SMPS range is added to support
PMD9655 PMIC
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: I5571801debec25527fd763d95aff27cc42f53bde
---
drivers/regulator/qcom_spmi-regulator.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -480,6 +480,7 @@ static struct spmi_voltage_range ln_ldo_
};
static struct spmi_voltage_range smps_ranges[] = {
+ SPMI_VOLTAGE_RANGE(2, 670000, 670000, 990000, 990000, 8000),
SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
};

35
target/linux/ipq807x/patches-5.10/134-regulator-qcom_spmi-Initialize-slew-rate-only-if-req.patch
View File

@ -1,35 +0,0 @@
From 0890aba3f364ed0764fdfa79bd77db130396e594 Mon Sep 17 00:00:00 2001
From: PRAVEENKUMAR I <ipkumar@codeaurora.org>
Date: Tue, 5 May 2020 07:57:21 +0530
Subject: [PATCH 3/6] regulator: qcom_spmi: Initialize slew rate only if
required
Initialize slew rate only if set_voltage_time_sel in ops
is defined.
Change-Id: I661c88d2f4a8f26cc85b1e2d4c8aa3170420ba6c
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
(cherry picked from commit 608a6f171ef4017197fbe2069b5910b582923027)
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: Ida3cf3d754e1207e34a164d6d86c6e1aa109ef1e
---
drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -1610,6 +1610,13 @@ static int spmi_regulator_init_slew_rate
int step, delay, slew_rate, step_delay;
const struct spmi_voltage_range *range;
+ /*
+ * Slew rate need not be initialized if
+ * set_voltage_time_sel in the ops is not defined.
+ */
+ if (!vreg->desc.ops->set_voltage_time_sel)
+ return 0;
+
ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
if (ret) {
dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);

159
target/linux/ipq807x/patches-5.10/135-regulator-qcom_spmi-Add-support-for-VMPWM_CTL-subtyp.patch
View File

@ -1,159 +0,0 @@
From 50b5c040b8c1928990baad8e07126df63aa09cce Mon Sep 17 00:00:00 2001
From: PRAVEENKUMAR I <ipkumar@codeaurora.org>
Date: Tue, 5 May 2020 07:57:52 +0530
Subject: [PATCH 4/6] regulator: qcom_spmi: Add support for VMPWM_CTL subtype
Support for Voltage Mode PWM Controller (VMPWM_CTL).
Set/Get microvolts functions added. Function to find the
voltage range for this particular subtype added.
Change-Id: Ib4bf35ee65de17a917f01e63208368c7770401d4
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
(cherry picked from commit 31e7e4183b5afaf18dbca3548f4988c420ebb58b)
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: Id7a3caef84499b9e2eefda9f57576923c84234f0
---
drivers/regulator/qcom_spmi-regulator.c | 82 +++++++++++++++++++++++++
1 file changed, 82 insertions(+)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -163,6 +163,7 @@ enum spmi_regulator_subtype {
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
+ SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a,
};
enum spmi_common_regulator_registers {
@@ -288,6 +289,10 @@ enum spmi_common_control_register_index
#define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
#define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
+#define SPMI_SMPS_VMPWM_VSET_UB_SHIFT 8
+#define SPMI_SMPS_VMPWM_VSET_UB_MASK 0xf00
+#define SPMI_SMPS_VMPWM_VSET_LB_MASK 0xff
+
/* Clock rate in kHz of the FTSMPS regulator reference clock. */
#define SPMI_FTSMPS_CLOCK_RATE 19200
@@ -485,6 +490,10 @@ static struct spmi_voltage_range smps_ra
SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
};
+static struct spmi_voltage_range smps_vmpwm_ranges[] = {
+ SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000),
+};
+
static struct spmi_voltage_range ftsmps_ranges[] = {
SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
@@ -550,6 +559,7 @@ static DEFINE_SPMI_SET_POINTS(nldo2);
static DEFINE_SPMI_SET_POINTS(nldo3);
static DEFINE_SPMI_SET_POINTS(ln_ldo);
static DEFINE_SPMI_SET_POINTS(smps);
+static DEFINE_SPMI_SET_POINTS(smps_vmpwm);
static DEFINE_SPMI_SET_POINTS(ftsmps);
static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
static DEFINE_SPMI_SET_POINTS(ftsmps426);
@@ -740,6 +750,24 @@ spmi_regulator_find_range(struct spmi_re
return NULL;
}
+static const struct spmi_voltage_range *
+spmi_regulator_find_uV_range(struct spmi_regulator *vreg, int min, int max)
+{
+ const struct spmi_voltage_range *range, *end;
+
+ if (!vreg->set_points || !vreg->set_points->count)
+ return 0;
+
+ range = vreg->set_points->range;
+ end = range + vreg->set_points->count;
+
+ for (; range < end; range++)
+ if ((range->min_uV <= min) && (range->max_uV >= max))
+ return range;
+
+ return 0;
+}
+
static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
int min_uV, int max_uV)
{
@@ -961,6 +989,47 @@ static int spmi_regulator_ult_lo_smps_ge
return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
}
+static int spmi_regulator_smps_vmpwm_set_vol_uV(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
+ const struct spmi_voltage_range *range;
+ int req_vol;
+ u8 reg[2];
+
+ range = spmi_regulator_find_uV_range(vreg, min_uV, max_uV);
+ if (!range)
+ return -EINVAL;
+
+ *selector = spmi_regulator_select_voltage(vreg, min_uV, max_uV);
+ req_vol = range->set_point_min_uV + (range->step_uV * (*selector));
+
+ /* Convert uV to mV as the register supports mV */
+ req_vol = req_vol/1000;
+
+ /*
+ * Voltage set point bits<7:0>. 2-Byte Word (lower byte word)
+ */
+ reg[0] = req_vol & SPMI_SMPS_VMPWM_VSET_LB_MASK;
+ /*
+ * Voltage set point bit <11:8>. 2-Byte Word (upper byte word)
+ */
+ reg[1] = (req_vol & SPMI_SMPS_VMPWM_VSET_UB_MASK)
+ >> SPMI_SMPS_VMPWM_VSET_UB_SHIFT;
+
+ return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, reg, 2);
+}
+
+static int spmi_regulator_smps_vmpwm_get_vol_uV(struct regulator_dev *rdev)
+{
+ struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
+ u8 reg[2];
+
+ spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, reg, 2);
+
+ return ((reg[1] << SPMI_SMPS_VMPWM_VSET_UB_SHIFT) | reg[0]) * 1000;
+}
+
static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
unsigned selector)
{
@@ -1309,6 +1378,18 @@ static const struct regulator_ops spmi_s
.set_pull_down = spmi_regulator_common_set_pull_down,
};
+static const struct regulator_ops spmi_smps_vmpwm_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_voltage = spmi_regulator_smps_vmpwm_set_vol_uV,
+ .get_voltage = spmi_regulator_smps_vmpwm_get_vol_uV,
+ .map_voltage = spmi_regulator_common_map_voltage,
+ .list_voltage = spmi_regulator_common_list_voltage,
+ .set_mode = spmi_regulator_common_set_mode,
+ .get_mode = spmi_regulator_common_get_mode,
+};
+
static const struct regulator_ops spmi_ldo_ops = {
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
@@ -1454,6 +1535,7 @@ static const struct regulator_ops spmi_h
static const struct spmi_regulator_mapping supported_regulators[] = {
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
+ SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0),
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),

53
target/linux/ipq807x/patches-5.10/136-ipq807x-sdhc-Fixed-SDR104-mode-card-detection.patch
View File

@ -1,53 +0,0 @@
From 84d0ae645dc1c3d8726bf8cd482be052f915f00b Mon Sep 17 00:00:00 2001
From: Vasudevan Murugesan <vmuruges@codeaurora.org>
Date: Thu, 8 Jun 2017 19:13:48 +0530
Subject: [PATCH 5/6] ipq807x: sdhc: Fixed SDR104 mode card detection
Change-Id: I353356284d28d09d79bf7d318c4ebcdbc15e5b02
Signed-off-by: Vasudevan Murugesan <vmuruges@codeaurora.org>
Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
(cherry picked from commit 080d3f390aa409ef2b5adf59a175b6bb2aa863fd)
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: Ie5edb7b3d972e06f3eb2525e10597b49e9bae14d
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
drivers/regulator/qcom_spmi-regulator.c | 3 +++
2 files changed, 3 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -425,7 +425,6 @@
status = "disabled";
};
-
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x2b000>;
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -164,6 +164,7 @@ enum spmi_regulator_subtype {
SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
SPMI_REGULATOR_SUBTYPE_VMPWM_CTL = 0x0a,
+ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
};
enum spmi_common_regulator_registers {
@@ -492,6 +493,7 @@ static struct spmi_voltage_range smps_ra
static struct spmi_voltage_range smps_vmpwm_ranges[] = {
SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000),
+ SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000),
};
static struct spmi_voltage_range ftsmps_ranges[] = {
@@ -1535,6 +1537,7 @@ static const struct regulator_ops spmi_h
static const struct spmi_regulator_mapping supported_regulators[] = {
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
+ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0),
SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0),
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),

49
target/linux/ipq807x/patches-5.10/137-ipq807x-spmi-regulator-Add-separate-voltage-range-fo.patch
View File

@ -1,49 +0,0 @@
From c603c7a1e2d5cc432d8e1250baff8130755a6f43 Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Mon, 13 Jul 2020 18:13:48 +0530
Subject: [PATCH 6/6] ipq807x: spmi regulator: Add separate voltage range for
LDO
When LDO voltage range added in SMPS voltage range structure,
selector value used during set voltage is wrongly calculated.
Because the SMPS voltage range is also taken into account for LDO.
So, a separate voltage range structure is introduced for LDO.
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: I883518ae0686762a3774750b1dd480c4fe7298f3
---
drivers/regulator/qcom_spmi-regulator.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
--- a/drivers/regulator/qcom_spmi-regulator.c
+++ b/drivers/regulator/qcom_spmi-regulator.c
@@ -493,7 +493,10 @@ static struct spmi_voltage_range smps_ra
static struct spmi_voltage_range smps_vmpwm_ranges[] = {
SPMI_VOLTAGE_RANGE(0, 664000, 664000, 1104000, 1104000, 8000),
- SPMI_VOLTAGE_RANGE(1, 1104000, 1104000, 3300000, 3300000, 8000),
+};
+
+static struct spmi_voltage_range ldo_vmpwm_ranges[] = {
+ SPMI_VOLTAGE_RANGE(0, 1104000, 1104000, 3300000, 3300000, 8000),
};
static struct spmi_voltage_range ftsmps_ranges[] = {
@@ -562,6 +565,7 @@ static DEFINE_SPMI_SET_POINTS(nldo3);
static DEFINE_SPMI_SET_POINTS(ln_ldo);
static DEFINE_SPMI_SET_POINTS(smps);
static DEFINE_SPMI_SET_POINTS(smps_vmpwm);
+static DEFINE_SPMI_SET_POINTS(ldo_vmpwm);
static DEFINE_SPMI_SET_POINTS(ftsmps);
static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
static DEFINE_SPMI_SET_POINTS(ftsmps426);
@@ -1537,7 +1541,7 @@ static const struct regulator_ops spmi_h
static const struct spmi_regulator_mapping supported_regulators[] = {
/* type subtype dig_min dig_max ltype ops setpoints hpm_min */
- SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, smps_vmpwm, 0),
+ SPMI_VREG(LDO, HT_P150, 0, INF, LDO, smps_vmpwm, ldo_vmpwm, 0),
SPMI_VREG(BUCK, VMPWM_CTL, 0, INF, SMPS, smps_vmpwm, smps_vmpwm, 0),
SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),

84
target/linux/ipq807x/patches-5.10/138-arm64-dts-ipq8074-add-SPMI-PMIC-regulators.patch
View File

@ -1,84 +0,0 @@
From df848f06020c609950107f87c39f41e7eee92b5e Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 13 May 2021 11:54:35 +0200
Subject: [PATCH] arm64: dts: ipq8074: add SPMI PMIC regulators
PMD9655 is used in IPQ8074 and provides S3 for cores,
S4 for UBI core and LDO11 for SDIO/eMMC.
So, lets add the nodes in preparation for DVFS later.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/spmi/spmi.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8074";
@@ -136,6 +137,15 @@
};
};
+ e_smps1_reg: fixed-regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "e-smps1-reg";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
soc: soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -402,6 +412,42 @@
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
+
+ pmic@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulators {
+ compatible = "qcom,pmd9655-regulators";
+ vdd_s3-supply = <&e_smps1_reg>;
+ vdd_s4-supply = <&e_smps1_reg>;
+ vdd_ldo11-supply = <&e_smps1_reg>;
+
+ s3: s3 {
+ regulator-name = "pmd9655_s3";
+ regulator-min-microvolt = <592000>;
+ regulator-max-microvolt = <1064000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ s4: s4 {
+ regulator-name = "pmd9655_s4";
+ regulator-min-microvolt = <712000>;
+ regulator-max-microvolt = <992000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo11: ldo11 {
+ regulator-name = "pmd9655_ldo11";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
};
sdhc_1: sdhci@7824900 {

328
target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch
View File

@ -1,328 +0,0 @@
From 6961b02dd2765b71b201f065172998a16ff9c2eb Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Sun, 22 Mar 2020 20:22:29 +0530
Subject: [PATCH 1/3] ipq8074: clk: apss: Added APSS clock driver
apss-ipq8074 files are snapshot form eggplant branch,
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/commit/?h=keggplant/eggplant&id=f2fb70e8315ef1c450171e59d681c6a156b1a4e8
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: I17ecad1f1731c88d8d91485d5d5f8a38b76f7104
---
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq8074.c | 210 +++++++++++++++++++
drivers/clk/qcom/clk-alpha-pll.c | 12 ++
drivers/clk/qcom/clk-alpha-pll.h | 3 +
include/dt-bindings/clock/qca,apss-ipq8074.h | 25 +++
6 files changed, 258 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq8074.c
create mode 100644 include/dt-bindings/clock/qca,apss-ipq8074.h
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -156,6 +156,13 @@ config IPQ_GCC_8074
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq8074.
+config IPQ_APSS_8074
+ tristate "IPQ8074 APSS Clock Controller"
+ select IPQ_GCC_8074
+ help
+ Support for APSS clock controller on ipq8074 devices.
+ Say Y if you want to use APSS clocks such as CPU.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
help
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq401
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
+obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq8074.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2017,2020. The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include <linux/reset-controller.h>
+#include <dt-bindings/clock/qca,apss-ipq8074.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPLL2,
+ P_GPLL4,
+ P_APSS_PLL_EARLY,
+ P_APSS_PLL
+};
+
+static struct clk_alpha_pll apss_pll_early = {
+ .offset = 0x5000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS],
+ .clkr = {
+ .enable_reg = 0x5000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apss_pll_early",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv apss_pll = {
+ .offset = 0x5000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS],
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apss_pll",
+ .parent_names = (const char *[]){ "apss_pll_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
+static const char * const parents_apcs_alias0_clk_src[] = {
+ "xo",
+ "gpll0",
+ "gpll2",
+ "gpll4",
+ "apss_pll",
+ "apss_pll_early",
+};
+
+static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 4 },
+ { P_GPLL2, 2 },
+ { P_GPLL4, 1 },
+ { P_APSS_PLL, 3 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+struct freq_tbl ftbl_apcs_alias0_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(403200000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(806400000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0),
+ F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0),
+ { }
+};
+
+struct clk_rcg2 apcs_alias0_clk_src = {
+ .cmd_rcgr = 0x0050,
+ .freq_tbl = ftbl_apcs_alias0_clk_src,
+ .hid_width = 5,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_names = parents_apcs_alias0_clk_src,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apcs_alias0_core_clk = {
+ .halt_reg = 0x0058,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x0058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_core_clk",
+ .parent_names = (const char *[]){
+ "apcs_alias0_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT |
+ CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *apss_ipq807x_clks[] = {
+ [APSS_PLL_EARLY] = &apss_pll_early.clkr,
+ [APSS_PLL] = &apss_pll.clkr,
+ [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
+ [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
+};
+
+static const struct of_device_id apss_ipq807x_match_table[] = {
+ { .compatible = "qcom,apss-ipq807x" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, apss_ipq807x_match_table);
+
+static const struct regmap_config apss_ipq807x_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x5ffc,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc apss_ipq807x_desc = {
+ .config = &apss_ipq807x_regmap_config,
+ .clks = apss_ipq807x_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq807x_clks),
+};
+
+static int apss_ipq807x_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = qcom_cc_probe(pdev, &apss_ipq807x_desc);
+
+ dev_dbg(&pdev->dev, "Registered ipq807x apss clock provider\n");
+
+ return ret;
+}
+
+static int apss_ipq807x_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver apss_ipq807x_driver = {
+ .probe = apss_ipq807x_probe,
+ .remove = apss_ipq807x_remove,
+ .driver = {
+ .name = "qcom,apss-ipq807x",
+ .owner = THIS_MODULE,
+ .of_match_table = apss_ipq807x_match_table,
+ },
+};
+
+static int __init apss_ipq807x_init(void)
+{
+ return platform_driver_register(&apss_ipq807x_driver);
+}
+core_initcall(apss_ipq807x_init);
+
+static void __exit apss_ipq807x_exit(void)
+{
+ platform_driver_unregister(&apss_ipq807x_driver);
+}
+module_exit(apss_ipq807x_exit);
+
+MODULE_DESCRIPTION("QCA APSS IPQ807x Driver");
+MODULE_LICENSE("Dual BSD/GPLv2");
+MODULE_ALIAS("platform:apss-ipq807x");
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -116,6 +116,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MA
[PLL_OFF_OPMODE] = 0x38,
[PLL_OFF_ALPHA_VAL] = 0x40,
},
+ [CLK_ALPHA_PLL_TYPE_APSS] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_ALPHA_VAL_U] = 0xff,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_USER_CTL_U] = 0xff,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+ [PLL_OFF_STATUS] = 0x28,
+ }
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -15,6 +15,7 @@ enum {
CLK_ALPHA_PLL_TYPE_FABIA,
CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
+ CLK_ALPHA_PLL_TYPE_APSS,
CLK_ALPHA_PLL_TYPE_MAX,
};
@@ -69,6 +70,8 @@ struct clk_alpha_pll {
#define SUPPORTS_OFFLINE_REQ BIT(0)
#define SUPPORTS_FSM_MODE BIT(2)
#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
+
+
u8 flags;
struct clk_regmap clkr;
--- /dev/null
+++ b/include/dt-bindings/clock/qca,apss-ipq8074.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017,2020. The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H
+#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H
+
+#define APSS_PLL_EARLY 0
+#define APSS_PLL 1
+#define APCS_ALIAS0_CLK_SRC 2
+#define APCS_ALIAS0_CORE_CLK 3
+
+#endif

105
target/linux/ipq807x/patches-5.10/140-clk-qcom-ipq8074-make-apss-clock-as-child-of-mailbox.patch
View File

@ -1,105 +0,0 @@
From b5c28ea3b9a963d425ae88ef53d266ff8ae95bc2 Mon Sep 17 00:00:00 2001
From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Date: Fri, 24 Apr 2020 23:05:50 +0530
Subject: [PATCH 2/3] clk: qcom: ipq8074: make apss clock as child of mailbox
both apcs mailbox and apss clock controller access the same register
space, resource request will fail for one of the two drivers.
to resolve this make apss clock controller as child of mailbox, the apss
clock controller will use mailbox regmap for resource request and probe.
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Change-Id: Ic26ee78b6f680fa0655a73d3176bae271725ab05
---
drivers/clk/qcom/apss-ipq8074.c | 14 ++++++--------
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 18 +++++++++++++++---
2 files changed, 21 insertions(+), 11 deletions(-)
--- a/drivers/clk/qcom/apss-ipq8074.c
+++ b/drivers/clk/qcom/apss-ipq8074.c
@@ -147,12 +147,6 @@ static struct clk_regmap *apss_ipq807x_c
[APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
};
-static const struct of_device_id apss_ipq807x_match_table[] = {
- { .compatible = "qcom,apss-ipq807x" },
- { }
-};
-MODULE_DEVICE_TABLE(of, apss_ipq807x_match_table);
-
static const struct regmap_config apss_ipq807x_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -170,8 +164,13 @@ static const struct qcom_cc_desc apss_ip
static int apss_ipq807x_probe(struct platform_device *pdev)
{
int ret;
+ struct regmap *regmap;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
- ret = qcom_cc_probe(pdev, &apss_ipq807x_desc);
+ ret = qcom_cc_really_probe(pdev, &apss_ipq807x_desc, regmap);
dev_dbg(&pdev->dev, "Registered ipq807x apss clock provider\n");
@@ -189,7 +188,6 @@ static struct platform_driver apss_ipq80
.driver = {
.name = "qcom,apss-ipq807x",
.owner = THIS_MODULE,
- .of_match_table = apss_ipq807x_match_table,
},
};
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -65,7 +65,7 @@ static const struct regmap_config apcs_r
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
- .max_register = 0xFFC,
+ .max_register = 0x5FFC,
.fast_io = true,
};
@@ -82,6 +82,16 @@ static const struct mbox_chan_ops qcom_a
.send_data = qcom_apcs_ipc_send_data,
};
+static const struct of_device_id apcs_clk_match_table[] = {
+ { .compatible = "qcom,msm8916-apcs-kpss-global",
+ . data = "qcom-apcs-msm8916-clk", },
+ { .compatible = "qcom,qcs404-apcs-apps-global",
+ .data = "qcom-apcs-msm8916-clk", },
+ { .compatible = "qcom,ipq8074-apcs-apps-global",
+ .data = "qcom,apss-ipq807x", },
+ {}
+};
+
static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{
struct qcom_apcs_ipc *apcs;
@@ -91,6 +101,7 @@ static int qcom_apcs_ipc_probe(struct pl
void __iomem *base;
unsigned long i;
int ret;
+ const struct of_device_id *device_id;
apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
if (!apcs)
@@ -125,9 +136,10 @@ static int qcom_apcs_ipc_probe(struct pl
return ret;
}
- if (apcs_data->clk_name) {
+ device_id = of_match_device(apcs_clk_match_table, &pdev->dev);
+ if (device_id) {
apcs->clk = platform_device_register_data(&pdev->dev,
- apcs_data->clk_name,
+ device_id->data,
PLATFORM_DEVID_AUTO,
NULL, 0);
if (IS_ERR(apcs->clk))

70
target/linux/ipq807x/patches-5.10/141-arm64-dts-ipq8074-add-APPS-CPU-clock.patch
View File

@ -1,70 +0,0 @@
From 99841b41e13b4a0512de1e06191cdcaf7ee0e1d1 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 13 May 2021 12:42:05 +0200
Subject: [PATCH 3/3] arm64: dts: ipq8074: add APPS CPU clock
In preparation for frequency scaling add the APPS
clock support.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/clock/qca,apss-ipq8074.h>
#include <dt-bindings/spmi/spmi.h>
/ {
@@ -33,6 +34,8 @@
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
next-level-cache = <&L2_0>;
enable-method = "psci";
};
@@ -42,6 +45,8 @@
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
next-level-cache = <&L2_0>;
};
@@ -50,6 +55,8 @@
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
next-level-cache = <&L2_0>;
};
@@ -58,6 +65,8 @@
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
+ clock-names = "cpu";
next-level-cache = <&L2_0>;
};
@@ -897,8 +906,9 @@
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq8074-apcs-apps-global";
- reg = <0x0b111000 0x1000>;
+ reg = <0x0b111000 0x6000>;
+ #clock-cells = <1>;
#mbox-cells = <1>;
};

26
target/linux/ipq807x/patches-5.10/142-arm64-dts-ipq8074-add-label-to-cpus.patch
View File

@ -1,26 +0,0 @@
From fb5a1fff750f99dbf7cabda0de9fbf7463a07586 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 13 May 2021 13:13:46 +0200
Subject: [PATCH] arm64: dts: ipq8074: add label to cpus
Add label to cpus node as that makes it
easy to add OPP table in SoC model specific
DTSI as IPQ8074 family has differing clocks
and voltages based on model.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -26,7 +26,7 @@
};
};
- cpus {
+ cpus: cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;

133
target/linux/ipq807x/patches-5.10/143-arm64-dts-ipq8074-Add-WLAN-node.patch
View File

@ -1,133 +0,0 @@
From 0fb054684bdf40f17ab59226dae21ddfe0d79466 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Thu, 13 May 2021 15:15:46 +0200
Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
IPQ8074 is supported by ath11k, so add the required
DT node.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
1 file changed, 111 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -962,6 +962,117 @@
};
};
+ wifi: wifi@c0000000 {
+ compatible = "qcom,ipq8074-wifi";
+ reg = <0xc000000 0x2000000>;
+
+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "misc-pulse1",
+ "misc-latch",
+ "sw-exception",
+ "ce0",
+ "ce1",
+ "ce2",
+ "ce3",
+ "ce4",
+ "ce5",
+ "ce6",
+ "ce7",
+ "ce8",
+ "ce9",
+ "ce10",
+ "ce11",
+ "host2wbm-desc-feed",
+ "host2reo-re-injection",
+ "host2reo-command",
+ "host2rxdma-monitor-ring3",
+ "host2rxdma-monitor-ring2",
+ "host2rxdma-monitor-ring1",
+ "reo2ost-exception",
+ "wbm2host-rx-release",
+ "reo2host-status",
+ "reo2host-destination-ring4",
+ "reo2host-destination-ring3",
+ "reo2host-destination-ring2",
+ "reo2host-destination-ring1",
+ "rxdma2host-monitor-destination-mac3",
+ "rxdma2host-monitor-destination-mac2",
+ "rxdma2host-monitor-destination-mac1",
+ "ppdu-end-interrupts-mac3",
+ "ppdu-end-interrupts-mac2",
+ "ppdu-end-interrupts-mac1",
+ "rxdma2host-monitor-status-ring-mac3",
+ "rxdma2host-monitor-status-ring-mac2",
+ "rxdma2host-monitor-status-ring-mac1",
+ "host2rxdma-host-buf-ring-mac3",
+ "host2rxdma-host-buf-ring-mac2",
+ "host2rxdma-host-buf-ring-mac1",
+ "rxdma2host-destination-ring-mac3",
+ "rxdma2host-destination-ring-mac2",
+ "rxdma2host-destination-ring-mac1",
+ "host2tcl-input-ring4",
+ "host2tcl-input-ring3",
+ "host2tcl-input-ring2",
+ "host2tcl-input-ring1",
+ "wbm2host-tx-completions-ring3",
+ "wbm2host-tx-completions-ring2",
+ "wbm2host-tx-completions-ring1",
+ "tcl2host-status-ring";
+ qcom,rproc = <&q6v5_wcss>;
+ status = "disabled";
+ };
+
ess_switch: ess-switch@3a000000 {
compatible = "qcom,ess-switch-ipq807x";
reg = <0x3a000000 0x1000000>;

28
target/linux/ipq807x/patches-5.10/144-arm64-dts-ipq8074-add-NSS-reserved-memory-node.patch
View File

@ -1,28 +0,0 @@
From 22865119dada2a40a5e5e8c5f22b5bec08651021 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 14 May 2021 19:43:41 +0200
Subject: [PATCH] arm64: dts: ipq8074: add NSS reserved memory node
NSS FW has its own dedicated memory it needs to get loaded to.
Since it simply uses ioremap() that memory must be reserved
so the kernel will allow using ioremap() on it.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -91,6 +91,11 @@
#size-cells = <2>;
ranges;
+ nss@40000000 {
+ no-map;
+ reg = <0x0 0x40000000 0x0 0x01000000>;
+ };
+
smem_region: memory@4ab00000 {
no-map;
reg = <0x0 0x4ab00000 0x0 0x00100000>;

29
target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch
View File

@ -1,29 +0,0 @@
From a801cc475f0d1fdf29d7b6b56d64df090bf83f8d Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Fri, 3 Apr 2020 12:57:37 +0530
Subject: [PATCH] clk: qcom: ipq8074: disable SW_COLLAPSE for USB GDSCR's
Change-Id: Id347be781e2bb449bd7cdf05e3535e8ca3c3ffd6
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
(cherry picked from commit 5e100df9c29ed7e5ad12583aa39053f4a9761efe)
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Change-Id: I17beca334be79d738a35587860847aa0b1f96fa9
---
drivers/clk/qcom/gcc-ipq8074.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -5061,6 +5061,11 @@ static int gcc_ipq8074_probe(struct plat
/* SW Workaround for UBI32 Huayra PLL */
regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
+ /* Disable SW_COLLAPSE for USB0 GDSCR */
+ regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0);
+ /* Disable SW_COLLAPSE for USB1 GDSCR */
+ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
+
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);

46
target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch
View File

@ -1,46 +0,0 @@
From 5f707d3ff1b22c089253e39906b5edeeb5f10fdc Mon Sep 17 00:00:00 2001
From: Praveenkumar I <ipkumar@codeaurora.org>
Date: Fri, 3 Apr 2020 15:31:59 +0530
Subject: [PATCH] clk: qcom: ipq8074: SW workaround for UBI PLL lock
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Some chip’s Huyara PLL is unable to lock in 5 us and
generating UBI PLL lock error.
WARNING: CPU: 1 PID: 625 at drivers/clk/qcom/clk-alpha-pll.c:114
wait_for_pll+0xbc/0xe0()
ubi32_pll_main failed to enable!
CPU: 1 PID: 625 Comm: kmodloader Not tainted 4.4.60 #1
Hardware name: Generic DT based system
(unwind_backtrace) from [<8021b550>] (show_stack+0x10/0x14)
(show_stack) from [<803f6b24>] (dump_stack+0x80/0xa0)
(dump_stack) from [<80228ff0>] (warn_slowpath_common+0x84/0xb0)
(warn_slowpath_common) from [<80229048>] (warn_slowpath_fmt+0x2c/0x3c)
(warn_slowpath_fmt) from [<8054d53c>] (wait_for_pll+0xbc/0xe0)
(wait_for_pll) from [<8054d6cc>] (clk_alpha_pll_enable+0xe0/0x128)
(clk_alpha_pll_enable) from [<80547b68>] (clk_core_enable+0x68/0x98)
(clk_core_enable) from [<80547b48>] (clk_core_enable+0x48/0x98)
This is BUG in Huayra PLL HW for which SW workaround
is to set bit 26 of TEST_CTL register.
Change-Id: Ib5473f4011e3410515f382b2445bee2d66dd654a
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq8074.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -5066,6 +5066,9 @@ static int gcc_ipq8074_probe(struct plat
/* Disable SW_COLLAPSE for USB1 GDSCR */
regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);
+ /* SW Workaround for UBI Huayra PLL */
+ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
+
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);

41
target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch
View File

@ -1,41 +0,0 @@
From 52315bec6ed633b6a71f28b746029602f8bd70b9 Mon Sep 17 00:00:00 2001
From: Balaji Prakash J <bjagadee@codeaurora.org>
Date: Wed, 22 Apr 2020 20:35:30 +0530
Subject: [PATCH] clk: ipq8074: fix gcc_blsp1_ahb_clk properties
All the voting enabled clocks does not support the enable
from CBCR register. So, updated gcc_blsp1_ahb_clk enable
register and mask to enable bit in APCS_CLOCK_BRANCH_ENA_VOTE.
Also, the voting controlled clocks are shared among multiple
components like APSS, RPM, NSS, TZ, etc. So, turning the
voting off from APSS does not make the clock off if it has
been voted from another component. Added the flag
BRANCH_HALT_VOTED in order to skip checking the clock
disable status.
This change is referred from the below commits,
1. 246b4fb3af9bd65d8af794aac2f0e7b1ed9cc2dd
2. c8374157d5ae91d3b3e0d513d62808a798b32d3a
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230
---
drivers/clk/qcom/gcc-ipq8074.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -2112,9 +2112,10 @@ struct clk_rcg2 adss_pwm_clk_src = {
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
+ .halt_check = BRANCH_HALT_VOTED,
.clkr = {
- .enable_reg = 0x01008,
- .enable_mask = BIT(0),
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_ahb_clk",
.parent_names = (const char *[]){

47
target/linux/ipq807x/patches-5.10/149-remoteproc-wcss-disable-auto-boot-for-IPQ8074.patch
View File

@ -1,47 +0,0 @@
From 256eda666b4687c5242b9f075caf4e09ad642daa Mon Sep 17 00:00:00 2001
From: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Date: Fri, 17 Apr 2020 16:37:10 +0530
Subject: [PATCH] remoteproc: wcss: disable auto boot for IPQ8074
auto boot is disabled for IPQ8074 the wifi driver brings up the wcss.
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Change-Id: Ia82edb7ee52f2bd010c099f151179d69a953ac88
---
drivers/remoteproc/qcom_q6v5_wcss.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -161,6 +161,7 @@ struct wcss_data {
const struct rproc_ops *ops;
bool requires_force_stop;
bool need_mem_protection;
+ bool need_auto_boot;
};
static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -1147,6 +1148,7 @@ static int q6v5_wcss_probe(struct platfo
desc->sysmon_name,
desc->ssctl_id);
+ rproc->auto_boot = desc->need_auto_boot;
ret = rproc_add(rproc);
if (ret)
goto free_rproc;
@@ -1183,6 +1185,7 @@ static const struct wcss_data wcss_ipq80
.ops = &q6v5_wcss_ipq8074_ops,
.requires_force_stop = true,
.need_mem_protection = true,
+ .need_auto_boot = false,
};
static const struct wcss_data wcss_qcs404_res_init = {
@@ -1199,6 +1202,7 @@ static const struct wcss_data wcss_qcs40
.ssctl_id = 0x12,
.ops = &q6v5_wcss_qcs404_ops,
.requires_force_stop = false,
+ .need_auto_boot = true,
};
static const struct of_device_id q6v5_wcss_of_match[] = {

65
target/linux/ipq807x/patches-5.10/150-arm64-dts-ipq8074-add-missing-reserved-memory-nodes.patch
View File

@ -1,65 +0,0 @@
From 158bd87b3db04bdd1effe4a92424f9572224a6c3 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 15 May 2021 00:09:21 +0200
Subject: [PATCH] arm64: dts: ipq8074: add missing reserved memory nodes
Downstream kernel has more reserved memory nodes.
Without these ath11k will cause a board reset.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 36 +++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -96,15 +96,47 @@
reg = <0x0 0x40000000 0x0 0x01000000>;
};
- smem_region: memory@4ab00000 {
+ tzapp: tzapp@4a400000 {
+ no-map;
+ reg = <0x0 0x4a400000 0x0 0x00200000>;
+ };
+
+
+ uboot@4a600000 {
+ no-map;
+ reg = <0x0 0x4a600000 0x0 0x00400000>;
+ };
+
+ sbl@4aa00000 {
+ no-map;
+ reg = <0x0 0x4aa00000 0x0 0x00100000>;
+ };
+
+ smem_region: smem@4ab00000 {
no-map;
reg = <0x0 0x4ab00000 0x0 0x00100000>;
};
- q6_region: memory@4b000000 {
+ tz@4ac00000 {
+ no-map;
+ reg = <0x0 0x4ac00000 0x0 0x00400000>;
+ };
+
+ q6_region: wcnss@4b000000 {
no-map;
reg = <0x0 0x4b000000 0x0 0x05f00000>;
};
+
+ q6_etr_region: q6_etr_dump@50f00000 {
+ no-map;
+ reg = <0x0 0x50f00000 0x0 0x00100000>;
+ };
+
+ m3_dump@51000000 {
+ no-map;
+ reg = <0x0 0x51000000 0x0 0x100000>;
+ };
+
};
firmware {

24
target/linux/ipq807x/patches-5.10/151-arm64-dts-ipq8074-add-q6_etr-memory-region-to-remote.patch
View File

@ -1,24 +0,0 @@
From 86aa6afcf280a61150a3e6c796f629d09db88d55 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 15 May 2021 00:18:32 +0200
Subject: [PATCH] arm64: dts: ipq8074: add q6_etr memory region to remoteproc
Q6v5 remoteprocessor also has a q6_etr memor region
reserved for it, so add it to the node.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -986,7 +986,7 @@
qcom,smem-state-names = "shutdown",
"stop";
- memory-region = <&q6_region>;
+ memory-region = <&q6_region>, <&q6_etr_region>;
glink-edge {
interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;

99
target/linux/ipq807x/patches-5.10/152-thermal-qcom-tsens-Add-IPQ8074-support.patch
View File

@ -1,99 +0,0 @@
From 98130cb1cb992593b050baa9c4d8484d6fd6e8f6 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 20 Nov 2020 13:52:43 +0100
Subject: [PATCH] thermal: qcom: tsens: Add IPQ8074 support
Qualcomm IPQ807x SoC-s use tsens v2.3.0 IP, but they
only have one interrupt and not a dedicated critical interrupt.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
drivers/thermal/qcom/tsens-v2.c | 14 ++++++++++++++
drivers/thermal/qcom/tsens.c | 27 ++++++++++++++++++---------
drivers/thermal/qcom/tsens.h | 2 +-
3 files changed, 33 insertions(+), 10 deletions(-)
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -36,6 +36,14 @@ static struct tsens_features tsens_v2_fe
.max_sensors = 16,
};
+static struct tsens_features tsens_ipq8074_feat = {
+ .ver_major = VER_2_X,
+ .crit_int = 0,
+ .adc = 0,
+ .srot_split = 1,
+ .max_sensors = 16,
+};
+
static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
/* ----- SROT ------ */
/* VERSION */
@@ -101,6 +109,12 @@ struct tsens_plat_data data_tsens_v2 = {
.fields = tsens_v2_regfields,
};
+struct tsens_plat_data data_tsens_ipq8074 = {
+ .ops = &ops_generic_v2,
+ .feat = &tsens_ipq8074_feat,
+ .fields = tsens_v2_regfields,
+};
+
/* Kept around for backward compatibility with old msm8996.dtsi */
struct tsens_plat_data data_8996 = {
.num_sensors = 13,
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -323,16 +323,22 @@ static int tsens_read_irq_state(struct t
ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask);
if (ret)
return ret;
- ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
- &d->crit_irq_clear);
- if (ret)
- return ret;
- ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
- &d->crit_irq_mask);
- if (ret)
- return ret;
+ if (priv->feat->crit_int) {
+ ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
+ &d->crit_irq_clear);
+ if (ret)
+ return ret;
+ ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
+ &d->crit_irq_mask);
+ if (ret)
+ return ret;
- d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id);
+ d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id);
+ } else {
+ d->crit_irq_clear = 0;
+ d->crit_irq_mask = 0;
+ d->crit_thresh = 0;
+ }
} else {
/* No mask register on older TSENS */
d->up_irq_mask = 0;
@@ -923,6 +929,9 @@ static const struct of_device_id tsens_t
}, {
.compatible = "qcom,tsens-v2",
.data = &data_tsens_v2,
+ }, {
+ .compatible = "qcom,ipq8074-tsens",
+ .data = &data_tsens_ipq8074,
},
{}
};
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -591,6 +591,6 @@ extern struct tsens_plat_data data_8916,
extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956;
/* TSENS v2 targets */
-extern struct tsens_plat_data data_8996, data_tsens_v2;
+extern struct tsens_plat_data data_8996, data_tsens_v2, data_tsens_ipq8074;
#endif /* __QCOM_TSENS_H__ */

Some files were not shown because too many files have changed in this diff Show More