From 8cb632045f56dd31d9184816eb013d405d864ae0 Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Tue, 2 Aug 2022 23:25:07 +0800 Subject: [PATCH] rockchip: 5.15: introduce rk3568 support Due to the missing ATF for normally boot, there are still a lot of bugs on this platform. At the same time, the GMAC driver also lacks a part. --- target/linux/rockchip/armv8/config-5.15 | 18 +- ...-thermal-Allow-more-resets-for-tsadc.patch | 28 + ...dd-GFP_DMA32-for-rx-buffers-if-no-64.patch | 67 ++ ...hip-add-pmu-and-qos-nodes-for-rk3568.patch | 266 ++++++++ ...-rockchip-add-saradc-node-for-rk3568.patch | 35 + ...chip-move-rk3568-dtsi-to-rk356x-dtsi.patch | 21 + ...ts-rockchip-split-rk3568-device-tree.patch | 135 ++++ ...6-arm64-dts-rockchip-add-rk3566-dtsi.patch | 39 ++ ...-dts-rockchip-add-watchdog-to-rk3568.patch | 31 + ...64-dts-rockchip-fix-rk3568-mbi-alias.patch | 28 + ...4-dts-rockchip-add-rk356x-gmac1-node.patch | 72 ++ ...ts-rockchip-adjust-rk3568-pll-clocks.patch | 36 + ...ts-rockchip-add-gmac0-node-to-rk3568.patch | 73 ++ ...-add-core-io-domains-node-for-rk356x.patch | 28 + ...chip-add-rk356x-gpio-debounce-clocks.patch | 63 ++ ...-dts-rockchip-add-rk3568-tsadc-nodes.patch | 139 ++++ ...p-add-missing-grf-property-to-rk356x.patch | 31 + ...ts-rockchip-add-pwm-nodes-for-rk3568.patch | 207 ++++++ ...ts-rockchip-add-spdif-node-to-rk356x.patch | 38 ++ ...rm64-dts-rockchip-Add-i2s1-on-rk356x.patch | 53 ++ ...-fix-resets-in-tsadc-node-for-rk356x.patch | 31 + ...dts-rockchip-Add-spi-nodes-on-rk356x.patch | 97 +++ ...add-usb2-nodes-to-rk3568-device-tree.patch | 139 ++++ ...ockchip-drop-pclk_xpcs-from-gmac0-on.patch | 54 ++ ...chip-inno-usb2-support-address-cells.patch | 45 ++ ...no-usb2-support-standalone-phy-nodes.patch | 44 ++ ...p-inno-usb2-support-muxed-interrupts.patch | 237 +++++++ ...ockchip-inno-usb2-add-rk3568-support.patch | 104 +++ ...-rename-and-sort-the-rk356x-usb2-phy.patch | 105 +++ ...chip-add-naneng-combo-phy-for-RK3568.patch | 633 ++++++++++++++++++ ...kchip-add-naneng-combo-phy-nodes-for.patch | 122 ++++ ...ts-rockchip-Add-sata-nodes-to-rk356x.patch | 76 +++ ...-use-3.0-clock-when-operating-in-2.0.patch | 46 ++ ...port-setting-f_min-from-host-drivers.patch | 54 ++ ...hip-Fix-handling-invalid-clock-rates.patch | 79 +++ ...8-Add-support-for-power-off-on-RK817.patch | 27 + ...-rk808-Add-reboot-support-to-rk808.c.patch | 110 +++ ...c-rockchip-set-dwc3-clock-for-rk3566.patch | 51 ++ ...-rockchip-add-rk356x-dwc3-usb3-nodes.patch | 118 ++++ ...kchip-dwc-Reset-core-at-driver-probe.patch | 72 ++ ...hip-dwc-Add-legacy-interrupt-support.patch | 163 +++++ ...-dts-rockchip-add-rk356x-sfc-support.patch | 35 + ...ts-rockchip-add-clocks-to-rk356x-cru.patch | 26 + ...ckchip-Add-rk3568-PCIe2x1-controller.patch | 74 ++ ...5.20-arm64-enable-THP_SWAP-for-arm64.patch | 123 ++++ ...drivers-phy-rockchip-Support-PCIe-v3.patch | 392 +++++++++++ ...ts-rockchip-rk3568-Add-PCIe-v3-nodes.patch | 144 ++++ ...ip-rk356x-add-support-for-new-boards.patch | 12 + 48 files changed, 4606 insertions(+), 15 deletions(-) create mode 100644 target/linux/rockchip/patches-5.15/009-v5.16-drivers-rockchip-thermal-Allow-more-resets-for-tsadc.patch create mode 100644 target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch create mode 100644 target/linux/rockchip/patches-5.15/011-v5.16-arm64-dts-rockchip-add-pmu-and-qos-nodes-for-rk3568.patch create mode 100644 target/linux/rockchip/patches-5.15/012-v5.16-arm64-dts-rockchip-add-saradc-node-for-rk3568.patch create mode 100644 target/linux/rockchip/patches-5.15/013-v5.16-arm64-dts-rockchip-move-rk3568-dtsi-to-rk356x-dtsi.patch create mode 100644 target/linux/rockchip/patches-5.15/014-v5.16-arm64-dts-rockchip-split-rk3568-device-tree.patch create mode 100644 target/linux/rockchip/patches-5.15/015-v5.16-arm64-dts-rockchip-add-rk3566-dtsi.patch create mode 100644 target/linux/rockchip/patches-5.15/016-v5.16-arm64-dts-rockchip-add-watchdog-to-rk3568.patch create mode 100644 target/linux/rockchip/patches-5.15/017-v5.16-arm64-dts-rockchip-fix-rk3568-mbi-alias.patch create mode 100644 target/linux/rockchip/patches-5.15/018-v5.16-arm64-dts-rockchip-add-rk356x-gmac1-node.patch create mode 100644 target/linux/rockchip/patches-5.15/019-v5.16-arm64-dts-rockchip-adjust-rk3568-pll-clocks.patch create mode 100644 target/linux/rockchip/patches-5.15/020-v5.16-arm64-dts-rockchip-add-gmac0-node-to-rk3568.patch create mode 100644 target/linux/rockchip/patches-5.15/021-v5.16-arm64-dts-rockchip-add-core-io-domains-node-for-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/022-v5.16-arm64-dts-rockchip-add-rk356x-gpio-debounce-clocks.patch create mode 100644 target/linux/rockchip/patches-5.15/023-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch create mode 100644 target/linux/rockchip/patches-5.15/024-v5.16-arm64-dts-rockchip-add-missing-grf-property-to-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/025-v5.16-arm64-dts-rockchip-add-pwm-nodes-for-rk3568.patch create mode 100644 target/linux/rockchip/patches-5.15/026-v5.16-arm64-dts-rockchip-add-spdif-node-to-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/027-v5.16-arm64-dts-rockchip-Add-i2s1-on-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/028-v5.16-arm64-dts-rockchip-fix-resets-in-tsadc-node-for-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/029-v5.17-arm64-dts-rockchip-Add-spi-nodes-on-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/030-v5.17-arm64-dts-rockchip-add-usb2-nodes-to-rk3568-device-tree.patch create mode 100644 target/linux/rockchip/patches-5.15/031-v5.17-arm64-dts-rockchip-drop-pclk_xpcs-from-gmac0-on.patch create mode 100644 target/linux/rockchip/patches-5.15/032-v5.17-phy-rockchip-inno-usb2-support-address-cells.patch create mode 100644 target/linux/rockchip/patches-5.15/033-v5.17-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch create mode 100644 target/linux/rockchip/patches-5.15/034-v5.17-phy-rockchip-inno-usb2-support-muxed-interrupts.patch create mode 100644 target/linux/rockchip/patches-5.15/035-v5.17-phy-rockchip-inno-usb2-add-rk3568-support.patch create mode 100644 target/linux/rockchip/patches-5.15/036-v5.18-arm64-dts-rockchip-rename-and-sort-the-rk356x-usb2-phy.patch create mode 100644 target/linux/rockchip/patches-5.15/037-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch create mode 100644 target/linux/rockchip/patches-5.15/038-v5.18-arm64-dts-rockchip-add-naneng-combo-phy-nodes-for.patch create mode 100644 target/linux/rockchip/patches-5.15/039-v5.18-arm64-dts-rockchip-Add-sata-nodes-to-rk356x.patch create mode 100644 target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch create mode 100644 target/linux/rockchip/patches-5.15/050-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch create mode 100644 target/linux/rockchip/patches-5.15/051-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch create mode 100644 target/linux/rockchip/patches-5.15/052-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch create mode 100644 target/linux/rockchip/patches-5.15/053-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch create mode 100644 target/linux/rockchip/patches-5.15/054-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch create mode 100644 target/linux/rockchip/patches-5.15/055-v5.19-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch create mode 100644 target/linux/rockchip/patches-5.15/056-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch create mode 100644 target/linux/rockchip/patches-5.15/057-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch create mode 100644 target/linux/rockchip/patches-5.15/058-v5.19-arm64-dts-rockchip-add-rk356x-sfc-support.patch create mode 100644 target/linux/rockchip/patches-5.15/059-v5.19-arm64-dts-rockchip-add-clocks-to-rk356x-cru.patch create mode 100644 target/linux/rockchip/patches-5.15/060-v5.20-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch create mode 100644 target/linux/rockchip/patches-5.15/061-v5.20-arm64-enable-THP_SWAP-for-arm64.patch create mode 100644 target/linux/rockchip/patches-5.15/108-drivers-phy-rockchip-Support-PCIe-v3.patch create mode 100644 target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch create mode 100644 target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch diff --git a/target/linux/rockchip/armv8/config-5.15 b/target/linux/rockchip/armv8/config-5.15 index 4f13a6e3a..88dab52a2 100644 --- a/target/linux/rockchip/armv8/config-5.15 +++ b/target/linux/rockchip/armv8/config-5.15 @@ -69,14 +69,7 @@ CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PSCI_FW=y CONFIG_ARM_RK3328_DMC_DEVFREQ=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -CONFIG_ARM_SCMI_CPUFREQ=y -CONFIG_ARM_SCMI_HAVE_SHMEM=y -CONFIG_ARM_SCMI_HAVE_TRANSPORT=y -CONFIG_ARM_SCMI_POWER_DOMAIN=y CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y -CONFIG_ARM_SCMI_TRANSPORT_SMC=y -# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCPI_POWER_DOMAIN=y CONFIG_ARM_SCPI_PROTOCOL=y @@ -151,7 +144,7 @@ CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y @@ -305,7 +298,6 @@ CONFIG_I2C_CHARDEV=y CONFIG_I2C_COMPAT=y CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_RK3X=y -# CONFIG_IIO_SCMI is not set CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_INDIRECT_PIO=y CONFIG_INPUT=y @@ -399,6 +391,7 @@ CONFIG_MMC_SDHCI_OF_DWCMSHC=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MOTORCOMM_PHY=y CONFIG_MQ_IOSCHED_DEADLINE=y # CONFIG_MTD_CFI is not set CONFIG_MTD_CMDLINE_PARTS=y @@ -461,8 +454,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIEPORTBUS=y CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y -CONFIG_PCIE_DW=y -CONFIG_PCIE_DW_HOST=y # CONFIG_PCIE_MICROCHIP_HOST is not set CONFIG_PCIE_PME=y CONFIG_PCIE_ROCKCHIP=y @@ -492,7 +483,7 @@ CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set -CONFIG_PINCTRL_RK805=y +# CONFIG_PINCTRL_RK805 is not set CONFIG_PINCTRL_ROCKCHIP=y # CONFIG_PINCTRL_SINGLE is not set CONFIG_PL330_DMA=y @@ -542,7 +533,6 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y -# CONFIG_REGULATOR_ARM_SCMI is not set # CONFIG_REGULATOR_DA9121 is not set CONFIG_REGULATOR_FAN53555=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -553,7 +543,6 @@ CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_RTQ6752 is not set CONFIG_RELOCATABLE=y CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_SCMI=y CONFIG_RFS_ACCEL=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_ROCKCHIP_GRF=y @@ -585,7 +574,6 @@ CONFIG_SCSI_SAS_LIBSAS=y # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set -# CONFIG_SENSORS_ARM_SCMI is not set CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_MAX127 is not set diff --git a/target/linux/rockchip/patches-5.15/009-v5.16-drivers-rockchip-thermal-Allow-more-resets-for-tsadc.patch b/target/linux/rockchip/patches-5.15/009-v5.16-drivers-rockchip-thermal-Allow-more-resets-for-tsadc.patch new file mode 100644 index 000000000..41a4a1c88 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/009-v5.16-drivers-rockchip-thermal-Allow-more-resets-for-tsadc.patch @@ -0,0 +1,28 @@ +From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Thu, 30 Sep 2021 13:05:16 +0200 +Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc + node + +The tsadc node in rk356x.dtsi has more resets then currently supported +by the rockchip_thermal.c driver, so use +devm_reset_control_array_get() to reset them all. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com +Signed-off-by: Daniel Lezcano +--- + drivers/thermal/rockchip_thermal.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/thermal/rockchip_thermal.c ++++ b/drivers/thermal/rockchip_thermal.c +@@ -1383,7 +1383,7 @@ static int rockchip_thermal_probe(struct platform_device *pdev) + if (IS_ERR(thermal->regs)) + return PTR_ERR(thermal->regs); + +- thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); ++ thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); + if (IS_ERR(thermal->reset)) { + error = PTR_ERR(thermal->reset); + dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); diff --git a/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch b/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch new file mode 100644 index 000000000..499506ef8 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch @@ -0,0 +1,67 @@ +From 884d2b845477cd0a18302444dc20fe2d9a01743e Mon Sep 17 00:00:00 2001 +From: David Wu +Date: Mon, 13 Dec 2021 19:15:15 +0800 +Subject: [PATCH] net: stmmac: Add GFP_DMA32 for rx buffers if no 64 capability + +Use page_pool_alloc_pages instead of page_pool_dev_alloc_pages, which +can give the gfp parameter, in the case of not supporting 64-bit width, +using 32-bit address memory can reduce a copy from swiotlb. + +Signed-off-by: David Wu +Signed-off-by: David S. Miller +--- + .../net/ethernet/stmicro/stmmac/stmmac_main.c | 16 ++++++++++++---- + 1 file changed, 12 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -1463,16 +1463,20 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, + { + struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; + struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; ++ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); ++ ++ if (priv->dma_cap.addr64 <= 32) ++ gfp |= GFP_DMA32; + + if (!buf->page) { +- buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); ++ buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); + if (!buf->page) + return -ENOMEM; + buf->page_offset = stmmac_rx_offset(priv); + } + + if (priv->sph && !buf->sec_page) { +- buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); ++ buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); + if (!buf->sec_page) + return -ENOMEM; + +@@ -4496,6 +4500,10 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) + struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; + int dirty = stmmac_rx_dirty(priv, queue); + unsigned int entry = rx_q->dirty_rx; ++ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); ++ ++ if (priv->dma_cap.addr64 <= 32) ++ gfp |= GFP_DMA32; + + while (dirty-- > 0) { + struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; +@@ -4508,13 +4516,13 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) + p = rx_q->dma_rx + entry; + + if (!buf->page) { +- buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); ++ buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); + if (!buf->page) + break; + } + + if (priv->sph && !buf->sec_page) { +- buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); ++ buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); + if (!buf->sec_page) + break; + diff --git a/target/linux/rockchip/patches-5.15/011-v5.16-arm64-dts-rockchip-add-pmu-and-qos-nodes-for-rk3568.patch b/target/linux/rockchip/patches-5.15/011-v5.16-arm64-dts-rockchip-add-pmu-and-qos-nodes-for-rk3568.patch new file mode 100644 index 000000000..b59e3b710 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/011-v5.16-arm64-dts-rockchip-add-pmu-and-qos-nodes-for-rk3568.patch @@ -0,0 +1,266 @@ +From e1152a526b16951fbebba5540cfcbb9394532431 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Thu, 24 Jun 2021 21:10:27 +0800 +Subject: [PATCH] arm64: dts: rockchip: add pmu and qos nodes for rk3568 + +Add the power-management and QoS nodes to the core rk3568 dtsi. + +Signed-off-by: Liang Chen +Link: https://lore.kernel.org/r/20210624131027.3719-1-cl@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++ + 1 file changed, 229 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -257,6 +258,99 @@ + status = "disabled"; + }; + ++ pmu: power-management@fdd90000 { ++ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0xfdd90000 0x0 0x1000>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3568-power-controller"; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* These power domains are grouped by VD_GPU */ ++ power-domain@RK3568_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU_PRE>, ++ <&cru PCLK_GPU_PRE>; ++ pm_qos = <&qos_gpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ /* These power domains are grouped by VD_LOGIC */ ++ power-domain@RK3568_PD_VI { ++ reg = ; ++ clocks = <&cru HCLK_VI>, ++ <&cru PCLK_VI>; ++ pm_qos = <&qos_isp>, ++ <&qos_vicap0>, ++ <&qos_vicap1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VO { ++ reg = ; ++ clocks = <&cru HCLK_VO>, ++ <&cru PCLK_VO>, ++ <&cru ACLK_VOP_PRE>; ++ pm_qos = <&qos_hdcp>, ++ <&qos_vop_m0>, ++ <&qos_vop_m1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RGA { ++ reg = ; ++ clocks = <&cru HCLK_RGA_PRE>, ++ <&cru PCLK_RGA_PRE>; ++ pm_qos = <&qos_ebc>, ++ <&qos_iep>, ++ <&qos_jpeg_dec>, ++ <&qos_jpeg_enc>, ++ <&qos_rga_rd>, ++ <&qos_rga_wr>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VPU { ++ reg = ; ++ clocks = <&cru HCLK_VPU_PRE>; ++ pm_qos = <&qos_vpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVDEC { ++ clocks = <&cru HCLK_RKVDEC_PRE>; ++ reg = ; ++ pm_qos = <&qos_rkvdec>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVENC { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC_PRE>; ++ pm_qos = <&qos_rkvenc_rd_m0>, ++ <&qos_rkvenc_rd_m1>, ++ <&qos_rkvenc_wr_m0>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_pcie3x1>, ++ <&qos_pcie3x2>, ++ <&qos_sata0>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; +@@ -271,6 +365,141 @@ + status = "disabled"; + }; + ++ qos_gpu: qos@fe128000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe128000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m0: qos@fe138080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138080 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m1: qos@fe138100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138100 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_wr_m0: qos@fe138180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138180 0x0 0x20>; ++ }; ++ ++ qos_isp: qos@fe148000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148000 0x0 0x20>; ++ }; ++ ++ qos_vicap0: qos@fe148080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148080 0x0 0x20>; ++ }; ++ ++ qos_vicap1: qos@fe148100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148100 0x0 0x20>; ++ }; ++ ++ qos_vpu: qos@fe150000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe150000 0x0 0x20>; ++ }; ++ ++ qos_ebc: qos@fe158000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158000 0x0 0x20>; ++ }; ++ ++ qos_iep: qos@fe158100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158100 0x0 0x20>; ++ }; ++ ++ qos_jpeg_dec: qos@fe158180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158180 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc: qos@fe158200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158200 0x0 0x20>; ++ }; ++ ++ qos_rga_rd: qos@fe158280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158280 0x0 0x20>; ++ }; ++ ++ qos_rga_wr: qos@fe158300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158300 0x0 0x20>; ++ }; ++ ++ qos_npu: qos@fe180000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe180000 0x0 0x20>; ++ }; ++ ++ qos_pcie2x1: qos@fe190000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190000 0x0 0x20>; ++ }; ++ ++ qos_pcie3x1: qos@fe190080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190080 0x0 0x20>; ++ }; ++ ++ qos_pcie3x2: qos@fe190100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190100 0x0 0x20>; ++ }; ++ ++ qos_sata0: qos@fe190200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190200 0x0 0x20>; ++ }; ++ ++ qos_sata1: qos@fe190280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190280 0x0 0x20>; ++ }; ++ ++ qos_sata2: qos@fe190300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190300 0x0 0x20>; ++ }; ++ ++ qos_usb3_0: qos@fe190380 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190380 0x0 0x20>; ++ }; ++ ++ qos_usb3_1: qos@fe190400 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190400 0x0 0x20>; ++ }; ++ ++ qos_rkvdec: qos@fe198000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe198000 0x0 0x20>; ++ }; ++ ++ qos_hdcp: qos@fe1a8000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8000 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@fe1a8080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8080 0x0 0x20>; ++ }; ++ ++ qos_vop_m1: qos@fe1a8100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8100 0x0 0x20>; ++ }; ++ + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-5.15/012-v5.16-arm64-dts-rockchip-add-saradc-node-for-rk3568.patch b/target/linux/rockchip/patches-5.15/012-v5.16-arm64-dts-rockchip-add-saradc-node-for-rk3568.patch new file mode 100644 index 000000000..ff28d8060 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/012-v5.16-arm64-dts-rockchip-add-saradc-node-for-rk3568.patch @@ -0,0 +1,35 @@ +From 2076121eecc18fa31ae749c6ddc5648be96f0b5e Mon Sep 17 00:00:00 2001 +From: Simon Xue +Date: Mon, 5 Jul 2021 09:26:10 +0800 +Subject: [PATCH] arm64: dts: rockchip: add saradc node for rk3568 + +Add the core dt-node for the rk3568's saradc. + +Signed-off-by: Simon Xue +Link: https://lore.kernel.org/r/20210705012610.3831-1-xxm@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -754,6 +754,18 @@ + status = "disabled"; + }; + ++ saradc: saradc@fe720000 { ++ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; ++ reg = <0x0 0xfe720000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ resets = <&cru SRST_P_SARADC>; ++ reset-names = "saradc-apb"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; diff --git a/target/linux/rockchip/patches-5.15/013-v5.16-arm64-dts-rockchip-move-rk3568-dtsi-to-rk356x-dtsi.patch b/target/linux/rockchip/patches-5.15/013-v5.16-arm64-dts-rockchip-move-rk3568-dtsi-to-rk356x-dtsi.patch new file mode 100644 index 000000000..f75c2f04c --- /dev/null +++ b/target/linux/rockchip/patches-5.15/013-v5.16-arm64-dts-rockchip-move-rk3568-dtsi-to-rk356x-dtsi.patch @@ -0,0 +1,21 @@ +From 4e50d2173b67115a5574f4f4ce64ec9c5d9c136e Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Sat, 10 Jul 2021 11:10:31 -0400 +Subject: [PATCH] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi + +In preparation for separating the rk3568 and rk3566 device trees, move +the base rk3568 dtsi to rk356x dtsi. +This will allow us to strip out the rk3568 specific nodes. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210710151034.32857-2-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/{rk3568.dtsi => rk356x.dtsi} | 0 + 1 file changed, 0 insertions(+), 0 deletions(-) + rename arch/arm64/boot/dts/rockchip/{rk3568.dtsi => rk356x.dtsi} (100%) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +similarity index 100% +rename from arch/arm64/boot/dts/rockchip/rk3568.dtsi +rename to arch/arm64/boot/dts/rockchip/rk356x.dtsi diff --git a/target/linux/rockchip/patches-5.15/014-v5.16-arm64-dts-rockchip-split-rk3568-device-tree.patch b/target/linux/rockchip/patches-5.15/014-v5.16-arm64-dts-rockchip-split-rk3568-device-tree.patch new file mode 100644 index 000000000..d2fdff18f --- /dev/null +++ b/target/linux/rockchip/patches-5.15/014-v5.16-arm64-dts-rockchip-split-rk3568-device-tree.patch @@ -0,0 +1,135 @@ +From 5067f459e5ee22857eeb4f659219db8e28c6263e Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Sat, 10 Jul 2021 11:10:32 -0400 +Subject: [PATCH] arm64: dts: rockchip: split rk3568 device tree + +In preparation for the rk3566 inclusion, split apart the rk3568 specific +nodes into a separate device tree. +This allows us to create the rk3566 device tree without deleting nodes. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210710151034.32857-3-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 48 ++++++++++++++++++++++++ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 36 ------------------ + 2 files changed, 48 insertions(+), 36 deletions(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -0,0 +1,48 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include "rk356x.dtsi" ++ ++/ { ++ compatible = "rockchip,rk3568"; ++ ++ qos_pcie3x1: qos@fe190080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190080 0x0 0x20>; ++ }; ++ ++ qos_pcie3x2: qos@fe190100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190100 0x0 0x20>; ++ }; ++ ++ qos_sata0: qos@fe190200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190200 0x0 0x20>; ++ }; ++}; ++ ++&cpu0_opp_table { ++ opp-1992000000 { ++ opp-hz = /bits/ 64 <1992000000>; ++ opp-microvolt = <1150000 1150000 1150000>; ++ }; ++}; ++ ++&power { ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_pcie3x1>, ++ <&qos_pcie3x2>, ++ <&qos_sata0>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; ++ }; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -13,8 +13,6 @@ + #include + + / { +- compatible = "rockchip,rk3568"; +- + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; +@@ -121,11 +119,6 @@ + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; + }; +- +- opp-1992000000 { +- opp-hz = /bits/ 64 <1992000000>; +- opp-microvolt = <1150000 1150000 1150000>; +- }; + }; + + firmware { +@@ -334,20 +327,6 @@ + <&qos_rkvenc_wr_m0>; + #power-domain-cells = <0>; + }; +- +- power-domain@RK3568_PD_PIPE { +- reg = ; +- clocks = <&cru PCLK_PIPE>; +- pm_qos = <&qos_pcie2x1>, +- <&qos_pcie3x1>, +- <&qos_pcie3x2>, +- <&qos_sata0>, +- <&qos_sata1>, +- <&qos_sata2>, +- <&qos_usb3_0>, +- <&qos_usb3_1>; +- #power-domain-cells = <0>; +- }; + }; + }; + +@@ -445,21 +424,6 @@ + reg = <0x0 0xfe190000 0x0 0x20>; + }; + +- qos_pcie3x1: qos@fe190080 { +- compatible = "rockchip,rk3568-qos", "syscon"; +- reg = <0x0 0xfe190080 0x0 0x20>; +- }; +- +- qos_pcie3x2: qos@fe190100 { +- compatible = "rockchip,rk3568-qos", "syscon"; +- reg = <0x0 0xfe190100 0x0 0x20>; +- }; +- +- qos_sata0: qos@fe190200 { +- compatible = "rockchip,rk3568-qos", "syscon"; +- reg = <0x0 0xfe190200 0x0 0x20>; +- }; +- + qos_sata1: qos@fe190280 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190280 0x0 0x20>; diff --git a/target/linux/rockchip/patches-5.15/015-v5.16-arm64-dts-rockchip-add-rk3566-dtsi.patch b/target/linux/rockchip/patches-5.15/015-v5.16-arm64-dts-rockchip-add-rk3566-dtsi.patch new file mode 100644 index 000000000..6fe9ccd8c --- /dev/null +++ b/target/linux/rockchip/patches-5.15/015-v5.16-arm64-dts-rockchip-add-rk3566-dtsi.patch @@ -0,0 +1,39 @@ +From 016c0e8a7a6e7820fb54d8ff8a4a2928a3016421 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Sat, 10 Jul 2021 11:10:33 -0400 +Subject: [PATCH] arm64: dts: rockchip: add rk3566 dtsi + +Add the rk3566 dtsi which includes the soc specific changes for this +chip. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210710151034.32857-4-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x.dtsi" ++ ++/ { ++ compatible = "rockchip,rk3566"; ++}; ++ ++&power { ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; ++ }; ++}; diff --git a/target/linux/rockchip/patches-5.15/016-v5.16-arm64-dts-rockchip-add-watchdog-to-rk3568.patch b/target/linux/rockchip/patches-5.15/016-v5.16-arm64-dts-rockchip-add-watchdog-to-rk3568.patch new file mode 100644 index 000000000..d29a7d008 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/016-v5.16-arm64-dts-rockchip-add-watchdog-to-rk3568.patch @@ -0,0 +1,31 @@ +From 0edcfec3fafa1fe58fd9a3be727742881ec340c3 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Tue, 22 Jun 2021 12:29:07 +0200 +Subject: [PATCH] arm64: dts: rockchip: add watchdog to rk3568 + +Add the watchdog node to rk3568. + +Signed-off-by: Liang Chen +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210622102907.99242-2-heiko@sntech.de +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -592,6 +592,14 @@ + status = "disabled"; + }; + ++ wdt: watchdog@fe600000 { ++ compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; ++ reg = <0x0 0xfe600000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; ++ clock-names = "tclk", "pclk"; ++ }; ++ + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-5.15/017-v5.16-arm64-dts-rockchip-fix-rk3568-mbi-alias.patch b/target/linux/rockchip/patches-5.15/017-v5.16-arm64-dts-rockchip-fix-rk3568-mbi-alias.patch new file mode 100644 index 000000000..a9343a233 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/017-v5.16-arm64-dts-rockchip-fix-rk3568-mbi-alias.patch @@ -0,0 +1,28 @@ +From b6c1a590148c63f822091912b4c09c79fbb13971 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:27 -0400 +Subject: [PATCH] arm64: dts: rockchip: fix rk3568 mbi-alias + +The mbi-alias incorrectly points to 0xfd100000 when it should point to +0xfd410000. +This fixes MSIs on rk3568. + +Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210728180034.717953-2-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -195,7 +195,7 @@ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; +- mbi-alias = <0x0 0xfd100000>; ++ mbi-alias = <0x0 0xfd410000>; + mbi-ranges = <296 24>; + msi-controller; + }; diff --git a/target/linux/rockchip/patches-5.15/018-v5.16-arm64-dts-rockchip-add-rk356x-gmac1-node.patch b/target/linux/rockchip/patches-5.15/018-v5.16-arm64-dts-rockchip-add-rk356x-gmac1-node.patch new file mode 100644 index 000000000..9cb8822c8 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/018-v5.16-arm64-dts-rockchip-add-rk356x-gmac1-node.patch @@ -0,0 +1,72 @@ +From 0dcec571cee519989d9536fd31328cdcbc0a45c7 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:30 -0400 +Subject: [PATCH] arm64: dts: rockchip: add rk356x gmac1 node + +Add the gmac1 controller to the rk356x device tree. +This is the controller common to both the rk3568 and rk3566. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210728180034.717953-5-pgwipeout@gmail.com +[adjusted sorting a bit] +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ + 1 file changed, 47 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -344,6 +344,53 @@ + status = "disabled"; + }; + ++ gmac1: ethernet@fe010000 { ++ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe010000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, ++ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, ++ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, ++ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; ++ clock-names = "stmmaceth", "mac_clk_rx", ++ "mac_clk_tx", "clk_mac_refout", ++ "aclk_mac", "pclk_mac", ++ "clk_mac_speed", "ptp_ref"; ++ resets = <&cru SRST_A_GMAC1>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&grf>; ++ snps,axi-config = <&gmac1_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac1_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <8>; ++ snps,wr_osr_lmt = <4>; ++ }; ++ ++ gmac1_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ ++ gmac1_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ }; ++ + qos_gpu: qos@fe128000 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe128000 0x0 0x20>; diff --git a/target/linux/rockchip/patches-5.15/019-v5.16-arm64-dts-rockchip-adjust-rk3568-pll-clocks.patch b/target/linux/rockchip/patches-5.15/019-v5.16-arm64-dts-rockchip-adjust-rk3568-pll-clocks.patch new file mode 100644 index 000000000..4b20477f9 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/019-v5.16-arm64-dts-rockchip-adjust-rk3568-pll-clocks.patch @@ -0,0 +1,36 @@ +From f7c5b9c2a1af765de0aae3a21073e051e95448bf Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:32 -0400 +Subject: [PATCH] arm64: dts: rockchip: adjust rk3568 pll clocks + +The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. +These are set incorrectly by the bootloader, so fix them here. + +gpll boots at 1188mhz, but to get most accurate dividers for all +gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream +isn't quite right. + +ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is +required to reach a 100mhz clock input for them. + +The vendor-kernel also makes this fix. + +Signed-off-by: Peter Geis +[pulled deeper explanation from discussion into commit message] +Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -222,6 +222,8 @@ + reg = <0x0 0xfdd20000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; ++ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; ++ assigned-clock-rates = <1200000000>, <200000000>; + }; + + i2c0: i2c@fdd40000 { diff --git a/target/linux/rockchip/patches-5.15/020-v5.16-arm64-dts-rockchip-add-gmac0-node-to-rk3568.patch b/target/linux/rockchip/patches-5.15/020-v5.16-arm64-dts-rockchip-add-gmac0-node-to-rk3568.patch new file mode 100644 index 000000000..99b81f753 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/020-v5.16-arm64-dts-rockchip-add-gmac0-node-to-rk3568.patch @@ -0,0 +1,73 @@ +From b8d41e5053cd823817344cc5e7a2bfda508effff Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Thu, 29 Jul 2021 11:39:12 +0200 +Subject: [PATCH] arm64: dts: rockchip: add gmac0 node to rk3568 + +While both RK3566 and RK3568 feature the gmac1 node, the gmac0 +node is exclusive to the RK3568. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 49 ++++++++++++++++++++++++ + 1 file changed, 49 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -22,6 +22,55 @@ + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190200 0x0 0x20>; + }; ++ ++ gmac0: ethernet@fe2a0000 { ++ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; ++ reg = <0x0 0xfe2a0000 0x0 0x10000>; ++ interrupts = , ++ ; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, ++ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, ++ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, ++ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, ++ <&cru PCLK_XPCS>; ++ clock-names = "stmmaceth", "mac_clk_rx", ++ "mac_clk_tx", "clk_mac_refout", ++ "aclk_mac", "pclk_mac", ++ "clk_mac_speed", "ptp_ref", ++ "pclk_xpcs"; ++ resets = <&cru SRST_A_GMAC0>; ++ reset-names = "stmmaceth"; ++ rockchip,grf = <&grf>; ++ snps,axi-config = <&gmac0_stmmac_axi_setup>; ++ snps,mixed-burst; ++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; ++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; ++ snps,tso; ++ status = "disabled"; ++ ++ mdio0: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ }; ++ ++ gmac0_stmmac_axi_setup: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <8>; ++ snps,wr_osr_lmt = <4>; ++ }; ++ ++ gmac0_mtl_rx_setup: rx-queues-config { ++ snps,rx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ ++ gmac0_mtl_tx_setup: tx-queues-config { ++ snps,tx-queues-to-use = <1>; ++ queue0 {}; ++ }; ++ }; + }; + + &cpu0_opp_table { diff --git a/target/linux/rockchip/patches-5.15/021-v5.16-arm64-dts-rockchip-add-core-io-domains-node-for-rk356x.patch b/target/linux/rockchip/patches-5.15/021-v5.16-arm64-dts-rockchip-add-core-io-domains-node-for-rk356x.patch new file mode 100644 index 000000000..78d386891 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/021-v5.16-arm64-dts-rockchip-add-core-io-domains-node-for-rk356x.patch @@ -0,0 +1,28 @@ +From 2dbcb2514c83416f2d0731bb0744a6c132f5c8c6 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Thu, 5 Aug 2021 14:01:03 +0200 +Subject: [PATCH] arm64: dts: rockchip: add core io domains node for rk356x + +Enable the PMU IO domains for the RK3566 and the RK3568. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20210805120107.27007-4-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -203,6 +203,11 @@ + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; ++ ++ pmu_io_domains: io-domains { ++ compatible = "rockchip,rk3568-pmu-io-voltage-domain"; ++ status = "disabled"; ++ }; + }; + + grf: syscon@fdc60000 { diff --git a/target/linux/rockchip/patches-5.15/022-v5.16-arm64-dts-rockchip-add-rk356x-gpio-debounce-clocks.patch b/target/linux/rockchip/patches-5.15/022-v5.16-arm64-dts-rockchip-add-rk356x-gpio-debounce-clocks.patch new file mode 100644 index 000000000..16d443a37 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/022-v5.16-arm64-dts-rockchip-add-rk356x-gpio-debounce-clocks.patch @@ -0,0 +1,63 @@ +From 3d9170c3ea221f495902cc42fcea1c072c0af7c7 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:29 -0400 +Subject: [PATCH] arm64: dts: rockchip: add rk356x gpio debounce clocks + +The rk356x added a debounce clock to the gpio devices. This clock is +necessary for the new v2 gpio driver to bind. +Add the clocks to the rk356x device tree. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210728180034.717953-4-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -804,7 +804,7 @@ + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; +- clocks = <&pmucru PCLK_GPIO0>; ++ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -815,7 +815,7 @@ + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; +- clocks = <&cru PCLK_GPIO1>; ++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -826,7 +826,7 @@ + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; +- clocks = <&cru PCLK_GPIO2>; ++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -837,7 +837,7 @@ + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = ; +- clocks = <&cru PCLK_GPIO3>; ++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; +@@ -848,7 +848,7 @@ + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; +- clocks = <&cru PCLK_GPIO4>; ++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; diff --git a/target/linux/rockchip/patches-5.15/023-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch b/target/linux/rockchip/patches-5.15/023-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch new file mode 100644 index 000000000..478fa7a30 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/023-v5.16-arm64-dts-rockchip-add-rk3568-tsadc-nodes.patch @@ -0,0 +1,139 @@ +From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:31 -0400 +Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes + +Add the thermal and tsadc nodes to the rk3568 device tree. +There are two sensors, one for the cpu, one for the gpu. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 9 +++ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++ + 2 files changed, 79 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +@@ -3108,4 +3108,13 @@ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; ++ ++ tsadc { ++ /omit-if-no-ref/ ++ tsadc_pin: tsadc-pin { ++ rockchip,pins = ++ /* tsadc_pin */ ++ <0 RK_PA1 0 &pcfg_pull_none>; ++ }; ++ }; + }; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -50,6 +50,7 @@ + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + clocks = <&scmi_clk 0>; ++ #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; +@@ -58,6 +59,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; ++ #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; +@@ -66,6 +68,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; ++ #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; +@@ -74,6 +77,7 @@ + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; ++ #cooling-cells = <2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>; + }; +@@ -780,6 +784,72 @@ + status = "disabled"; + }; + ++ thermal_zones: thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <100>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&tsadc 0>; ++ ++ trips { ++ cpu_alert0: cpu_alert0 { ++ temperature = <70000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ cpu_alert1: cpu_alert1 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ cpu_crit: cpu_crit { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert0>; ++ cooling-device = ++ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, ++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ gpu_thermal: gpu-thermal { ++ polling-delay-passive = <20>; /* milliseconds */ ++ polling-delay = <1000>; /* milliseconds */ ++ ++ thermal-sensors = <&tsadc 1>; ++ }; ++ }; ++ ++ tsadc: tsadc@fe710000 { ++ compatible = "rockchip,rk3568-tsadc"; ++ reg = <0x0 0xfe710000 0x0 0x100>; ++ interrupts = ; ++ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; ++ assigned-clock-rates = <17000000>, <700000>; ++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; ++ clock-names = "tsadc", "apb_pclk"; ++ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, ++ <&cru SRST_TSADCPHY>; ++ reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; ++ rockchip,grf = <&grf>; ++ rockchip,hw-tshut-temp = <95000>; ++ pinctrl-names = "init", "default", "sleep"; ++ pinctrl-0 = <&tsadc_pin>; ++ pinctrl-1 = <&tsadc_shutorg>; ++ pinctrl-2 = <&tsadc_pin>; ++ #thermal-sensor-cells = <1>; ++ status = "disabled"; ++ }; ++ + saradc: saradc@fe720000 { + compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xfe720000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-5.15/024-v5.16-arm64-dts-rockchip-add-missing-grf-property-to-rk356x.patch b/target/linux/rockchip/patches-5.15/024-v5.16-arm64-dts-rockchip-add-missing-grf-property-to-rk356x.patch new file mode 100644 index 000000000..29acd549a --- /dev/null +++ b/target/linux/rockchip/patches-5.15/024-v5.16-arm64-dts-rockchip-add-missing-grf-property-to-rk356x.patch @@ -0,0 +1,31 @@ +From 95ad4dbe5f43bf67036775df56c848aa8ffea8e2 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Mon, 23 Aug 2021 14:39:11 +0200 +Subject: [PATCH] arm64: dts: rockchip: add missing rockchip,grf property to + rk356x + +This commit fixes the error messages + + rockchip_clk_register_muxgrf: regmap not available + rockchip_clk_register_branches: failed to register clock clk_ddr1x: -524 + +during boot by providing the missing rockchip,grf property. + +Signed-off-by: Michael Riesch +Tested-by: Peter Geis +Link: https://lore.kernel.org/r/20210823123911.12095-2-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -233,6 +233,7 @@ + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <1200000000>, <200000000>; ++ rockchip,grf = <&grf>; + }; + + i2c0: i2c@fdd40000 { diff --git a/target/linux/rockchip/patches-5.15/025-v5.16-arm64-dts-rockchip-add-pwm-nodes-for-rk3568.patch b/target/linux/rockchip/patches-5.15/025-v5.16-arm64-dts-rockchip-add-pwm-nodes-for-rk3568.patch new file mode 100644 index 000000000..38ef82128 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/025-v5.16-arm64-dts-rockchip-add-pwm-nodes-for-rk3568.patch @@ -0,0 +1,207 @@ +From 98419a39d1dc276ac395c230ba2e6cf435a624b9 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Mon, 26 Jul 2021 11:03:55 +0200 +Subject: [PATCH] arm64: dts: rockchip: add pwm nodes for rk3568 + +Add the pwm controller nodes to the core rk3568 dtsi. + +Signed-off-by: Liang Chen +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210726090355.1548483-2-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 176 +++++++++++++++++++++++ + 1 file changed, 176 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -263,6 +263,50 @@ + status = "disabled"; + }; + ++ pwm0: pwm@fdd70000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70000 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm0m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@fdd70010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70010 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm1m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm2: pwm@fdd70020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70020 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm2m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm3: pwm@fdd70030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfdd70030 0x0 0x10>; ++ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm3_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + pmu: power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfdd90000 0x0 0x1000>; +@@ -863,6 +907,138 @@ + status = "disabled"; + }; + ++ pwm4: pwm@fe6e0000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm4_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm5: pwm@fe6e0010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm5_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm6: pwm@fe6e0020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm6_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm7: pwm@fe6e0030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6e0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm7_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm8: pwm@fe6f0000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0000 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm8m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm9: pwm@fe6f0010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0010 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm9m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm10: pwm@fe6f0020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0020 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm10m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm11: pwm@fe6f0030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe6f0030 0x0 0x10>; ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm11m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm12: pwm@fe700000 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700000 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm12m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm13: pwm@fe700010 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700010 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm13m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm14: pwm@fe700020 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700020 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm14m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm15: pwm@fe700030 { ++ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; ++ reg = <0x0 0xfe700030 0x0 0x10>; ++ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; ++ clock-names = "pwm", "pclk"; ++ pinctrl-0 = <&pwm15m0_pins>; ++ pinctrl-names = "active"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; diff --git a/target/linux/rockchip/patches-5.15/026-v5.16-arm64-dts-rockchip-add-spdif-node-to-rk356x.patch b/target/linux/rockchip/patches-5.15/026-v5.16-arm64-dts-rockchip-add-spdif-node-to-rk356x.patch new file mode 100644 index 000000000..a707595fa --- /dev/null +++ b/target/linux/rockchip/patches-5.15/026-v5.16-arm64-dts-rockchip-add-spdif-node-to-rk356x.patch @@ -0,0 +1,38 @@ +From a65e6523e6dcf1dc4ea167ab78ca6fad01f16d91 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 15 Oct 2021 13:13:01 +0200 +Subject: [PATCH] arm64: dts: rockchip: add spdif node to rk356x + +This adds the spdif node to the rk356x device tree. + +Signed-off-by: Peter Geis +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20211015111303.1365328-1-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -608,6 +608,20 @@ + status = "disabled"; + }; + ++ spdif: spdif@fe460000 { ++ compatible = "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe460000 0x0 0x1000>; ++ interrupts = ; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; ++ dmas = <&dmac1 1>; ++ dma-names = "tx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdifm0_tx>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-5.15/027-v5.16-arm64-dts-rockchip-Add-i2s1-on-rk356x.patch b/target/linux/rockchip/patches-5.15/027-v5.16-arm64-dts-rockchip-Add-i2s1-on-rk356x.patch new file mode 100644 index 000000000..d63649c0f --- /dev/null +++ b/target/linux/rockchip/patches-5.15/027-v5.16-arm64-dts-rockchip-Add-i2s1-on-rk356x.patch @@ -0,0 +1,53 @@ +From ef5c913570040df1955dd49cea221783468faeaf Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Sat, 16 Oct 2021 12:53:52 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add i2s1 on rk356x + +This adds the necessary device tree node on rk3566 and rk3568 +to enable the I2S1 TDM audio controller. + +I2S0 has not been added, as it is connected to HDMI and there is +no way to test that it's working without a functioning video +clock (read: VOP2 driver). + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20211016105354.116513-4-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 25 ++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -622,6 +622,31 @@ + status = "disabled"; + }; + ++ i2s1_8ch: i2s@fe410000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe410000 0x0 0x1000>; ++ interrupts = ; ++ assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; ++ assigned-clock-rates = <1188000000>, <1188000000>; ++ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, ++ <&cru HCLK_I2S1_8CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 3>, <&dmac1 2>; ++ dma-names = "rx", "tx"; ++ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; ++ reset-names = "tx-m", "rx-m"; ++ rockchip,grf = <&grf>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx ++ &i2s1m0_lrcktx &i2s1m0_lrckrx ++ &i2s1m0_sdi0 &i2s1m0_sdi1 ++ &i2s1m0_sdi2 &i2s1m0_sdi3 ++ &i2s1m0_sdo0 &i2s1m0_sdo1 ++ &i2s1m0_sdo2 &i2s1m0_sdo3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-5.15/028-v5.16-arm64-dts-rockchip-fix-resets-in-tsadc-node-for-rk356x.patch b/target/linux/rockchip/patches-5.15/028-v5.16-arm64-dts-rockchip-fix-resets-in-tsadc-node-for-rk356x.patch new file mode 100644 index 000000000..2ba981a3c --- /dev/null +++ b/target/linux/rockchip/patches-5.15/028-v5.16-arm64-dts-rockchip-fix-resets-in-tsadc-node-for-rk356x.patch @@ -0,0 +1,31 @@ +From 5c9e66c6b75a754025c74bde7b7a6c52674d8aa1 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Thu, 30 Sep 2021 13:05:17 +0200 +Subject: [PATCH] arm64: dts: rockchip: fix resets in tsadc node for rk356x + +In the rockchip_thermal.c driver we now get the resets with +a devm_reset_control_array_get() function, so remove +the reset-names property as it is no longer needed. +Although no longer required in rockchip-thermal.yaml +sort tsadc-apb as first item. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210930110517.14323-4-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -921,9 +921,8 @@ + assigned-clock-rates = <17000000>, <700000>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; +- resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, ++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, + <&cru SRST_TSADCPHY>; +- reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + pinctrl-names = "init", "default", "sleep"; diff --git a/target/linux/rockchip/patches-5.15/029-v5.17-arm64-dts-rockchip-Add-spi-nodes-on-rk356x.patch b/target/linux/rockchip/patches-5.15/029-v5.17-arm64-dts-rockchip-Add-spi-nodes-on-rk356x.patch new file mode 100644 index 000000000..dcdb56326 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/029-v5.17-arm64-dts-rockchip-Add-spi-nodes-on-rk356x.patch @@ -0,0 +1,97 @@ +From aaa552d84580e9213d0e2bf0f9243477d1227bdd Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Sat, 27 Nov 2021 15:19:08 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add spi nodes on rk356x + +This adds the four spi nodes (spi0, spi1, spi2, spi3) to the +rk356x dtsi. These are from the downstream device tree, though +I have double-checked that their interrupts and DMA numbers are +correct. I have also tested spi1 with an SPI device. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++ + 1 file changed, 64 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -39,6 +39,10 @@ + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; + }; + + cpus { +@@ -742,6 +746,66 @@ + clock-names = "tclk", "pclk"; + }; + ++ spi0: spi@fe610000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe610000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 20>, <&dmac0 21>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@fe620000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe620000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 22>, <&dmac0 23>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@fe630000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe630000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 24>, <&dmac0 25>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@fe640000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe640000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 26>, <&dmac0 27>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; diff --git a/target/linux/rockchip/patches-5.15/030-v5.17-arm64-dts-rockchip-add-usb2-nodes-to-rk3568-device-tree.patch b/target/linux/rockchip/patches-5.15/030-v5.17-arm64-dts-rockchip-add-usb2-nodes-to-rk3568-device-tree.patch new file mode 100644 index 000000000..7664b94c9 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/030-v5.17-arm64-dts-rockchip-add-usb2-nodes-to-rk3568-device-tree.patch @@ -0,0 +1,139 @@ +From cca4da59db28cdd284d34835be9f109f37bf0803 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 15 Dec 2021 16:02:51 -0500 +Subject: [PATCH] arm64: dts: rockchip: add usb2 nodes to rk3568 device tree + +Add the requisite nodes to the rk3568 device tree to enable the usb2 +device controllers. +Includes the usb2phy nodes, usb2phy grf nodes, and usb2 controller +nodes. + +Signed-off-by: Peter Geis +Tested-by: Michael Riesch +Link: https://lore.kernel.org/r/20211215210252.120923-8-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 98 ++++++++++++++++++++++++ + 1 file changed, 98 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -208,6 +208,50 @@ + msi-controller; + }; + ++ usb_host0_ehci: usb@fd800000 { ++ compatible = "generic-ehci"; ++ reg = <0x0 0xfd800000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&u2phy1_otg>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host0_ohci: usb@fd840000 { ++ compatible = "generic-ohci"; ++ reg = <0x0 0xfd840000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&u2phy1_otg>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host1_ehci: usb@fd880000 { ++ compatible = "generic-ehci"; ++ reg = <0x0 0xfd880000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&u2phy1_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ usb_host1_ohci: usb@fd8c0000 { ++ compatible = "generic-ohci"; ++ reg = <0x0 0xfd8c0000 0x0 0x40000>; ++ interrupts = ; ++ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, ++ <&cru PCLK_USB>; ++ phys = <&u2phy1_host>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; +@@ -223,6 +267,16 @@ + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + ++ usb2phy0_grf: syscon@fdca0000 { ++ compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; ++ reg = <0x0 0xfdca0000 0x0 0x8000>; ++ }; ++ ++ usb2phy1_grf: syscon@fdca8000 { ++ compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; ++ reg = <0x0 0xfdca8000 0x0 0x8000>; ++ }; ++ + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; +@@ -1141,6 +1195,50 @@ + status = "disabled"; + }; + ++ u2phy0: usb2phy@fe8a0000 { ++ compatible = "rockchip,rk3568-usb2phy"; ++ reg = <0x0 0xfe8a0000 0x0 0x10000>; ++ clocks = <&pmucru CLK_USBPHY0_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "clk_usbphy0_480m"; ++ interrupts = ; ++ rockchip,usbgrf = <&usb2phy0_grf>; ++ #clock-cells = <0>; ++ status = "disabled"; ++ ++ u2phy0_host: host-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ u2phy0_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ ++ u2phy1: usb2phy@fe8b0000 { ++ compatible = "rockchip,rk3568-usb2phy"; ++ reg = <0x0 0xfe8b0000 0x0 0x10000>; ++ clocks = <&pmucru CLK_USBPHY1_REF>; ++ clock-names = "phyclk"; ++ clock-output-names = "clk_usbphy1_480m"; ++ interrupts = ; ++ rockchip,usbgrf = <&usb2phy1_grf>; ++ #clock-cells = <0>; ++ status = "disabled"; ++ ++ u2phy1_host: host-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ u2phy1_otg: otg-port { ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; diff --git a/target/linux/rockchip/patches-5.15/031-v5.17-arm64-dts-rockchip-drop-pclk_xpcs-from-gmac0-on.patch b/target/linux/rockchip/patches-5.15/031-v5.17-arm64-dts-rockchip-drop-pclk_xpcs-from-gmac0-on.patch new file mode 100644 index 000000000..fccec455f --- /dev/null +++ b/target/linux/rockchip/patches-5.15/031-v5.17-arm64-dts-rockchip-drop-pclk_xpcs-from-gmac0-on.patch @@ -0,0 +1,54 @@ +From 85a8bccfa945680dc561f06b65ea01341d2033fc Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Sun, 23 Jan 2022 14:35:10 +0100 +Subject: [PATCH] arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568 + +pclk_xpcs is not supported by mainline driver and breaks dtbs_check + +following warnings occour, and many more + +rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks: + [[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181], + [15, 389], [15, 185], [15, 172]] is too long + From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml +rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names: + ['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac', + 'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long + From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml + +after removing it, the clock and other warnings are gone. + +pclk_xpcs on gmac is used to support QSGMII, but this requires a driver +supporting it. +Once xpcs support is introduced, the clock can be added to the +documentation and both controllers. + +Fixes: b8d41e5053cd ("arm64: dts: rockchip: add gmac0 node to rk3568") +Co-developed-by: Peter Geis +Signed-off-by: Peter Geis +Signed-off-by: Frank Wunderlich +Acked-by: Michael Riesch +Link: https://lore.kernel.org/r/20220123133510.135651-1-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -32,13 +32,11 @@ + clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, + <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, +- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, +- <&cru PCLK_XPCS>; ++ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", +- "clk_mac_speed", "ptp_ref", +- "pclk_xpcs"; ++ "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; diff --git a/target/linux/rockchip/patches-5.15/032-v5.17-phy-rockchip-inno-usb2-support-address-cells.patch b/target/linux/rockchip/patches-5.15/032-v5.17-phy-rockchip-inno-usb2-support-address-cells.patch new file mode 100644 index 000000000..3e24bcc35 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/032-v5.17-phy-rockchip-inno-usb2-support-address-cells.patch @@ -0,0 +1,45 @@ +From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 15 Dec 2021 16:02:47 -0500 +Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2 + +New Rockchip devices have the usb phy nodes as standalone devices. +These nodes have register nodes with #address_cells = 2, but only use 32 +bit addresses. + +Adjust the driver to check if the returned address is "0", and adjust +the index in that case. + +Signed-off-by: Peter Geis +Tested-by: Michael Riesch +Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -1090,12 +1090,21 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) + rphy->usbgrf = NULL; + } + +- if (of_property_read_u32(np, "reg", ®)) { ++ if (of_property_read_u32_index(np, "reg", 0, ®)) { + dev_err(dev, "the reg property is not assigned in %pOFn node\n", + np); + return -EINVAL; + } + ++ /* support address_cells=2 */ ++ if (reg == 0) { ++ if (of_property_read_u32_index(np, "reg", 1, ®)) { ++ dev_err(dev, "the reg property is not assigned in %pOFn node\n", ++ np); ++ return -EINVAL; ++ } ++ } ++ + rphy->dev = dev; + phy_cfgs = match->data; + rphy->chg_state = USB_CHG_STATE_UNDEFINED; diff --git a/target/linux/rockchip/patches-5.15/033-v5.17-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch b/target/linux/rockchip/patches-5.15/033-v5.17-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch new file mode 100644 index 000000000..1e8bfcbdc --- /dev/null +++ b/target/linux/rockchip/patches-5.15/033-v5.17-phy-rockchip-inno-usb2-support-standalone-phy-nodes.patch @@ -0,0 +1,44 @@ +From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 15 Dec 2021 16:02:48 -0500 +Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes + +New Rockchip devices have the usb2 phy devices as standalone nodes +instead of children of the grf node. +Allow the driver to find the grf node from a phandle. + +Signed-off-by: Peter Geis +Tested-by: Michael Riesch +Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++----- + 1 file changed, 12 insertions(+), 5 deletions(-) + +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -1073,12 +1073,19 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) + return -EINVAL; + } + +- if (!dev->parent || !dev->parent->of_node) +- return -EINVAL; ++ if (!dev->parent || !dev->parent->of_node) { ++ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf"); ++ if (IS_ERR(rphy->grf)) { ++ dev_err(dev, "failed to locate usbgrf\n"); ++ return PTR_ERR(rphy->grf); ++ } ++ } + +- rphy->grf = syscon_node_to_regmap(dev->parent->of_node); +- if (IS_ERR(rphy->grf)) +- return PTR_ERR(rphy->grf); ++ else { ++ rphy->grf = syscon_node_to_regmap(dev->parent->of_node); ++ if (IS_ERR(rphy->grf)) ++ return PTR_ERR(rphy->grf); ++ } + + if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { + rphy->usbgrf = diff --git a/target/linux/rockchip/patches-5.15/034-v5.17-phy-rockchip-inno-usb2-support-muxed-interrupts.patch b/target/linux/rockchip/patches-5.15/034-v5.17-phy-rockchip-inno-usb2-support-muxed-interrupts.patch new file mode 100644 index 000000000..b69b8ed32 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/034-v5.17-phy-rockchip-inno-usb2-support-muxed-interrupts.patch @@ -0,0 +1,237 @@ +From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 15 Dec 2021 16:02:49 -0500 +Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts + +The rk3568 usb2phy has a single muxed interrupt that handles all +interrupts. +Allow the driver to plug in only a single interrupt as necessary. + +Signed-off-by: Peter Geis +Tested-by: Michael Riesch +Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++----- + 1 file changed, 119 insertions(+), 49 deletions(-) + +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port { + * @dcd_retries: The retry count used to track Data contact + * detection process. + * @edev: extcon device for notification registration ++ * @irq: muxed interrupt for single irq configuration + * @phy_cfg: phy register configuration, assigned by driver data. + * @ports: phy port instance. + */ +@@ -218,6 +219,7 @@ struct rockchip_usb2phy { + enum power_supply_type chg_type; + u8 dcd_retries; + struct extcon_dev *edev; ++ int irq; + const struct rockchip_usb2phy_cfg *phy_cfg; + struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; + }; +@@ -926,6 +928,102 @@ static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) + return IRQ_NONE; + } + ++static irqreturn_t rockchip_usb2phy_irq(int irq, void *data) ++{ ++ struct rockchip_usb2phy *rphy = data; ++ struct rockchip_usb2phy_port *rport; ++ irqreturn_t ret = IRQ_NONE; ++ unsigned int index; ++ ++ for (index = 0; index < rphy->phy_cfg->num_ports; index++) { ++ rport = &rphy->ports[index]; ++ if (!rport->phy) ++ continue; ++ ++ /* Handle linestate irq for both otg port and host port */ ++ ret = rockchip_usb2phy_linestate_irq(irq, rport); ++ } ++ ++ return ret; ++} ++ ++static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy, ++ struct rockchip_usb2phy_port *rport, ++ struct device_node *child_np) ++{ ++ int ret; ++ ++ /* ++ * If the usb2 phy used combined irq for otg and host port, ++ * don't need to init otg and host port irq separately. ++ */ ++ if (rphy->irq > 0) ++ return 0; ++ ++ switch (rport->port_id) { ++ case USB2PHY_PORT_HOST: ++ rport->ls_irq = of_irq_get_byname(child_np, "linestate"); ++ if (rport->ls_irq < 0) { ++ dev_err(rphy->dev, "no linestate irq provided\n"); ++ return rport->ls_irq; ++ } ++ ++ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, ++ rockchip_usb2phy_linestate_irq, ++ IRQF_ONESHOT, ++ "rockchip_usb2phy", rport); ++ if (ret) { ++ dev_err(rphy->dev, "failed to request linestate irq handle\n"); ++ return ret; ++ } ++ break; ++ case USB2PHY_PORT_OTG: ++ /* ++ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate ++ * interrupts muxed together, so probe the otg-mux interrupt first, ++ * if not found, then look for the regular interrupts one by one. ++ */ ++ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); ++ if (rport->otg_mux_irq > 0) { ++ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, ++ NULL, ++ rockchip_usb2phy_otg_mux_irq, ++ IRQF_ONESHOT, ++ "rockchip_usb2phy_otg", ++ rport); ++ if (ret) { ++ dev_err(rphy->dev, ++ "failed to request otg-mux irq handle\n"); ++ return ret; ++ } ++ } else { ++ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); ++ if (rport->bvalid_irq < 0) { ++ dev_err(rphy->dev, "no vbus valid irq provided\n"); ++ ret = rport->bvalid_irq; ++ return ret; ++ } ++ ++ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, ++ NULL, ++ rockchip_usb2phy_bvalid_irq, ++ IRQF_ONESHOT, ++ "rockchip_usb2phy_bvalid", ++ rport); ++ if (ret) { ++ dev_err(rphy->dev, ++ "failed to request otg-bvalid irq handle\n"); ++ return ret; ++ } ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, + struct rockchip_usb2phy_port *rport, + struct device_node *child_np) +@@ -939,18 +1037,9 @@ static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, + mutex_init(&rport->mutex); + INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); + +- rport->ls_irq = of_irq_get_byname(child_np, "linestate"); +- if (rport->ls_irq < 0) { +- dev_err(rphy->dev, "no linestate irq provided\n"); +- return rport->ls_irq; +- } +- +- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, +- rockchip_usb2phy_linestate_irq, +- IRQF_ONESHOT, +- "rockchip_usb2phy", rport); ++ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); + if (ret) { +- dev_err(rphy->dev, "failed to request linestate irq handle\n"); ++ dev_err(rphy->dev, "failed to setup host irq\n"); + return ret; + } + +@@ -999,44 +1088,10 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, + INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); + INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); + +- /* +- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate +- * interrupts muxed together, so probe the otg-mux interrupt first, +- * if not found, then look for the regular interrupts one by one. +- */ +- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); +- if (rport->otg_mux_irq > 0) { +- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, +- NULL, +- rockchip_usb2phy_otg_mux_irq, +- IRQF_ONESHOT, +- "rockchip_usb2phy_otg", +- rport); +- if (ret) { +- dev_err(rphy->dev, +- "failed to request otg-mux irq handle\n"); +- goto out; +- } +- } else { +- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); +- if (rport->bvalid_irq < 0) { +- dev_err(rphy->dev, "no vbus valid irq provided\n"); +- ret = rport->bvalid_irq; +- goto out; +- } +- +- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, +- NULL, +- rockchip_usb2phy_bvalid_irq, +- IRQF_ONESHOT, +- "rockchip_usb2phy_bvalid", +- rport); +- if (ret) { +- dev_err(rphy->dev, +- "failed to request otg-bvalid irq handle\n"); +- goto out; +- } +- } ++ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np); ++ if (ret) { ++ dev_err(rphy->dev, "failed to init irq for host port\n"); ++ goto out; + + if (!IS_ERR(rphy->edev)) { + rport->event_nb.notifier_call = rockchip_otg_event; +@@ -1116,6 +1171,7 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) + phy_cfgs = match->data; + rphy->chg_state = USB_CHG_STATE_UNDEFINED; + rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; ++ rphy->irq = platform_get_irq_optional(pdev, 0); + platform_set_drvdata(pdev, rphy); + + ret = rockchip_usb2phy_extcon_register(rphy); +@@ -1195,6 +1251,20 @@ static int rockchip_usb2phy_probe(struct platform_device *pdev) + } + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ if (rphy->irq > 0) { ++ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL, ++ rockchip_usb2phy_irq, ++ IRQF_ONESHOT, ++ "rockchip_usb2phy", ++ rphy); ++ if (ret) { ++ dev_err(rphy->dev, ++ "failed to request usb2phy irq handle\n"); ++ goto put_child; ++ } ++ } ++ + return PTR_ERR_OR_ZERO(provider); + + put_child: diff --git a/target/linux/rockchip/patches-5.15/035-v5.17-phy-rockchip-inno-usb2-add-rk3568-support.patch b/target/linux/rockchip/patches-5.15/035-v5.17-phy-rockchip-inno-usb2-add-rk3568-support.patch new file mode 100644 index 000000000..860a4b06d --- /dev/null +++ b/target/linux/rockchip/patches-5.15/035-v5.17-phy-rockchip-inno-usb2-add-rk3568-support.patch @@ -0,0 +1,104 @@ +From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 15 Dec 2021 16:02:50 -0500 +Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support + +The rk3568 usb2phy is a standalone device with a single muxed interrupt. +Add support for the registers to the usb2phy driver. + +Signed-off-by: Peter Geis +Tested-by: Michael Riesch +Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++ + 1 file changed, 65 insertions(+) + +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -1092,6 +1092,7 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, + if (ret) { + dev_err(rphy->dev, "failed to init irq for host port\n"); + goto out; ++ } + + if (!IS_ERR(rphy->edev)) { + rport->event_nb.notifier_call = rockchip_otg_event; +@@ -1503,6 +1504,69 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { + { /* sentinel */ } + }; + ++static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { ++ { ++ .reg = 0xfe8a0000, ++ .num_ports = 2, ++ .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, ++ .port_cfgs = { ++ [USB2PHY_PORT_OTG] = { ++ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 }, ++ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 }, ++ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 }, ++ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 }, ++ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 }, ++ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 }, ++ }, ++ [USB2PHY_PORT_HOST] = { ++ /* Select suspend control from controller */ ++ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 }, ++ .ls_det_en = { 0x0080, 1, 1, 0, 1 }, ++ .ls_det_st = { 0x0084, 1, 1, 0, 1 }, ++ .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, ++ .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, ++ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } ++ } ++ }, ++ .chg_det = { ++ .opmode = { 0x0000, 3, 0, 5, 1 }, ++ .cp_det = { 0x00c0, 24, 24, 0, 1 }, ++ .dcp_det = { 0x00c0, 23, 23, 0, 1 }, ++ .dp_det = { 0x00c0, 25, 25, 0, 1 }, ++ .idm_sink_en = { 0x0008, 8, 8, 0, 1 }, ++ .idp_sink_en = { 0x0008, 7, 7, 0, 1 }, ++ .idp_src_en = { 0x0008, 9, 9, 0, 1 }, ++ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 }, ++ .vdm_src_en = { 0x0008, 12, 12, 0, 1 }, ++ .vdp_src_en = { 0x0008, 11, 11, 0, 1 }, ++ }, ++ }, ++ { ++ .reg = 0xfe8b0000, ++ .num_ports = 2, ++ .clkout_ctl = { 0x0008, 4, 4, 1, 0 }, ++ .port_cfgs = { ++ [USB2PHY_PORT_OTG] = { ++ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 }, ++ .ls_det_en = { 0x0080, 0, 0, 0, 1 }, ++ .ls_det_st = { 0x0084, 0, 0, 0, 1 }, ++ .ls_det_clr = { 0x0088, 0, 0, 0, 1 }, ++ .utmi_ls = { 0x00c0, 5, 4, 0, 1 }, ++ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 } ++ }, ++ [USB2PHY_PORT_HOST] = { ++ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 }, ++ .ls_det_en = { 0x0080, 1, 1, 0, 1 }, ++ .ls_det_st = { 0x0084, 1, 1, 0, 1 }, ++ .ls_det_clr = { 0x0088, 1, 1, 0, 1 }, ++ .utmi_ls = { 0x00c0, 17, 16, 0, 1 }, ++ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 } ++ } ++ }, ++ }, ++ { /* sentinel */ } ++}; ++ + static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { + { + .reg = 0x100, +@@ -1552,6 +1616,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = { + { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, + { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, + { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, ++ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs }, + { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, + {} + }; diff --git a/target/linux/rockchip/patches-5.15/036-v5.18-arm64-dts-rockchip-rename-and-sort-the-rk356x-usb2-phy.patch b/target/linux/rockchip/patches-5.15/036-v5.18-arm64-dts-rockchip-rename-and-sort-the-rk356x-usb2-phy.patch new file mode 100644 index 000000000..d59c91559 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/036-v5.18-arm64-dts-rockchip-rename-and-sort-the-rk356x-usb2-phy.patch @@ -0,0 +1,105 @@ +From 78f7186095db5a64009d44c18843a03dbc72d896 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Thu, 27 Jan 2022 20:04:55 +0100 +Subject: [PATCH] arm64: dts: rockchip: rename and sort the rk356x usb2 phy + handles + +All nodes and handles related to USB have the prefix usb or usb2, +whereas the phy handles are prefixed with u2phy. Rename for +consistency reasons and to facilitate sorting. + +This patch also updates the handles in the only board file that +uses them (rk3566-quartz64-a.dts). + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220127190456.2195527-1-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3566-quartz64-a.dts | 18 ++++++++--------- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 +++++++++---------- + 2 files changed, 19 insertions(+), 19 deletions(-) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -214,7 +214,7 @@ + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; +- phys = <&u2phy1_otg>; ++ phys = <&usb2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; +@@ -225,7 +225,7 @@ + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; +- phys = <&u2phy1_otg>; ++ phys = <&usb2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; +@@ -236,7 +236,7 @@ + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; +- phys = <&u2phy1_host>; ++ phys = <&usb2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; +@@ -247,7 +247,7 @@ + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; +- phys = <&u2phy1_host>; ++ phys = <&usb2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; +@@ -1211,7 +1211,7 @@ + status = "disabled"; + }; + +- u2phy0: usb2phy@fe8a0000 { ++ usb2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY0_REF>; +@@ -1222,18 +1222,18 @@ + #clock-cells = <0>; + status = "disabled"; + +- u2phy0_host: host-port { ++ usb2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + +- u2phy0_otg: otg-port { ++ usb2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + +- u2phy1: usb2phy@fe8b0000 { ++ usb2phy1: usb2phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY1_REF>; +@@ -1244,12 +1244,12 @@ + #clock-cells = <0>; + status = "disabled"; + +- u2phy1_host: host-port { ++ usb2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + +- u2phy1_otg: otg-port { ++ usb2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; diff --git a/target/linux/rockchip/patches-5.15/037-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch b/target/linux/rockchip/patches-5.15/037-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch new file mode 100644 index 000000000..fa701574d --- /dev/null +++ b/target/linux/rockchip/patches-5.15/037-v5.18-phy-rockchip-add-naneng-combo-phy-for-RK3568.patch @@ -0,0 +1,633 @@ +From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001 +From: Yifeng Zhao +Date: Tue, 8 Feb 2022 17:13:25 +0800 +Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568 + +This patch implements a combo phy driver for Rockchip SoCs +with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, +sata-phy or sgmii-phy. + +Signed-off-by: Yifeng Zhao +Signed-off-by: Johan Jonker +Tested-by: Peter Geis +Tested-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com +Signed-off-by: Vinod Koul +--- + drivers/phy/rockchip/Kconfig | 8 + + drivers/phy/rockchip/Makefile | 1 + + .../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++ + 3 files changed, 590 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c + +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY + Enable this to support the Rockchip MIPI/LVDS/TTL PHY with + Innosilicon IP block. + ++config PHY_ROCKCHIP_NANENG_COMBO_PHY ++ tristate "Rockchip NANENG COMBO PHY Driver" ++ depends on ARCH_ROCKCHIP && OF ++ select GENERIC_PHY ++ help ++ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII ++ combo PHY with NaNeng IP block. ++ + config PHY_ROCKCHIP_PCIE + tristate "Rockchip PCIe PHY Driver" + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY) += phy-rockchip-inno-csidphy.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o ++obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o + obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o + obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o +--- /dev/null ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -0,0 +1,581 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver ++ * ++ * Copyright (C) 2021 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BIT_WRITEABLE_SHIFT 16 ++#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) ++#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) ++#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) ++ ++/* COMBO PHY REG */ ++#define PHYREG6 0x14 ++#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6) ++#define PHYREG6_PLL_DIV_SHIFT 6 ++#define PHYREG6_PLL_DIV_2 1 ++ ++#define PHYREG7 0x18 ++#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4) ++#define PHYREG7_TX_RTERM_SHIFT 4 ++#define PHYREG7_TX_RTERM_50OHM 8 ++#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0) ++#define PHYREG7_RX_RTERM_SHIFT 0 ++#define PHYREG7_RX_RTERM_44OHM 15 ++ ++#define PHYREG8 0x1C ++#define PHYREG8_SSC_EN BIT(4) ++ ++#define PHYREG11 0x28 ++#define PHYREG11_SU_TRIM_0_7 0xF0 ++ ++#define PHYREG12 0x2C ++#define PHYREG12_PLL_LPF_ADJ_VALUE 4 ++ ++#define PHYREG13 0x30 ++#define PHYREG13_RESISTER_MASK GENMASK(5, 4) ++#define PHYREG13_RESISTER_SHIFT 0x4 ++#define PHYREG13_RESISTER_HIGH_Z 3 ++#define PHYREG13_CKRCV_AMP0 BIT(7) ++ ++#define PHYREG14 0x34 ++#define PHYREG14_CKRCV_AMP1 BIT(0) ++ ++#define PHYREG15 0x38 ++#define PHYREG15_CTLE_EN BIT(0) ++#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6) ++#define PHYREG15_SSC_CNT_SHIFT 6 ++#define PHYREG15_SSC_CNT_VALUE 1 ++ ++#define PHYREG16 0x3C ++#define PHYREG16_SSC_CNT_VALUE 0x5f ++ ++#define PHYREG18 0x44 ++#define PHYREG18_PLL_LOOP 0x32 ++ ++#define PHYREG32 0x7C ++#define PHYREG32_SSC_MASK GENMASK(7, 4) ++#define PHYREG32_SSC_DIR_SHIFT 4 ++#define PHYREG32_SSC_UPWARD 0 ++#define PHYREG32_SSC_DOWNWARD 1 ++#define PHYREG32_SSC_OFFSET_SHIFT 6 ++#define PHYREG32_SSC_OFFSET_500PPM 1 ++ ++#define PHYREG33 0x80 ++#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) ++#define PHYREG33_PLL_KVCO_SHIFT 2 ++#define PHYREG33_PLL_KVCO_VALUE 2 ++ ++struct rockchip_combphy_priv; ++ ++struct combphy_reg { ++ u16 offset; ++ u16 bitend; ++ u16 bitstart; ++ u16 disable; ++ u16 enable; ++}; ++ ++struct rockchip_combphy_grfcfg { ++ struct combphy_reg pcie_mode_set; ++ struct combphy_reg usb_mode_set; ++ struct combphy_reg sgmii_mode_set; ++ struct combphy_reg qsgmii_mode_set; ++ struct combphy_reg pipe_rxterm_set; ++ struct combphy_reg pipe_txelec_set; ++ struct combphy_reg pipe_txcomp_set; ++ struct combphy_reg pipe_clk_25m; ++ struct combphy_reg pipe_clk_100m; ++ struct combphy_reg pipe_phymode_sel; ++ struct combphy_reg pipe_rate_sel; ++ struct combphy_reg pipe_rxterm_sel; ++ struct combphy_reg pipe_txelec_sel; ++ struct combphy_reg pipe_txcomp_sel; ++ struct combphy_reg pipe_clk_ext; ++ struct combphy_reg pipe_sel_usb; ++ struct combphy_reg pipe_sel_qsgmii; ++ struct combphy_reg pipe_phy_status; ++ struct combphy_reg con0_for_pcie; ++ struct combphy_reg con1_for_pcie; ++ struct combphy_reg con2_for_pcie; ++ struct combphy_reg con3_for_pcie; ++ struct combphy_reg con0_for_sata; ++ struct combphy_reg con1_for_sata; ++ struct combphy_reg con2_for_sata; ++ struct combphy_reg con3_for_sata; ++ struct combphy_reg pipe_con0_for_sata; ++ struct combphy_reg pipe_xpcs_phy_ready; ++}; ++ ++struct rockchip_combphy_cfg { ++ const struct rockchip_combphy_grfcfg *grfcfg; ++ int (*combphy_cfg)(struct rockchip_combphy_priv *priv); ++}; ++ ++struct rockchip_combphy_priv { ++ u8 type; ++ void __iomem *mmio; ++ int num_clks; ++ struct clk_bulk_data *clks; ++ struct device *dev; ++ struct regmap *pipe_grf; ++ struct regmap *phy_grf; ++ struct phy *phy; ++ struct reset_control *phy_rst; ++ const struct rockchip_combphy_cfg *cfg; ++ bool enable_ssc; ++ bool ext_refclk; ++ struct clk *refclk; ++}; ++ ++static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, ++ int mask, int val, int reg) ++{ ++ unsigned int temp; ++ ++ temp = readl(priv->mmio + reg); ++ temp = (temp & ~(mask)) | val; ++ writel(temp, priv->mmio + reg); ++} ++ ++static int rockchip_combphy_param_write(struct regmap *base, ++ const struct combphy_reg *reg, bool en) ++{ ++ u32 val, mask, tmp; ++ ++ tmp = en ? reg->enable : reg->disable; ++ mask = GENMASK(reg->bitend, reg->bitstart); ++ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); ++ ++ return regmap_write(base, reg->offset, val); ++} ++ ++static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ u32 mask, val; ++ ++ mask = GENMASK(cfg->pipe_phy_status.bitend, ++ cfg->pipe_phy_status.bitstart); ++ ++ regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); ++ val = (val & mask) >> cfg->pipe_phy_status.bitstart; ++ ++ return val; ++} ++ ++static int rockchip_combphy_init(struct phy *phy) ++{ ++ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ u32 val; ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); ++ if (ret) { ++ dev_err(priv->dev, "failed to enable clks\n"); ++ return ret; ++ } ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ case PHY_TYPE_USB3: ++ case PHY_TYPE_SATA: ++ case PHY_TYPE_SGMII: ++ case PHY_TYPE_QSGMII: ++ if (priv->cfg->combphy_cfg) ++ ret = priv->cfg->combphy_cfg(priv); ++ break; ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (ret) { ++ dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); ++ goto err_clk; ++ } ++ ++ ret = reset_control_deassert(priv->phy_rst); ++ if (ret) ++ goto err_clk; ++ ++ if (priv->type == PHY_TYPE_USB3) { ++ ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, ++ priv, val, ++ val == cfg->pipe_phy_status.enable, ++ 10, 1000); ++ if (ret) ++ dev_warn(priv->dev, "wait phy status ready timeout\n"); ++ } ++ ++ return 0; ++ ++err_clk: ++ clk_bulk_disable_unprepare(priv->num_clks, priv->clks); ++ ++ return ret; ++} ++ ++static int rockchip_combphy_exit(struct phy *phy) ++{ ++ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); ++ ++ clk_bulk_disable_unprepare(priv->num_clks, priv->clks); ++ reset_control_assert(priv->phy_rst); ++ ++ return 0; ++} ++ ++static const struct phy_ops rochchip_combphy_ops = { ++ .init = rockchip_combphy_init, ++ .exit = rockchip_combphy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) ++{ ++ struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); ++ ++ if (args->args_count != 1) { ++ dev_err(dev, "invalid number of arguments\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ if (priv->type != PHY_NONE && priv->type != args->args[0]) ++ dev_warn(dev, "phy type select %d overwriting type %d\n", ++ args->args[0], priv->type); ++ ++ priv->type = args->args[0]; ++ ++ return priv->phy; ++} ++ ++static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) ++{ ++ int i; ++ ++ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); ++ if (priv->num_clks < 1) ++ return -EINVAL; ++ ++ priv->refclk = NULL; ++ for (i = 0; i < priv->num_clks; i++) { ++ if (!strncmp(priv->clks[i].id, "ref", 3)) { ++ priv->refclk = priv->clks[i].clk; ++ break; ++ } ++ } ++ ++ if (!priv->refclk) { ++ dev_err(dev, "no refclk found\n"); ++ return -EINVAL; ++ } ++ ++ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); ++ if (IS_ERR(priv->pipe_grf)) { ++ dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); ++ return PTR_ERR(priv->pipe_grf); ++ } ++ ++ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); ++ if (IS_ERR(priv->phy_grf)) { ++ dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); ++ return PTR_ERR(priv->phy_grf); ++ } ++ ++ priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); ++ ++ priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); ++ ++ priv->phy_rst = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(priv->phy_rst)) ++ return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); ++ ++ return 0; ++} ++ ++static int rockchip_combphy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct rockchip_combphy_priv *priv; ++ const struct rockchip_combphy_cfg *phy_cfg; ++ struct resource *res; ++ int ret; ++ ++ phy_cfg = of_device_get_match_data(dev); ++ if (!phy_cfg) { ++ dev_err(dev, "no OF match data provided\n"); ++ return -EINVAL; ++ } ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(priv->mmio)) { ++ ret = PTR_ERR(priv->mmio); ++ return ret; ++ } ++ ++ priv->dev = dev; ++ priv->type = PHY_NONE; ++ priv->cfg = phy_cfg; ++ ++ ret = rockchip_combphy_parse_dt(dev, priv); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_assert(priv->phy_rst); ++ if (ret) { ++ dev_err(dev, "failed to reset phy\n"); ++ return ret; ++ } ++ ++ priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); ++ if (IS_ERR(priv->phy)) { ++ dev_err(dev, "failed to create combphy\n"); ++ return PTR_ERR(priv->phy); ++ } ++ ++ dev_set_drvdata(dev, priv); ++ phy_set_drvdata(priv->phy, priv); ++ ++ phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) ++{ ++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; ++ unsigned long rate; ++ u32 val; ++ ++ switch (priv->type) { ++ case PHY_TYPE_PCIE: ++ /* Set SSC downward spread spectrum. */ ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, ++ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, ++ PHYREG32); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); ++ break; ++ ++ case PHY_TYPE_USB3: ++ /* Set SSC downward spread spectrum. */ ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, ++ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, ++ PHYREG32); ++ ++ /* Enable adaptive CTLE for USB3.0 Rx. */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ ++ /* Set PLL KVCO fine tuning signals. */ ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, ++ PHYREG33); ++ ++ /* Enable controlling random jitter. */ ++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ ++ /* Set PLL input clock divider 1/2. */ ++ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, ++ PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, ++ PHYREG6); ++ ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); ++ break; ++ ++ case PHY_TYPE_SATA: ++ /* Enable adaptive CTLE for SATA Rx. */ ++ val = readl(priv->mmio + PHYREG15); ++ val |= PHYREG15_CTLE_EN; ++ writel(val, priv->mmio + PHYREG15); ++ /* ++ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. ++ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) ++ */ ++ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; ++ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; ++ writel(val, priv->mmio + PHYREG7); ++ ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); ++ break; ++ ++ case PHY_TYPE_SGMII: ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); ++ break; ++ ++ case PHY_TYPE_QSGMII: ++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); ++ break; ++ ++ default: ++ dev_err(priv->dev, "incompatible PHY type\n"); ++ return -EINVAL; ++ } ++ ++ rate = clk_get_rate(priv->refclk); ++ ++ switch (rate) { ++ case REF_CLOCK_24MHz: ++ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { ++ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ ++ val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, ++ val, PHYREG15); ++ ++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); ++ } ++ break; ++ ++ case REF_CLOCK_25MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); ++ break; ++ ++ case REF_CLOCK_100MHz: ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); ++ if (priv->type == PHY_TYPE_PCIE) { ++ /* PLL KVCO fine tuning. */ ++ val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, ++ val, PHYREG33); ++ ++ /* Enable controlling random jitter. */ ++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); ++ ++ val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, ++ val, PHYREG6); ++ ++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); ++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); ++ } else if (priv->type == PHY_TYPE_SATA) { ++ /* downward spread spectrum +500ppm */ ++ val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; ++ val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; ++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); ++ } ++ break; ++ ++ default: ++ dev_err(priv->dev, "unsupported rate: %lu\n", rate); ++ return -EINVAL; ++ } ++ ++ if (priv->ext_refclk) { ++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); ++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { ++ val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; ++ val |= PHYREG13_CKRCV_AMP0; ++ rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); ++ ++ val = readl(priv->mmio + PHYREG14); ++ val |= PHYREG14_CKRCV_AMP1; ++ writel(val, priv->mmio + PHYREG14); ++ } ++ } ++ ++ if (priv->enable_ssc) { ++ val = readl(priv->mmio + PHYREG8); ++ val |= PHYREG8_SSC_EN; ++ writel(val, priv->mmio + PHYREG8); ++ } ++ ++ return 0; ++} ++ ++static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { ++ /* pipe-phy-grf */ ++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, ++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, ++ .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, ++ .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, ++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, ++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, ++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, ++ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, ++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, ++ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, ++ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, ++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, ++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, ++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, ++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, ++ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, ++ .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, ++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, ++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, ++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, ++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, ++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, ++ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, ++ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, ++ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, ++ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, ++ /* pipe-grf */ ++ .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, ++ .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, ++}; ++ ++static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { ++ .grfcfg = &rk3568_combphy_grfcfgs, ++ .combphy_cfg = rk3568_combphy_cfg, ++}; ++ ++static const struct of_device_id rockchip_combphy_of_match[] = { ++ { ++ .compatible = "rockchip,rk3568-naneng-combphy", ++ .data = &rk3568_combphy_cfgs, ++ }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); ++ ++static struct platform_driver rockchip_combphy_driver = { ++ .probe = rockchip_combphy_probe, ++ .driver = { ++ .name = "rockchip-naneng-combphy", ++ .of_match_table = rockchip_combphy_of_match, ++ }, ++}; ++module_platform_driver(rockchip_combphy_driver); ++ ++MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/rockchip/patches-5.15/038-v5.18-arm64-dts-rockchip-add-naneng-combo-phy-nodes-for.patch b/target/linux/rockchip/patches-5.15/038-v5.18-arm64-dts-rockchip-add-naneng-combo-phy-nodes-for.patch new file mode 100644 index 000000000..300ced428 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/038-v5.18-arm64-dts-rockchip-add-naneng-combo-phy-nodes-for.patch @@ -0,0 +1,122 @@ +From 3cc8cd2d25954ed5794df2d190b81c7325c584e3 Mon Sep 17 00:00:00 2001 +From: Yifeng Zhao +Date: Tue, 8 Feb 2022 17:13:26 +0800 +Subject: [PATCH] arm64: dts: rockchip: add naneng combo phy nodes for rk3568 + +Add the core dt-node for the rk3568's naneng combo phys. + +Signed-off-by: Yifeng Zhao +Signed-off-by: Johan Jonker +Tested-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220208091326.12495-5-yifeng.zhao@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ + 2 files changed, 68 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -8,6 +8,11 @@ + / { + compatible = "rockchip,rk3568"; + ++ pipe_phy_grf0: syscon@fdc70000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc70000 0x0 0x1000>; ++ }; ++ + qos_pcie3x1: qos@fe190080 { + compatible = "rockchip,rk3568-qos", "syscon"; + reg = <0x0 0xfe190080 0x0 0x20>; +@@ -71,6 +76,22 @@ + queue0 {}; + }; + }; ++ ++ combphy0: phy@fe820000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe820000 0x0 0x100>; ++ clocks = <&pmucru CLK_PCIEPHY0_REF>, ++ <&cru PCLK_PIPEPHY0>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; ++ assigned-clock-rates = <100000000>; ++ resets = <&cru SRST_PIPEPHY0>; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf0>; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; + }; + + &cpu0_opp_table { +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -296,11 +296,26 @@ + }; + }; + ++ pipegrf: syscon@fdc50000 { ++ compatible = "rockchip,rk3568-pipe-grf", "syscon"; ++ reg = <0x0 0xfdc50000 0x0 0x1000>; ++ }; ++ + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + }; + ++ pipe_phy_grf1: syscon@fdc80000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc80000 0x0 0x1000>; ++ }; ++ ++ pipe_phy_grf2: syscon@fdc90000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc90000 0x0 0x1000>; ++ }; ++ + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; +@@ -1307,6 +1322,38 @@ + status = "disabled"; + }; + ++ combphy1: phy@fe830000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe830000 0x0 0x100>; ++ clocks = <&pmucru CLK_PCIEPHY1_REF>, ++ <&cru PCLK_PIPEPHY1>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; ++ assigned-clock-rates = <100000000>; ++ resets = <&cru SRST_PIPEPHY1>; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf1>; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ combphy2: phy@fe840000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe840000 0x0 0x100>; ++ clocks = <&pmucru CLK_PCIEPHY2_REF>, ++ <&cru PCLK_PIPEPHY2>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; ++ assigned-clock-rates = <100000000>; ++ resets = <&cru SRST_PIPEPHY2>; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf2>; ++ #phy-cells = <1>; ++ status = "disabled"; ++ }; ++ + usb2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.15/039-v5.18-arm64-dts-rockchip-Add-sata-nodes-to-rk356x.patch b/target/linux/rockchip/patches-5.15/039-v5.18-arm64-dts-rockchip-Add-sata-nodes-to-rk356x.patch new file mode 100644 index 000000000..55ae092eb --- /dev/null +++ b/target/linux/rockchip/patches-5.15/039-v5.18-arm64-dts-rockchip-Add-sata-nodes-to-rk356x.patch @@ -0,0 +1,76 @@ +From 16c0f95d9ed14f033b5f1bd37e96d257b60c198c Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Fri, 11 Mar 2022 22:03:57 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add sata nodes to rk356x + +RK356x supports up to 3 sata controllers which were compatible with the +existing snps,dwc-ahci binding. + +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220311210357.222830-7-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++++++++++++++ + 2 files changed, 42 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -8,6 +8,20 @@ + / { + compatible = "rockchip,rk3568"; + ++ sata0: sata@fc000000 { ++ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfc000000 0 0x1000>; ++ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, ++ <&cru CLK_SATA0_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ phys = <&combphy0 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; ++ }; ++ + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -196,6 +196,34 @@ + }; + }; + ++ sata1: sata@fc400000 { ++ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfc400000 0 0x1000>; ++ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, ++ <&cru CLK_SATA1_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ phys = <&combphy1 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; ++ }; ++ ++ sata2: sata@fc800000 { ++ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; ++ reg = <0 0xfc800000 0 0x1000>; ++ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, ++ <&cru CLK_SATA2_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ phys = <&combphy2 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ diff --git a/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch b/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch new file mode 100644 index 000000000..3471ee919 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/040-v5.18-usb-dwc3-core-do-not-use-3.0-clock-when-operating-in-2.0.patch @@ -0,0 +1,46 @@ +From 62b20e6e0dde8d5633e3d94b028f86fb24b31d22 Mon Sep 17 00:00:00 2001 +From: Bin Yang +Date: Mon, 28 Feb 2022 08:56:56 -0500 +Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 + mode + +In the 3.0 device core, if the core is programmed to operate in +2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes +the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) +clock. Enabling this feature allows the pipe3 clock to be not-running +when forcibly operating in 2.0 device mode. + +Tested-by: Michael Riesch +Signed-off-by: Bin Yang +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220228135700.1089526-6-pgwipeout@gmail.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc3/core.c | 5 +++++ + drivers/usb/dwc3/core.h | 1 + + 2 files changed, 6 insertions(+) + +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -1061,6 +1061,11 @@ static int dwc3_core_init(struct dwc3 *dwc) + if (dwc->parkmode_disable_ss_quirk) + reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; + ++ if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && ++ (dwc->maximum_speed == USB_SPEED_HIGH || ++ dwc->maximum_speed == USB_SPEED_FULL)) ++ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; ++ + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -258,6 +258,7 @@ + /* Global User Control 1 Register */ + #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) + #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) ++#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) + #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) + #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) + diff --git a/target/linux/rockchip/patches-5.15/050-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch b/target/linux/rockchip/patches-5.15/050-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch new file mode 100644 index 000000000..b8eae8a19 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/050-v5.18-mmc-dw_mmc-Support-setting-f_min-from-host-drivers.patch @@ -0,0 +1,54 @@ +From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Sat, 5 Mar 2022 16:58:34 -0500 +Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers + +Host drivers may not be able to support frequencies as low as dw-mmc +supports. Unfortunately f_min isn't available when the drv_data->init +function is called, as the mmc_host struct hasn't been set up yet. + +Support the host drivers saving the requested minimum frequency, so we +can later set f_min when it is available. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/dw_mmc.c | 7 ++++++- + drivers/mmc/host/dw_mmc.h | 2 ++ + 2 files changed, 8 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/dw_mmc.c ++++ b/drivers/mmc/host/dw_mmc.c +@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) + if (host->pdata->caps2) + mmc->caps2 = host->pdata->caps2; + +- mmc->f_min = DW_MCI_FREQ_MIN; ++ /* if host has set a minimum_freq, we should respect it */ ++ if (host->minimum_speed) ++ mmc->f_min = host->minimum_speed; ++ else ++ mmc->f_min = DW_MCI_FREQ_MIN; ++ + if (!mmc->f_max) + mmc->f_max = DW_MCI_FREQ_MAX; + +--- a/drivers/mmc/host/dw_mmc.h ++++ b/drivers/mmc/host/dw_mmc.h +@@ -99,6 +99,7 @@ struct dw_mci_dma_slave { + * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus + * rate and timeout calculations. + * @current_speed: Configured rate of the controller. ++ * @minimum_speed: Stored minimum rate of the controller. + * @fifoth_val: The value of FIFOTH register. + * @verid: Denote Version ID. + * @dev: Device associated with the MMC controller. +@@ -200,6 +201,7 @@ struct dw_mci { + + u32 bus_hz; + u32 current_speed; ++ u32 minimum_speed; + u32 fifoth_val; + u16 verid; + struct device *dev; diff --git a/target/linux/rockchip/patches-5.15/051-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch b/target/linux/rockchip/patches-5.15/051-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch new file mode 100644 index 000000000..90aa7c23b --- /dev/null +++ b/target/linux/rockchip/patches-5.15/051-v5.18-mmc-dw-mmc-rockchip-Fix-handling-invalid-clock-rates.patch @@ -0,0 +1,79 @@ +From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Sat, 5 Mar 2022 16:58:35 -0500 +Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates + +The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc +hardware supports. This leads to a situation during card initialization +where the clock is set lower than the clock driver can support. The +dw-mmc-rockchip driver spews errors when this happens. +For normal operation this only happens a few times during boot, but when +cd-broken is enabled (in cases such as the SoQuartz module) this fires +multiple times each poll cycle. + +Fix this by testing the lowest possible frequency that the clock driver +can support which is within the mmc specification. Divide that rate by +the internal divider and set f_min to this. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++---- + 1 file changed, 23 insertions(+), 4 deletions(-) + +--- a/drivers/mmc/host/dw_mmc-rockchip.c ++++ b/drivers/mmc/host/dw_mmc-rockchip.c +@@ -15,7 +15,9 @@ + #include "dw_mmc.h" + #include "dw_mmc-pltfm.h" + +-#define RK3288_CLKGEN_DIV 2 ++#define RK3288_CLKGEN_DIV 2 ++ ++static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 }; + + struct dw_mci_rockchip_priv_data { + struct clk *drv_clk; +@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) + + ret = clk_set_rate(host->ciu_clk, cclkin); + if (ret) +- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); ++ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret); + + bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; + if (bus_hz != host->bus_hz) { +@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host) + + static int dw_mci_rockchip_init(struct dw_mci *host) + { ++ int ret, i; ++ + /* It is slot 8 on Rockchip SoCs */ + host->sdio_id0 = 8; + +- if (of_device_is_compatible(host->dev->of_node, +- "rockchip,rk3288-dw-mshc")) ++ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) { + host->bus_hz /= RK3288_CLKGEN_DIV; + ++ /* clock driver will fail if the clock is less than the lowest source clock ++ * divided by the internal clock divider. Test for the lowest available ++ * clock and set the minimum freq to clock / clock divider. ++ */ ++ ++ for (i = 0; i < ARRAY_SIZE(freqs); i++) { ++ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV); ++ if (ret > 0) { ++ host->minimum_speed = ret / RK3288_CLKGEN_DIV; ++ break; ++ } ++ } ++ if (ret < 0) ++ dev_warn(host->dev, "no valid minimum freq: %d\n", ret); ++ } ++ + return 0; + } + diff --git a/target/linux/rockchip/patches-5.15/052-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch b/target/linux/rockchip/patches-5.15/052-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch new file mode 100644 index 000000000..74f99511d --- /dev/null +++ b/target/linux/rockchip/patches-5.15/052-v5.16-mfd-rk808-Add-support-for-power-off-on-RK817.patch @@ -0,0 +1,27 @@ +From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Sun, 29 Aug 2021 04:51:53 +0200 +Subject: [PATCH] mfd: rk808: Add support for power off on RK817 + +RK817 has a power-off bit in SYS_CFG3. Add support for powering +off the PMIC. + +Signed-off-by: Ondrej Jirman +Signed-off-by: Lee Jones +--- + drivers/mfd/rk808.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -543,6 +543,10 @@ static void rk808_pm_power_off(void) + reg = RK808_DEVCTRL_REG, + bit = DEV_OFF_RST; + break; ++ case RK817_ID: ++ reg = RK817_SYS_CFG(3); ++ bit = DEV_OFF; ++ break; + case RK818_ID: + reg = RK818_DEVCTRL_REG; + bit = DEV_OFF; diff --git a/target/linux/rockchip/patches-5.15/053-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch b/target/linux/rockchip/patches-5.15/053-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch new file mode 100644 index 000000000..a540cfe75 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/053-v5.18-mfd-rk808-Add-reboot-support-to-rk808.c.patch @@ -0,0 +1,110 @@ +From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Tue, 8 Feb 2022 14:40:23 -0500 +Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c + +This adds reboot support to the rk808 pmic driver and enables it for +the rk809 and rk817 devices. +This only enables if the rockchip,system-power-controller flag is set. + +Signed-off-by: Peter Geis +Signed-off-by: Frank Wunderlich +Reviewed-by: Dmitry Osipenko +Signed-off-by: Lee Jones +Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com +--- + drivers/mfd/rk808.c | 44 +++++++++++++++++++++++++++++++++++++++ + include/linux/mfd/rk808.h | 1 + + 2 files changed, 45 insertions(+) + +--- a/drivers/mfd/rk808.c ++++ b/drivers/mfd/rk808.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + struct rk808_reg_data { + int addr; +@@ -543,6 +544,7 @@ static void rk808_pm_power_off(void) + reg = RK808_DEVCTRL_REG, + bit = DEV_OFF_RST; + break; ++ case RK809_ID: + case RK817_ID: + reg = RK817_SYS_CFG(3); + bit = DEV_OFF; +@@ -559,6 +561,34 @@ static void rk808_pm_power_off(void) + dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n"); + } + ++static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd) ++{ ++ struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client); ++ unsigned int reg, bit; ++ int ret; ++ ++ switch (rk808->variant) { ++ case RK809_ID: ++ case RK817_ID: ++ reg = RK817_SYS_CFG(3); ++ bit = DEV_RST; ++ break; ++ ++ default: ++ return NOTIFY_DONE; ++ } ++ ret = regmap_update_bits(rk808->regmap, reg, bit, bit); ++ if (ret) ++ dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n"); ++ ++ return NOTIFY_DONE; ++} ++ ++static struct notifier_block rk808_restart_handler = { ++ .notifier_call = rk808_restart_notify, ++ .priority = 192, ++}; ++ + static void rk8xx_shutdown(struct i2c_client *client) + { + struct rk808 *rk808 = i2c_get_clientdata(client); +@@ -727,6 +757,18 @@ static int rk808_probe(struct i2c_client *client, + if (of_property_read_bool(np, "rockchip,system-power-controller")) { + rk808_i2c_client = client; + pm_power_off = rk808_pm_power_off; ++ ++ switch (rk808->variant) { ++ case RK809_ID: ++ case RK817_ID: ++ ret = register_restart_handler(&rk808_restart_handler); ++ if (ret) ++ dev_warn(&client->dev, "failed to register rst handler, %d\n", ret); ++ break; ++ default: ++ dev_dbg(&client->dev, "pmic controlled board reset not supported\n"); ++ break; ++ } + } + + return 0; +@@ -749,6 +791,8 @@ static int rk808_remove(struct i2c_client *client) + if (pm_power_off == rk808_pm_power_off) + pm_power_off = NULL; + ++ unregister_restart_handler(&rk808_restart_handler); ++ + return 0; + } + +--- a/include/linux/mfd/rk808.h ++++ b/include/linux/mfd/rk808.h +@@ -373,6 +373,7 @@ enum rk805_reg { + #define SWITCH2_EN BIT(6) + #define SWITCH1_EN BIT(5) + #define DEV_OFF_RST BIT(3) ++#define DEV_RST BIT(2) + #define DEV_OFF BIT(0) + #define RTC_STOP BIT(0) + diff --git a/target/linux/rockchip/patches-5.15/054-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch b/target/linux/rockchip/patches-5.15/054-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch new file mode 100644 index 000000000..680211ec3 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/054-v5.19-soc-rockchip-set-dwc3-clock-for-rk3566.patch @@ -0,0 +1,51 @@ +From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 8 Apr 2022 11:12:34 -0400 +Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566 + +The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to +the combophy as the clock source. As combophy0 doesn't exist on rk3566, +we need to set the clock source to the usb2 phy instead. + +Add handling to the grf driver to handle this on boot. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + drivers/soc/rockchip/grf.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/drivers/soc/rockchip/grf.c ++++ b/drivers/soc/rockchip/grf.c +@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk3399_grf __initconst = { + .num_values = ARRAY_SIZE(rk3399_defaults), + }; + ++#define RK3566_GRF_USB3OTG0_CON1 0x0104 ++ ++static const struct rockchip_grf_value rk3566_defaults[] __initconst = { ++ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) }, ++ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) }, ++ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) }, ++}; ++ ++static const struct rockchip_grf_info rk3566_pipegrf __initconst = { ++ .values = rk3566_defaults, ++ .num_values = ARRAY_SIZE(rk3566_defaults), ++}; ++ ++ + static const struct of_device_id rockchip_grf_dt_match[] __initconst = { + { + .compatible = "rockchip,rk3036-grf", +@@ -130,6 +144,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = { + }, { + .compatible = "rockchip,rk3399-grf", + .data = (void *)&rk3399_grf, ++ }, { ++ .compatible = "rockchip,rk3566-pipe-grf", ++ .data = (void *)&rk3566_pipegrf, + }, + { /* sentinel */ }, + }; diff --git a/target/linux/rockchip/patches-5.15/055-v5.19-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch b/target/linux/rockchip/patches-5.15/055-v5.19-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch new file mode 100644 index 000000000..4856b382a --- /dev/null +++ b/target/linux/rockchip/patches-5.15/055-v5.19-arm64-dts-rockchip-add-rk356x-dwc3-usb3-nodes.patch @@ -0,0 +1,118 @@ +From 9f4c480f24e2ce1d464ff9d5f8a249a485acdc7f Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 8 Apr 2022 11:12:35 -0400 +Subject: [PATCH] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes + +Add the dwc3 device nodes to the rk356x device trees. +The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable +dwc3 host controller. +The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable +dwc3 host controller. + +Signed-off-by: Peter Geis +Tested-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++ + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++ + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++- + 3 files changed, 54 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi +@@ -6,6 +6,10 @@ + compatible = "rockchip,rk3566"; + }; + ++&pipegrf { ++ compatible = "rockchip,rk3566-pipe-grf", "syscon"; ++}; ++ + &power { + power-domain@RK3568_PD_PIPE { + reg = ; +@@ -18,3 +22,10 @@ + #power-domain-cells = <0>; + }; + }; ++ ++&usb_host0_xhci { ++ phys = <&usb2phy0_otg>; ++ phy-names = "usb2-phy"; ++ extcon = <&usb2phy0>; ++ maximum-speed = "high-speed"; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -113,6 +113,10 @@ + }; + }; + ++&pipegrf { ++ compatible = "rockchip,rk3568-pipe-grf", "syscon"; ++}; ++ + &power { + power-domain@RK3568_PD_PIPE { + reg = ; +@@ -128,3 +132,8 @@ + #power-domain-cells = <0>; + }; + }; ++ ++&usb_host0_xhci { ++ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -258,6 +258,40 @@ + status = "disabled"; + }; + ++ usb_host0_xhci: usb@fcc00000 { ++ compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfcc00000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, ++ <&cru ACLK_USB3OTG0>; ++ clock-names = "ref_clk", "suspend_clk", ++ "bus_clk"; ++ dr_mode = "host"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ resets = <&cru SRST_USB3OTG0>; ++ snps,dis_u2_susphy_quirk; ++ status = "disabled"; ++ }; ++ ++ usb_host1_xhci: usb@fd000000 { ++ compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; ++ reg = <0x0 0xfd000000 0x0 0x400000>; ++ interrupts = ; ++ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, ++ <&cru ACLK_USB3OTG1>; ++ clock-names = "ref_clk", "suspend_clk", ++ "bus_clk"; ++ dr_mode = "host"; ++ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ phy_type = "utmi_wide"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ resets = <&cru SRST_USB3OTG1>; ++ snps,dis_u2_susphy_quirk; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ +@@ -325,7 +359,6 @@ + }; + + pipegrf: syscon@fdc50000 { +- compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + diff --git a/target/linux/rockchip/patches-5.15/056-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch b/target/linux/rockchip/patches-5.15/056-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch new file mode 100644 index 000000000..0efa18ed3 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/056-v5.19-PCI-rockchip-dwc-Reset-core-at-driver-probe.patch @@ -0,0 +1,72 @@ +From 431e7d2eece5b906578926d15ee22a70504c364d Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 29 Apr 2022 08:38:28 -0400 +Subject: [PATCH] PCI: rockchip-dwc: Reset core at driver probe + +The PCIe controller is in an unknown state at driver probe. This can +lead to undesireable effects when the driver attempts to configure the +controller. + +Prevent issues in the future by resetting the core during probe. + +Link: https://lore.kernel.org/r/20220429123832.2376381-3-pgwipeout@gmail.com +Tested-by: Nicolas Frattaroli +Signed-off-by: Peter Geis +Signed-off-by: Lorenzo Pieralisi +--- + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++----------- + 1 file changed, 10 insertions(+), 13 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c ++++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c +@@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev, + if (IS_ERR(rockchip->rst_gpio)) + return PTR_ERR(rockchip->rst_gpio); + ++ rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev); ++ if (IS_ERR(rockchip->rst)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst), ++ "failed to get reset lines\n"); ++ + return 0; + } + +@@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip) + phy_power_off(rockchip->phy); + } + +-static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip) +-{ +- struct device *dev = rockchip->pci.dev; +- +- rockchip->rst = devm_reset_control_array_get_exclusive(dev); +- if (IS_ERR(rockchip->rst)) +- return dev_err_probe(dev, PTR_ERR(rockchip->rst), +- "failed to get reset lines\n"); +- +- return reset_control_deassert(rockchip->rst); +-} +- + static const struct dw_pcie_ops dw_pcie_ops = { + .link_up = rockchip_pcie_link_up, + .start_link = rockchip_pcie_start_link, +@@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct platform_device *pdev) + if (ret) + return ret; + ++ ret = reset_control_assert(rockchip->rst); ++ if (ret) ++ return ret; ++ + /* DON'T MOVE ME: must be enable before PHY init */ + rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3"); + if (IS_ERR(rockchip->vpcie3v3)) { +@@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev) + if (ret) + goto disable_regulator; + +- ret = rockchip_pcie_reset_control_release(rockchip); ++ ret = reset_control_deassert(rockchip->rst); + if (ret) + goto deinit_phy; + diff --git a/target/linux/rockchip/patches-5.15/057-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch b/target/linux/rockchip/patches-5.15/057-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch new file mode 100644 index 000000000..1f695c42f --- /dev/null +++ b/target/linux/rockchip/patches-5.15/057-v5.19-PCI-rockchip-dwc-Add-legacy-interrupt-support.patch @@ -0,0 +1,163 @@ +From e8aae154df6121167e5b4f156cfc2402e651d2b1 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 29 Apr 2022 08:38:29 -0400 +Subject: [PATCH] PCI: rockchip-dwc: Add legacy interrupt support + +The legacy interrupts on the rk356x PCIe controller are handled by a +single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip +driver to support the virtual domain. + +Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com +Signed-off-by: Peter Geis +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Marc Zyngier +--- + drivers/pci/controller/dwc/pcie-dw-rockchip.c | 96 ++++++++++++++++++- + 1 file changed, 94 insertions(+), 2 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c ++++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c +@@ -10,9 +10,12 @@ + + #include + #include ++#include ++#include + #include + #include + #include ++#include + #include + #include + #include +@@ -26,6 +29,7 @@ + */ + #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) + #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) ++#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val) + + #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) + +@@ -36,10 +40,12 @@ + #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) + #define PCIE_L0S_ENTRY 0x11 + #define PCIE_CLIENT_GENERAL_CONTROL 0x0 ++#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 ++#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c + #define PCIE_CLIENT_GENERAL_DEBUG 0x104 +-#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 ++#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 + #define PCIE_CLIENT_LTSSM_STATUS 0x300 +-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) ++#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) + #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) + + struct rockchip_pcie { +@@ -51,6 +57,7 @@ struct rockchip_pcie { + struct reset_control *rst; + struct gpio_desc *rst_gpio; + struct regulator *vpcie3v3; ++ struct irq_domain *irq_domain; + }; + + static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, +@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, + writel_relaxed(val, rockchip->apb_base + reg); + } + ++static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) ++{ ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); ++ unsigned long reg, hwirq; ++ ++ chained_irq_enter(chip, desc); ++ ++ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY); ++ ++ for_each_set_bit(hwirq, ®, 4) ++ generic_handle_domain_irq(rockchip->irq_domain, hwirq); ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static void rockchip_intx_mask(struct irq_data *data) ++{ ++ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), ++ HIWORD_UPDATE_BIT(BIT(data->hwirq)), ++ PCIE_CLIENT_INTR_MASK_LEGACY); ++}; ++ ++static void rockchip_intx_unmask(struct irq_data *data) ++{ ++ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data), ++ HIWORD_DISABLE_BIT(BIT(data->hwirq)), ++ PCIE_CLIENT_INTR_MASK_LEGACY); ++}; ++ ++static struct irq_chip rockchip_intx_irq_chip = { ++ .name = "INTx", ++ .irq_mask = rockchip_intx_mask, ++ .irq_unmask = rockchip_intx_unmask, ++ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, ++}; ++ ++static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq); ++ irq_set_chip_data(irq, domain->host_data); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops intx_domain_ops = { ++ .map = rockchip_pcie_intx_map, ++}; ++ ++static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) ++{ ++ struct device *dev = rockchip->pci.dev; ++ struct device_node *intc; ++ ++ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); ++ if (!intc) { ++ dev_err(dev, "missing child interrupt-controller node\n"); ++ return -EINVAL; ++ } ++ ++ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, ++ &intx_domain_ops, rockchip); ++ of_node_put(intc); ++ if (!rockchip->irq_domain) { ++ dev_err(dev, "failed to get a INTx IRQ domain\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) + { + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, +@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struct pcie_port *pp) + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); ++ struct device *dev = rockchip->pci.dev; + u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); ++ int irq, ret; ++ ++ irq = of_irq_get_byname(dev->of_node, "legacy"); ++ if (irq < 0) ++ return irq; ++ ++ ret = rockchip_pcie_init_irq_domain(rockchip); ++ if (ret < 0) ++ dev_err(dev, "failed to init irq domain\n"); ++ ++ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, ++ rockchip); + + /* LTSSM enable control mode */ + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); diff --git a/target/linux/rockchip/patches-5.15/058-v5.19-arm64-dts-rockchip-add-rk356x-sfc-support.patch b/target/linux/rockchip/patches-5.15/058-v5.19-arm64-dts-rockchip-add-rk356x-sfc-support.patch new file mode 100644 index 000000000..bb7769d90 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/058-v5.19-arm64-dts-rockchip-add-rk356x-sfc-support.patch @@ -0,0 +1,35 @@ +From 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 29 Apr 2022 07:52:49 -0400 +Subject: [PATCH] arm64: dts: rockchip: add rk356x sfc support + +Add the sfc node to the rk356x device tree. This enables spi flash +support for this soc. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220429115252.2360496-5-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -778,6 +778,17 @@ + status = "disabled"; + }; + ++ sfc: spi@fe300000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xfe300000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&fspi_pins>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ + sdhci: mmc@fe310000 { + compatible = "rockchip,rk3568-dwcmshc"; + reg = <0x0 0xfe310000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.15/059-v5.19-arm64-dts-rockchip-add-clocks-to-rk356x-cru.patch b/target/linux/rockchip/patches-5.15/059-v5.19-arm64-dts-rockchip-add-clocks-to-rk356x-cru.patch new file mode 100644 index 000000000..b2d863ca4 --- /dev/null +++ b/target/linux/rockchip/patches-5.15/059-v5.19-arm64-dts-rockchip-add-clocks-to-rk356x-cru.patch @@ -0,0 +1,26 @@ +From cd2d081d18de396cb45636c215dc589a330b3f4e Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 11 May 2022 11:01:13 -0400 +Subject: [PATCH] arm64: dts: rockchip: add clocks to rk356x cru + +The rk356x cru requires a 24m clock input to function. Add the clocks +properties to the cru to clear some dtbs_check warnings. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220511150117.113070-3-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -397,6 +397,8 @@ + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; ++ clocks = <&xin24m>; ++ clock-names = "xin24m"; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; diff --git a/target/linux/rockchip/patches-5.15/060-v5.20-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch b/target/linux/rockchip/patches-5.15/060-v5.20-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch new file mode 100644 index 000000000..c36cfa69e --- /dev/null +++ b/target/linux/rockchip/patches-5.15/060-v5.20-arm64-dts-rockchip-Add-rk3568-PCIe2x1-controller.patch @@ -0,0 +1,74 @@ +From 66b51ea7d70fcc2ede87161c413fe1db4422bdac Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 29 Apr 2022 08:38:30 -0400 +Subject: [PATCH] arm64: dts: rockchip: Add rk3568 PCIe2x1 controller + +The PCIe2x1 controller is common between the rk3568 and rk3566. It is a +single lane PCIe2 compliant controller. + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20220429123832.2376381-5-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -752,6 +752,56 @@ + reg = <0x0 0xfe1a8100 0x0 0x20>; + }; + ++ pcie2x1: pcie@fe260000 { ++ compatible = "rockchip,rk3568-pcie"; ++ reg = <0x3 0xc0000000 0x0 0x00400000>, ++ <0x0 0xfe260000 0x0 0x00010000>, ++ <0x3 0x3f000000 0x0 0x01000000>; ++ reg-names = "dbi", "apb", "config"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, ++ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, ++ <&cru CLK_PCIE20_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc 0>, ++ <0 0 0 2 &pcie_intc 1>, ++ <0 0 0 3 &pcie_intc 2>, ++ <0 0 0 4 &pcie_intc 3>; ++ linux,pci-domain = <0>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <2>; ++ msi-map = <0x0 &gic 0x0 0x1000>; ++ num-lanes = <1>; ++ phys = <&combphy2 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000 ++ 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>; ++ resets = <&cru SRST_PCIE20_POWERUP>; ++ reset-names = "pipe"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ status = "disabled"; ++ ++ pcie_intc: legacy-interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; diff --git a/target/linux/rockchip/patches-5.15/061-v5.20-arm64-enable-THP_SWAP-for-arm64.patch b/target/linux/rockchip/patches-5.15/061-v5.20-arm64-enable-THP_SWAP-for-arm64.patch new file mode 100644 index 000000000..73df40e4d --- /dev/null +++ b/target/linux/rockchip/patches-5.15/061-v5.20-arm64-enable-THP_SWAP-for-arm64.patch @@ -0,0 +1,123 @@ +From d0637c505f8a1d8c4088642f1f3e9e3b22da14f6 Mon Sep 17 00:00:00 2001 +From: Barry Song +Date: Wed, 20 Jul 2022 21:37:37 +1200 +Subject: [PATCH] arm64: enable THP_SWAP for arm64 + +THP_SWAP has been proven to improve the swap throughput significantly +on x86_64 according to commit bd4c82c22c367e ("mm, THP, swap: delay +splitting THP after swapped out"). +As long as arm64 uses 4K page size, it is quite similar with x86_64 +by having 2MB PMD THP. THP_SWAP is architecture-independent, thus, +enabling it on arm64 will benefit arm64 as well. +A corner case is that MTE has an assumption that only base pages +can be swapped. We won't enable THP_SWAP for ARM64 hardware with +MTE support until MTE is reworked to coexist with THP_SWAP. + +A micro-benchmark is written to measure thp swapout throughput as +below, + + unsigned long long tv_to_ms(struct timeval tv) + { + return tv.tv_sec * 1000 + tv.tv_usec / 1000; + } + + main() + { + struct timeval tv_b, tv_e;; + #define SIZE 400*1024*1024 + volatile void *p = mmap(NULL, SIZE, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (!p) { + perror("fail to get memory"); + exit(-1); + } + + madvise(p, SIZE, MADV_HUGEPAGE); + memset(p, 0x11, SIZE); /* write to get mem */ + + gettimeofday(&tv_b, NULL); + madvise(p, SIZE, MADV_PAGEOUT); + gettimeofday(&tv_e, NULL); + + printf("swp out bandwidth: %ld bytes/ms\n", + SIZE/(tv_to_ms(tv_e) - tv_to_ms(tv_b))); + } + +Testing is done on rk3568 64bit Quad Core Cortex-A55 platform - +ROCK 3A. +thp swp throughput w/o patch: 2734bytes/ms (mean of 10 tests) +thp swp throughput w/ patch: 3331bytes/ms (mean of 10 tests) + +Cc: "Huang, Ying" +Cc: Minchan Kim +Cc: Johannes Weiner +Cc: Hugh Dickins +Cc: Andrea Arcangeli +Cc: Steven Price +Cc: Yang Shi +Reviewed-by: Anshuman Khandual +Signed-off-by: Barry Song +Link: https://lore.kernel.org/r/20220720093737.133375-1-21cnbao@gmail.com +Signed-off-by: Will Deacon +--- + arch/arm64/Kconfig | 1 + + arch/arm64/include/asm/pgtable.h | 6 ++++++ + include/linux/huge_mm.h | 12 ++++++++++++ + mm/swap_slots.c | 2 +- + 4 files changed, 20 insertions(+), 1 deletion(-) + +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -101,6 +101,7 @@ config ARM64 + select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP + select ARCH_WANT_LD_ORPHAN_WARN + select ARCH_WANTS_NO_INSTR ++ select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES + select ARCH_HAS_UBSAN_SANITIZE_ALL + select ARM_AMBA + select ARM_ARCH_TIMER +--- a/arch/arm64/include/asm/pgtable.h ++++ b/arch/arm64/include/asm/pgtable.h +@@ -45,6 +45,12 @@ + __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1) + #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ + ++static inline bool arch_thp_swp_supported(void) ++{ ++ return !system_supports_mte(); ++} ++#define arch_thp_swp_supported arch_thp_swp_supported ++ + /* + * Outside of a few very special situations (e.g. hibernation), we always + * use broadcast TLB invalidation instructions, therefore a spurious page +--- a/include/linux/huge_mm.h ++++ b/include/linux/huge_mm.h +@@ -461,4 +461,16 @@ static inline int split_folio_to_list(struct folio *folio, + return PAGE_SIZE << thp_order(page); + } + ++/* ++ * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to ++ * limitations in the implementation like arm64 MTE can override this to ++ * false ++ */ ++#ifndef arch_thp_swp_supported ++static inline bool arch_thp_swp_supported(void) ++{ ++ return true; ++} ++#endif ++ + #endif /* _LINUX_HUGE_MM_H */ +--- a/mm/swap_slots.c ++++ b/mm/swap_slots.c +@@ -307,7 +307,7 @@ swp_entry_t folio_alloc_swap(struct folio *folio) + entry.val = 0; + + if (PageTransHuge(page)) { +- if (IS_ENABLED(CONFIG_THP_SWAP)) ++ if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported()) + get_swap_pages(1, &entry, HPAGE_PMD_NR); + goto out; + } diff --git a/target/linux/rockchip/patches-5.15/108-drivers-phy-rockchip-Support-PCIe-v3.patch b/target/linux/rockchip/patches-5.15/108-drivers-phy-rockchip-Support-PCIe-v3.patch new file mode 100644 index 000000000..955bd6eaf --- /dev/null +++ b/target/linux/rockchip/patches-5.15/108-drivers-phy-rockchip-Support-PCIe-v3.patch @@ -0,0 +1,392 @@ +From cfb1aa4c805e58287dd0ce292b5c64309e3dba2f Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Thu, 25 Aug 2022 21:38:34 +0200 +Subject: [PATCH] phy: rockchip: Support PCIe v3 + +RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566. +It use a dedicated PCIe-phy. Add support for this. + +Initial support by Shawn Lin, modifications by Peter Geis and Frank +Wunderlich. + +Add data-lanes property for splitting pcie-lanes across controllers. + +The data-lanes is an array where x=0 means lane is disabled and x > 0 +means controller x is assigned to phy lane. + +Signed-off-by: Shawn Lin +Suggested-by: Peter Geis +Signed-off-by: Frank Wunderlich +--- + drivers/phy/rockchip/Kconfig | 9 + + drivers/phy/rockchip/Makefile | 1 + + .../phy/rockchip/phy-rockchip-snps-pcie3.c | 319 ++++++++++++++++++ + include/linux/phy/pcie.h | 12 + + 4 files changed, 341 insertions(+) + create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c + create mode 100644 include/linux/phy/pcie.h + +--- a/drivers/phy/rockchip/Kconfig ++++ b/drivers/phy/rockchip/Kconfig +@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE + help + Enable this to support the Rockchip PCIe PHY. + ++config PHY_ROCKCHIP_SNPS_PCIE3 ++ tristate "Rockchip Snps PCIe3 PHY Driver" ++ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST ++ depends on HAS_IOMEM ++ select GENERIC_PHY ++ select MFD_SYSCON ++ help ++ Enable this to support the Rockchip snps PCIe3 PHY. ++ + config PHY_ROCKCHIP_TYPEC + tristate "Rockchip TYPEC PHY Driver" + depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST) +--- a/drivers/phy/rockchip/Makefile ++++ b/drivers/phy/rockchip/Makefile +@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o + obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o + obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o + obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o ++obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o + obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o + obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o +--- /dev/null ++++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +@@ -0,0 +1,319 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip PCIE3.0 phy driver ++ * ++ * Copyright (C) 2022 Rockchip Electronics Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Register for RK3568 */ ++#define GRF_PCIE30PHY_CON1 0x4 ++#define GRF_PCIE30PHY_CON6 0x18 ++#define GRF_PCIE30PHY_CON9 0x24 ++#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31)) ++#define GRF_PCIE30PHY_STATUS0 0x80 ++#define GRF_PCIE30PHY_WR_EN (0xf << 16) ++#define SRAM_INIT_DONE(reg) (reg & BIT(14)) ++ ++#define RK3568_BIFURCATION_LANE_0_1 BIT(0) ++ ++/* Register for RK3588 */ ++#define PHP_GRF_PCIESEL_CON 0x100 ++#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 ++#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 ++#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 ++#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) ++ ++#define RK3588_BIFURCATION_LANE_0_1 BIT(0) ++#define RK3588_BIFURCATION_LANE_2_3 BIT(1) ++#define RK3588_LANE_AGGREGATION BIT(2) ++ ++struct rockchip_p3phy_ops; ++ ++struct rockchip_p3phy_priv { ++ const struct rockchip_p3phy_ops *ops; ++ void __iomem *mmio; ++ /* mode: RC, EP */ ++ int mode; ++ /* pcie30_phymode: Aggregation, Bifurcation */ ++ int pcie30_phymode; ++ struct regmap *phy_grf; ++ struct regmap *pipe_grf; ++ struct reset_control *p30phy; ++ struct phy *phy; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ int num_lanes; ++ u32 lanes[4]; ++}; ++ ++struct rockchip_p3phy_ops { ++ int (*phy_init)(struct rockchip_p3phy_priv *priv); ++}; ++ ++static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) ++{ ++ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); ++ ++ /* Actually We don't care EP/RC mode, but just record it */ ++ switch (submode) { ++ case PHY_MODE_PCIE_RC: ++ priv->mode = PHY_MODE_PCIE_RC; ++ break; ++ case PHY_MODE_PCIE_EP: ++ priv->mode = PHY_MODE_PCIE_EP; ++ break; ++ default: ++ dev_err(&phy->dev, "%s, invalid mode\n", __func__); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv) ++{ ++ struct phy *phy = priv->phy; ++ bool bifurcation = false; ++ int ret, i; ++ u32 reg; ++ ++ /* Deassert PCIe PMA output clamp mode */ ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM); ++ ++ for (i = 0; i < priv->num_lanes; i++) { ++ dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); ++ if (priv->lanes[i] > 1) ++ bifurcation = true; ++ } ++ ++ /* Set bifurcation if needed, and it doesn't care RC/EP */ ++ if (bifurcation) { ++ dev_info(&phy->dev, "bifurcation enabled\n"); ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, ++ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1); ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1, ++ GRF_PCIE30PHY_DA_OCM); ++ } else { ++ dev_dbg(&phy->dev, "bifurcation disabled\n"); ++ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6, ++ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1); ++ } ++ ++ reset_control_deassert(priv->p30phy); ++ ++ ret = regmap_read_poll_timeout(priv->phy_grf, ++ GRF_PCIE30PHY_STATUS0, ++ reg, SRAM_INIT_DONE(reg), ++ 0, 500); ++ if (ret) ++ dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n", ++ __func__, reg); ++ return ret; ++} ++ ++static const struct rockchip_p3phy_ops rk3568_ops = { ++ .phy_init = rockchip_p3phy_rk3568_init, ++}; ++ ++static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) ++{ ++ u32 reg = 0; ++ u8 mode = 0; ++ int i, ret; ++ ++ /* Deassert PCIe PMA output clamp mode */ ++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); ++ ++ /* Set bifurcation if needed */ ++ for (i = 0; i < priv->num_lanes; i++) { ++ if (!priv->lanes[i]) ++ mode |= (BIT(i) << 3); ++ ++ if (priv->lanes[i] > 1) ++ mode |= (BIT(i) >> 1); ++ } ++ ++ if (!mode) ++ reg = RK3588_LANE_AGGREGATION; ++ else { ++ if (mode & (BIT(0) | BIT(1))) ++ reg |= RK3588_BIFURCATION_LANE_0_1; ++ ++ if (mode & (BIT(2) | BIT(3))) ++ reg |= RK3588_BIFURCATION_LANE_2_3; ++ } ++ ++ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); ++ ++ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ ++ if (!IS_ERR(priv->pipe_grf)) { ++ reg = (mode & (BIT(6) | BIT(7))) >> 6; ++ if (reg) ++ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, ++ (reg << 16) | reg); ++ } ++ ++ reset_control_deassert(priv->p30phy); ++ ++ ret = regmap_read_poll_timeout(priv->phy_grf, ++ RK3588_PCIE3PHY_GRF_PHY0_STATUS1, ++ reg, RK3588_SRAM_INIT_DONE(reg), ++ 0, 500); ++ ret |= regmap_read_poll_timeout(priv->phy_grf, ++ RK3588_PCIE3PHY_GRF_PHY1_STATUS1, ++ reg, RK3588_SRAM_INIT_DONE(reg), ++ 0, 500); ++ if (ret) ++ dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n", ++ reg); ++ return ret; ++} ++ ++static const struct rockchip_p3phy_ops rk3588_ops = { ++ .phy_init = rockchip_p3phy_rk3588_init, ++}; ++ ++static int rochchip_p3phy_init(struct phy *phy) ++{ ++ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); ++ if (ret) { ++ dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret); ++ return ret; ++ } ++ ++ reset_control_assert(priv->p30phy); ++ udelay(1); ++ ++ if (priv->ops->phy_init) { ++ ret = priv->ops->phy_init(priv); ++ if (ret) ++ clk_bulk_disable_unprepare(priv->num_clks, priv->clks); ++ } ++ ++ return ret; ++} ++ ++static int rochchip_p3phy_exit(struct phy *phy) ++{ ++ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); ++ ++ clk_bulk_disable_unprepare(priv->num_clks, priv->clks); ++ reset_control_assert(priv->p30phy); ++ return 0; ++} ++ ++static const struct phy_ops rochchip_p3phy_ops = { ++ .init = rochchip_p3phy_init, ++ .exit = rochchip_p3phy_exit, ++ .set_mode = rockchip_p3phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static int rockchip_p3phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct rockchip_p3phy_priv *priv; ++ struct device_node *np = dev->of_node; ++ struct resource *res; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ priv->mmio = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->mmio)) { ++ ret = PTR_ERR(priv->mmio); ++ return ret; ++ } ++ ++ priv->ops = of_device_get_match_data(&pdev->dev); ++ if (!priv->ops) { ++ dev_err(dev, "no of match data provided\n"); ++ return -EINVAL; ++ } ++ ++ priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf"); ++ if (IS_ERR(priv->phy_grf)) { ++ dev_err(dev, "failed to find rockchip,phy_grf regmap\n"); ++ return PTR_ERR(priv->phy_grf); ++ } ++ ++ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, ++ "rockchip,pipe-grf"); ++ if (IS_ERR(priv->pipe_grf)) ++ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n"); ++ ++ priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", ++ priv->lanes, 2, ++ ARRAY_SIZE(priv->lanes)); ++ ++ /* if no data-lanes assume aggregation */ ++ if (priv->num_lanes == -EINVAL) { ++ dev_dbg(dev, "no data-lanes property found\n"); ++ priv->num_lanes = 1; ++ priv->lanes[0] = 1; ++ } else if (priv->num_lanes < 0) { ++ dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes); ++ return priv->num_lanes; ++ } ++ ++ priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); ++ if (IS_ERR(priv->phy)) { ++ dev_err(dev, "failed to create combphy\n"); ++ return PTR_ERR(priv->phy); ++ } ++ ++ priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy"); ++ if (IS_ERR(priv->p30phy)) { ++ return dev_err_probe(dev, PTR_ERR(priv->p30phy), ++ "failed to get phy reset control\n"); ++ } ++ if (!priv->p30phy) ++ dev_info(dev, "no phy reset control specified\n"); ++ ++ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); ++ if (priv->num_clks < 1) ++ return -ENODEV; ++ ++ dev_set_drvdata(dev, priv); ++ phy_set_drvdata(priv->phy, priv); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id rockchip_p3phy_of_match[] = { ++ { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops }, ++ { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match); ++ ++static struct platform_driver rockchip_p3phy_driver = { ++ .probe = rockchip_p3phy_probe, ++ .driver = { ++ .name = "rockchip-snps-pcie3-phy", ++ .of_match_table = rockchip_p3phy_of_match, ++ }, ++}; ++module_platform_driver(rockchip_p3phy_driver); ++MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver"); ++MODULE_LICENSE("GPL"); +--- /dev/null ++++ b/include/linux/phy/pcie.h +@@ -0,0 +1,12 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd. ++ */ ++#ifndef __PHY_PCIE_H ++#define __PHY_PCIE_H ++ ++#define PHY_MODE_PCIE_RC 20 ++#define PHY_MODE_PCIE_EP 21 ++#define PHY_MODE_PCIE_BIFURCATION 22 ++ ++#endif diff --git a/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch b/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch new file mode 100644 index 000000000..fe99dd11b --- /dev/null +++ b/target/linux/rockchip/patches-5.15/109-arm64-dts-rockchip-rk3568-Add-PCIe-v3-nodes.patch @@ -0,0 +1,144 @@ +From 4b3da1efaa295802ffad3c2bf310ef73af416f12 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Thu, 25 Aug 2022 21:38:35 +0200 +Subject: [PATCH] arm64: dts: rockchip: rk3568: Add PCIe v3 nodes + +Add nodes to rk356x devicetree to support PCIe v3. + +Signed-off-by: Peter Geis +Signed-off-by: Frank Wunderlich +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ + 1 file changed, 122 insertions(+) + +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { + reg = <0x0 0xfe190200 0x0 0x20>; + }; + ++ pcie30_phy_grf: syscon@fdcb8000 { ++ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; ++ reg = <0x0 0xfdcb8000 0x0 0x10000>; ++ }; ++ ++ pcie30phy: phy@fe8c0000 { ++ compatible = "rockchip,rk3568-pcie3-phy"; ++ reg = <0x0 0xfe8c0000 0x0 0x20000>; ++ #phy-cells = <0>; ++ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, ++ <&cru PCLK_PCIE30PHY>; ++ clock-names = "refclk_m", "refclk_n", "pclk"; ++ resets = <&cru SRST_PCIE30PHY>; ++ reset-names = "phy"; ++ rockchip,phy-grf = <&pcie30_phy_grf>; ++ status = "disabled"; ++ }; ++ ++ pcie3x1: pcie@fe270000 { ++ compatible = "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, ++ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, ++ <&cru CLK_PCIE30X1_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, ++ <0 0 0 2 &pcie3x1_intc 1>, ++ <0 0 0 3 &pcie3x1_intc 2>, ++ <0 0 0 4 &pcie3x1_intc 3>; ++ linux,pci-domain = <1>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x0 &gic 0x1000 0x1000>; ++ num-lanes = <1>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ reg = <0x3 0xc0400000 0x0 0x00400000>, ++ <0x0 0xfe270000 0x0 0x00010000>, ++ <0x3 0x7f000000 0x0 0x01000000>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X1_POWERUP>; ++ reset-names = "pipe"; ++ /* bifurcation; lane1 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x1_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie3x2: pcie@fe280000 { ++ compatible = "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, ++ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, ++ <&cru CLK_PCIE30X2_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, ++ <0 0 0 2 &pcie3x2_intc 1>, ++ <0 0 0 3 &pcie3x2_intc 2>, ++ <0 0 0 4 &pcie3x2_intc 3>; ++ linux,pci-domain = <2>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x0 &gic 0x2000 0x1000>; ++ num-lanes = <2>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ reg = <0x3 0xc0800000 0x0 0x00400000>, ++ <0x0 0xfe280000 0x0 0x00010000>, ++ <0x3 0xbf000000 0x0 0x01000000>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X2_POWERUP>; ++ reset-names = "pipe"; ++ /* bifurcation; lane0 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x2_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; diff --git a/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch new file mode 100644 index 000000000..7e76665aa --- /dev/null +++ b/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch @@ -0,0 +1,12 @@ +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -58,3 +58,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h68k.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r68s.dtb