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kernel: bump 5.10 to 5.10.212 (#11961)
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@ -1,2 +1,2 @@
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LINUX_VERSION-5.10 = .210
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LINUX_KERNEL_HASH-5.10.210 = 4ea63c5a90fdc3c459ab35c11ee8c93d2364a7cdbfb101100f8cab70d490ef6d
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LINUX_VERSION-5.10 = .212
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LINUX_KERNEL_HASH-5.10.212 = 0cf3e467bd8d35533888327e9f8a9a9d354fdf83e8f82e9fe5a234f896a07493
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@ -1,172 +0,0 @@
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From bd568cc04c675b7fa97214d278a54794c2ecc2ad Mon Sep 17 00:00:00 2001
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From: Reto Schneider <reto.schneider@husqvarnagroup.com>
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Date: Thu, 11 Feb 2021 12:36:19 +0100
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Subject: [PATCH] mtd: spinand: gigadevice: Support GD5F1GQ5UExxG
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The relevant changes to the already existing GD5F1GQ4UExxG support has
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been determined by consulting the GigaDevice product change notice
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AN-0392-10, version 1.0 from November 30, 2020.
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As the overlaps are huge, variable names have been generalized
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accordingly.
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Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),
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the new device ID, and the extra quad IO dummy byte, no changes had to
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be taken into account.
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New hardware features are not supported, namely:
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- Power on reset
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- Unique ID
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- Double transfer rate (DTR)
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- Parameter page
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- Random data quad IO
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The inverted semantic of the "driver strength" register bits, defaulting
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to 100% instead of 50% for the Q5 devices, got ignored as the driver has
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never touched them anyway.
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The no longer supported "read from cache during block erase"
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functionality is not reflected as the current SPI NAND core does not
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support it anyway.
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Implementation has been tested on MediaTek MT7688 based GARDENA smart
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Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
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Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
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Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
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Reviewed-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch
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(cherry picked from commit 469b992489852b500d39048aa0013639dfe9f2e6)
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---
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drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++----
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1 file changed, 60 insertions(+), 9 deletions(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -13,7 +13,10 @@
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#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
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#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
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-#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
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+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4)
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+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4)
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+
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+#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
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#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
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#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
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@@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(str
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return -EINVAL;
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}
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-static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
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+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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@@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_e
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return 0;
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}
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-static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
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+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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@@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_f
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return 0;
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}
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-static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
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- .ecc = gd5fxgq4_variant2_ooblayout_ecc,
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- .free = gd5fxgq4_variant2_ooblayout_free,
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+/* Valid for Q4/Q5 and Q6 (untested) devices */
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+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
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+ .ecc = gd5fxgqx_variant2_ooblayout_ecc,
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+ .free = gd5fxgqx_variant2_ooblayout_free,
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};
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static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
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@@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status(
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u8 status)
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{
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u8 status2;
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- struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
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+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
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&status2);
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int ret;
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@@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status(
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return -EINVAL;
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}
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+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ u8 status2;
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+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
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+ &status2);
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+ int ret;
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+
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+ switch (status & STATUS_ECC_MASK) {
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+ case STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
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+ /*
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+ * Read status2 register to determine a more fine grained
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+ * bit error status
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+ */
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+ ret = spi_mem_exec_op(spinand->spimem, &op);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * 1 ... 4 bits are flipped (and corrected)
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+ */
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+ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
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+ return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
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+
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+ case STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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@@ -282,7 +323,7 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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- SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UFxxG",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
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@@ -292,8 +333,18 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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- SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq4ufxxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ5UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
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@ -1,44 +0,0 @@
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From a4f9dd55c5e1bb951db6f1dee20e62e0103f3438 Mon Sep 17 00:00:00 2001
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From: Chuanhong Guo <gch981213@gmail.com>
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Date: Sun, 20 Mar 2022 17:59:57 +0800
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Subject: [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG
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Read From Cache Quad IO (EBH) uses 2 dummy bytes on this chip according
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to page 23 of the datasheet[0].
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[0]: https://www.gigadevice.com/datasheet/gd5f1gq5xexxg/
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Fixes: 469b99248985 ("mtd: spinand: gigadevice: Support GD5F1GQ5UExxG")
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Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-2-gch981213@gmail.com
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---
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drivers/mtd/nand/spi/gigadevice.c | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -39,6 +39,14 @@ static SPINAND_OP_VARIANTS(read_cache_va
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SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
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+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
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+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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+
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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@@ -339,7 +347,7 @@ static const struct spinand_info gigadev
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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@ -19,7 +19,7 @@ Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -333,6 +333,36 @@ static const struct spinand_info gigadev
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@@ -335,6 +335,36 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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@ -14,7 +14,7 @@ Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-4-gch981213@gmail.
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -383,6 +383,16 @@ static const struct spinand_info gigadev
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@@ -385,6 +385,16 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq5xexxg_ecc_get_status)),
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@ -35,7 +35,7 @@ Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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@@ -391,6 +399,46 @@ static const struct spinand_info gigadev
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@@ -393,6 +401,46 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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@ -22,7 +22,7 @@ Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -441,6 +441,66 @@ static const struct spinand_info gigadev
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@@ -443,6 +443,66 @@ static const struct spinand_info gigadev
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq5xexxg_ecc_get_status)),
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