rockchip: fix NanoPi R2C stmmac phy

This commit is contained in:
coolsnowwolf 2022-12-11 14:51:27 +08:00 committed by AmadeusGhost
parent 547fc7765c
commit 8ab47a669f
4 changed files with 22 additions and 6 deletions

View File

@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,51 @@ @@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@ -30,6 +30,8 @@
+ +
+&gmac2io { +&gmac2io {
+ phy-handle = <&yt8521s>; + phy-handle = <&yt8521s>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+ +
+ mdio { + mdio {
+ /delete-node/ ethernet-phy@1; + /delete-node/ ethernet-phy@1;
@ -38,6 +40,8 @@
+ compatible = "ethernet-phy-id0000.011a", + compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <3>; + reg = <3>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ reset-assert-us = <10000>; + reset-assert-us = <10000>;
@ -56,7 +60,7 @@
+}; +};
+ +
+&usb_eth { +&usb_eth {
+ realtek,led-data = <0x78>; + realtek,led-data = <0x78>;
+}; +};
+ +
+&wan_led { +&wan_led {

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@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,51 @@ @@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@ -30,6 +30,8 @@
+ +
+&gmac2io { +&gmac2io {
+ phy-handle = <&yt8521s>; + phy-handle = <&yt8521s>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+ +
+ mdio { + mdio {
+ /delete-node/ ethernet-phy@1; + /delete-node/ ethernet-phy@1;
@ -38,6 +40,8 @@
+ compatible = "ethernet-phy-id0000.011a", + compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <3>; + reg = <3>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ reset-assert-us = <10000>; + reset-assert-us = <10000>;

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@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,51 @@ @@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@ -30,6 +30,8 @@
+ +
+&gmac2io { +&gmac2io {
+ phy-handle = <&yt8521s>; + phy-handle = <&yt8521s>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+ +
+ mdio { + mdio {
+ /delete-node/ ethernet-phy@1; + /delete-node/ ethernet-phy@1;
@ -38,6 +40,8 @@
+ compatible = "ethernet-phy-id0000.011a", + compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <3>; + reg = <3>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ reset-assert-us = <10000>; + reset-assert-us = <10000>;
@ -56,7 +60,7 @@
+}; +};
+ +
+&usb_eth { +&usb_eth {
+ realtek,led-data = <0x78>; + realtek,led-data = <0x78>;
+}; +};
+ +
+&wan_led { +&wan_led {

View File

@ -10,7 +10,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
--- /dev/null --- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,51 @@ @@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* +/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
@ -30,6 +30,8 @@
+ +
+&gmac2io { +&gmac2io {
+ phy-handle = <&yt8521s>; + phy-handle = <&yt8521s>;
+ tx_delay = <0x22>;
+ rx_delay = <0x12>;
+ +
+ mdio { + mdio {
+ /delete-node/ ethernet-phy@1; + /delete-node/ ethernet-phy@1;
@ -38,6 +40,8 @@
+ compatible = "ethernet-phy-id0000.011a", + compatible = "ethernet-phy-id0000.011a",
+ "ethernet-phy-ieee802.3-c22"; + "ethernet-phy-ieee802.3-c22";
+ reg = <3>; + reg = <3>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&eth_phy_reset_pin>; + pinctrl-0 = <&eth_phy_reset_pin>;
+ pinctrl-names = "default"; + pinctrl-names = "default";
+ reset-assert-us = <10000>; + reset-assert-us = <10000>;