298977887/lede
1
0
Fork 0
mirror of https://github.com/coolsnowwolf/lede.git synced 2025-04-16 14:23:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

kernel: fixes 5.15/6.1 build error

Browse Source 
Sorry for the delay, I was scolded all night
and I could only fix it until now.

Fixes: #11209, #11213, #11214
This commit is contained in:
AmadeusGhost 2023-05-16 23:39:29 +08:00
parent 7640b82748
commit 88c143124a
2 changed files with 26 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

69
target/linux/generic/backport-5.15/430-v6.3-ubi-Fix-failure-attaching-when-vid_hdr-offset-equals.patch
View File

@ -1,69 +0,0 @@
From 1e020e1b96afdecd20680b5b5be2a6ffc3d27628 Mon Sep 17 00:00:00 2001
From: Zhihao Cheng <chengzhihao1@huawei.com>
Date: Mon, 6 Mar 2023 09:33:08 +0800
Subject: [PATCH] ubi: Fix failure attaching when vid_hdr offset equals to
(sub)page size
Following process will make ubi attaching failed since commit
1b42b1a36fc946 ("ubi: ensure that VID header offset ... size"):
ID="0xec,0xa1,0x00,0x15" # 128M 128KB 2KB
modprobe nandsim id_bytes=$ID
flash_eraseall /dev/mtd0
modprobe ubi mtd="0,2048" # set vid_hdr offset as 2048 (one page)
(dmesg):
ubi0 error: ubi_attach_mtd_dev [ubi]: VID header offset 2048 too large.
UBI error: cannot attach mtd0
UBI error: cannot initialize UBI, error -22
Rework original solution, the key point is making sure
'vid_hdr_shift + UBI_VID_HDR_SIZE < ubi->vid_hdr_alsize',
so we should check vid_hdr_shift rather not vid_hdr_offset.
Then, ubi still support (sub)page aligined VID header offset.
Fixes: 1b42b1a36fc946 ("ubi: ensure that VID header offset ... size")
Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com>
Tested-by: Nicolas Schichan <nschichan@freebox.fr>
Tested-by: Miquel Raynal <miquel.raynal@bootlin.com> # v5.10, v4.19
Signed-off-by: Richard Weinberger <richard@nod.at>
---
drivers/mtd/ubi/build.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -664,12 +664,6 @@ static int io_init(struct ubi_device *ub
ubi->ec_hdr_alsize = ALIGN(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size);
ubi->vid_hdr_alsize = ALIGN(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size);
- if (ubi->vid_hdr_offset && ((ubi->vid_hdr_offset + UBI_VID_HDR_SIZE) >
- ubi->vid_hdr_alsize)) {
- ubi_err(ubi, "VID header offset %d too large.", ubi->vid_hdr_offset);
- return -EINVAL;
- }
-
dbg_gen("min_io_size %d", ubi->min_io_size);
dbg_gen("max_write_size %d", ubi->max_write_size);
dbg_gen("hdrs_min_io_size %d", ubi->hdrs_min_io_size);
@@ -687,6 +681,21 @@ static int io_init(struct ubi_device *ub
ubi->vid_hdr_aloffset;
}
+ /*
+ * Memory allocation for VID header is ubi->vid_hdr_alsize
+ * which is described in comments in io.c.
+ * Make sure VID header shift + UBI_VID_HDR_SIZE not exceeds
+ * ubi->vid_hdr_alsize, so that all vid header operations
+ * won't access memory out of bounds.
+ */
+ if ((ubi->vid_hdr_shift + UBI_VID_HDR_SIZE) > ubi->vid_hdr_alsize) {
+ ubi_err(ubi, "Invalid VID header offset %d, VID header shift(%d)"
+ " + VID header size(%zu) > VID header aligned size(%d).",
+ ubi->vid_hdr_offset, ubi->vid_hdr_shift,
+ UBI_VID_HDR_SIZE, ubi->vid_hdr_alsize);
+ return -EINVAL;
+ }
+
/* Similar for the data offset */
ubi->leb_start = ubi->vid_hdr_offset + UBI_VID_HDR_SIZE;
ubi->leb_start = ALIGN(ubi->leb_start, ubi->min_io_size);

75
target/linux/rockchip/patches-6.1/113-ethernet-stmicro-stmmac-Add-SGMII-QSGMII-support.patch
View File

@ -32,15 +32,24 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
@@ -60,6 +63,7 @@ struct rk_priv_data { @@ -40,7 +43,7 @@ struct rk_gmac_ops {
struct clk *clk_mac_speed; };
struct clk *aclk_mac;
struct clk *pclk_mac;
+ struct clk *pclk_xpcs;
struct clk *clk_phy;
struct reset_control *phy_reset; static const char * const rk_clocks[] = {
@@ -69,6 +73,7 @@ struct rk_priv_data { - "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
+ "aclk_mac", "pclk_mac", "pclk_xpcs", "mac_clk_tx", "clk_mac_speed",
};
static const char * const rk_rmii_clocks[] = {
@@ -50,6 +53,7 @@ static const char * const rk_rmii_clocks[] = {
enum rk_clocks_index {
RK_ACLK_MAC = 0,
RK_PCLK_MAC,
+ RK_PCLK_XPCS,
RK_MAC_CLK_TX,
RK_CLK_MAC_SPEED,
RK_MAC_CLK_RX,
@@ -81,6 +85,7 @@ struct rk_priv_data {
struct regmap *grf; struct regmap *grf;
struct regmap *php_grf; struct regmap *php_grf;
@ -48,7 +57,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
}; };
#define HIWORD_UPDATE(val, mask, shift) \ #define HIWORD_UPDATE(val, mask, shift) \
@@ -81,6 +86,128 @@ struct rk_priv_data { @@ -93,6 +98,128 @@ struct rk_priv_data {
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
@ -177,7 +186,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
#define PX30_GRF_GMAC_CON1 0x0904 #define PX30_GRF_GMAC_CON1 0x0904
/* PX30_GRF_GMAC_CON1 */ /* PX30_GRF_GMAC_CON1 */
@@ -1008,6 +1135,7 @@ static const struct rk_gmac_ops rk3399_o @@ -1021,6 +1148,7 @@ static const struct rk_gmac_ops rk3399_ops = {
#define RK3568_GRF_GMAC1_CON1 0x038c #define RK3568_GRF_GMAC1_CON1 0x038c
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
@ -185,7 +194,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
#define RK3568_GMAC_PHY_INTF_SEL_RGMII \ #define RK3568_GMAC_PHY_INTF_SEL_RGMII \
(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
#define RK3568_GMAC_PHY_INTF_SEL_RMII \ #define RK3568_GMAC_PHY_INTF_SEL_RMII \
@@ -1023,6 +1151,46 @@ static const struct rk_gmac_ops rk3399_o @@ -1036,6 +1164,46 @@ static const struct rk_gmac_ops rk3399_ops = {
#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
@ -232,7 +241,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay) int tx_delay, int rx_delay)
{ {
@@ -1094,6 +1262,8 @@ static void rk3568_set_gmac_speed(struct @@ -1108,6 +1276,8 @@ static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
static const struct rk_gmac_ops rk3568_ops = { static const struct rk_gmac_ops rk3568_ops = {
.set_to_rgmii = rk3568_set_to_rgmii, .set_to_rgmii = rk3568_set_to_rgmii,
.set_to_rmii = rk3568_set_to_rmii, .set_to_rmii = rk3568_set_to_rmii,
@ -241,39 +250,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
.set_rgmii_speed = rk3568_set_gmac_speed, .set_rgmii_speed = rk3568_set_gmac_speed,
.set_rmii_speed = rk3568_set_gmac_speed, .set_rmii_speed = rk3568_set_gmac_speed,
.regs_valid = true, .regs_valid = true,
@@ -1517,6 +1687,12 @@ static int rk_gmac_clk_init(struct plat_ @@ -1580,7 +1750,7 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
dev_err(dev, "cannot get clock %s\n",
"clk_mac_refout");
}
+ } else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_SGMII ||
+ bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
+ bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
+ if (IS_ERR(bsp_priv->pclk_xpcs))
+ dev_err(dev, "cannot get clock %s\n",
+ "pclk_xpcs");
}
bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
@@ -1572,6 +1748,9 @@ static int gmac_clk_enable(struct rk_pri
if (!IS_ERR(bsp_priv->pclk_mac))
clk_prepare_enable(bsp_priv->pclk_mac);
+ if (!IS_ERR(bsp_priv->pclk_xpcs))
+ clk_prepare_enable(bsp_priv->pclk_xpcs);
+
if (!IS_ERR(bsp_priv->mac_clk_tx))
clk_prepare_enable(bsp_priv->mac_clk_tx);
@@ -1605,6 +1784,8 @@ static int gmac_clk_enable(struct rk_pri
clk_disable_unprepare(bsp_priv->pclk_mac);
+ clk_disable_unprepare(bsp_priv->pclk_xpcs);
+
clk_disable_unprepare(bsp_priv->mac_clk_tx);
clk_disable_unprepare(bsp_priv->clk_mac_speed);
@@ -1623,7 +1804,7 @@ static int gmac_clk_enable(struct rk_pri
return 0; return 0;
} }
@ -282,7 +259,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
{ {
struct regulator *ldo = bsp_priv->regulator; struct regulator *ldo = bsp_priv->regulator;
int ret; int ret;
@@ -1728,6 +1909,18 @@ static struct rk_priv_data *rk_gmac_setu @@ -1679,6 +1849,18 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
"rockchip,grf"); "rockchip,grf");
bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node, bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
"rockchip,php-grf"); "rockchip,php-grf");
@ -301,7 +278,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
if (plat->phy_node) { if (plat->phy_node) {
bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node, bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
@@ -1805,11 +1998,19 @@ static int rk_gmac_powerup(struct rk_pri @@ -1756,11 +1938,19 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
dev_info(dev, "init for RMII\n"); dev_info(dev, "init for RMII\n");
bsp_priv->ops->set_to_rmii(bsp_priv); bsp_priv->ops->set_to_rmii(bsp_priv);
break; break;
@ -322,7 +299,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
if (ret) { if (ret) {
gmac_clk_enable(bsp_priv, false); gmac_clk_enable(bsp_priv, false);
return ret; return ret;
@@ -1830,7 +2031,7 @@ static void rk_gmac_powerdown(struct rk_ @@ -1781,7 +1971,7 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
pm_runtime_put_sync(&gmac->pdev->dev); pm_runtime_put_sync(&gmac->pdev->dev);
@ -331,7 +308,7 @@ Signed-off-by: David Wu <david.wu@rock-chips.com>
gmac_clk_enable(gmac, false); gmac_clk_enable(gmac, false);
} }
@@ -1851,6 +2052,9 @@ static void rk_fix_speed(void *priv, uns @@ -1802,6 +1992,9 @@ static void rk_fix_speed(void *priv, unsigned int speed)
if (bsp_priv->ops->set_rmii_speed) if (bsp_priv->ops->set_rmii_speed)
bsp_priv->ops->set_rmii_speed(bsp_priv, speed); bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
break; break;