diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index 8bbbea82e..73da79eaa 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -5,7 +5,7 @@ include $(TOPDIR)/rules.mk ARCH:=arm BOARD:=mediatek BOARDNAME:=MediaTek Ralink ARM -SUBTARGETS:=mt7622 mt7623 mt7629 mt7981 filogic +SUBTARGETS:=mt7622 mt7623 mt7629 filogic FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb KERNEL_PATCHVER:=5.15 diff --git a/target/linux/mediatek/image/mt7981.mk b/target/linux/mediatek/image/mt7981.mk deleted file mode 100644 index 4c290c687..000000000 --- a/target/linux/mediatek/image/mt7981.mk +++ /dev/null @@ -1,175 +0,0 @@ -DTS_DIR := $(DTS_DIR)/mediatek - -KERNEL_LOADADDR := 0x48080000 - -define Device/mt7981-spim-nor-rfb - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-spim-nor-rfb - DEVICE_DTS := mt7981-spim-nor-rfb - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-spim-nor-rfb -endef -TARGET_DEVICES += mt7981-spim-nor-rfb - -define Device/mt7981-spim-nand-2500wan-gmac2 - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-spim-nand-2500wan-gmac2 - DEVICE_DTS := mt7981-spim-nand-2500wan-gmac2 - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-spim-snand-2500wan-gmac2-rfb - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k - KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-spim-nand-2500wan-gmac2 - -define Device/mt7981-spim-nand-rfb - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-spim-nand-rfb - DEVICE_DTS := mt7981-spim-nand-rfb - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-spim-snand-rfb - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k - KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-spim-nand-rfb - -define Device/mt7981-spim-nand-gsw - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-spim-nand-gsw - DEVICE_DTS := mt7981-spim-nand-gsw - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-rfb,ubi - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k - KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-spim-nand-gsw - -define Device/mt7981-emmc-rfb - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-emmc-rfb - DEVICE_DTS := mt7981-emmc-rfb - SUPPORTED_DEVICES := mediatek,mt7981-emmc-rfb - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - DEVICE_PACKAGES := mkf2fs e2fsprogs blkid blockdev losetup kmod-fs-ext4 \ - kmod-mmc kmod-fs-f2fs kmod-fs-vfat kmod-nls-cp437 \ - kmod-nls-iso8859-1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-emmc-rfb - -define Device/mt7981-sd-rfb - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-sd-rfb - DEVICE_DTS := mt7981-sd-rfb - SUPPORTED_DEVICES := mediatek,mt7981-sd-rfb - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - DEVICE_PACKAGES := mkf2fs e2fsprogs blkid blockdev losetup kmod-fs-ext4 \ - kmod-mmc kmod-fs-f2fs kmod-fs-vfat kmod-nls-cp437 \ - kmod-nls-iso8859-1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-sd-rfb - -define Device/mt7981-snfi-nand-2500wan-p5 - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-snfi-nand-2500wan-p5 - DEVICE_DTS := mt7981-snfi-nand-2500wan-p5 - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-snfi-snand-pcie-2500wan-p5-rfb - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k - KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-snfi-nand-2500wan-p5 - -define Device/mt7981-fpga-spim-nor - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-fpga-spim-nor - DEVICE_DTS := mt7981-fpga-spim-nor - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-fpga-nor -endef -TARGET_DEVICES += mt7981-fpga-spim-nor - -define Device/mt7981-fpga-snfi-nand - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-fpga-snfi-nand - DEVICE_DTS := mt7981-fpga-snfi-nand - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-fpga-snfi-snand - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k - KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-fpga-snfi-nand - -define Device/mt7981-fpga-spim-nand - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-fpga-spim-nand - DEVICE_DTS := mt7981-fpga-spim-nand - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - SUPPORTED_DEVICES := mediatek,mt7981-fpga-spim-snand - UBINIZE_OPTS := -E 5 - BLOCKSIZE := 128k - PAGESIZE := 2048 - IMAGE_SIZE := 65536k - KERNEL_IN_UBI := 1 - IMAGES += factory.bin - IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-fpga-spim-nand - -define Device/mt7981-fpga-emmc - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-fpga-emmc - DEVICE_DTS := mt7981-fpga-emmc - SUPPORTED_DEVICES := mediatek,mt7981-fpga-emmc - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - DEVICE_PACKAGES := mkf2fs e2fsprogs blkid blockdev losetup kmod-fs-ext4 \ - kmod-mmc kmod-fs-f2fs kmod-fs-vfat kmod-nls-cp437 \ - kmod-nls-iso8859-1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-fpga-emmc - -define Device/mt7981-fpga-sd - DEVICE_VENDOR := MediaTek - DEVICE_MODEL := mt7981-fpga-sd - DEVICE_DTS := mt7981-fpga-sd - SUPPORTED_DEVICES := mediatek,mt7981-fpga-sd - DEVICE_DTS_DIR := $(DTS_DIR)/mediatek - DEVICE_PACKAGES := mkf2fs e2fsprogs blkid blockdev losetup kmod-fs-ext4 \ - kmod-mmc kmod-fs-f2fs kmod-fs-vfat kmod-nls-cp437 \ - kmod-nls-iso8859-1 - IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata -endef -TARGET_DEVICES += mt7981-fpga-sd diff --git a/target/linux/mediatek/mt7981/config-5.15 b/target/linux/mediatek/mt7981/config-5.15 deleted file mode 100644 index 3fc7e51df..000000000 --- a/target/linux/mediatek/mt7981/config-5.15 +++ /dev/null @@ -1,506 +0,0 @@ -CONFIG_64BIT=y -CONFIG_AHCI_MTK=y -# CONFIG_AIROHA_EN8801SC_PHY is not set -# CONFIG_AIROHA_EN8801S_PHY is not set -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -CONFIG_ARM64_CNP=y -CONFIG_ARM64_CONT_SHIFT=4 -CONFIG_ARM64_ERRATUM_1165522=y -CONFIG_ARM64_ERRATUM_1286807=y -CONFIG_ARM64_ERRATUM_1418040=y -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PAN=y -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -CONFIG_ARM64_PTR_AUTH=y -CONFIG_ARM64_SSBD=y -CONFIG_ARM64_SVE=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_UAO=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -CONFIG_ARM64_VHE=y -CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_DM=y -CONFIG_BLK_DEV_DM_BUILTIN=y -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_MD is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_BT=y -CONFIG_BT_BCM=y -CONFIG_BT_BREDR=y -CONFIG_BT_DEBUGFS=y -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_BCM=y -# CONFIG_BT_HCIUART_INTEL is not set -# CONFIG_BT_HCIUART_NOKIA is not set -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_SERDEV=y -CONFIG_BT_HCIVHCI=y -CONFIG_BT_HS=y -CONFIG_BT_LE=y -CONFIG_BT_MTKUART=y -CONFIG_BT_QCA=y -CONFIG_CAVIUM_TX2_ERRATUM_219=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLOCK_THERMAL=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2712 is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7981=y -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_SAFEXCEL=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_KPP=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_USER=y -CONFIG_CRYPTO_USER_API=y -CONFIG_CRYPTO_USER_API_AEAD=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_MISC=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DM_BUFIO=y -# CONFIG_DM_CRYPT is not set -# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set -CONFIG_DM_INIT=y -# CONFIG_DM_MIRROR is not set -# CONFIG_DM_SNAPSHOT is not set -CONFIG_DM_VERITY=y -# CONFIG_DM_VERITY_FEC is not set -# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set -CONFIG_DRM_RCAR_WRITEBACK=y -CONFIG_DTC=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_FUJITSU_ERRATUM_010001=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GPY211_PHY=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HOTPLUG_CPU=y -# CONFIG_HW_NAT is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_MTK is not set -CONFIG_HZ=250 -CONFIG_HZ_250=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JUMP_LABEL=y -# CONFIG_LEDS_UBNT_LEDBAR is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -# CONFIG_MAXLINEAR_GPHY is not set -CONFIG_MD=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -# CONFIG_MEDIATEK_2P5GE_PHY is not set -# CONFIG_MEDIATEK_GE_PHY is not set -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_NETSYS_V2=y -# CONFIG_MEDIATEK_NETSYS_V3 is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MT753X_GSW=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -# CONFIG_MTD_SPI_NAND_W25N01KV is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_EFUSE=y -CONFIG_MTK_HSDMA=y -# CONFIG_MTK_ICE_DEBUG is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -# CONFIG_MTK_SOC_THERMAL_LVTS is not set -CONFIG_MTK_SPI_NAND=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NMBM=y -# CONFIG_NMBM_LOG_LEVEL_DEBUG is not set -# CONFIG_NMBM_LOG_LEVEL_EMERG is not set -# CONFIG_NMBM_LOG_LEVEL_ERR is not set -CONFIG_NMBM_LOG_LEVEL_INFO=y -# CONFIG_NMBM_LOG_LEVEL_NONE is not set -# CONFIG_NMBM_LOG_LEVEL_WARN is not set -CONFIG_NMBM_MTD=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -# CONFIG_NTFS3_FS is not set -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -# CONFIG_PCIE_MEDIATEK is not set -CONFIG_PCIE_MEDIATEK_GEN3=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6797 is not set -# CONFIG_PINCTRL_MT7622 is not set -CONFIG_PINCTRL_MT7981=y -# CONFIG_PINCTRL_MT7986 is not set -# CONFIG_PINCTRL_MT7988 is not set -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PLUGIN_HOSTCC="g++" -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -# CONFIG_PSTORE_842_COMPRESS is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -# CONFIG_PSTORE_CONSOLE is not set -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_PMSG is not set -CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_RCU_NEED_SEGCBLIST=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -# CONFIG_REGULATOR_RT5190A is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_TI_SYSCON=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_STORAGE=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_UAS=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -CONFIG_USB_XHCI_MTK_DEBUGFS=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y diff --git a/target/linux/mediatek/mt7981/target.mk b/target/linux/mediatek/mt7981/target.mk deleted file mode 100644 index 942dad183..000000000 --- a/target/linux/mediatek/mt7981/target.mk +++ /dev/null @@ -1,10 +0,0 @@ -ARCH:=aarch64 -SUBTARGET:=mt7981 -BOARDNAME:=Filogic 820 (MT7981) -CPU_TYPE:=cortex-a53 - -KERNELNAME:=Image dtbs - -define Target/Description - Build firmware images for MediaTek MT7981 ARM based boards. -endef diff --git a/target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch b/target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch deleted file mode 100644 index 7740963b8..000000000 --- a/target/linux/mediatek/patches-5.10/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -82,6 +82,7 @@ struct serial8250_config { - #define UART_CAP_MINI (1 << 17) /* Mini UART on BCM283X family lacks: - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ -+#define UART_CAP_NMOD (1 << 18) /* UART doesn't do termios */ - - #define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -288,7 +288,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2713,6 +2713,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch b/target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch deleted file mode 100644 index a3356d586..000000000 --- a/target/linux/mediatek/patches-5.10/510-net-mediatek-add-flow-offload-for-mt7623.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 4823778b116c08e9c55dbc5b5042223289ea6a0c Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Wed, 31 Mar 2021 15:34:37 +0200 -Subject: [PATCH] net: mediatek: add flow offload for mt7623 - -mt7623 uses offload version 2 too - -tested on Bananapi-R2 - -Signed-off-by: Frank Wunderlich ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3398,6 +3398,7 @@ static const struct mtk_soc_data mt7623_ - .hw_features = MTK_HW_FEATURES, - .required_clks = MT7623_CLKS_BITMAP, - .required_pctl = true, -+ .offload_version = 2, - }; - - static const struct mtk_soc_data mt7629_data = { diff --git a/target/linux/mediatek/patches-5.15/951-add-mt7981-clock-support.patch b/target/linux/mediatek/patches-5.15/951-add-mt7981-clock-support.patch deleted file mode 100644 index 1587c803e..000000000 --- a/target/linux/mediatek/patches-5.15/951-add-mt7981-clock-support.patch +++ /dev/null @@ -1,1302 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7981 -+ bool "Clock driver for MediaTek MT7981" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7981 basic clocks and clocks -+ required for various peripherals found on MediaTek. -+ -+config COMMON_CLK_MT7981_ETHSYS -+ bool "Clock driver for MediaTek MT7981 ETHSYS" -+ depends on COMMON_CLK_MT7981 -+ default COMMON_CLK_MT7981 -+ help -+ This driver adds support for clocks for Ethernet and SGMII -+ required on MediaTek MT7981 SoC. -+ - config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -46,6 +46,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c -@@ -0,0 +1,103 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-gate.h" -+#include "clk-mtk.h" -+#include "clk-mux.h" -+ -+ -+#include -+#include -+ -+#define MT7981_PLL_FMAX (2500UL * MHZ) -+#define CON0_MT7981_RST_BAR BIT(27) -+ -+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ -+ _div_table, _parent_name) \ -+ { \ -+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, .flags = _flags, \ -+ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ -+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, .div_table = _div_table, \ -+ .parent_name = _parent_name, \ -+ } -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ -+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ -+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ -+ "clkxtal") -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32, -+ 0x0200, 4, 0, 0x0204, 0), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, -+ 0x0210, 4, 0, 0x0214, 0), -+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, -+ 0x0220, 4, 0, 0x0224, 0), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, -+ 0x0230, 4, 0, 0x0234, 0), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, -+ 0x0240, 4, 0, 0x0244, 0), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, -+ 0x0250, 4, 0, 0x0254, 0), -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, -+ 0x0260, 4, 0, 0x0264, 0), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, -+ 0x0278, 4, 0, 0x027C, 0), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_apmixed[] = { -+ { .compatible = "mediatek,mt7981-apmixedsys", }, -+ {} -+}; -+ -+static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ -+ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_apmixed_data; -+ } -+ return r; -+ -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7981_apmixed_drv = { -+ .probe = clk_mt7981_apmixed_probe, -+ .driver = { -+ .name = "clk-mt7981-apmixed", -+ .of_match_table = of_match_clk_mt7981_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_apmixed_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-eth.c -@@ -0,0 +1,138 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-mtk.h" -+#include "clk-gate.h" -+ -+#include -+ -+static const struct mtk_gate_regs sgmii0_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII0(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii0_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] __initconst = { -+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), -+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), -+ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs sgmii1_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII1(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii1_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii1_clks[] __initconst = { -+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), -+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), -+ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs eth_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETH(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ð_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate eth_clks[] __initconst = { -+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), -+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), -+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), -+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), -+}; -+ -+static void __init mtk_sgmiisys_0_init(struct device_node *node) -+{ -+ struct clk_onecell_data *clk_data; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); -+ -+ mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), -+ clk_data); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ if (r) -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+} -+CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7981-sgmiisys_0", -+ mtk_sgmiisys_0_init); -+ -+static void __init mtk_sgmiisys_1_init(struct device_node *node) -+{ -+ struct clk_onecell_data *clk_data; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); -+ -+ mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), -+ clk_data); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ -+ if (r) -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+} -+CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7981-sgmiisys_1", -+ mtk_sgmiisys_1_init); -+ -+static void __init mtk_ethsys_init(struct device_node *node) -+{ -+ struct clk_onecell_data *clk_data; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); -+ -+ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ -+ if (r) -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+} -+CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7981-ethsys", mtk_ethsys_init); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c -@@ -0,0 +1,323 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor infra_divs[] = { -+ FACTOR(CLK_INFRA_CK_F26M, "infra_ck_f26m", "csw_f26m_sel", 1, 1), -+ FACTOR(CLK_INFRA_UART, "infra_uart", "uart_sel", 1, 1), -+ FACTOR(CLK_INFRA_ISPI0, "infra_ispi0", "spi_sel", 1, 1), -+ FACTOR(CLK_INFRA_I2C, "infra_i2c", "i2c_sel", 1, 1), -+ FACTOR(CLK_INFRA_ISPI1, "infra_ispi1", "spim_mst_sel", 1, 1), -+ FACTOR(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 1, 1), -+ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), -+ FACTOR(CLK_INFRA_CK_F32K, "infra_ck_f32k", "cb_rtc_32p7k", 1, 1), -+ FACTOR(CLK_INFRA_PCIE_CK, "infra_pcie", "pextp_tl_ck_sel", 1, 1), -+ FACTOR(CLK_INFRA_PWM_BCK, "infra_pwm_bck", "infra_pwm_bsel", 1, 1), -+ FACTOR(CLK_INFRA_PWM_CK1, "infra_pwm_ck1", "infra_pwm1_sel", 1, 1), -+ FACTOR(CLK_INFRA_PWM_CK2, "infra_pwm_ck2", "infra_pwm2_sel", 1, 1), -+ FACTOR(CLK_INFRA_133M_HCK, "infra_133m_hck", "sysaxi", 1, 1), -+ FACTOR(CLK_INFRA_66M_PHCK, "infra_66m_phck", "infra_133m_hck", 1, 1), -+ FACTOR(CLK_INFRA_FAUD_L_CK, "infra_faud_l", "aud_l", 1, 1), -+ FACTOR(CLK_INFRA_FAUD_AUD_CK, "infra_faud_aud", "a1sys", 1, 1), -+ FACTOR(CLK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", "a_tuner", 1, 1), -+ FACTOR(CLK_INFRA_I2CS_CK, "infra_i2cs", "i2c_bck", 1, 1), -+ FACTOR(CLK_INFRA_MUX_UART0, "infra_mux_uart0", "infra_uart0_sel", 1, 1), -+ FACTOR(CLK_INFRA_MUX_UART1, "infra_mux_uart1", "infra_uart1_sel", 1, 1), -+ FACTOR(CLK_INFRA_MUX_UART2, "infra_mux_uart2", "infra_uart2_sel", 1, 1), -+ FACTOR(CLK_INFRA_NFI_CK, "infra_nfi", "nfi1x", 1, 1), -+ FACTOR(CLK_INFRA_SPINFI_CK, "infra_spinfi", "spinfi_bck", 1, 1), -+ FACTOR(CLK_INFRA_MUX_SPI0, "infra_mux_spi0", "infra_spi0_sel", 1, 1), -+ FACTOR(CLK_INFRA_MUX_SPI1, "infra_mux_spi1", "infra_spi1_sel", 1, 1), -+ FACTOR(CLK_INFRA_MUX_SPI2, "infra_mux_spi2", "infra_spi2_sel", 1, 1), -+ FACTOR(CLK_INFRA_RTC_32K, "infra_rtc_32k", "cb_rtc_32k", 1, 1), -+ FACTOR(CLK_INFRA_FMSDC_CK, "infra_fmsdc", "emmc_400m", 1, 1), -+ FACTOR(CLK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", "emmc_208m", 1, 1), -+ FACTOR(CLK_INFRA_PERI_133M, "infra_peri_133m", "sysaxi", 1, 1), -+ FACTOR(CLK_INFRA_133M_PHCK, "infra_133m_phck", "sysaxi", 1, 1), -+ FACTOR(CLK_INFRA_USB_SYS_CK, "infra_usb_sys", "u2u3_sys", 1, 1), -+ FACTOR(CLK_INFRA_USB_CK, "infra_usb", "u2u3_ref", 1, 1), -+ FACTOR(CLK_INFRA_USB_XHCI_CK, "infra_usb_xhci", "u2u3_xhci", 1, 1), -+ FACTOR(CLK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", "pextp_tl", 1, 1), -+ FACTOR(CLK_INFRA_F26M_CK0, "infra_f26m_ck0", "csw_f26m", 1, 1), -+ FACTOR(CLK_INFRA_133M_MCK, "infra_133m_mck", "sysaxi", 1, 1), -+}; -+ -+static int clk_mt7981_infracfg_probe(struct platform_device *pdev) -+{ -+ struct clk_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int nr = ARRAY_SIZE(infra_divs); -+ void __iomem *base; -+ int r; -+ -+ base = of_iomap(node, 0); -+ if (!base) { -+ pr_err("%s(): ioremap failed\n", __func__); -+ return -ENOMEM; -+ } -+ -+ clk_data = mtk_alloc_clk_data(nr); -+ -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_infracfg_data; -+ } -+ return r; -+ -+free_infracfg_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+ -+} -+ -+static const struct of_device_id of_match_clk_mt7981_infracfg[] = { -+ { .compatible = "mediatek,mt7981-infracfg", }, -+ {} -+}; -+ -+static struct platform_driver clk_mt7981_infracfg_drv = { -+ .probe = clk_mt7981_infracfg_probe, -+ .driver = { -+ .name = "clk-mt7981-infracfg", -+ .of_match_table = of_match_clk_mt7981_infracfg, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_infracfg_drv); -+ -+ -+static const char * const infra_uart0_parents[] __initconst = { -+ "infra_ck_f26m", -+ "infra_uart" -+}; -+ -+static const char * const infra_spi0_parents[] __initconst = { -+ "infra_i2c", -+ "infra_ispi0" -+}; -+ -+static const char * const infra_spi1_parents[] __initconst = { -+ "infra_i2c", -+ "infra_ispi1" -+}; -+ -+static const char * const infra_pwm1_parents[] __initconst = { -+ "infra_pwm" -+}; -+ -+static const char * const infra_pwm_bsel_parents[] __initconst = { -+ "infra_ck_f32k", -+ "infra_ck_f26m", -+ "infra_66m_mck", -+ "infra_pwm" -+}; -+ -+static const char * const infra_pcie_parents[] __initconst = { -+ "infra_ck_f32k", -+ "infra_ck_f26m", -+ "cb_cksq_40m", -+ "infra_pcie" -+}; -+ -+static const struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", -+ infra_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", -+ infra_uart0_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", -+ infra_uart0_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", -+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", -+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", -+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1, -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &infra0_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &infra1_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &infra2_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+static const struct mtk_gate infra_clks[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), -+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), -+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bck", 2), -+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm_ck1", 3), -+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm_ck2", 4), -+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "infra_133m_hck", 6), -+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "infra_66m_phck", 8), -+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "infra_ck_f26m", 9), -+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "infra_faud_l", 10), -+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "infra_faud_aud", 11), -+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "infra_faud_eg2", 13), -+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "infra_ck_f26m", 14), -+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), -+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), -+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), -+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "infra_ck_f26m", 25), -+ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "infra_ck_f26m", 0), -+ GATE_INFRA1(CLK_INFRA_I2CO_CK, "infra_i2co", "infra_i2cs", 1), -+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_mux_uart0", 2), -+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_mux_uart1", 3), -+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_mux_uart2", 4), -+ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_mux_spi2", 6), -+ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), -+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "infra_nfi", 8), -+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "infra_spinfi", 9), -+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), -+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_mux_spi0", 11), -+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_mux_spi1", 12), -+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", 13), -+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", 14), -+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "infra_rtc_32k", 15), -+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "infra_fmsdc", 16), -+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "infra_fmsdc_hck", 17), -+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "infra_peri_133m", 18), -+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_66m_phck", 19), -+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m", 20), -+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), -+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "infra_nfi", 23), -+ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "infra_133m_mck", 25), -+ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "infra_133m_phck", 0), -+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_66m_phck", 1), -+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "infra_usb_sys", 2), -+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "infra_usb", 3), -+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "infra_pcie_mux", 12), -+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", 13), -+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "infra_f26m_ck0", 14), -+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "infra_133m_phck", 15), -+}; -+ -+static int clk_mt7981_infracfg_ao_probe(struct platform_device *pdev) -+{ -+ struct clk_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks); -+ void __iomem *base; -+ int r; -+ -+ base = of_iomap(node, 0); -+ if (!base) { -+ pr_err("%s(): ioremap failed\n", __func__); -+ return -ENOMEM; -+ } -+ -+ clk_data = mtk_alloc_clk_data(nr); -+ -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, -+ &mt7981_clk_lock, clk_data); -+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -+ clk_data); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_infracfg_data; -+ } -+ return r; -+ -+free_infracfg_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+ -+} -+ -+static const struct of_device_id of_match_clk_mt7981_infracfg_ao[] = { -+ { .compatible = "mediatek,mt7981-infracfg_ao", }, -+ {} -+}; -+ -+static struct platform_driver clk_mt7981_infracfg_ao_drv = { -+ .probe = clk_mt7981_infracfg_ao_probe, -+ .driver = { -+ .name = "clk-mt7981-infracfg_ao", -+ .of_match_table = of_match_clk_mt7981_infracfg_ao, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_infracfg_ao_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c -@@ -0,0 +1,431 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor top_divs[] = { -+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), -+ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), -+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), -+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), -+ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), -+ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), -+ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), -+ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), -+ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), -+ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), -+ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), -+ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), -+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), -+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), -+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), -+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), -+ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), -+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), -+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), -+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), -+ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), -+ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), -+ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), -+ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), -+ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), -+ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), -+ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), -+ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), -+ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), -+ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), -+ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), -+ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), -+ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), -+}; -+ -+static const char * const nfi1x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "cb_m_d8" -+}; -+ -+static const char * const spinfi_parents[] __initconst = { -+ "cksq_40m_d2", -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "mm_d6_d2", -+ "cb_m_d8" -+}; -+ -+static const char * const spi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const uart_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d8", -+ "m_d8_d2" -+}; -+ -+static const char * const pwm_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "m_d8_d2", -+ "cb_rtc_32k" -+}; -+ -+static const char * const i2c_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const pextp_tl_ck_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_rtc_32k" -+}; -+ -+static const char * const emmc_208m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_net2_d4", -+ "cb_apll2_196m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_mm_d6" -+}; -+ -+static const char * const emmc_400m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d2", -+ "cb_mm_d2", -+ "cb_net2_d2" -+}; -+ -+static const char * const csw_f26m_parents[] __initconst = { -+ "cksq_40m_d2", -+ "m_d8_d2" -+}; -+ -+static const char * const dramc_md32_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_wedmcu_208m" -+}; -+ -+static const char * const sysaxi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2" -+}; -+ -+static const char * const sysapb_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d3_d2" -+}; -+ -+static const char * const arm_db_main_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d6" -+}; -+ -+static const char * const ap2cnn_host_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d4" -+}; -+ -+static const char * const netsys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d2" -+}; -+ -+static const char * const netsys_500m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5" -+}; -+ -+static const char * const netsys_mcu_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_720m", -+ "cb_net1_d4", -+ "cb_net1_d5", -+ "cb_m_416m" -+}; -+ -+static const char * const netsys_2x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_800m", -+ "cb_mm_720m" -+}; -+ -+static const char * const sgm_325m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_sgm_325m" -+}; -+ -+static const char * const sgm_reg_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d4" -+}; -+ -+static const char * const eip97b_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5", -+ "cb_m_416m", -+ "cb_mm_d2", -+ "net1_d5_d2" -+}; -+ -+static const char * const aud_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m" -+}; -+ -+static const char * const a1sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4" -+}; -+ -+static const char * const aud_l_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m", -+ "m_d8_d2" -+}; -+ -+static const char * const a_tuner_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4" -+}; -+ -+static const char * const usb_frmcnt_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d3_d5" -+}; -+ -+static const struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", -+ nfi1x_parents, 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", -+ spinfi_parents, 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", -+ spi_parents, 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", -+ spi_parents, 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", -+ uart_parents, 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", -+ pwm_parents, 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", -+ i2c_parents, 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", -+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", -+ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", -+ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x1C0, 9), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, 0x1C0, 10), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, 7, 0x1C0, 12), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, 0x1C0, 13), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", -+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", -+ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", -+ netsys_parents, 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", -+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", -+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", -+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", -+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -+ sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", -+ eip97b_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", -+ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", -+ aud_parents, 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", -+ a1sys_parents, 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", -+ aud_l_parents, 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -+ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", -+ u2u3_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", -+ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), -+}; -+ -+static struct mtk_composite top_aud_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", -+ 0x0420, 0, 0x0420, 8, 8), -+}; -+ -+static int clk_mt7981_topckgen_probe(struct platform_device *pdev) -+{ -+ struct clk_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ void __iomem *base; -+ int nr = ARRAY_SIZE(top_divs) + ARRAY_SIZE(top_muxes); -+ -+ base = of_iomap(node, 0); -+ if (!base) { -+ pr_err("%s(): ioremap failed\n", __func__); -+ return -ENOMEM; -+ } -+ -+ clk_data = mtk_alloc_clk_data(nr); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, -+ &mt7981_clk_lock, clk_data); -+ mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), -+ base, &mt7981_clk_lock, clk_data); -+ -+ clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]); -+ clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]); -+ clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]); -+ clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]); -+ clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]); -+ -+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -+ -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_topckgen_data; -+ } -+ return r; -+ -+free_topckgen_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static const struct of_device_id of_match_clk_mt7981_topckgen[] = { -+ { .compatible = "mediatek,mt7981-topckgen", }, -+ {} -+}; -+ -+static struct platform_driver clk_mt7981_topckgen_drv = { -+ .probe = clk_mt7981_topckgen_probe, -+ .driver = { -+ .name = "clk-mt7981-topckgen", -+ .of_match_table = of_match_clk_mt7981_topckgen, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_topckgen_drv); ---- /dev/null -+++ b/include/dt-bindings/clock/mt7981-clk.h -@@ -0,0 +1,253 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Wenzhen.Yu -+ * Author: Jianhui Zhao -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7981_H -+#define _DT_BINDINGS_CLK_MT7981_H -+ -+/* INFRACFG */ -+#define CLK_INFRA_CK_F26M 0 -+#define CLK_INFRA_UART 1 -+#define CLK_INFRA_ISPI0 2 -+#define CLK_INFRA_I2C 3 -+#define CLK_INFRA_ISPI1 4 -+#define CLK_INFRA_PWM 5 -+#define CLK_INFRA_66M_MCK 6 -+#define CLK_INFRA_CK_F32K 7 -+#define CLK_INFRA_PCIE_CK 8 -+#define CLK_INFRA_PWM_BCK 9 -+#define CLK_INFRA_PWM_CK1 10 -+#define CLK_INFRA_PWM_CK2 11 -+#define CLK_INFRA_133M_HCK 12 -+#define CLK_INFRA_66M_PHCK 13 -+#define CLK_INFRA_FAUD_L_CK 14 -+#define CLK_INFRA_FAUD_AUD_CK 15 -+#define CLK_INFRA_FAUD_EG2_CK 16 -+#define CLK_INFRA_I2CS_CK 17 -+#define CLK_INFRA_MUX_UART0 18 -+#define CLK_INFRA_MUX_UART1 19 -+#define CLK_INFRA_MUX_UART2 20 -+#define CLK_INFRA_NFI_CK 21 -+#define CLK_INFRA_SPINFI_CK 22 -+#define CLK_INFRA_MUX_SPI0 23 -+#define CLK_INFRA_MUX_SPI1 24 -+#define CLK_INFRA_MUX_SPI2 25 -+#define CLK_INFRA_RTC_32K 26 -+#define CLK_INFRA_FMSDC_CK 27 -+#define CLK_INFRA_FMSDC_HCK_CK 28 -+#define CLK_INFRA_PERI_133M 29 -+#define CLK_INFRA_133M_PHCK 30 -+#define CLK_INFRA_USB_SYS_CK 31 -+#define CLK_INFRA_USB_CK 32 -+#define CLK_INFRA_USB_XHCI_CK 33 -+#define CLK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -+#define CLK_INFRA_F26M_CK0 35 -+#define CLK_INFRA_133M_MCK 36 -+ -+/* TOPCKGEN */ -+#define CLK_TOP_CB_CKSQ_40M 0 -+#define CLK_TOP_CB_M_416M 1 -+#define CLK_TOP_CB_M_D2 2 -+#define CLK_TOP_CB_M_D3 3 -+#define CLK_TOP_M_D3_D2 4 -+#define CLK_TOP_CB_M_D4 5 -+#define CLK_TOP_CB_M_D8 6 -+#define CLK_TOP_M_D8_D2 7 -+#define CLK_TOP_CB_MM_720M 8 -+#define CLK_TOP_CB_MM_D2 9 -+#define CLK_TOP_CB_MM_D3 10 -+#define CLK_TOP_CB_MM_D3_D5 11 -+#define CLK_TOP_CB_MM_D4 12 -+#define CLK_TOP_CB_MM_D6 13 -+#define CLK_TOP_MM_D6_D2 14 -+#define CLK_TOP_CB_MM_D8 15 -+#define CLK_TOP_CB_APLL2_196M 16 -+#define CLK_TOP_APLL2_D2 17 -+#define CLK_TOP_APLL2_D4 18 -+#define CLK_TOP_NET1_2500M 19 -+#define CLK_TOP_CB_NET1_D4 20 -+#define CLK_TOP_CB_NET1_D5 21 -+#define CLK_TOP_NET1_D5_D2 22 -+#define CLK_TOP_NET1_D5_D4 23 -+#define CLK_TOP_CB_NET1_D8 24 -+#define CLK_TOP_NET1_D8_D2 25 -+#define CLK_TOP_NET1_D8_D4 26 -+#define CLK_TOP_CB_NET2_800M 27 -+#define CLK_TOP_CB_NET2_D2 28 -+#define CLK_TOP_CB_NET2_D4 29 -+#define CLK_TOP_NET2_D4_D2 30 -+#define CLK_TOP_NET2_D4_D4 31 -+#define CLK_TOP_CB_NET2_D6 32 -+#define CLK_TOP_CB_WEDMCU_208M 33 -+#define CLK_TOP_CB_SGM_325M 34 -+#define CLK_TOP_CKSQ_40M_D2 35 -+#define CLK_TOP_CB_RTC_32K 36 -+#define CLK_TOP_CB_RTC_32P7K 37 -+#define CLK_TOP_USB_TX250M 38 -+#define CLK_TOP_FAUD 39 -+#define CLK_TOP_NFI1X 40 -+#define CLK_TOP_USB_EQ_RX250M 41 -+#define CLK_TOP_USB_CDR_CK 42 -+#define CLK_TOP_USB_LN0_CK 43 -+#define CLK_TOP_SPINFI_BCK 44 -+#define CLK_TOP_SPI 45 -+#define CLK_TOP_SPIM_MST 46 -+#define CLK_TOP_UART_BCK 47 -+#define CLK_TOP_PWM_BCK 48 -+#define CLK_TOP_I2C_BCK 49 -+#define CLK_TOP_PEXTP_TL 50 -+#define CLK_TOP_EMMC_208M 51 -+#define CLK_TOP_EMMC_400M 52 -+#define CLK_TOP_DRAMC_REF 53 -+#define CLK_TOP_DRAMC_MD32 54 -+#define CLK_TOP_SYSAXI 55 -+#define CLK_TOP_SYSAPB 56 -+#define CLK_TOP_ARM_DB_MAIN 57 -+#define CLK_TOP_AP2CNN_HOST 58 -+#define CLK_TOP_NETSYS 59 -+#define CLK_TOP_NETSYS_500M 60 -+#define CLK_TOP_NETSYS_WED_MCU 61 -+#define CLK_TOP_NETSYS_2X 62 -+#define CLK_TOP_SGM_325M 63 -+#define CLK_TOP_SGM_REG 64 -+#define CLK_TOP_F26M 65 -+#define CLK_TOP_EIP97B 66 -+#define CLK_TOP_USB3_PHY 67 -+#define CLK_TOP_AUD 68 -+#define CLK_TOP_A1SYS 69 -+#define CLK_TOP_AUD_L 70 -+#define CLK_TOP_A_TUNER 71 -+#define CLK_TOP_U2U3_REF 72 -+#define CLK_TOP_U2U3_SYS 73 -+#define CLK_TOP_U2U3_XHCI 74 -+#define CLK_TOP_USB_FRMCNT 75 -+#define CLK_TOP_NFI1X_SEL 76 -+#define CLK_TOP_SPINFI_SEL 77 -+#define CLK_TOP_SPI_SEL 78 -+#define CLK_TOP_SPIM_MST_SEL 79 -+#define CLK_TOP_UART_SEL 80 -+#define CLK_TOP_PWM_SEL 81 -+#define CLK_TOP_I2C_SEL 82 -+#define CLK_TOP_PEXTP_TL_SEL 83 -+#define CLK_TOP_EMMC_208M_SEL 84 -+#define CLK_TOP_EMMC_400M_SEL 85 -+#define CLK_TOP_F26M_SEL 86 -+#define CLK_TOP_DRAMC_SEL 87 -+#define CLK_TOP_DRAMC_MD32_SEL 88 -+#define CLK_TOP_SYSAXI_SEL 89 -+#define CLK_TOP_SYSAPB_SEL 90 -+#define CLK_TOP_ARM_DB_MAIN_SEL 91 -+#define CLK_TOP_AP2CNN_HOST_SEL 92 -+#define CLK_TOP_NETSYS_SEL 93 -+#define CLK_TOP_NETSYS_500M_SEL 94 -+#define CLK_TOP_NETSYS_MCU_SEL 95 -+#define CLK_TOP_NETSYS_2X_SEL 96 -+#define CLK_TOP_SGM_325M_SEL 97 -+#define CLK_TOP_SGM_REG_SEL 98 -+#define CLK_TOP_EIP97B_SEL 99 -+#define CLK_TOP_USB3_PHY_SEL 100 -+#define CLK_TOP_AUD_SEL 101 -+#define CLK_TOP_A1SYS_SEL 102 -+#define CLK_TOP_AUD_L_SEL 103 -+#define CLK_TOP_A_TUNER_SEL 104 -+#define CLK_TOP_U2U3_SEL 105 -+#define CLK_TOP_U2U3_SYS_SEL 106 -+#define CLK_TOP_U2U3_XHCI_SEL 107 -+#define CLK_TOP_USB_FRMCNT_SEL 108 -+#define CLK_TOP_AUD_I2S_M 109 -+ -+/* INFRACFG_AO */ -+#define CLK_INFRA_UART0_SEL 0 -+#define CLK_INFRA_UART1_SEL 1 -+#define CLK_INFRA_UART2_SEL 2 -+#define CLK_INFRA_SPI0_SEL 3 -+#define CLK_INFRA_SPI1_SEL 4 -+#define CLK_INFRA_SPI2_SEL 5 -+#define CLK_INFRA_PWM1_SEL 6 -+#define CLK_INFRA_PWM2_SEL 7 -+#define CLK_INFRA_PWM3_SEL 8 -+#define CLK_INFRA_PWM_BSEL 9 -+#define CLK_INFRA_PCIE_SEL 10 -+#define CLK_INFRA_GPT_STA 11 -+#define CLK_INFRA_PWM_HCK 12 -+#define CLK_INFRA_PWM_STA 13 -+#define CLK_INFRA_PWM1_CK 14 -+#define CLK_INFRA_PWM2_CK 15 -+#define CLK_INFRA_PWM3_CK 16 -+#define CLK_INFRA_CQ_DMA_CK 17 -+#define CLK_INFRA_AUD_BUS_CK 18 -+#define CLK_INFRA_AUD_26M_CK 19 -+#define CLK_INFRA_AUD_L_CK 20 -+#define CLK_INFRA_AUD_AUD_CK 21 -+#define CLK_INFRA_AUD_EG2_CK 22 -+#define CLK_INFRA_DRAMC_26M_CK 23 -+#define CLK_INFRA_DBG_CK 24 -+#define CLK_INFRA_AP_DMA_CK 25 -+#define CLK_INFRA_SEJ_CK 26 -+#define CLK_INFRA_SEJ_13M_CK 27 -+#define CLK_INFRA_THERM_CK 28 -+#define CLK_INFRA_I2CO_CK 29 -+#define CLK_INFRA_UART0_CK 30 -+#define CLK_INFRA_UART1_CK 31 -+#define CLK_INFRA_UART2_CK 32 -+#define CLK_INFRA_SPI2_CK 33 -+#define CLK_INFRA_SPI2_HCK_CK 34 -+#define CLK_INFRA_NFI1_CK 35 -+#define CLK_INFRA_SPINFI1_CK 36 -+#define CLK_INFRA_NFI_HCK_CK 37 -+#define CLK_INFRA_SPI0_CK 38 -+#define CLK_INFRA_SPI1_CK 39 -+#define CLK_INFRA_SPI0_HCK_CK 40 -+#define CLK_INFRA_SPI1_HCK_CK 41 -+#define CLK_INFRA_FRTC_CK 42 -+#define CLK_INFRA_MSDC_CK 43 -+#define CLK_INFRA_MSDC_HCK_CK 44 -+#define CLK_INFRA_MSDC_133M_CK 45 -+#define CLK_INFRA_MSDC_66M_CK 46 -+#define CLK_INFRA_ADC_26M_CK 47 -+#define CLK_INFRA_ADC_FRC_CK 48 -+#define CLK_INFRA_FBIST2FPC_CK 49 -+#define CLK_INFRA_I2C_MCK_CK 50 -+#define CLK_INFRA_I2C_PCK_CK 51 -+#define CLK_INFRA_IUSB_133_CK 52 -+#define CLK_INFRA_IUSB_66M_CK 53 -+#define CLK_INFRA_IUSB_SYS_CK 54 -+#define CLK_INFRA_IUSB_CK 55 -+#define CLK_INFRA_IPCIE_CK 56 -+#define CLK_INFRA_IPCIE_PIPE_CK 57 -+#define CLK_INFRA_IPCIER_CK 58 -+#define CLK_INFRA_IPCIEB_CK 59 -+ -+/* APMIXEDSYS */ -+#define CLK_APMIXED_ARMPLL 0 -+#define CLK_APMIXED_NET2PLL 1 -+#define CLK_APMIXED_MMPLL 2 -+#define CLK_APMIXED_SGMPLL 3 -+#define CLK_APMIXED_WEDMCUPLL 4 -+#define CLK_APMIXED_NET1PLL 5 -+#define CLK_APMIXED_MPLL 6 -+#define CLK_APMIXED_APLL2 7 -+ -+/* SGMIISYS_0 */ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGM0_CK0_EN 2 -+#define CLK_SGM0_CDR_CK0_EN 3 -+ -+/* SGMIISYS_1 */ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGM1_CK1_EN 2 -+#define CLK_SGM1_CDR_CK1_EN 3 -+ -+/* ETHSYS */ -+#define CLK_ETH_FE_EN 0 -+#define CLK_ETH_GP2_EN 1 -+#define CLK_ETH_GP1_EN 2 -+#define CLK_ETH_WOCPU0_EN 3 -+ -+#endif /* _DT_BINDINGS_CLK_MT7981_H */ -+