rockchip: sync dts changes from upstream

package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch

@@ -36,7 +36,7 @@
 +};
 --- /dev/null
 +++ b/arch/arm/dts/rk3568-radxa-e25.dts
-@@ -0,0 +1,13 @@
+@@ -0,0 +1,8 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +
 +#include "rk3568-evb.dts"
@@ -44,11 +44,6 @@
 +/ {
 +	model = "Radxa E25";
 +	compatible = "radxa,e25", "rockchip,rk3568";
-+
-+	aliases {
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
 +};
 --- /dev/null
 +++ b/configs/radxa-e25-rk3568_defconfig

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi

@@ -1,13 +1,12 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/input/input.h>
 #include "rk3568.dtsi"
 
 / {
-	model = "Radxa CM3 Industrial Board";
 	compatible = "radxa,cm3i", "rockchip,rk3568";
 
 	aliases {

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts

@@ -4,12 +4,11 @@
 #include "rk3568-radxa-cm3i.dtsi"
 
 / {
-	model = "Radxa E25";
+	model = "Radxa E25 Carrier Board";
 	compatible = "radxa,e25", "rockchip,rk3568";
 
 	aliases {
-		mmc0 = &sdmmc0;
+		mmc1 = &sdmmc0;
-		mmc1 = &sdhci;
 	};
 
 	chosen {

target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts

@@ -533,13 +533,16 @@
 &i2c5 {
 	status = "okay";
 
-	hym8563: hym8563@51 {
+	hym8563: rtc@51 {
 		compatible = "haoyu,hym8563";
 		reg = <0x51>;
 		interrupt-parent = <&gpio0>;
 		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+		#clock-cells = <0>;
+		clock-output-names = "rtcic_32kout";
 		pinctrl-names = "default";
 		pinctrl-0 = <&hym8563_int>;
+		wakeup-source;
 	};
 };
 
@@ -703,6 +706,7 @@
 };
 
 &usb_host0_xhci {
+	extcon = <&usb2phy0>;
 	status = "okay";
 };
 

target/linux/rockchip/patches-5.15/061-v6.2-arm64-dts-rockchip-add-missing-interrupt-cells.patch

@@ -0,0 +1,26 @@
+From a323e6b5737bb6e3d3946369b97099abb7dde695 Mon Sep 17 00:00:00 2001
+From: Jensen Huang <jensenhuang@friendlyarm.com>
+Date: Fri, 13 Jan 2023 14:44:57 +0800
+Subject: [PATCH] arm64: dts: rockchip: add missing #interrupt-cells to rk356x
+ pcie2x1
+
+This fixes the following issue:
+  pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22
+
+Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
+Link: https://lore.kernel.org/r/20230113064457.7105-1-jensenhuang@friendlyarm.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -722,6 +722,7 @@
+ 		clock-names = "aclk_mst", "aclk_slv",
+ 			      "aclk_dbi", "pclk", "aux";
+ 		device_type = "pci";
++		#interrupt-cells = <1>;
+ 		interrupt-map-mask = <0 0 0 7>;
+ 		interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ 				<0 0 0 2 &pcie_intc 1>,

target/linux/rockchip/patches-5.15/062-v6.3-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k.patch

@@ -0,0 +1,32 @@
+From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 10 Jan 2023 22:55:50 +0000
+Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
+
+clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
+and not to 32 kHz on RK356x.
+
+Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
+to clk_rtc32k_frac.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -367,8 +367,9 @@
+ 		clock-names = "xin24m";
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;
+-		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+-		assigned-clock-rates = <1200000000>, <200000000>;
++		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
++		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
++		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+ 		rockchip,grf = <&grf>;
+ 	};
+ 

target/linux/rockchip/patches-6.1/006-v6.3-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k.patch

@@ -0,0 +1,32 @@
+From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 10 Jan 2023 22:55:50 +0000
+Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
+
+clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
+and not to 32 kHz on RK356x.
+
+Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
+to clk_rtc32k_frac.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -422,8 +422,9 @@
+ 		clock-names = "xin24m";
+ 		#clock-cells = <1>;
+ 		#reset-cells = <1>;
+-		assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+-		assigned-clock-rates = <1200000000>, <200000000>;
++		assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
++		assigned-clock-rates = <32768>, <1200000000>, <200000000>;
++		assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
+ 		rockchip,grf = <&grf>;
+ 	};
+