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bcm53xx: update kernel patch support
This commit is contained in:
coolsnowwolf
parent
07903a1da4
commit
7b05c2ee4f
@ -0,0 +1,427 @@
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From c12fb1774deaa9c9408b19db8d43d3612f6e47a0 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Wed, 26 Sep 2018 21:31:03 +0200
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Subject: [PATCH] pinctrl: bcm: add Northstar driver
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This driver provides support for Northstar mux controller. It differs
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from Northstar Plus one so a new binding and driver were needed.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/bcm/Kconfig | 13 ++
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drivers/pinctrl/bcm/Makefile | 1 +
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drivers/pinctrl/bcm/pinctrl-ns.c | 372 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 386 insertions(+)
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create mode 100644 drivers/pinctrl/bcm/pinctrl-ns.c
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--- a/drivers/pinctrl/bcm/Kconfig
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+++ b/drivers/pinctrl/bcm/Kconfig
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@@ -72,6 +72,19 @@ config PINCTRL_CYGNUS_MUX
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configuration, with the exception that certain individual pins
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can be overridden to GPIO function
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+config PINCTRL_NS
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+ bool "Broadcom Northstar pins driver"
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+ depends on OF && (ARCH_BCM_5301X || COMPILE_TEST)
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+ select PINMUX
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+ select GENERIC_PINCONF
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+ default ARCH_BCM_5301X
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+ help
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+ Say yes here to enable the Broadcom NS SoC pins driver.
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+
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+ The Broadcom Northstar pins driver supports muxing multi-purpose pins
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+ that can be used for various functions (e.g. SPI, I2C, UART) as well
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+ as GPIOs.
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+
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config PINCTRL_NSP_GPIO
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bool "Broadcom NSP GPIO (with PINCONF) driver"
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depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
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--- a/drivers/pinctrl/bcm/Makefile
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+++ b/drivers/pinctrl/bcm/Makefile
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@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinct
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obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
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obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
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obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
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+obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
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obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o
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obj-$(CONFIG_PINCTRL_NS2_MUX) += pinctrl-ns2-mux.o
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obj-$(CONFIG_PINCTRL_NSP_MUX) += pinctrl-nsp-mux.o
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--- /dev/null
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+++ b/drivers/pinctrl/bcm/pinctrl-ns.c
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@@ -0,0 +1,372 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (C) 2018 Rafał Miłecki <rafal@milecki.pl>
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+ */
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+
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/pinctrl/pinconf-generic.h>
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+#include <linux/pinctrl/pinctrl.h>
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+#include <linux/pinctrl/pinmux.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+#define FLAG_BCM4708 BIT(1)
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+#define FLAG_BCM4709 BIT(2)
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+#define FLAG_BCM53012 BIT(3)
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+
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+struct ns_pinctrl {
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+ struct device *dev;
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+ unsigned int chipset_flag;
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+ struct pinctrl_dev *pctldev;
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+ void __iomem *base;
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+
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+ struct pinctrl_desc pctldesc;
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+ struct ns_pinctrl_group *groups;
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+ unsigned int num_groups;
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+ struct ns_pinctrl_function *functions;
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+ unsigned int num_functions;
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+};
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+
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+/*
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+ * Pins
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+ */
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+
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+static const struct pinctrl_pin_desc ns_pinctrl_pins[] = {
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+ { 0, "spi_clk", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 1, "spi_ss", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 2, "spi_mosi", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 3, "spi_miso", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 4, "i2c_scl", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 5, "i2c_sda", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 6, "mdc", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 7, "mdio", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 8, "pwm0", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 9, "pwm1", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 10, "pwm2", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 11, "pwm3", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 12, "uart1_rx", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 13, "uart1_tx", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 14, "uart1_cts", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 15, "uart1_rts", (void *)(FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 16, "uart2_rx", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 17, "uart2_tx", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
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+/* TODO { ??, "xtal_out", (void *)(FLAG_BCM4709) }, */
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+ { 22, "sdio_pwr", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
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+ { 23, "sdio_en_1p8v", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
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+};
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+
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+/*
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+ * Groups
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+ */
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+
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+struct ns_pinctrl_group {
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+ const char *name;
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+ const unsigned int *pins;
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+ const unsigned int num_pins;
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+ unsigned int chipsets;
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+};
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+
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+static const unsigned int spi_pins[] = { 0, 1, 2, 3 };
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+static const unsigned int i2c_pins[] = { 4, 5 };
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+static const unsigned int mdio_pins[] = { 6, 7 };
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+static const unsigned int pwm0_pins[] = { 8 };
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+static const unsigned int pwm1_pins[] = { 9 };
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+static const unsigned int pwm2_pins[] = { 10 };
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+static const unsigned int pwm3_pins[] = { 11 };
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+static const unsigned int uart1_pins[] = { 12, 13, 14, 15 };
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+static const unsigned int uart2_pins[] = { 16, 17 };
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+static const unsigned int sdio_pwr_pins[] = { 22 };
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+static const unsigned int sdio_1p8v_pins[] = { 23 };
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+
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+#define NS_GROUP(_name, _pins, _chipsets) \
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+{ \
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+ .name = _name, \
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+ .pins = _pins, \
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+ .num_pins = ARRAY_SIZE(_pins), \
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+ .chipsets = _chipsets, \
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+}
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+
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+static const struct ns_pinctrl_group ns_pinctrl_groups[] = {
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+ NS_GROUP("spi_grp", spi_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("i2c_grp", i2c_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("mdio_grp", mdio_pins, FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("pwm0_grp", pwm0_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("pwm1_grp", pwm1_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("pwm2_grp", pwm2_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("pwm3_grp", pwm3_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("uart1_grp", uart1_pins, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("uart2_grp", uart2_pins, FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("sdio_pwr_grp", sdio_pwr_pins, FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_GROUP("sdio_1p8v_grp", sdio_1p8v_pins, FLAG_BCM4709 | FLAG_BCM53012),
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+};
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+
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+/*
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+ * Functions
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+ */
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+
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+struct ns_pinctrl_function {
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+ const char *name;
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+ const char * const *groups;
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+ const unsigned int num_groups;
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+ unsigned int chipsets;
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+};
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+
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+static const char * const spi_groups[] = { "spi_grp" };
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+static const char * const i2c_groups[] = { "i2c_grp" };
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+static const char * const mdio_groups[] = { "mdio_grp" };
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+static const char * const pwm_groups[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp",
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+ "pwm3_grp" };
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+static const char * const uart1_groups[] = { "uart1_grp" };
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+static const char * const uart2_groups[] = { "uart2_grp" };
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+static const char * const sdio_groups[] = { "sdio_pwr_grp", "sdio_1p8v_grp" };
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+
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+#define NS_FUNCTION(_name, _groups, _chipsets) \
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+{ \
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+ .name = _name, \
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+ .groups = _groups, \
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+ .num_groups = ARRAY_SIZE(_groups), \
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+ .chipsets = _chipsets, \
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+}
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+
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+static const struct ns_pinctrl_function ns_pinctrl_functions[] = {
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+ NS_FUNCTION("spi", spi_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_FUNCTION("i2c", i2c_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_FUNCTION("mdio", mdio_groups, FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_FUNCTION("pwm", pwm_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_FUNCTION("uart1", uart1_groups, FLAG_BCM4708 | FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_FUNCTION("uart2", uart2_groups, FLAG_BCM4709 | FLAG_BCM53012),
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+ NS_FUNCTION("sdio", sdio_groups, FLAG_BCM4709 | FLAG_BCM53012),
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+};
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+
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+/*
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+ * Groups code
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+ */
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+
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+static int ns_pinctrl_get_groups_count(struct pinctrl_dev *pctrl_dev)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+
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+ return ns_pinctrl->num_groups;
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+}
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+
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+static const char *ns_pinctrl_get_group_name(struct pinctrl_dev *pctrl_dev,
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+ unsigned int selector)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+
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+ return ns_pinctrl->groups[selector].name;
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+}
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+
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+static int ns_pinctrl_get_group_pins(struct pinctrl_dev *pctrl_dev,
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+ unsigned int selector,
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+ const unsigned int **pins,
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+ unsigned int *num_pins)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+
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+ *pins = ns_pinctrl->groups[selector].pins;
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+ *num_pins = ns_pinctrl->groups[selector].num_pins;
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+
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+ return 0;
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+}
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+
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+static const struct pinctrl_ops ns_pinctrl_ops = {
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+ .get_groups_count = ns_pinctrl_get_groups_count,
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+ .get_group_name = ns_pinctrl_get_group_name,
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+ .get_group_pins = ns_pinctrl_get_group_pins,
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+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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+ .dt_free_map = pinconf_generic_dt_free_map,
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+};
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+
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+/*
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+ * Functions code
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+ */
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+
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+static int ns_pinctrl_get_functions_count(struct pinctrl_dev *pctrl_dev)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+
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+ return ns_pinctrl->num_functions;
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+}
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+
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+static const char *ns_pinctrl_get_function_name(struct pinctrl_dev *pctrl_dev,
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+ unsigned int selector)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+
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+ return ns_pinctrl->functions[selector].name;
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+}
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+
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+static int ns_pinctrl_get_function_groups(struct pinctrl_dev *pctrl_dev,
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+ unsigned int selector,
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+ const char * const **groups,
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+ unsigned * const num_groups)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+
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+ *groups = ns_pinctrl->functions[selector].groups;
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+ *num_groups = ns_pinctrl->functions[selector].num_groups;
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+
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+ return 0;
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+}
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+
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+static int ns_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
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+ unsigned int func_select,
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+ unsigned int grp_select)
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+{
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+ struct ns_pinctrl *ns_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
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+ u32 unset = 0;
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+ u32 tmp;
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+ int i;
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+
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+ for (i = 0; i < ns_pinctrl->groups[grp_select].num_pins; i++) {
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+ int pin_number = ns_pinctrl->groups[grp_select].pins[i];
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+
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+ unset |= BIT(pin_number);
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+ }
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+
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+ tmp = readl(ns_pinctrl->base);
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+ tmp &= ~unset;
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+ writel(tmp, ns_pinctrl->base);
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+
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+ return 0;
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+}
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+
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+static const struct pinmux_ops ns_pinctrl_pmxops = {
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+ .get_functions_count = ns_pinctrl_get_functions_count,
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+ .get_function_name = ns_pinctrl_get_function_name,
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+ .get_function_groups = ns_pinctrl_get_function_groups,
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+ .set_mux = ns_pinctrl_set_mux,
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+};
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+
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+/*
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+ * Controller code
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+ */
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+
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+static struct pinctrl_desc ns_pinctrl_desc = {
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+ .name = "pinctrl-ns",
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+ .pctlops = &ns_pinctrl_ops,
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+ .pmxops = &ns_pinctrl_pmxops,
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+};
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+
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+static const struct of_device_id ns_pinctrl_of_match_table[] = {
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+ { .compatible = "brcm,bcm4708-pinmux", .data = (void *)FLAG_BCM4708, },
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+ { .compatible = "brcm,bcm4709-pinmux", .data = (void *)FLAG_BCM4709, },
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+ { .compatible = "brcm,bcm53012-pinmux", .data = (void *)FLAG_BCM53012, },
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+ { }
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+};
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+
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+static int ns_pinctrl_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ const struct of_device_id *of_id;
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+ struct ns_pinctrl *ns_pinctrl;
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+ struct pinctrl_desc *pctldesc;
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+ struct pinctrl_pin_desc *pin;
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+ struct ns_pinctrl_group *group;
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+ struct ns_pinctrl_function *function;
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+ struct resource *res;
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+ int i;
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+
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+ ns_pinctrl = devm_kzalloc(dev, sizeof(*ns_pinctrl), GFP_KERNEL);
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+ if (!ns_pinctrl)
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+ return -ENOMEM;
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+ pctldesc = &ns_pinctrl->pctldesc;
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+ platform_set_drvdata(pdev, ns_pinctrl);
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+
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+ /* Set basic properties */
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+
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+ ns_pinctrl->dev = dev;
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+
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+ of_id = of_match_device(ns_pinctrl_of_match_table, dev);
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+ if (!of_id)
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+ return -EINVAL;
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+ ns_pinctrl->chipset_flag = (unsigned int)of_id->data;
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+
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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+ "cru_gpio_control");
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+ ns_pinctrl->base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(ns_pinctrl->base)) {
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+ dev_err(dev, "Failed to map pinctrl regs\n");
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+ return PTR_ERR(ns_pinctrl->base);
|
||||
+ }
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+
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+ memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));
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+
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+ /* Set pinctrl properties */
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+
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+ pctldesc->pins = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_pins),
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+ sizeof(struct pinctrl_pin_desc),
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+ GFP_KERNEL);
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+ if (!pctldesc->pins)
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+ return -ENOMEM;
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+ for (i = 0, pin = (struct pinctrl_pin_desc *)&pctldesc->pins[0];
|
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+ i < ARRAY_SIZE(ns_pinctrl_pins); i++) {
|
||||
+ const struct pinctrl_pin_desc *src = &ns_pinctrl_pins[i];
|
||||
+ unsigned int chipsets = (unsigned int)src->drv_data;
|
||||
+
|
||||
+ if (chipsets & ns_pinctrl->chipset_flag) {
|
||||
+ memcpy(pin++, src, sizeof(*src));
|
||||
+ pctldesc->npins++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ ns_pinctrl->groups = devm_kcalloc(dev, ARRAY_SIZE(ns_pinctrl_groups),
|
||||
+ sizeof(struct ns_pinctrl_group),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!ns_pinctrl->groups)
|
||||
+ return -ENOMEM;
|
||||
+ for (i = 0, group = &ns_pinctrl->groups[0];
|
||||
+ i < ARRAY_SIZE(ns_pinctrl_groups); i++) {
|
||||
+ const struct ns_pinctrl_group *src = &ns_pinctrl_groups[i];
|
||||
+
|
||||
+ if (src->chipsets & ns_pinctrl->chipset_flag) {
|
||||
+ memcpy(group++, src, sizeof(*src));
|
||||
+ ns_pinctrl->num_groups++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ ns_pinctrl->functions = devm_kcalloc(dev,
|
||||
+ ARRAY_SIZE(ns_pinctrl_functions),
|
||||
+ sizeof(struct ns_pinctrl_function),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!ns_pinctrl->functions)
|
||||
+ return -ENOMEM;
|
||||
+ for (i = 0, function = &ns_pinctrl->functions[0];
|
||||
+ i < ARRAY_SIZE(ns_pinctrl_functions); i++) {
|
||||
+ const struct ns_pinctrl_function *src = &ns_pinctrl_functions[i];
|
||||
+
|
||||
+ if (src->chipsets & ns_pinctrl->chipset_flag) {
|
||||
+ memcpy(function++, src, sizeof(*src));
|
||||
+ ns_pinctrl->num_functions++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Register */
|
||||
+
|
||||
+ ns_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, ns_pinctrl);
|
||||
+ if (IS_ERR(ns_pinctrl->pctldev)) {
|
||||
+ dev_err(dev, "Failed to register pinctrl\n");
|
||||
+ return PTR_ERR(ns_pinctrl->pctldev);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver ns_pinctrl_driver = {
|
||||
+ .probe = ns_pinctrl_probe,
|
||||
+ .driver = {
|
||||
+ .name = "ns-pinmux",
|
||||
+ .of_match_table = ns_pinctrl_of_match_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(ns_pinctrl_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Rafał Miłecki");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_DEVICE_TABLE(of, ns_pinctrl_of_match_table);
|
||||
@ -0,0 +1,38 @@
|
||||
From ce7bdb957b8e3f1cbf0a3358f1deef385dff6502 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Thu, 11 Oct 2018 13:23:40 +0200
|
||||
Subject: [PATCH] pinctrl: bcm: ns: Use uintptr_t for casting data
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Fix up a compiler error on 64bit architectures where pointers
|
||||
and integers differ in size.
|
||||
|
||||
Suggested-by: Arnd Bergmann <arnd@arndb.de>
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
drivers/pinctrl/bcm/pinctrl-ns.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/bcm/pinctrl-ns.c
|
||||
+++ b/drivers/pinctrl/bcm/pinctrl-ns.c
|
||||
@@ -285,7 +285,7 @@ static int ns_pinctrl_probe(struct platf
|
||||
of_id = of_match_device(ns_pinctrl_of_match_table, dev);
|
||||
if (!of_id)
|
||||
return -EINVAL;
|
||||
- ns_pinctrl->chipset_flag = (unsigned int)of_id->data;
|
||||
+ ns_pinctrl->chipset_flag = (uintptr_t)of_id->data;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
||||
"cru_gpio_control");
|
||||
@@ -307,7 +307,7 @@ static int ns_pinctrl_probe(struct platf
|
||||
for (i = 0, pin = (struct pinctrl_pin_desc *)&pctldesc->pins[0];
|
||||
i < ARRAY_SIZE(ns_pinctrl_pins); i++) {
|
||||
const struct pinctrl_pin_desc *src = &ns_pinctrl_pins[i];
|
||||
- unsigned int chipsets = (unsigned int)src->drv_data;
|
||||
+ unsigned int chipsets = (uintptr_t)src->drv_data;
|
||||
|
||||
if (chipsets & ns_pinctrl->chipset_flag) {
|
||||
memcpy(pin++, src, sizeof(*src));
|
||||
@ -0,0 +1,73 @@
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 9 Nov 2018 09:53:56 +0100
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Describe Northstar pins mux controller
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This describes hardware & will allow referencing pin functions. The
|
||||
first usage is UART1 which allows supporting devices using it.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
---
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -37,6 +37,8 @@
|
||||
reg = <0x0400 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&iprocslow>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pinmux_uart1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -391,6 +393,48 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ dmu@1800c000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ ranges = <0 0x1800c000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ cru@100 {
|
||||
+ compatible = "simple-bus";
|
||||
+ reg = <0x100 0x1a4>;
|
||||
+ ranges;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ pin-controller@1c0 {
|
||||
+ compatible = "brcm,bcm4708-pinmux";
|
||||
+ reg = <0x1c0 0x24>;
|
||||
+ reg-names = "cru_gpio_control";
|
||||
+
|
||||
+ spi-pins {
|
||||
+ groups = "spi_grp";
|
||||
+ function = "spi";
|
||||
+ };
|
||||
+
|
||||
+ i2c {
|
||||
+ groups = "i2c_grp";
|
||||
+ function = "i2c";
|
||||
+ };
|
||||
+
|
||||
+ pwm {
|
||||
+ groups = "pwm0_grp", "pwm1_grp",
|
||||
+ "pwm2_grp", "pwm3_grp";
|
||||
+ function = "pwm";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_uart1: uart1 {
|
||||
+ groups = "uart1_grp";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
lcpll0: lcpll0@1800c100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-lcpll0";
|
||||
@ -0,0 +1,64 @@
|
||||
---
|
||||
arch/arm/boot/dts/Makefile | 1 +
|
||||
arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts | 41 +++++++++++++++++++++++++
|
||||
2 files changed, 42 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
|
||||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
||||
bcm4708-asus-rt-ac68u.dtb \
|
||||
bcm4708-buffalo-wzr-1750dhp.dtb \
|
||||
bcm4708-linksys-ea6300-v1.dtb \
|
||||
+ bcm4708-linksys-ea6500-v2.dtb \
|
||||
bcm4708-luxul-xap-1510.dtb \
|
||||
bcm4708-luxul-xwc-1000.dtb \
|
||||
bcm4708-netgear-r6250.dtb \
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts
|
||||
@@ -0,0 +1,45 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (C) 2017 Rafał Miłecki <rafal@milecki.pl>
|
||||
+ * Copyright (C) 2018 Rene Kjellerup <rk.katana.steel@gmail.com>
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "bcm4708.dtsi"
|
||||
+#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "linksys,ea6500-v2", "brcm,bcm4708";
|
||||
+ model = "Linksys EA6500 V2";
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "console=ttyS0,115200";
|
||||
+ };
|
||||
+
|
||||
+ memory {
|
||||
+ reg = <0x00000000 0x08000000>;
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ wps {
|
||||
+ label = "WPS";
|
||||
+ linux,code = <KEY_WPS_BUTTON>;
|
||||
+ gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ restart {
|
||||
+ label = "Reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+&usb3_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -0,0 +1,25 @@
|
||||
From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Thu, 22 Nov 2018 09:21:49 +0100
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Describe partition formats
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
It's needed by OpenWrt for custom partitioning.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
---
|
||||
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
|
||||
@@ -34,6 +34,7 @@
|
||||
partition@0 {
|
||||
label = "firmware";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
+ compatible = "seama";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1,146 +0,0 @@
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Subject: [PATCH] Revert "spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance"
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This reverts commit 345309fa7c0c9206a5344d379b174499952d79d9.
|
||||
|
||||
BSPI reads became unstable starting with above commit. There are BSPI
|
||||
timeouts like this:
|
||||
[ 15.637809] bcm_iproc 18029200.spi: timeout waiting for BSPI
|
||||
(...)
|
||||
[ 15.997809] bcm_iproc 18029200.spi: timeout waiting for BSPI
|
||||
which cause filesystem stability problems.
|
||||
|
||||
Before above commit every time that bcm_qspi_bspi_lr_l2_isr() called
|
||||
bcm_qspi_bspi_lr_l2_isr() it was resulting in bspi_rf_msg_len becoming
|
||||
0.
|
||||
With that change it's not the case anymore which suggests there may be
|
||||
some bug around that code.
|
||||
|
||||
It has changed and the new behavior seems to be causing problems.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
---
|
||||
|
||||
--- a/drivers/spi/spi-bcm-qspi.c
|
||||
+++ b/drivers/spi/spi-bcm-qspi.c
|
||||
@@ -88,7 +88,7 @@
|
||||
#define BSPI_BPP_MODE_SELECT_MASK BIT(8)
|
||||
#define BSPI_BPP_ADDR_SELECT_MASK BIT(16)
|
||||
|
||||
-#define BSPI_READ_LENGTH 512
|
||||
+#define BSPI_READ_LENGTH 256
|
||||
|
||||
/* MSPI register offsets */
|
||||
#define MSPI_SPCR0_LSB 0x000
|
||||
@@ -806,7 +806,7 @@ static int bcm_qspi_bspi_flash_read(stru
|
||||
struct spi_flash_read_message *msg)
|
||||
{
|
||||
struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
|
||||
- u32 addr = 0, len, rdlen, len_words;
|
||||
+ u32 addr = 0, len, len_words;
|
||||
int ret = 0;
|
||||
unsigned long timeo = msecs_to_jiffies(100);
|
||||
struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
|
||||
@@ -819,7 +819,7 @@ static int bcm_qspi_bspi_flash_read(stru
|
||||
bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
|
||||
|
||||
/*
|
||||
- * when using flex mode we need to send
|
||||
+ * when using flex mode mode we need to send
|
||||
* the upper address byte to bspi
|
||||
*/
|
||||
if (bcm_qspi_bspi_ver_three(qspi) == false) {
|
||||
@@ -833,56 +833,47 @@ static int bcm_qspi_bspi_flash_read(stru
|
||||
else
|
||||
addr = msg->from & 0x00ffffff;
|
||||
|
||||
+ /* set BSPI RAF buffer max read length */
|
||||
+ len = msg->len;
|
||||
+ if (len > BSPI_READ_LENGTH)
|
||||
+ len = BSPI_READ_LENGTH;
|
||||
+
|
||||
if (bcm_qspi_bspi_ver_three(qspi) == true)
|
||||
addr = (addr + 0xc00000) & 0xffffff;
|
||||
|
||||
- /*
|
||||
- * read into the entire buffer by breaking the reads
|
||||
- * into RAF buffer read lengths
|
||||
- */
|
||||
- len = msg->len;
|
||||
+ reinit_completion(&qspi->bspi_done);
|
||||
+ bcm_qspi_enable_bspi(qspi);
|
||||
+ len_words = (len + 3) >> 2;
|
||||
+ qspi->bspi_rf_msg = msg;
|
||||
+ qspi->bspi_rf_msg_status = 0;
|
||||
qspi->bspi_rf_msg_idx = 0;
|
||||
+ qspi->bspi_rf_msg_len = len;
|
||||
+ dev_dbg(&qspi->pdev->dev, "bspi xfr addr 0x%x len 0x%x", addr, len);
|
||||
|
||||
- do {
|
||||
- if (len > BSPI_READ_LENGTH)
|
||||
- rdlen = BSPI_READ_LENGTH;
|
||||
- else
|
||||
- rdlen = len;
|
||||
-
|
||||
- reinit_completion(&qspi->bspi_done);
|
||||
- bcm_qspi_enable_bspi(qspi);
|
||||
- len_words = (rdlen + 3) >> 2;
|
||||
- qspi->bspi_rf_msg = msg;
|
||||
- qspi->bspi_rf_msg_status = 0;
|
||||
- qspi->bspi_rf_msg_len = rdlen;
|
||||
- dev_dbg(&qspi->pdev->dev,
|
||||
- "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
|
||||
- bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
|
||||
- bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
|
||||
- bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
|
||||
- if (qspi->soc_intc) {
|
||||
- /*
|
||||
- * clear soc MSPI and BSPI interrupts and enable
|
||||
- * BSPI interrupts.
|
||||
- */
|
||||
- soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
|
||||
- soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
|
||||
- }
|
||||
+ bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
|
||||
+ bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
|
||||
+ bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
|
||||
+
|
||||
+ if (qspi->soc_intc) {
|
||||
+ /*
|
||||
+ * clear soc MSPI and BSPI interrupts and enable
|
||||
+ * BSPI interrupts.
|
||||
+ */
|
||||
+ soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
|
||||
+ soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
|
||||
+ }
|
||||
|
||||
- /* Must flush previous writes before starting BSPI operation */
|
||||
- mb();
|
||||
- bcm_qspi_bspi_lr_start(qspi);
|
||||
- if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
|
||||
- dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
|
||||
- ret = -ETIMEDOUT;
|
||||
- break;
|
||||
- }
|
||||
+ /* Must flush previous writes before starting BSPI operation */
|
||||
+ mb();
|
||||
|
||||
- /* set msg return length */
|
||||
- msg->retlen += rdlen;
|
||||
- addr += rdlen;
|
||||
- len -= rdlen;
|
||||
- } while (len);
|
||||
+ bcm_qspi_bspi_lr_start(qspi);
|
||||
+ if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
|
||||
+ dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
|
||||
+ ret = -ETIMEDOUT;
|
||||
+ } else {
|
||||
+ /* set the return length for the caller */
|
||||
+ msg->retlen = len;
|
||||
+ }
|
||||
|
||||
return ret;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user