298977887/lede
1
0
Fork 0
mirror of https://github.com/coolsnowwolf/lede.git synced 2025-04-16 04:13:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

ipq806x: switch to kernel 5.10

Browse Source
This commit is contained in:
coolsnowwolf 2024-01-19 23:15:22 +08:00
parent b23965cfb7
commit 7515f84eae
129 changed files with 4934 additions and 12388 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/linux/ipq806x/Makefile
View File

@ -10,8 +10,7 @@ CPU_TYPE:=cortex-a15
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic
KERNEL_PATCHVER:=5.4
KERNEL_TESTING_PATCHVER:=5.4
KERNEL_PATCHVER:=5.10
KERNELNAME:=zImage Image dtbs
@ -22,7 +21,6 @@ DEFAULT_PACKAGES += \
kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \
kmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \
kmod-ath10k-ct wpad-openssl uboot-envtools \
kmod-shortcut-fe kmod-qca-nss-drv kmod-qca-nss-ecm-standard kmod-qca-nss-gmac kmod-qca-nss-drv-pppoe kmod-qca-mcs \
autocore-arm htop automount autosamba luci-app-adbyby-plus luci-app-ipsec-vpnd luci-app-unblockmusic luci-app-zerotier
autocore-arm automount autosamba htop
$(eval $(call BuildTarget))

7
target/linux/ipq806x/base-files/etc/board.d/01_leds
View File

@ -21,9 +21,10 @@ edgecore,ecw5410)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy1tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy0tpt"
;;
linksys,e8350-v1)
ucidef_set_led_wlan "wlan" "WLAN" "${boardname}:green:wifi" "phy0tpt"
;;
meraki,mr52)
ucidef_set_led_netdev "eth0" "eth0" "green:lan1" "eth0"
ucidef_set_led_netdev "eth1" "eth1" "green:lan2" "eth1"
;;
nec,wg2600hp)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy1tpt"
ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy0tpt"

28
target/linux/ipq806x/base-files/etc/board.d/02_network
View File

@ -11,13 +11,12 @@ board_config_update
board=$(board_name)
case "$board" in
arris,rac2v1a)
arris,tr4400-v2)
ucidef_set_interfaces_lan_wan "eth1" "eth2"
ucidef_add_switch "switch0" \
"1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "0u@eth0"
;;
askey,rt4230w-rev6 |\
askey,rt4230w-rev9.3 |\
asrock,g10 |\
nec,wg2600hp)
ucidef_add_switch "switch0" \
@ -25,7 +24,6 @@ nec,wg2600hp)
;;
buffalo,wxr-2533dhp |\
compex,wpq864 |\
linksys,e8350-v1 |\
netgear,d7800 |\
netgear,r7500 |\
netgear,r7500v2 |\
@ -36,14 +34,6 @@ surf,g-nat200)
;;
edgecore,ecw5410)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
if [ -b "$(find_mtd_part 0:art)" ]; then
ucidef_set_interface_macaddr "lan" "$(mtd_get_mac_binary "0:art" 0x6)"
ucidef_set_interface_macaddr "wan" "$(mtd_get_mac_binary "0:art" 0x0)"
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
ucidef_set_interface_macaddr "lan" "$(mtd_get_mac_binary "0:ART" 0x6)"
ucidef_set_interface_macaddr "wan" "$(mtd_get_mac_binary "0:ART" 0x0)"
fi
;;
linksys,ea7500-v1)
hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
@ -59,6 +49,12 @@ linksys,ea8500)
ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
;;
meraki,mr42)
ucidef_set_interface_lan "eth0"
;;
meraki,mr52)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
nec,wg2600hp3)
ucidef_add_switch "switch0" \
"2:lan" "3:lan" "4:lan" "5:lan" "0@eth1" "1:wan" "6@eth0"
@ -70,13 +66,6 @@ tplink,vr2600v)
ucidef_add_switch "switch0" \
"1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0"
;;
norton,core-518)
hw_mac_addr=$(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr)
ucidef_add_switch "switch0" \
"2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0"
ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 1)"
;;
qcom,ipq8064-ap161)
ucidef_set_interface_lan "eth1 eth2"
ucidef_add_switch "switch0" \
@ -103,9 +92,6 @@ ubnt,unifi-ac-hd)
;;
zyxel,nbg6817)
hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr)
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
[ -n "$hw_mac_addr" ] || \
hw_mac_addr=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
ucidef_add_switch "switch0" \
"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)"

143
target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -9,6 +9,10 @@ board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:01:00.0.bin")
case "$board" in
meraki,mr52)
CI_UBIPART=art
caldata_extract_ubi "ART" 0x1000 0x844
;;
ruijie,rg-mtfi-m520)
caldata_extract "ART" 0x1000 0x844
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii PRODUCTINFO ethaddr) 2)
@ -25,149 +29,70 @@ case "$FIRMWARE" in
;;
"ath10k/pre-cal-pci-0000:01:00.0.bin")
case $board in
arris,rac2v1a)
caldata_extract "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary fw_env 0x12)
;;
askey,rt4230w-rev6 |\
askey,rt4230w-rev9.3)
askey,rt4230w-rev6)
caldata_extract "0:ART" 0x1000 0x2f20
;;
asrock,g10)
if [ -b "$(find_mtd_part 0:art)" ]; then
caldata_extract "0:art" 0x1000 0x2f20
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
caldata_extract "0:ART" 0x1000 0x2f20
fi
;;
buffalo,wxr-2533dhp)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary ART 0x1e)
;;
edgecore,ecw5410)
if [ -b "$(find_mtd_part 0:art)" ]; then
caldata_extract "0:art" 0x1000 0x2f20
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
caldata_extract "0:ART" 0x1000 0x2f20
fi
caldata_extract "0:art" 0x1000 0x2f20
;;
linksys,ea7500-v1 |\
linksys,ea8500)
caldata_extract "art" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 1)
;;
nec,wg2600hp |\
nec,wg2600hp3)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary PRODUCTDATA 0x12)
;;
netgear,d7800 |\
netgear,r7500v2 |\
netgear,r7800 |\
netgear,xr500)
caldata_extract "art" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x6) 1)
;;
norton,core-518)
caldata_extract_mmc "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 2)
;;
tplink,ad7200 |\
tplink,c2600)
caldata_extract "radio" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 0x8) -1)
;;
tplink,vr2600v)
caldata_extract "ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary default-mac 0x0) -1)
meraki,mr42)
CI_UBIPART=art
caldata_extract_ubi "ART" 0x1000 0x2f20
;;
zyxel,nbg6817)
if [ -b "$(find_mtd_part 0:art)" ]; then
caldata_extract "0:art" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:appsblenv ethaddr) 1)
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
caldata_extract "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV ethaddr) 1)
fi
caldata_extract "0:art" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:appsblenv ethaddr) 1)
;;
esac
;;
"ath10k/pre-cal-pci-0001:01:00.0.bin")
case $board in
arris,rac2v1a)
caldata_extract "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary fw_env 0xc)
;;
askey,rt4230w-rev6 |\
askey,rt4230w-rev9.3)
askey,rt4230w-rev6)
caldata_extract "0:ART" 0x5000 0x2f20
;;
asrock,g10)
if [ -b "$(find_mtd_part 0:art)" ]; then
caldata_extract "0:art" 0x5000 0x2f20
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
caldata_extract "0:ART" 0x5000 0x2f20
fi
caldata_extract "0:art" 0x5000 0x2f20
;;
buffalo,wxr-2533dhp)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary ART 0x18)
edgecore,ecw5410)
caldata_extract "0:art" 0x1000 0x2f20
;;
linksys,ea7500-v1 |\
linksys,ea8500)
caldata_extract "art" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 2)
;;
nec,wg2600hp |\
nec,wg2600hp3)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary PRODUCTDATA 0xc)
;;
netgear,d7800 |\
netgear,r7500v2 |\
netgear,r7800 |\
netgear,xr500)
caldata_extract "art" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x6) 2)
;;
norton,core-518)
caldata_extract_mmc "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 3)
;;
tplink,ad7200 |\
tplink,c2600)
caldata_extract "radio" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary default-mac 0x8)
;;
tplink,vr2600v)
caldata_extract "ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_binary default-mac 0x0)
meraki,mr42 |\
meraki,mr52)
CI_UBIPART=art
caldata_extract_ubi "ART" 0x5000 0x2f20
;;
zyxel,nbg6817)
if [ -b "$(find_mtd_part 0:art)" ]; then
caldata_extract "0:art" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii 0:appsblenv ethaddr)
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
caldata_extract "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii 0:APPSBLENV ethaddr)
fi
caldata_extract "0:art" 0x5000 0x2f20
ath10k_patch_mac $(mtd_get_mac_ascii 0:appsblenv ethaddr)
;;
esac
;;
"ath10k/cal-pci-0002:01:00.0.bin")
case "$board" in
meraki,mr42)
CI_UBIPART=art
caldata_extract_ubi "ART" 0x9000 0x844
;;
esac
;;
"ath10k/pre-cal-pci-0002:01:00.0.bin")
case $board in
edgecore,ecw5410)
if [ -b "$(find_mtd_part 0:art)" ]; then
caldata_extract "0:art" 0x5000 0x2f20
else
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
caldata_extract "0:ART" 0x5000 0x2f20
fi
caldata_extract "0:art" 0x5000 0x2f20
;;
meraki,mr52)
CI_UBIPART=art
caldata_extract_ubi "ART" 0x9000 0x2f20
;;
esac
;;

25
target/linux/ipq806x/base-files/etc/init.d/bootcount
View File

@ -16,30 +16,5 @@ boot() {
linksys,ea8500)
mtd resetbc s_env || true
;;
norton,core-518)
. /lib/functions/caldata.sh
FIRMWARE='ath10k/pre-cal-pci-0000:01:00.0.bin'
[ -e /lib/firmware/$FIRMWARE ] || {
caldata_extract_mmc "0:ART" 0x1000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 2)
}
FIRMWARE='ath10k/pre-cal-pci-0001:01:00.0.bin'
[ -e /lib/firmware/$FIRMWARE ] || {
caldata_extract_mmc "0:ART" 0x5000 0x2f20
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii_mmc 0:APPSBLENV ethaddr) 3)
}
[ -e /etc/config/wireless ] || {
/sbin/wifi config
/sbin/wifi up
}
[ -s /etc/config/wireless ] || {
rm /etc/config/wireless
/sbin/wifi config
/sbin/wifi up
}
;;
esac
}

8
target/linux/ipq806x/base-files/etc/init.d/cpu_freq
View File

@ -9,13 +9,9 @@ boot() {
if [ "$governor" = "ondemand" ]; then
# Effective only with ondemand
echo 600000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq
echo 600000 > /sys/devices/system/cpu/cpufreq/policy1/scaling_min_freq
echo 10 > /sys/devices/system/cpu/cpufreq/ondemand/sampling_down_factor
echo 50 > /sys/devices/system/cpu/cpufreq/ondemand/up_threshold
fi
echo 1000000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq
echo 1000000 > /sys/devices/system/cpu/cpu1/cpufreq/scaling_min_freq
sysctl -w vm.min_free_kbytes=65536
sysctl -w net.netfilter.nf_conntrack_max=65535
}

11
target/linux/ipq806x/base-files/etc/uci-defaults/05_fix-compat-version Normal file
View File

@ -0,0 +1,11 @@
. /lib/functions.sh
case "$(board_name)" in
linksys,ea7500-v1|\
linksys,ea8500)
uci set system.@system[0].compat_version="2.0"
uci commit system
;;
esac
exit 0

2
target/linux/ipq806x/base-files/lib/upgrade/asrock.sh
View File

@ -2,8 +2,6 @@
asrock_bootconfig_mangle() {
local mtdnum="$(find_mtd_index 0:bootconfig)"
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
[ -n "$mtdnum" ] || mtdnum="$(find_mtd_index 0:BOOTCONFIG)"
if [ -z "$mtdnum" ]; then
echo "cannot find bootconfig mtd partition"

20
target/linux/ipq806x/base-files/lib/upgrade/linksys.sh
View File

@ -9,7 +9,7 @@ linksys_get_target_firmware() {
cur_boot_part=$(/usr/sbin/fw_printenv -n boot_part)
if [ -z "${cur_boot_part}" ] ; then
mtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)
case $(egrep ^mtd${mtd_ubi0}: /proc/mtd | cut -d '"' -f 2) in
case $(grep -E ^mtd${mtd_ubi0}: /proc/mtd | cut -d '"' -f 2) in
kernel1|rootfs1)
cur_boot_part=1
;;
@ -44,10 +44,6 @@ linksys_get_target_firmware() {
esac
}
linksys_get_root_magic() {
(get_image "$@" | dd skip=786432 bs=4 count=1 | hexdump -v -n 4 -e '1/1 "%02x"') 2>/dev/null
}
platform_do_upgrade_linksys() {
local magic_long="$(get_magic_long "$1")"
@ -101,18 +97,6 @@ platform_do_upgrade_linksys() {
nand_upgrade_tar "$1"
}
[ "$magic_long" = "27051956" ] && {
# check firmwares' rootfs types
local oldroot="$(linksys_get_root_magic $target_mtd)"
local newroot="$(linksys_get_root_magic "$1")"
if [ "$newroot" = "55424923" -a "$oldroot" = "55424923" ]
# we're upgrading from a firmware with UBI to one with UBI
then
# erase everything to be safe
mtd erase $part_label
get_image "$1" | mtd -n write - $part_label
else
get_image "$1" | mtd write - $part_label
fi
get_image "$1" | mtd write - $part_label
}
}

110
target/linux/ipq806x/base-files/lib/upgrade/norton.sh
View File

@ -1,110 +0,0 @@
#
# Copyright (C) 2016 lede-project.org
#
norton_get_rootfs() {
local rootfsdev
if read cmdline < /proc/cmdline; then
case "$cmdline" in
*root=*)
rootfsdev="${cmdline##*root=}"
rootfsdev="${rootfsdev%% *}"
;;
esac
echo "${rootfsdev}"
fi
}
norton_do_flash() {
local tar_file=$1
local kernel=$2
local rootfs=$3
# keep sure its unbound
losetup --detach-all || {
echo Failed to detach all loop devices. Skip this try.
reboot -f
}
# use the first found directory in the tar archive
local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
echo "flashing kernel to $kernel"
mkdir /tmp/upgrade
dd if=/dev/zero bs=40 count=1 > /tmp/upgrade/pad40
tar xf $tar_file ${board_dir}/kernel -C /tmp/upgrade/
cat /tmp/upgrade/pad40 /tmp/upgrade/${board_dir}/kernel > $kernel
echo "flashing rootfs to ${rootfs}"
tar xf $tar_file ${board_dir}/root -O > $rootfs
# a padded rootfs is needed for overlay fs creation
local offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)
[ $offset -lt 65536 ] && {
echo Wrong size for rootfs: $offset
sleep 10
reboot -f
}
[ -e /tmp/sysupgrade.tgz ] || {
echo "formating rootfs_data /dev/mmcblk0p25"
mkfs.ext4 -F -L rootfs_data /dev/mmcblk0p25
}
# flashing successful
case "$rootfs" in
"/dev/mmcblk0p10")
;;
"/dev/mmcblk0p21")
;;
esac
# Cleanup
losetup -d $loopdev >/dev/null 2>&1
sync
umount -a
reboot -f
}
norton_do_upgrade() {
local tar_file="$1"
local board=$(board_name)
local rootfs="$(norton_get_rootfs)"
local kernel=
[ -b "${rootfs}" ] || return 1
case "$board" in
norton,core-518)
case "$rootfs" in
"/dev/mmcblk0p10")
# booted from the primary partition set
# write to the alternative set
kernel="/dev/mmcblk0p9"
rootfs="/dev/mmcblk0p10"
;;
"/dev/mmcblk0p21")
# booted from the alternative partition set
# write to the primary set
kernel="/dev/mmcblk0p20"
rootfs="/dev/mmcblk0p21"
;;
*)
return 1
;;
esac
;;
*)
return 1
;;
esac
norton_do_flash $tar_file $kernel $rootfs
nand_do_upgrade "$1"
return 0
}

24
target/linux/ipq806x/base-files/lib/upgrade/platform.sh
View File

@ -1,7 +1,7 @@
PART_NAME=firmware
REQUIRE_IMAGE_METADATA=1
RAMFS_COPY_BIN='fw_printenv fw_setenv fwtool'
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_check_image() {
@ -10,9 +10,8 @@ platform_check_image() {
platform_do_upgrade() {
case "$(board_name)" in
arris,rac2v1a |\
arris,tr4400-v2 |\
askey,rt4230w-rev6 |\
askey,rt4230w-rev9.3 |\
compex,wpq864 |\
netgear,d7800 |\
netgear,r7500 |\
@ -23,10 +22,6 @@ platform_do_upgrade() {
qcom,ipq8064-ap161)
nand_do_upgrade "$1"
;;
linksys,e8350-v1)
fwtool -q -t -i /dev/null "$1"
nand_do_upgrade "$1"
;;
asrock,g10)
asrock_upgrade_prepare
nand_do_upgrade "$1"
@ -51,6 +46,14 @@ platform_do_upgrade() {
linksys,ea8500)
platform_do_upgrade_linksys "$1"
;;
meraki,mr42 |\
meraki,mr52)
CI_KERNPART="bootkernel2"
nand_do_upgrade "$1"
;;
ruijie,rg-mtfi-m520)
ruijie_do_upgrade "$1"
;;
tplink,ad7200 |\
tplink,c2600)
PART_NAME="os-image:rootfs"
@ -58,16 +61,9 @@ platform_do_upgrade() {
default_do_upgrade "$1"
;;
tplink,vr2600v)
PART_NAME="kernel:rootfs"
MTD_CONFIG_ARGS="-s 0x200000"
default_do_upgrade "$1"
;;
norton,core-518)
norton_do_upgrade "$1"
;;
ruijie,rg-mtfi-m520)
ruijie_do_upgrade "$1"
;;
zyxel,nbg6817)
zyxel_do_upgrade "$1"
;;

3
target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh
View File

@ -91,9 +91,6 @@ zyxel_do_upgrade() {
case "$board" in
zyxel,nbg6817)
local dualflagmtd="$(find_mtd_part 0:dual_flag)"
# XXX: drop upper case after kernel v5.4 is gone (qcom-smem)
[ -b $dualflagmtd ] || \
dualflagmtd="$(find_mtd_part 0:DUAL_FLAG)"
[ -b $dualflagmtd ] || return 1
case "$rootfs" in

86
target/linux/ipq806x/config-5.4 → target/linux/ipq806x/config-5.10
View File

@ -3,8 +3,8 @@ CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR8216_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# CONFIG_ARCH_IPQ40XX is not set
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
@ -18,6 +18,8 @@ CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
@ -41,7 +43,7 @@ CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
CONFIG_ARM_QCOM_CPUFREQ_KRAIT=y
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_ARM_QCOM_CPUIDLE=y
CONFIG_ARM_QCOM_SPM_CPUIDLE=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
@ -70,8 +72,8 @@ CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
@ -97,25 +99,19 @@ CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLAKE2S=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA256=y
@ -123,9 +119,16 @@ CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
@ -146,6 +149,7 @@ CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
@ -163,10 +167,9 @@ CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GRO_CELLS=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
@ -176,7 +179,7 @@ CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HIGHPTE=y
CONFIG_HWMON=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
@ -186,26 +189,29 @@ CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
# CONFIG_IPQ_APSS_PLL is not set
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_6018 is not set
CONFIG_IPQ_GCC_806X=y
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_KPSS_XCC=y
CONFIG_KRAITCC=y
CONFIG_KRAIT_CLOCKS=y
CONFIG_KRAIT_L2_ACCESSORS=y
CONFIG_LEDS_TRIGGER_DISK=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
@ -214,11 +220,13 @@ CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ8064=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_QCOM_RPM=y
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
@ -228,6 +236,7 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_CQHCI=y
CONFIG_MMC_QCOM_DML=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
@ -237,18 +246,22 @@ CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MSM_GCC_8660=y
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_IOMMU is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOMSMEM_PARTS=y
@ -277,7 +290,7 @@ CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
# CONFIG_NVME_TCP is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
@ -304,28 +317,35 @@ CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCS_XPCS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLINK=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
CONFIG_PHY_QCOM_IPQ806X_SATA=y
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_UFS is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
# CONFIG_PINCTRL_IPQ4019 is not set
# CONFIG_PINCTRL_IPQ6018 is not set
CONFIG_PINCTRL_IPQ8064=y
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
@ -336,6 +356,9 @@ CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_DEVFREQ=y
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
@ -348,19 +371,20 @@ CONFIG_QCOM_ADM=y
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_CLK_RPM=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
CONFIG_QCOM_GSBI=y
CONFIG_QCOM_HFPLL=y
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_PM=y
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
CONFIG_QCOM_RPMCC=y
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
CONFIG_QCOM_SCM_32=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
@ -369,22 +393,19 @@ CONFIG_QCOM_TCSR=y
CONFIG_QCOM_TSENS=y
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
# CONFIG_QRTR is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_REFCOUNT_FULL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_NSS_VOLT=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_REGULATOR_QCOM_RPM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
@ -394,6 +415,12 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
@ -409,12 +436,18 @@ CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
@ -438,6 +471,7 @@ CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"

45
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts
View File

@ -317,6 +317,17 @@
label = "ART";
reg = <0x02e0000 0x0040000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@320000 {
@ -359,6 +370,9 @@
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
@ -379,6 +393,9 @@
ieee80211-freq-limit = <2400000 2483000>;
qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
@ -416,7 +433,8 @@
phy-mode = "rgmii";
qcom,id = <1>;
mdiobus = <&mdio0>;
mtd-mac-address = <&factory 0x0>;
nvmem-cells = <&macaddr_factory_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -429,10 +447,33 @@
phy-mode = "sgmii";
qcom,id = <2>;
mdiobus = <&mdio0>;
mtd-mac-address = <&factory 0x6>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&factory {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_factory_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_PRODUCTDATA_c: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_PRODUCTDATA_12: macaddr@12 {
reg = <0x12 0x6>;
};
};

47
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi
View File

@ -45,32 +45,35 @@
/delete-node/opp-1200000000;
/delete-node/opp-1400000000;
/*
* Voltage thresholds are <target min max>
*/
opp-384000000 {
opp-microvolt-speed0-pvs0-v0 = <902500 950000 997500>;
opp-microvolt-speed0-pvs1-v0 = <855000 900000 945000>;
opp-microvolt-speed0-pvs2-v0 = <807500 850000 892500>;
opp-microvolt-speed0-pvs3-v0 = <760000 800000 840000>;
opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>;
opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>;
opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>;
};
opp-600000000 {
opp-microvolt-speed0-pvs0-v0 = <950000 1000000 1050000>;
opp-microvolt-speed0-pvs1-v0 = <945000 950000 955000>;
opp-microvolt-speed0-pvs2-v0 = <895000 900000 905000>;
opp-microvolt-speed0-pvs3-v0 = <845000 850000 855000>;
opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>;
opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>;
};
opp-800000000 {
opp-microvolt-speed0-pvs0-v0 = <997500 1050000 1102500>;
opp-microvolt-speed0-pvs1-v0 = < 995000 1000000 1005000>;
opp-microvolt-speed0-pvs2-v0 = < 945000 950000 955000>;
opp-microvolt-speed0-pvs3-v0 = < 895000 900000 905000>;
opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>;
opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>;
};
opp-1000000000 {
opp-microvolt-speed0-pvs0-v0 = <1045000 1100000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <997500 1050000 1102500>;
opp-microvolt-speed0-pvs2-v0 = < 995000 1000000 1005000>;
opp-microvolt-speed0-pvs3-v0 = < 945000 950000 955000>;
opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>;
};
};
@ -93,15 +96,3 @@
&smb208_s2b {
regulator-max-microvolt = <1150000>;
};
&nss0 {
qcom,low-frequency = <550000000>; /* orig value 110000000 */
qcom,mid-frequency = <550000000>; /* orig value 275000000 */
qcom,max-frequency = <550000000>;
};
&nss1 {
qcom,low-frequency = <550000000>; /* orig value 110000000 */
qcom,mid-frequency = <550000000>; /* orig value 275000000 */
qcom,max-frequency = <550000000>;
};

342
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi
View File

@ -82,152 +82,169 @@
spi-max-frequency = <50000000>;
reg = <0>;
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x40000 0x20000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
partition@60000 {
label = "SBL3";
reg = <0x60000 0x30000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x40000 0x20000>;
read-only;
};
partition@90000 {
label = "DDRCONFIG";
reg = <0x90000 0x10000>;
read-only;
};
partition@60000 {
label = "SBL3";
reg = <0x60000 0x30000>;
read-only;
};
partition@a0000 {
label = "SSD";
reg = <0xa0000 0x10000>;
read-only;
};
partition@90000 {
label = "DDRCONFIG";
reg = <0x90000 0x10000>;
read-only;
};
partition@b0000 {
label = "TZ";
reg = <0xb0000 0x30000>;
read-only;
};
partition@a0000 {
label = "SSD";
reg = <0xa0000 0x10000>;
read-only;
};
partition@e0000 {
label = "RPM";
reg = <0xe0000 0x20000>;
read-only;
};
partition@b0000 {
label = "TZ";
reg = <0xb0000 0x30000>;
read-only;
};
partition@100000 {
label = "fs-uboot";
reg = <0x100000 0x70000>;
read-only;
};
partition@e0000 {
label = "RPM";
reg = <0xe0000 0x20000>;
read-only;
};
partition@170000 {
label = "uboot-env";
reg = <0x170000 0x40000>;
read-only;
};
partition@100000 {
label = "fs-uboot";
reg = <0x100000 0x70000>;
read-only;
};
partition@1b0000 {
label = "radio";
reg = <0x1b0000 0x40000>;
read-only;
};
partition@170000 {
label = "uboot-env";
reg = <0x170000 0x40000>;
read-only;
};
partition@1f0000 {
label = "os-image";
reg = <0x1f0000 0x400000>;
};
partition@1b0000 {
label = "radio";
reg = <0x1b0000 0x40000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
partition@5f0000 {
label = "rootfs";
reg = <0x5f0000 0x1900000>;
};
precal_radio_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
defaultmac: partition@1ef0000 {
label = "default-mac";
reg = <0x1ef0000 0x00200>;
read-only;
};
precal_radio_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@1ef0200 {
label = "pin";
reg = <0x1ef0200 0x00200>;
read-only;
};
partition@1f0000 {
label = "os-image";
reg = <0x1f0000 0x400000>;
};
partition@1ef0400 {
label = "product-info";
reg = <0x1ef0400 0x0fc00>;
read-only;
};
partition@5f0000 {
label = "rootfs";
reg = <0x5f0000 0x1900000>;
};
partition@1f00000 {
label = "partition-table";
reg = <0x1f00000 0x10000>;
read-only;
};
defaultmac: partition@1ef0000 {
label = "default-mac";
reg = <0x1ef0000 0x00200>;
read-only;
};
partition@1f10000 {
label = "soft-version";
reg = <0x1f10000 0x10000>;
read-only;
};
partition@1ef0200 {
label = "pin";
reg = <0x1ef0200 0x00200>;
read-only;
};
partition@1f20000 {
label = "support-list";
reg = <0x1f20000 0x10000>;
read-only;
};
partition@1ef0400 {
label = "product-info";
reg = <0x1ef0400 0x0fc00>;
read-only;
};
partition@1f30000 {
label = "profile";
reg = <0x1f30000 0x10000>;
read-only;
};
partition@1f00000 {
label = "partition-table";
reg = <0x1f00000 0x10000>;
read-only;
};
partition@1f40000 {
label = "default-config";
reg = <0x1f40000 0x10000>;
read-only;
};
partition@1f10000 {
label = "soft-version";
reg = <0x1f10000 0x10000>;
read-only;
};
partition@1f50000 {
label = "user-config";
reg = <0x1f50000 0x40000>;
read-only;
};
partition@1f20000 {
label = "support-list";
reg = <0x1f20000 0x10000>;
read-only;
};
partition@1f90000 {
label = "qos-db";
reg = <0x1f90000 0x40000>;
read-only;
};
partition@1f30000 {
label = "profile";
reg = <0x1f30000 0x10000>;
read-only;
};
partition@1fd0000 {
label = "usb-config";
reg = <0x1fd0000 0x10000>;
read-only;
};
partition@1f40000 {
label = "default-config";
reg = <0x1f40000 0x10000>;
read-only;
};
partition@1fe0000 {
label = "log";
reg = <0x1fe0000 0x20000>;
read-only;
partition@1f50000 {
label = "user-config";
reg = <0x1f50000 0x40000>;
read-only;
};
partition@1f90000 {
label = "qos-db";
reg = <0x1f90000 0x40000>;
read-only;
};
partition@1fd0000 {
label = "usb-config";
reg = <0x1fd0000 0x10000>;
read-only;
};
partition@1fe0000 {
label = "log";
reg = <0x1fe0000 0x20000>;
read-only;
};
};
};
};
@ -249,11 +266,42 @@
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(-1)>;
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&mdio0 {
@ -282,29 +330,16 @@
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&defaultmac 0x8>;
mtd-mac-address-increment = <1>;
nvmem-cells = <&macaddr_defaultmac_8>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
fixed-link {
speed = <1000>;
full-duplex;
@ -313,24 +348,11 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&defaultmac 0x8>;
nvmem-cells = <&macaddr_defaultmac_8>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -341,3 +363,13 @@
&adm_dma {
status = "okay";
};
&defaultmac {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_defaultmac_8: macaddr@8 {
reg = <0x8 0x6>;
};
};

101
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
View File

@ -11,6 +11,13 @@
device_type = "memory";
};
reserved-memory {
rsvd@5fe00000 {
reg = <0x5fe00000 0x200000>;
reusable;
};
};
aliases {
mdio-gpio0 = &mdio0;
@ -175,6 +182,22 @@
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(1)>;
};
};
};
&pcie1 {
@ -183,6 +206,29 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(2)>;
};
};
};
&pcie2 {
status = "okay";
reset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};
&nand_controller {
@ -228,10 +274,29 @@
read-only;
};
art: art@1200000 {
art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
artbak: art@1340000 {
@ -285,27 +350,14 @@
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&art 6>;
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -315,24 +367,11 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&art 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;

279
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-e8350-v1.dts
View File

@ -1,279 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Linksys E8350 V1 WiFi Router";
compatible = "linksys,e8350-v1", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
serial0 = &gsbi4_serial;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
wifi {
label = "wifi";
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
nand-controller@1ac00000 {
compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
<&gcc EBI2_AON_CLK>;
clock-names = "core", "aon";
dmas = <&adm_dma 3>;
dma-names = "rxtx";
qcom,cmd-crci = <15>;
qcom,data-crci = <3>;
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
partition@0 {
label = "ubi";
reg = <0 0x4000000>;
};
partition@4000000 {
label = "extra";
reg = <0x4000000 0x4000000>;
};
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power: power {
label = "e8350-v1:green:power";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wps {
label = "e8350-v1:green:wps";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
wifi {
label = "e8350-v1:green:wifi";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio68","gpio65", "gpio67";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio26","gpio53", "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&gsbi4 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi5: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <51200000>;
reg = <0>;
partitions {
compatible = "qcom,smem";
};
};
};
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&usb3_0 {
clocks = <&gcc USB30_1_MASTER_CLK>;
status = "okay";
};
&usb3_1 {
clocks = <&gcc USB30_0_MASTER_CLK>;
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pcie2 {
status = "okay";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x00010 0x2613a0 /* PWS_REG */
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <0>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&tcsr {
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
compatible = "qcom,tcsr";
};
&adm_dma {
status = "okay";
};

44
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi
View File

@ -133,12 +133,12 @@
partition@f80000 {
label = "kernel1";
reg = <0x0f80000 0x2800000>; /* 3 MB spill to rootfs */
reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
};
partition@1280000 {
partition@1380000 {
label = "rootfs1";
reg = <0x1280000 0x2500000>;
reg = <0x1380000 0x2400000>;
};
partition@3780000 {
@ -146,9 +146,9 @@
reg = <0x3780000 0x2800000>;
};
partition@3a80000 {
partition@3b80000 {
label = "rootfs2";
reg = <0x3a80000 0x2500000>;
reg = <0x3b80000 0x2400000>;
};
};
};
@ -173,30 +173,13 @@
0x00094 0x4e /* PORT6_STATUS */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <0>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
@ -209,22 +192,9 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;

34
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g-nat200.dts
View File

@ -236,30 +236,13 @@
0x00094 0x4e /* PORT6_STATUS */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
@ -274,22 +257,9 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&ART 0xc>;

67
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts
View File

@ -122,26 +122,13 @@
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
qcom,id = <1>;
fixed-link {
speed = <1000>;
full-duplex;
@ -150,22 +137,9 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>;
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
@ -196,10 +170,6 @@
0x00094 0x4e /* PORT6_STATUS */
>;
};
ethernet-phy@4 {
reg = <4>;
};
};
&nand_controller {
@ -216,6 +186,9 @@
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x1200000>;
partitions {
compatible = "qcom,smem-part";
};
@ -224,10 +197,36 @@
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi5g: wifi@1,0 {
reg = <0x00010000 0 0 0 0>;
compatible = "qcom,ath10k";
qcom,ath10k-calibration-variant = "ASRock-G10";
};
};
};
&pcie1 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2g: wifi@1,0 {
reg = <0x00010000 0 0 0 0>;
compatible = "qcom,ath10k";
qcom,ath10k-calibration-variant = "ASRock-G10";
};
};
};
&qcom_pinmux {

67
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
View File

@ -1,4 +1,4 @@
#include "qcom-ipq8064-v2.0.dtsi"
#include "qcom-ipq8064-v1.0.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
@ -148,12 +148,10 @@
};
&usb3_0 {
clocks = <&gcc USB30_1_MASTER_CLK>;
status = "okay";
};
&usb3_1 {
clocks = <&gcc USB30_0_MASTER_CLK>;
status = "okay";
};
@ -219,9 +217,20 @@
ubi@1740000 {
label = "ubi";
reg = <0x1740000 0x68C0000>;
reg = <0x1740000 0x1600000>;
};
netgear@2d40000 {
label = "netgear";
reg = <0x2d40000 0x0c00000>;
read-only;
};
reserve@3940000 {
label = "reserve";
reg = <0x3940000 0x46c0000>;
read-only;
};
};
};
};
@ -252,27 +261,14 @@
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&art 6>;
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -282,24 +278,11 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&art 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -315,3 +298,17 @@
&adm_dma {
status = "okay";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

87
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
View File

@ -186,6 +186,22 @@
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(1)>;
};
};
};
&pcie1 {
@ -194,6 +210,22 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(2)>;
};
};
};
&nand_controller {
@ -236,10 +268,29 @@
read-only;
};
art: art@1200000 {
art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
artbak: art@1340000 {
@ -293,27 +344,14 @@
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&art 6>;
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -323,24 +361,11 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&art 0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;

34
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-rg-mtfi-m520.dts
View File

@ -264,6 +264,7 @@
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
@ -276,29 +277,13 @@
0x00094 0x4e /* PORT6_STATUS */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <0>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
@ -311,22 +296,9 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;

20
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts
View File

@ -250,7 +250,8 @@
phy-mode = "sgmii";
qcom,id = <1>;
mtd-mac-address = <&eeprom 0x6>;
nvmem-cells = <&macaddr_eeprom_6>;
nvmem-cell-names = "mac-address";
};
&gmac2 {
@ -261,7 +262,8 @@
phy-mode = "sgmii";
qcom,id = <2>;
mtd-mac-address = <&eeprom 0x0>;
nvmem-cells = <&macaddr_eeprom_0>;
nvmem-cell-names = "mac-address";
};
&pcie0 {
@ -299,3 +301,17 @@
&usb3_1 {
status = "okay";
};
&eeprom {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_eeprom_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_eeprom_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

210
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
View File

@ -176,99 +176,124 @@
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
W25Q128@0 {
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
MIBIB@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
SBL2@40000 {
label = "SBL2";
reg = <0x40000 0x40000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
SBL3@80000 {
label = "SBL3";
reg = <0x80000 0x80000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x40000 0x40000>;
read-only;
};
DDRCONFIG@100000 {
label = "DDRCONFIG";
reg = <0x100000 0x10000>;
read-only;
};
partition@80000 {
label = "SBL3";
reg = <0x80000 0x80000>;
read-only;
};
SSD@110000 {
label = "SSD";
reg = <0x110000 0x10000>;
read-only;
};
partition@100000 {
label = "DDRCONFIG";
reg = <0x100000 0x10000>;
read-only;
};
TZ@120000 {
label = "TZ";
reg = <0x120000 0x80000>;
read-only;
};
partition@110000 {
label = "SSD";
reg = <0x110000 0x10000>;
read-only;
};
RPM@1a0000 {
label = "RPM";
reg = <0x1a0000 0x80000>;
read-only;
};
partition@120000 {
label = "TZ";
reg = <0x120000 0x80000>;
read-only;
};
APPSBL@220000 {
label = "APPSBL";
reg = <0x220000 0x80000>;
read-only;
};
partition@1a0000 {
label = "RPM";
reg = <0x1a0000 0x80000>;
read-only;
};
APPSBLENV@2a0000 {
label = "APPSBLENV";
reg = <0x2a0000 0x40000>;
read-only;
};
partition@220000 {
label = "APPSBL";
reg = <0x220000 0x80000>;
read-only;
};
OLDART@2e0000 {
label = "OLDART";
reg = <0x2e0000 0x40000>;
read-only;
};
partition@2a0000 {
label = "APPSBLENV";
reg = <0x2a0000 0x40000>;
read-only;
};
kernel@320000 {
label = "kernel";
reg = <0x320000 0x300000>;
};
partition@2e0000 {
label = "OLDART";
reg = <0x2e0000 0x40000>;
read-only;
};
rootfs@620000 {
label = "rootfs";
reg = <0x620000 0x960000>;
};
partition@320000 {
label = "firmware";
reg = <0x320000 0xc60000>;
compatible = "openwrt,uimage";
openwrt,offset = <512>; /* account for pad-extra 512 */
};
defaultmac: default-mac@0xfaf100 {
label = "default-mac";
reg = <0xfaf100 0x00200>;
read-only;
};
/* hole 0xf80000 - 0xfaf100 */
ART@fc0000 {
label = "ART";
reg = <0xfc0000 0x40000>;
read-only;
partition@faf100 {
label = "default-mac";
reg = <0xfaf100 0x00200>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_defaultmac_0: macaddr@0 {
reg = <0x0 0x6>;
};
};
partition@fc0000 {
label = "ART";
reg = <0xfc0000 0x40000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
};
};
@ -284,11 +309,42 @@
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(-1)>;
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&mdio0 {
@ -323,8 +379,9 @@
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&defaultmac 0>;
mtd-mac-address-increment = <1>;
nvmem-cells = <&macaddr_defaultmac_0>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
fixed-link {
speed = <1000>;
@ -337,7 +394,8 @@
phy-mode = "sgmii";
qcom,id = <2>;
mtd-mac-address = <&defaultmac 0>;
nvmem-cells = <&macaddr_defaultmac_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;

69
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
View File

@ -167,7 +167,8 @@
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&PRODUCTDATA 6>;
nvmem-cells = <&macaddr_PRODUCTDATA_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -181,7 +182,8 @@
phy-mode = "sgmii";
qcom,id = <2>;
mtd-mac-address = <&PRODUCTDATA 0>;
nvmem-cells = <&macaddr_PRODUCTDATA_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -281,6 +283,17 @@
label = "ART";
reg = <0x2e0000 0x40000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
TP@320000 {
@ -318,11 +331,41 @@
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&qcom_pinmux {
@ -380,3 +423,25 @@
};
};
};
&PRODUCTDATA {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_PRODUCTDATA_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_PRODUCTDATA_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_PRODUCTDATA_c: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_PRODUCTDATA_12: macaddr@12 {
reg = <0x12 0x6>;
};
};

68
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
View File

@ -229,7 +229,8 @@
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&ART 6>;
nvmem-cells = <&macaddr_ART_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -243,7 +244,8 @@
phy-mode = "sgmii";
qcom,id = <2>;
mtd-mac-address = <&ART 0>;
nvmem-cells = <&macaddr_ART_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -338,10 +340,38 @@
read-only;
};
ART: ART@180000 {
ART@180000 {
label = "ART";
reg = <0x180000 0x40000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_ART_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_ART_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_ART_18: macaddr@18 {
reg = <0x18 0x6>;
};
macaddr_ART_1e: macaddr@1e {
reg = <0x1e 0x6>;
};
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
BOOTCONFIG@1c0000 {
@ -393,11 +423,41 @@
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&qcom_pinmux {
@ -463,4 +523,4 @@
output-high;
};
};
};
};

462
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-core-518.dts
View File

@ -1,462 +0,0 @@
#include "qcom-ipq8065.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Norton Core 518";
compatible = "norton,core-518", "qcom,ipq8065", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x3e000000>;
device_type = "memory";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
aliases {
serial0 = &gsbi4_serial;
mdio-gpio0 = &mdio0;
sdcc1 = &sdcc1;
};
chosen {
bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd";
stdout-path = "serial0:115200n8";
append-rootblock = "root=/dev/mmcblk0p";
};
soc {
pinmux@800000 {
button_pins: button_pins {
mux {
pins = "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
hs_uart_pins: hs_uart_pins {
mux {
pins = "gpio6", "gpio7", "gpio8", "gpio9";
function = "gsbi7";
drive-strength = <0xc>;
bias-disable;
};
};
serial_pins: serial_pins {
mux {
pins = "gpio55", "gpio56";
function = "gsbi6";
drive-strength = <0xc>;
bias-disable;
};
};
i2c_pins: i2c_pins {
mux {
pins = "gpio57", "gpio58";
function = "gsbi6";
drive-strength = <0xc>;
bias-disable;
};
};
sdcc1_pins: sdcc1_pinmux {
mux {
pins = "gpio38", "gpio39", "gpio40",
"gpio41", "gpio42", "gpio43",
"gpio44", "gpio45", "gpio46",
"gpio47";
function = "sdc1";
};
cmd {
pins = "gpio45";
drive-strength = <10>;
bias-pull-up;
};
data {
pins = "gpio38", "gpio39", "gpio40",
"gpio41", "gpio43", "gpio44",
"gpio46", "gpio47";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio42";
drive-strength = <16>;
bias-disable;
};
};
mdio0_pins: mdio0_pins {
mux {
pins = "gpio0", "gpio1";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
mux {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
function = "rgmii2";
drive-strength = <8>;
bias-disable;
};
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
input-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
cs {
pins = "gpio20";
drive-strength = <12>;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio22", "gpio24";
function = "gpio";
drive-strength = <12>;
};
pwr {
pins = "gpio22";
bias-pull-down;
output-high;
};
ovc {
pins = "gpio24";
bias-pull-up;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio23", "gpio25";
function = "gpio";
drive-strength = <12>;
};
pwr {
pins = "gpio23";
bias-pull-down;
output-high;
};
ovc {
pins = "gpio25";
bias-pull-up;
};
};
};
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
serial@16340000 {
status = "okay";
};
/*
* The i2c device on gsbi4 should not be enabled.
* On ipq806x designs gsbi4 i2c is meant for exclusive
* RPM usage. Turning this on in kernel manifests as
* i2c failure for the RPM.
*/
};
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi4: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
flash: m25p80@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <51200000>;
reg = <0>;
partitions {
compatible = "qcom,smem";
};
};
};
};
// gsbi@16500000 {
// status = "okay";
// qcom,mode = < 0x06 >;
// i2c@16580000 {
// status = "okay";
// ncp5623@38 {
// compatible = "ncp5623";
// reg = < 0x38 >;
// white {
// label = "white";
// led_group = < 0x05 >;
// linux,default-trigger = "timer";
// };
// amber {
// label = "amber";
// led_group = < 0x02 >;
// init_state = "full_on";
// linux,default-trigger = "none";
// };
// };
// };
// };
phy@100f8800 { /* USB3 port 1 HS phy */
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie1 {
status = "okay";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
0x00978 0x19008643 /* QM_PORT1_CTRL0 */
0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
0x00980 0x19008643 /* QM_PORT2_CTRL0 */
0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
0x00988 0x19008643 /* QM_PORT3_CTRL0 */
0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
0x00990 0x19008643 /* QM_PORT4_CTRL0 */
0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
qca,ar8327-initvals = <
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x0000c 0x80 /* PAD6_MODE */
>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
// &gmac1 {
// status = "okay";
// phy-mode = "rgmii";
// qcom,id = <1>;
// qcom,phy_mdio_addr = <4>;
// qcom,poll_required = <0>;
// qcom,rgmii_delay = <1>;
// qcom,phy_mii_type = <0>;
// qcom,emulation = <0>;
// qcom,irq = <255>;
// mdiobus = <&mdio0>;
// pinctrl-0 = <&rgmii2_pins>;
// pinctrl-names = "default";
// fixed-link {
// speed = <1000>;
// full-duplex;
// };
// };
// &gmac2 {
// status = "okay";
// phy-mode = "sgmii";
// qcom,id = <2>;
// qcom,phy_mdio_addr = <0>; /* none */
// qcom,poll_required = <0>; /* no polling */
// qcom,rgmii_delay = <0>;
// qcom,phy_mii_type = <1>;
// qcom,emulation = <0>;
// qcom,irq = <258>;
// mdiobus = <&mdio0>;
// fixed-link {
// speed = <1000>;
// full-duplex;
// };
// };
&pcie0 {
status = "okay";
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
&pcie1 {
status = "okay";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
};
&amba {
sdcc1: sdcc@12400000 {
status = "okay";
pinctrl-0 = <&sdcc1_pins>;
pinctrl-names = "default";
};
};
&adm_dma {
status = "okay";
};

26
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
View File

@ -268,20 +268,13 @@
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <0>;
qcom,rgmii_delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
@ -296,20 +289,13 @@
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mdio_addr = <0>; /* none */
qcom,poll_required = <0>; /* no polling */
qcom,rgmii_delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;

453
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi Normal file
View File

@ -0,0 +1,453 @@
#include "qcom-ipq8065.dtsi"
#include <dt-bindings/input/input.h>
/ {
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
rsvd@5fe00000 {
reg = <0x5fe00000 0x200000>;
reusable;
};
ramoops@42100000 {
compatible = "ramoops";
reg = <0x42100000 0x40000>;
record-size = <0x4000>;
console-size = <0x4000>;
ftrace-size = <0x4000>;
pmsg-size = <0x4000>;
};
};
aliases {
label-mac-device = &gmac2;
led-boot = &power_white;
led-failsafe = &power_amber;
led-running = &power_white;
led-upgrade = &power_amber;
mdio-gpio0 = &mdio0;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds: leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
power_white: power_white {
label = "white:power";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
power_amber: power_amber {
label = "amber:power";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wan_white {
label = "white:wan";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wan_amber {
label = "amber:wan";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
wifi {
label = "white:wifi";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
wps {
label = "white:wps";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9",
"gpio22", "gpio23", "gpio24",
"gpio26", "gpio53", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
mdio0_pins: mdio0_pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
tx {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32";
input-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
spi6_pins: spi6_pins {
mux {
pins = "gpio55", "gpio56", "gpio58";
function = "gsbi6";
bias-pull-down;
};
mosi {
pins = "gpio55";
drive-strength = <12>;
};
miso {
pins = "gpio56";
drive-strength = <14>;
};
cs {
pins = "gpio57";
drive-strength = <12>;
bias-pull-up;
};
clk {
pins = "gpio58";
drive-strength = <12>;
};
reset {
pins = "gpio33";
drive-strength = <10>;
bias-pull-down;
output-high;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio15";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio16", "gpio68";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
};
&nand_controller {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x1180000>;
partitions: partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "qcadata";
reg = <0x0000000 0x0c80000>;
read-only;
};
partition@c80000 {
label = "APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
partition@1180000 {
label = "APPSBLENV";
reg = <0x1180000 0x0080000>;
read-only;
};
art: partition@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@1340000 {
label = "artbak";
reg = <0x1340000 0x0140000>;
read-only;
};
partition@1480000 {
label = "kernel";
reg = <0x1480000 0x0400000>;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
0x00978 0x19008643 /* QM_PORT1_CTRL0 */
0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
0x00980 0x19008643 /* QM_PORT2_CTRL0 */
0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
0x00988 0x19008643 /* QM_PORT3_CTRL0 */
0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
0x00990 0x19008643 /* QM_PORT4_CTRL0 */
0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
>;
qca,ar8327-vlans = <
0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
0x2 0x21 /* VLAN2 Ports 0/5 */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
qca,ar8327-initvals = <
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x0000c 0x80 /* PAD6_MODE */
>;
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <0>;
qcom,rgmii_delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
qcom,poll_required = <0>; /* no polling */
qcom,rgmii_delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi0: wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi1: wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
};
};
};

474
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
View File

@ -1,466 +1,48 @@
#include "qcom-ipq8065.dtsi"
#include <dt-bindings/input/input.h>
#include "qcom-ipq8065-nighthawk.dtsi"
/ {
model = "Netgear Nighthawk X4S R7800";
compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064";
};
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
&leds {
usb1 {
label = "white:usb1";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
reserved-memory {
rsvd@5fe00000 {
reg = <0x5fe00000 0x200000>;
reusable;
};
usb2 {
label = "white:usb2";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &power_white;
led-failsafe = &power_amber;
led-running = &power_white;
led-upgrade = &power_amber;
label-mac-device = &gmac2;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
power_white: power_white {
label = "white:power";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
power_amber: power_amber {
label = "amber:power";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wan_white {
label = "white:wan";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wan_amber {
label = "amber:wan";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
usb1 {
label = "white:usb1";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb2 {
label = "white:usb2";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
esata {
label = "white:esata";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
wifi {
label = "white:wifi";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
wps {
label = "white:wps";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
esata {
label = "white:esata";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
&partitions {
partition@1880000 {
label = "ubi";
reg = <0x1880000 0x6080000>;
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
"gpio24","gpio26", "gpio53", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
mdio0_pins: mdio0_pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
input-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
spi6_pins: spi6_pins {
mux {
pins = "gpio55", "gpio56", "gpio58";
function = "gsbi6";
bias-pull-down;
};
mosi {
pins = "gpio55";
drive-strength = <12>;
};
miso {
pins = "gpio56";
drive-strength = <14>;
};
cs {
pins = "gpio57";
drive-strength = <12>;
bias-pull-up;
};
clk {
pins = "gpio58";
drive-strength = <12>;
};
reset {
pins = "gpio33";
drive-strength = <10>;
bias-pull-down;
output-high;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio15";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio16", "gpio68";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
partition@7900000 {
label = "reserve";
reg = <0x7900000 0x0700000>;
read-only;
};
};
&nand_controller {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x1180000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qcadata@0 {
label = "qcadata";
reg = <0x0000000 0x0c80000>;
read-only;
};
APPSBL@c80000 {
label = "APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
APPSBLENV@1180000 {
label = "APPSBLENV";
reg = <0x1180000 0x0080000>;
read-only;
};
art: art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
};
artbak: art@1340000 {
label = "artbak";
reg = <0x1340000 0x0140000>;
read-only;
};
kernel@1480000 {
label = "kernel";
reg = <0x1480000 0x0400000>;
};
ubi@1880000 {
label = "ubi";
reg = <0x1880000 0x6080000>;
};
reserve@7900000 {
label = "reserve";
reg = <0x7900000 0x0700000>;
read-only;
};
};
};
&wifi0 {
nvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(1)>;
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
0x00978 0x19008643 /* QM_PORT1_CTRL0 */
0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
0x00980 0x19008643 /* QM_PORT2_CTRL0 */
0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
0x00988 0x19008643 /* QM_PORT3_CTRL0 */
0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
0x00990 0x19008643 /* QM_PORT4_CTRL0 */
0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
>;
qca,ar8327-vlans = <
0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
0x2 0x21 /* VLAN2 Ports 0/5 */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
qca,ar8327-initvals = <
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x0000c 0x80 /* PAD6_MODE */
>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&art 6>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&art 0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
mtd-mac-address = <&art 6>;
mtd-mac-address-increment = <(1)>;
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
mtd-mac-address = <&art 6>;
mtd-mac-address-increment = <(2)>;
};
};
&wifi1 {
nvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
mac-address-increment = <(2)>;
};

312
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
View File

@ -1,13 +1,319 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065-rt4230w.dtsi"
#include "qcom-ipq8065.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Askey RT4230W REV6";
compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x3e000000>;
device_type = "memory";
};
aliases {
led-boot = &ledctrl3;
led-failsafe = &ledctrl1;
led-running = &ledctrl2;
led-upgrade = &ledctrl3;
};
chosen {
bootargs = "rootfstype=squashfs noinitrd";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
ledctrl1: ledctrl1 {
label = "ledctrl1";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
ledctrl2: ledctrl2 {
label = "ledctrl2";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
ledctrl3: ledctrl3 {
label = "ledctrl3";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
};
};
&ubi {
reg = <0x2400000 0x1a000000>;
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio54", "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio22", "gpio23", "gpio24";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
rgmii2_pins: rgmii2_pins {
mux {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
function = "rgmii2";
drive-strength = <8>;
bias-disable;
};
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
input-disable;
};
};
};
&nand_controller {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0000000 0x0040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x0040000 0x0140000>;
read-only;
};
partition@180000 {
label = "0:SBL2";
reg = <0x0180000 0x0140000>;
read-only;
};
partition@2c0000 {
label = "0:SBL3";
reg = <0x02c0000 0x0280000>;
read-only;
};
partition@540000 {
label = "0:DDRCONFIG";
reg = <0x0540000 0x0120000>;
read-only;
};
partition@660000 {
label = "0:SSD";
reg = <0x0660000 0x0120000>;
read-only;
};
partition@780000 {
label = "0:TZ";
reg = <0x0780000 0x0280000>;
read-only;
};
partition@a00000 {
label = "0:RPM";
reg = <0x0a00000 0x0280000>;
read-only;
};
partition@c80000 {
label = "0:APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
partition@1180000 {
label = "0:APPSBLENV";
reg = <0x1180000 0x0080000>;
};
ART: partition@1200000 {
label = "0:ART";
reg = <0x1200000 0x0140000>;
read-only;
};
partition@1340000 {
label = "0:BOOTCONFIG";
reg = <0x1340000 0x0060000>;
read-only;
};
partition@13a0000 {
label = "0:SBL2_1";
reg = <0x13a0000 0x0140000>;
read-only;
};
partition@14e0000 {
label = "0:SBL3_1";
reg = <0x14e0000 0x0280000>;
read-only;
};
partition@1760000 {
label = "0:DDRCONFIG_1";
reg = <0x1760000 0x0120000>;
read-only;
};
partition@1880000 {
label = "0:SSD_1";
reg = <0x1880000 0x0120000>;
read-only;
};
partition@19a0000 {
label = "0:TZ_1";
reg = <0x19a0000 0x0280000>;
read-only;
};
partition@1c20000 {
label = "0:RPM_1";
reg = <0x1c20000 0x0280000>;
read-only;
};
partition@1ea0000 {
label = "0:BOOTCONFIG1";
reg = <0x1ea0000 0x0060000>;
read-only;
};
partition@1f00000 {
label = "0:APPSBL_1";
reg = <0x1f00000 0x0500000>;
read-only;
};
partition@2400000 {
label = "ubi";
reg = <0x2400000 0x1a000000>;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0x0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
0x00050 0xcf02cf02 /* LED_CTRL_0 */
0x00054 0xc832c832 /* LED_CTRL_1 */
>;
};
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <0>;
nvmem-cells = <&macaddr_ART_0>;
nvmem-cell-names = "mac-address";
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac1 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <1>;
nvmem-cells = <&macaddr_ART_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
&pcie1 {
status = "okay";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
};
&ART {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_ART_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_ART_6: macaddr@6 {
reg = <0x6 0x6>;
};
};

13
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev9.3.dts
View File

@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065-rt4230w.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Askey RT4230W REV9.3";
compatible = "askey,rt4230w-rev9.3", "qcom,ipq8065", "qcom,ipq8064";
};
&ubi {
reg = <0x2400000 0xdc00000>;
};

364
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w.dtsi
View File

@ -1,364 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq8065.dtsi"
#include <dt-bindings/input/input.h>
/ {
memory@0 {
reg = <0x42000000 0x3e000000>;
device_type = "memory";
};
aliases {
led-boot = &ledctrl3;
led-failsafe = &ledctrl1;
led-running = &ledctrl2;
led-upgrade = &ledctrl3;
};
chosen {
bootargs = "rootfstype=squashfs noinitrd";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
ledctrl1: ledctrl1 {
label = "ledctrl1";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
ledctrl2: ledctrl2 {
label = "ledctrl2";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
ledctrl3: ledctrl3 {
label = "ledctrl3";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio54", "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio22", "gpio23", "gpio24";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
rgmii2_pins: rgmii2_pins {
mux {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
function = "rgmii2";
drive-strength = <8>;
bias-disable;
};
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
input-disable;
};
};
spi_pins: spi_pins {
cs {
pins = "gpio20";
drive-strength = <12>;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi4: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "everspin,mr25h256";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <40000000>;
reg = <0>;
};
};
};
&nand_controller {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x1180000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0000000 0x0040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x0040000 0x0140000>;
read-only;
};
partition@180000 {
label = "0:SBL2";
reg = <0x0180000 0x0140000>;
read-only;
};
partition@2c0000 {
label = "0:SBL3";
reg = <0x02c0000 0x0280000>;
read-only;
};
partition@540000 {
label = "0:DDRCONFIG";
reg = <0x0540000 0x0120000>;
read-only;
};
partition@660000 {
label = "0:SSD";
reg = <0x0660000 0x0120000>;
read-only;
};
partition@780000 {
label = "0:TZ";
reg = <0x0780000 0x0280000>;
read-only;
};
partition@a00000 {
label = "0:RPM";
reg = <0x0a00000 0x0280000>;
read-only;
};
partition@c80000 {
label = "0:APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
partition@1180000 {
label = "0:APPSBLENV";
reg = <0x1180000 0x0080000>;
};
ART: partition@1200000 {
label = "0:ART";
reg = <0x1200000 0x0140000>;
read-only;
};
partition@1340000 {
label = "0:BOOTCONFIG";
reg = <0x1340000 0x0060000>;
read-only;
};
partition@13a0000 {
label = "0:SBL2_1";
reg = <0x13a0000 0x0140000>;
read-only;
};
partition@14e0000 {
label = "0:SBL3_1";
reg = <0x14e0000 0x0280000>;
read-only;
};
partition@1760000 {
label = "0:DDRCONFIG_1";
reg = <0x1760000 0x0120000>;
read-only;
};
partition@1880000 {
label = "0:SSD_1";
reg = <0x1880000 0x0120000>;
read-only;
};
partition@19a0000 {
label = "0:TZ_1";
reg = <0x19a0000 0x0280000>;
read-only;
};
partition@1c20000 {
label = "0:RPM_1";
reg = <0x1c20000 0x0280000>;
read-only;
};
partition@1ea0000 {
label = "0:BOOTCONFIG1";
reg = <0x1ea0000 0x0060000>;
read-only;
};
partition@1f00000 {
label = "0:APPSBL_1";
reg = <0x1f00000 0x0500000>;
read-only;
};
ubi: partition@2400000 {
label = "ubi";
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0x0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
0x00050 0xcf02cf02 /* LED_CTRL_0 */
0x00054 0xc832c832 /* LED_CTRL_1 */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
};
&gmac0 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <0>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <0>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
mtd-mac-address = <&ART 0x0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <1>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&ART 0x6>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};
&usb3_0 {
status = "okay";
clocks = <&gcc USB30_1_MASTER_CLK>;
};
&usb3_1 {
status = "okay";
clocks = <&gcc USB30_0_MASTER_CLK>;
};
&pcie0 {
status = "okay";
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
&pcie1 {
status = "okay";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
};

91
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rac2v1a.dts → target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts
View File

@ -4,8 +4,8 @@
#include <dt-bindings/input/input.h>
/ {
model = "Arris RAC2V1A";
compatible = "arris,rac2v1a", "qcom,ipq8065", "qcom,ipq8064";
model = "Arris TR4400 v2";
compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
@ -110,8 +110,6 @@
flash@0 {
compatible = "everspin,mr25h256";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <40000000>;
reg = <0>;
};
@ -190,6 +188,17 @@
label = "0:ART";
reg = <0x1200000 0x0140000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@1340000 {
label = "rootfs_1";
@ -248,6 +257,26 @@
label = "fw_env";
reg = <0xa400000 0x0100000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_fw_env_0: macaddr@0 {
reg = <0x00 0x6>;
};
macaddr_fw_env_6: macaddr@6 {
reg = <0x06 0x6>;
};
macaddr_fw_env_c: macaddr@c {
reg = <0x0c 0x6>;
};
macaddr_fw_env_12: macaddr@12 {
reg = <0x12 0x6>;
};
macaddr_fw_env_18: macaddr@18 {
reg = <0x18 0x6>;
};
};
partition@a500000 {
label = "config";
@ -274,7 +303,7 @@
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
ethernet-phy@0 {
reg = <0x0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
@ -287,10 +316,6 @@
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
};
phy7: ethernet-phy@7 {
reg = <7>;
};
@ -300,13 +325,13 @@
status = "okay";
phy-mode = "rgmii";
qcom,id = <0>;
phy-handle = <&phy4>;
nvmem-cells = <&macaddr_fw_env_18>;
nvmem-cell-names = "mac-address";
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&fw_env 0x18>;
fixed-link {
speed = <1000>;
full-duplex;
@ -318,7 +343,8 @@
phy-mode = "sgmii";
qcom,id = <1>;
mtd-mac-address = <&fw_env 0x0>;
nvmem-cells = <&macaddr_fw_env_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
@ -332,21 +358,16 @@
qcom,id = <3>;
phy-handle = <&phy7>;
mtd-mac-address = <&fw_env 0x6>;
nvmem-cells = <&macaddr_fw_env_6>;
nvmem-cell-names = "mac-address";
};
&adm_dma {
status = "okay";
};
&usb3_0 {
status = "okay";
clocks = <&gcc USB30_1_MASTER_CLK>;
};
&usb3_1 {
status = "okay";
clocks = <&gcc USB30_0_MASTER_CLK>;
};
&pcie0 {
@ -354,6 +375,21 @@
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi0: wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
nvmem-cell-names = "pre-calibration", "mac-address";
};
};
};
&pcie1 {
@ -362,4 +398,19 @@
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi1: wifi@1,0 {
compatible = "pci168c,0040";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
nvmem-cell-names = "pre-calibration", "mac-address";
};
};
};

473
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts
View File

@ -1,461 +1,50 @@
#include "qcom-ipq8065.dtsi"
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/input/input.h>
#include "qcom-ipq8065-nighthawk.dtsi"
/ {
model = "Netgear Nighthawk Pro Gaming XR500";
model = "Netgear Nighthawk XR500";
compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
&leds {
usb1 {
label = "white:usb1";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
reserved-memory {
rsvd@5fe00000 {
reg = <0x5fe00000 0x200000>;
reusable;
};
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &led_power_white;
led-failsafe = &led_power_amber;
led-running = &led_power_white;
led-upgrade = &led_power_amber;
label-mac-device = &gmac2;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power_white: power_white {
label = "white:power";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
led_power_amber: power_amber {
label = "amber:power";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wan_white {
label = "white:wan";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wan_amber {
label = "amber:wan";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
usb1 {
label = "white:usb1";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
usb2 {
label = "white:usb2";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
wifi {
label = "white:wifi";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
wps {
label = "white:wps";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
usb2 {
label = "white:usb2";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
&partitions {
partition@1880000 {
label = "ubi";
reg = <0x1880000 0xce00000>;
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
"gpio24","gpio26", "gpio53", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
mdio0_pins: mdio0_pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2_pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
input-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
spi6_pins: spi6_pins {
mux {
pins = "gpio55", "gpio56", "gpio58";
function = "gsbi6";
bias-pull-down;
};
mosi {
pins = "gpio55";
drive-strength = <12>;
};
miso {
pins = "gpio56";
drive-strength = <14>;
};
cs {
pins = "gpio57";
drive-strength = <12>;
bias-pull-up;
};
clk {
pins = "gpio58";
drive-strength = <12>;
};
reset {
pins = "gpio33";
drive-strength = <10>;
bias-pull-down;
output-high;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio15";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio16", "gpio68";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
partition@e680000 {
label = "reserve";
reg = <0xe680000 0x0780000>;
read-only;
};
};
&nand_controller {
status = "okay";
&wifi0 {
nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
&wifi1 {
nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x1180000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qcadata@0 {
label = "qcadata";
reg = <0x0000000 0x0c80000>;
read-only;
};
APPSBL@c80000 {
label = "APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
APPSBLENV@1180000 {
label = "APPSBLENV";
reg = <0x1180000 0x0080000>;
read-only;
};
art: art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
};
artbak: art@1340000 {
label = "artbak";
reg = <0x1340000 0x0140000>;
read-only;
};
kernel@1480000 {
label = "kernel";
reg = <0x1480000 0x0400000>;
};
ubi@1880000 {
label = "ubi";
reg = <0x1880000 0xce00000>;
};
reserve@e680000 {
label = "reserve";
reg = <0xe680000 0x0780000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x00004 0x7600000 /* PAD0_MODE */
0x00008 0x1000000 /* PAD5_MODE */
0x0000c 0x80 /* PAD6_MODE */
0x000e4 0xaa545 /* MAC_POWER_SEL */
0x000e0 0xc74164de /* SGMII_CTRL */
0x0007c 0x4e /* PORT0_STATUS */
0x00094 0x4e /* PORT6_STATUS */
0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
0x00978 0x19008643 /* QM_PORT1_CTRL0 */
0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
0x00980 0x19008643 /* QM_PORT2_CTRL0 */
0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
0x00988 0x19008643 /* QM_PORT3_CTRL0 */
0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
0x00990 0x19008643 /* QM_PORT4_CTRL0 */
0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
>;
qca,ar8327-vlans = <
0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
0x2 0x21 /* VLAN2 Ports 0/5 */
>;
};
phy4: ethernet-phy@4 {
reg = <4>;
qca,ar8327-initvals = <
0x000e4 0x6a545 /* MAC_POWER_SEL */
0x0000c 0x80 /* PAD6_MODE */
>;
};
};
&gmac1 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "rgmii";
qcom,id = <1>;
qcom,pcs-chanid = <0>;
qcom,phy-mdio-addr = <4>;
qcom,poll-required = <0>;
qcom,rgmii-delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mtd-mac-address = <&art 6>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
compatible = "qcom,nss-gmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "sgmii";
qcom,id = <2>;
qcom,pcs-chanid = <1>;
qcom,phy-mdio-addr = <0>; /* none */
qcom,poll-required = <0>; /* no polling */
qcom,rgmii-delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,forced-speed = <1000>;
qcom,forced-duplex = <1>;
qcom,socver = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
mtd-mac-address = <&art 0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
mtd-mac-address = <&art 6>;
mtd-mac-address-increment = <(1)>;
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
mtd-mac-address = <&art 6>;
mtd-mac-address-increment = <(2)>;
};
&art {
macaddr_art_c: macaddr@c {
reg = <0xc 0x6>;
};
};

99
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi
View File

@ -97,80 +97,71 @@
/delete-node/opp-1200000000;
/*
* Voltage thresholds are <target min max>
*/
opp-384000000 {
opp-microvolt-speed0-pvs0-v0 = <926250 975000 1023750>;
opp-microvolt-speed0-pvs1-v0 = <902500 950000 997500>;
opp-microvolt-speed0-pvs2-v0 = <878750 925000 971250>;
opp-microvolt-speed0-pvs3-v0 = <855000 900000 945000>;
opp-microvolt-speed0-pvs4-v0 = <831250 875000 918750>;
opp-microvolt-speed0-pvs5-v0 = <783750 825000 866250>;
opp-microvolt-speed0-pvs6-v0 = <736250 775000 813750>;
opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
};
opp-600000000 {
opp-microvolt-speed0-pvs0-v0 = <950000 1000000 1050000>;
opp-microvolt-speed0-pvs1-v0 = <926250 975000 1023750>;
opp-microvolt-speed0-pvs2-v0 = <902500 950000 997500>;
opp-microvolt-speed0-pvs3-v0 = <878750 925000 971250>;
opp-microvolt-speed0-pvs4-v0 = <855000 900000 945000>;
opp-microvolt-speed0-pvs5-v0 = <807500 850000 892500>;
opp-microvolt-speed0-pvs6-v0 = <760000 800000 840000>;
opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
};
opp-800000000 {
opp-microvolt-speed0-pvs0-v0 = <997500 1050000 1102500>;
opp-microvolt-speed0-pvs1-v0 = <973750 1025000 1076250>;
opp-microvolt-speed0-pvs2-v0 = <950000 1000000 1050000>;
opp-microvolt-speed0-pvs3-v0 = <926250 975000 1023750>;
opp-microvolt-speed0-pvs4-v0 = <902500 950000 997500>;
opp-microvolt-speed0-pvs5-v0 = <855000 900000 945000>;
opp-microvolt-speed0-pvs6-v0 = <807500 850000 892500>;
opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
};
opp-1000000000 {
opp-microvolt-speed0-pvs0-v0 = <1045000 1100000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1021250 1075000 1128750>;
opp-microvolt-speed0-pvs2-v0 = <997500 1050000 1102500>;
opp-microvolt-speed0-pvs3-v0 = <973750 1025000 1076250>;
opp-microvolt-speed0-pvs4-v0 = <950000 1000000 1050000>;
opp-microvolt-speed0-pvs5-v0 = <902500 950000 997500>;
opp-microvolt-speed0-pvs6-v0 = <855000 900000 945000>;
opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
};
opp-1400000000 {
opp-microvolt-speed0-pvs0-v0 = <1116250 1175000 1233750>;
opp-microvolt-speed0-pvs1-v0 = <1092500 1150000 1207500>;
opp-microvolt-speed0-pvs2-v0 = <1068750 1125000 1181250>;
opp-microvolt-speed0-pvs3-v0 = <1045000 1100000 1155000>;
opp-microvolt-speed0-pvs4-v0 = <1021250 1075000 1128750>;
opp-microvolt-speed0-pvs5-v0 = <973750 1025000 1076250>;
opp-microvolt-speed0-pvs6-v0 = <926250 975000 1023750>;
opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
opp-level = <1>;
};
opp-1725000000 {
opp-hz = /bits/ 64 <1725000000>;
opp-microvolt-speed0-pvs0-v0 = <1199375 1262500 1325625>;
opp-microvolt-speed0-pvs1-v0 = <1163750 1225000 1286250>;
opp-microvolt-speed0-pvs2-v0 = <1140000 1200000 1260000>;
opp-microvolt-speed0-pvs3-v0 = <1116250 1175000 1233750>;
opp-microvolt-speed0-pvs4-v0 = <1092500 1150000 1207500>;
opp-microvolt-speed0-pvs5-v0 = <1045000 1100000 1155000>;
opp-microvolt-speed0-pvs6-v0 = <997500 1050000 1102500>;
opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
opp-supported-hw = <0x1>;
clock-latency-ns = <100000>;
opp-level = <2>;
};
};
&nss0 {
qcom,low-frequency = <800000000>;
qcom,mid-frequency = <800000000>;
qcom,max-frequency = <800000000>;
};
&nss1 {
qcom,low-frequency = <800000000>;
qcom,mid-frequency = <800000000>;
qcom,max-frequency = <800000000>;
};

239
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi Normal file
View File

@ -0,0 +1,239 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
#include "qcom-ipq8064-v2.0.dtsi"
/ {
memory {
device_type = "memory";
linux,usable-memory = <0x41500000 0x1ea00000>;
reg = <0x40000000 0x20000000>;
};
cpus {
idle-states {
CPU_SPC: spc {
status = "disabled";
};
};
};
chosen {
bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art";
};
};
&qcom_pinmux {
mdio0_pins_active: mdio0_pins_active {
mux {
pins = "gpio0", "gpio1";
function = "mdio";
drive-strength = <2>;
bias-pull-down;
output-low;
};
clk {
pins = "gpio1";
input-disable;
};
};
phy_active: phy_active {
phy {
pins = "gpio6", "gpio7";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
output-high;
};
};
uart1_pins: uart1_pins {
mux {
pins = "gpio51", "gpio52";
function = "gsbi1";
drive-strength = <4>;
bias-disable;
};
};
};
&gsbi1 {
status = "okay";
qcom,mode = <GSBI_PROT_UART_W_FC>;
serial@12450000 {
status = "okay";
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
};
};
&pcie0 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi0: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x10000 0 0 0 0>;
};
};
};
&pcie1 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi1: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x10000 0 0 0 0>;
};
};
};
&pcie2 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x10000 0 0 0 0>;
};
};
};
&adm_dma {
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
compatible = "qcom,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot_pages_size = <0x2140000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x140000>;
read-only;
};
partition@180000 {
label = "sbl2";
reg = <0x180000 0x140000>;
read-only;
};
partition@2c0000 {
label = "sbl3";
reg = <0x2c0000 0x280000>;
read-only;
};
partition@540000 {
label = "ddrconfig";
reg = <0x540000 0x120000>;
read-only;
};
partition@660000 {
label = "ssd";
reg = <0x660000 0x120000>;
read-only;
};
partition@780000 {
label = "tz";
reg = <0x780000 0x280000>;
read-only;
};
partition@a00000 {
label = "rpm";
reg = <0xa00000 0x280000>;
read-only;
};
partition@1fc0000 {
label = "u-boot";
reg = <0x1fc0000 0x180000>;
read-only;
};
partition@21c0000 {
label = "bootkernel1";
reg = <0x21c0000 0xa80000>;
};
partition@2c40000 {
label = "bootkernel2";
reg = <0x2c40000 0xa80000>;
};
partition@36c0000 {
label = "ubi";
reg = <0x36c0000 0x46c0000>;
};
partition@7d80000 {
label = "art";
reg = <0x7d80000 0x200000>;
read-only;
};
};
};
};

33
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts
View File

@ -34,9 +34,8 @@
aliases {
serial1 = &gsbi1_serial;
mdio-gpio0 = &mdio0;
ethernet0 = &gmac3;
ethernet1 = &gmac2;
ethernet0 = &gmac2;
ethernet1 = &gmac3;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
@ -293,26 +292,18 @@
};
};
&soc {
mdio1: mdio {
compatible = "virtual,mdio-gpio";
#address-cells = <1>;
#size-cells = <0>;
&mdio0 {
status = "okay";
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
@ -330,7 +321,7 @@
status = "okay";
qcom,id = <3>;
mdiobus = <&mdio1>;
mdiobus = <&mdio0>;
phy-mode = "sgmii";
phy-handle = <&phy0>;

204
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts Normal file
View File

@ -0,0 +1,204 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
#include "qcom-ipq8068-cryptid-common.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Meraki MR42";
compatible = "meraki,mr42", "qcom,ipq8064";
aliases {
serial1 = &gsbi1_serial;
ethernet0 = &gmac3;
led-boot = &led_active;
led-failsafe = &led_power;
led-running = &led_active;
led-upgrade = &led_active;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power: power {
label = "orange:power";
gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;
};
led_active: active {
label = "white:active";
gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>;
};
};
};
&gmac3 {
status = "okay";
qcom,id = <3>;
mdiobus = <&mdio0>;
phy-mode = "sgmii";
phy-handle = <&phy2>;
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
};
&gsbi2 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C>;
};
&gsbi2_i2c {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
ina2xx@40 {
compatible = "ina219";
shunt-resistor = <40000>;
reg = <0x40>;
};
eeprom@56 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x56>;
read-only;
#address-cells = <1>;
#size-cells = <1>;
mac_address: mac-address@66 {
reg = <0x66 0x6>;
};
};
};
&gsbi6 {
qcom,mode = <GSBI_PROT_I2C>;
status = "okay";
};
&gsbi6_i2c {
status = "okay";
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
tlc591xx@40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,tlc59108";
reg = <0x40>;
red@0 {
label = "red:user";
reg = <0x0>;
};
green@1 {
label = "green:user";
reg = <0x1>;
};
blue@2 {
label = "blue:user";
reg = <0x2>;
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
pinctrl-names = "default";
phy2: ethernet-phy2 {
reg = <2>;
reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <24000>;
eee-broken-100tx;
eee-broken-1000t;
};
};
&qcom_pinmux {
i2c0_pins: i2c0_pins {
mux {
pins = "gpio24", "gpio25";
function = "gsbi2";
drive-strength = <2>;
bias-pull-up;
input;
};
};
button_pins: button_pins {
mux {
pins = "gpio26";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
i2c1_pins: i2c1_pins {
mux {
pins = "gpio29", "gpio30";
function = "gsbi6";
drive-strength = <2>;
bias-pull-up;
input;
};
};
led_pins: led_pins {
mux {
pins = "gpio31", "gpio32";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-low;
};
};
};
&wifi0 {
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&wifi1 {
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <2>;
};
&wifi2 {
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <3>;
};

230
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts Normal file
View File

@ -0,0 +1,230 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
#include "qcom-ipq8068-cryptid-common.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Meraki MR52";
compatible = "meraki,mr52", "qcom,ipq8064";
aliases {
serial1 = &gsbi1_serial;
mdio-gpio0 = &mdio_gpio0;
ethernet0 = &gmac2;
ethernet1 = &gmac3;
led-boot = &led_active;
led-failsafe = &led_power;
led-running = &led_active;
led-upgrade = &led_active;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power: power {
label = "orange:power";
gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
};
lan2_green {
label = "green:lan2";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
lan1_green {
label = "green:lan1";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
led_active: active {
label = "white:active";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
lan2_orange {
label = "orange:lan2";
gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
};
lan1_orange {
label = "orange:lan1";
gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
};
};
};
&gmac2 {
status = "okay";
qcom,id = <2>;
mdiobus = <&mdio0>;
phy-mode = "sgmii";
phy-handle = <&phy0>;
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
};
&gmac3 {
status = "okay";
qcom,id = <3>;
mdiobus = <&mdio_gpio0>;
phy-mode = "sgmii";
phy-handle = <&phy4>;
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
};
&gsbi7 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C>;
};
&gsbi7_i2c {
status = "okay";
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
ina2xx@45 {
compatible = "ina219";
shunt-resistor = <80000>;
reg = <0x45>;
};
tlc591xx@49 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,tlc59108";
reg = <0x49>;
red@0 {
label = "red:user";
reg = <0x0>;
};
green@1 {
label = "green:user";
reg = <0x1>;
};
blue@2 {
label = "blue:user";
reg = <0x2>;
};
};
eeprom@52 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x52>;
read-only;
#address-cells = <1>;
#size-cells = <1>;
mac_address: mac-address@66 {
reg = <0x66 0x6>;
};
};
};
&qcom_pinmux {
i2c_pins: i2c_pins {
mux {
pins = "gpio8", "gpio9";
function = "gsbi7";
drive-strength = <2>;
bias-pull-up;
input;
};
};
led_pins: led_pins {
mux {
pins = "gpio19", "gpio26";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-low;
};
};
button_pins: button_pins {
mux {
pins = "gpio25";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
input;
};
};
};
&soc {
mdio_gpio0: mdio {
compatible = "virtual,mdio-gpio";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
pinctrl-names = "default";
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH
&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
phy0: ethernet-phy0 {
reg = <0>;
reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <24000>;
};
phy4: ethernet-phy4 {
reg = <4>;
reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
reset-assert-us = <24000>;
};
};
};
&wifi0 {
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <4>;
};
&wifi1 {
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <3>;
};
&wifi2 {
nvmem-cells = <&mac_address>;
nvmem-cell-names = "mac-address";
mac-address-increment = <2>;
};

24
target/linux/ipq806x/files/include/linux/regulator/nss-volt-ipq806x.h
View File

@ -1,24 +0,0 @@
/*
* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __QCOM_NSS_VOL_SCALING_H
#define __QCOM_NSS_VOL_SCALING_H
#include <linux/regulator/consumer.h>
int nss_ramp_voltage(unsigned long rate, bool ramp_up);
#endif

101
target/linux/ipq806x/files/include/net/netfilter/nf_conntrack_dscpremark_ext.h
View File

@ -1,101 +0,0 @@
/*
**************************************************************************
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
**************************************************************************
*/
/* DSCP remark conntrack extension APIs. */
#ifndef _NF_CONNTRACK_DSCPREMARK_H
#define _NF_CONNTRACK_DSCPREMARK_H
#include <net/netfilter/nf_conntrack.h>
#include <net/netfilter/nf_conntrack_extend.h>
/* Rule flags */
#define NF_CT_DSCPREMARK_EXT_DSCP_RULE_VALID 0x1
/* Rule validity */
#define NF_CT_DSCPREMARK_EXT_RULE_VALID 0x1
#define NF_CT_DSCPREMARK_EXT_RULE_NOT_VALID 0x0
/*
* DSCP remark conntrack extension structure.
*/
struct nf_ct_dscpremark_ext {
__u32 flow_priority; /* Original direction packet priority */
__u32 reply_priority; /* Reply direction packet priority */
__u16 igs_flow_qos_tag; /* Original direction ingress packet priority */
__u16 igs_reply_qos_tag; /* Reply direction ingress packet priority */
__u8 flow_dscp; /* IP DSCP value for original direction */
__u8 reply_dscp; /* IP DSCP value for reply direction */
__u16 rule_flags; /* Rule Validity flags */
};
/*
* nf_ct_dscpremark_ext_find()
* Finds the extension data of the conntrack entry if it exists.
*/
static inline struct nf_ct_dscpremark_ext *
nf_ct_dscpremark_ext_find(const struct nf_conn *ct)
{
#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
return nf_ct_ext_find(ct, NF_CT_EXT_DSCPREMARK);
#else
return NULL;
#endif
}
/*
* nf_ct_dscpremark_ext_add()
* Adds the extension data to the conntrack entry.
*/
static inline
struct nf_ct_dscpremark_ext *nf_ct_dscpremark_ext_add(struct nf_conn *ct,
gfp_t gfp)
{
#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
struct nf_ct_dscpremark_ext *ncde;
ncde = nf_ct_ext_add(ct, NF_CT_EXT_DSCPREMARK, gfp);
if (!ncde)
return NULL;
return ncde;
#else
return NULL;
#endif
};
#ifdef CONFIG_NF_CONNTRACK_DSCPREMARK_EXT
extern int nf_conntrack_dscpremark_ext_init(void);
extern void nf_conntrack_dscpremark_ext_fini(void);
extern int nf_conntrack_dscpremark_ext_set_dscp_rule_valid(struct nf_conn *ct);
extern int
nf_conntrack_dscpremark_ext_get_dscp_rule_validity(struct nf_conn *ct);
#else
/*
* nf_conntrack_dscpremark_ext_init()
*/
static inline int nf_conntrack_dscpremark_ext_init(void)
{
return 0;
}
/*
* nf_conntrack_dscpremark_ext_fini()
*/
static inline void nf_conntrack_dscpremark_ext_fini(void)
{
}
#endif /* CONFIG_NF_CONNTRACK_DSCPREMARK_EXT */
#endif /* _NF_CONNTRACK_DSCPREMARK_H */

36
target/linux/ipq806x/files/include/uapi/linux/tc_act/tc_nss_mirred.h
View File

@ -1,36 +0,0 @@
#ifndef __LINUX_TC_NSS_MIRRED_H
#define __LINUX_TC_NSS_MIRRED_H
#include <linux/pkt_cls.h>
/*
* Type of nss mirred action.
*/
#define TCA_ACT_MIRRED_NSS 17
/*
* Types of parameters for nss mirred action.
*/
enum {
TC_NSS_MIRRED_UNSPEC,
TC_NSS_MIRRED_TM,
TC_NSS_MIRRED_PARMS,
__TC_NSS_MIRRED_MAX
};
#define TC_NSS_MIRRED_MAX (__TC_NSS_MIRRED_MAX - 1)
/*
* tc_nss_mirred
* tc command structure for nss mirred action.
*/
struct tc_nss_mirred {
tc_gen; /* General tc structure. */
__u32 from_ifindex; /* ifindex of the port from which traffic
* will be redirected.
*/
__u32 to_ifindex; /* ifindex of the port to which traffic
* will be redirected.
*/
};
#endif /* __LINUX_TC_NSS_MIRRED_H */

92
target/linux/ipq806x/files/net/netfilter/nf_conntrack_dscpremark_ext.c
View File

@ -1,92 +0,0 @@
/*
**************************************************************************
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
**************************************************************************
*/
/* DSCP remark handling conntrack extension registration. */
#include <linux/netfilter.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/export.h>
#include <net/netfilter/nf_conntrack.h>
#include <net/netfilter/nf_conntrack_extend.h>
#include <net/netfilter/nf_conntrack_dscpremark_ext.h>
/* DSCP remark conntrack extension type declaration */
static struct nf_ct_ext_type dscpremark_extend __read_mostly = {
.len = sizeof(struct nf_ct_dscpremark_ext),
.align = __alignof__(struct nf_ct_dscpremark_ext),
.id = NF_CT_EXT_DSCPREMARK,
};
/* nf_conntrack_dscpremark_ext_init()
* Initializes the DSCP remark conntrack extension.
*/
int nf_conntrack_dscpremark_ext_init(void)
{
int ret;
ret = nf_ct_extend_register(&dscpremark_extend);
if (ret < 0) {
pr_warn("nf_conntrack_dscpremark: Unable to register extension\n");
return ret;
}
return 0;
}
/* nf_conntrack_dscpremark_ext_set_dscp_rule_valid()
* Set DSCP rule validity flag in the extension
*/
int nf_conntrack_dscpremark_ext_set_dscp_rule_valid(struct nf_conn *ct)
{
struct nf_ct_dscpremark_ext *ncde;
ncde = nf_ct_dscpremark_ext_find(ct);
if (!ncde)
return -1;
ncde->rule_flags = NF_CT_DSCPREMARK_EXT_DSCP_RULE_VALID;
return 0;
}
EXPORT_SYMBOL(nf_conntrack_dscpremark_ext_set_dscp_rule_valid);
/* nf_conntrack_dscpremark_ext_get_dscp_rule_validity()
* Check if the DSCP rule flag is valid from the extension
*/
int nf_conntrack_dscpremark_ext_get_dscp_rule_validity(struct nf_conn *ct)
{
struct nf_ct_dscpremark_ext *ncde;
ncde = nf_ct_dscpremark_ext_find(ct);
if (!ncde)
return NF_CT_DSCPREMARK_EXT_RULE_NOT_VALID;
if (ncde->rule_flags & NF_CT_DSCPREMARK_EXT_DSCP_RULE_VALID)
return NF_CT_DSCPREMARK_EXT_RULE_VALID;
return NF_CT_DSCPREMARK_EXT_RULE_NOT_VALID;
}
EXPORT_SYMBOL(nf_conntrack_dscpremark_ext_get_dscp_rule_validity);
/* nf_conntrack_dscpremark_ext_fini()
* De-initializes the DSCP remark conntrack extension.
*/
void nf_conntrack_dscpremark_ext_fini(void)
{
nf_ct_extend_unregister(&dscpremark_extend);
}

497
target/linux/ipq806x/image/Makefile
View File

@ -3,37 +3,6 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
DEVICE_VARS += TPLINK_BOARD_ID
define Build/buffalo-rootfs-cksum
( \
echo -ne "\x$$(od -A n -t u1 $@ | tr -s ' ' '\n' | \
$(STAGING_DIR_HOST)/bin/awk '{s+=$$0}END{printf "%x", 255-s%256}')"; \
) >> $@
endef
define Build/edimax-header
$(eval edimax_model=$(word 1,$(1)))
$(STAGING_DIR_HOST)/bin/mkedimaximg \
-b -s CSYS -m $(edimax_model) \
-f 0x70000 -S 0x1200000 \
-i $@ -o $@.new
@mv $@.new $@
endef
# tune addpattern for Linksys E8350-V1 fw pattern generation
define Build/linksys-bin
$(STAGING_DIR_HOST)/bin/addpattern -p $(FW_DEVICE_ID) -v $(FW_VERSION) $(if $(SERIAL),-s $(SERIAL)) -i $@ -o $@.new
mv $@.new $@
endef
# Use Linksys fw header generator to upgrade openwrt factory image over the native Linksys WEB interface
define Build/linksys-addfwhdr
-$(STAGING_DIR_HOST)/bin/addfwhdr -i $@ -o $@.new \
;mv "$@.new" "$@"
endef
define Device/Default
PROFILES := Default
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
@ -70,470 +39,6 @@ define Device/UbiFit
IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
endef
define Device/DniImage
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none
KERNEL_NAME := zImage
NETGEAR_BOARD_ID :=
NETGEAR_HW_ID :=
UBINIZE_OPTS := -E 5
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-ubi | netgear-dni
IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | append-metadata
endef
define Device/TpSafeImage
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none
KERNEL_NAME := zImage
TPLINK_BOARD_ID :=
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | tplink-safeloader factory
IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | append-metadata
endef
define Device/ZyXELImage
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE)
KERNEL_NAME := zImage
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to $$$$(BLOCKSIZE) | zyxel-ras-image separate-kernel
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata
endef
define Device/arris_rac2v1a
$(call Device/LegacyImage)
DEVICE_VENDOR := Arris
DEVICE_MODEL := RAC2V1A
DEVICE_ALT0_VENDOR := Arris
DEVICE_ALT0_MODEL := TR4400-AC
SOC := qcom-ipq8065
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_IN_UBI := 1
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += arris_rac2v1a
define Device/askey_rt4230w
$(call Device/LegacyImage)
DEVICE_VENDOR := Askey
DEVICE_MODEL := RT4230W
SOC := qcom-ipq8065
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_IN_UBI := 1
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
endef
define Device/askey_rt4230w-rev6
$(call Device/askey_rt4230w)
DEVICE_VARIANT := REV6
endef
TARGET_DEVICES += askey_rt4230w-rev6
define Device/askey_rt4230w-rev9.3
$(call Device/askey_rt4230w)
DEVICE_VARIANT := REV9.3
endef
TARGET_DEVICES += askey_rt4230w-rev9.3
define Device/asrock_g10
$(call Device/FitImage)
$(call Device/UbiFit)
SOC := qcom-ipq8064
DEVICE_VENDOR := ASRock
DEVICE_MODEL := G10
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 5332k
DEVICE_PACKAGES := kmod-i2c-gpio ath10k-firmware-qca99x0-ct
IMAGE/nand-factory.bin := append-ubi | edimax-header RN67
endef
TARGET_DEVICES += asrock_g10
define Device/buffalo_wxr-2533dhp
$(call Device/LegacyImage)
SOC := qcom-ipq8064
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := WXR-2533DHP
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := append-rootfs | buffalo-rootfs-cksum | \
sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += buffalo_wxr-2533dhp
define Device/compex_wpq864
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Compex
DEVICE_MODEL := WPQ864
BLOCKSIZE := 128k
PAGESIZE := 2048
SOC := qcom-ipq8064
DEVICE_PACKAGES := kmod-gpio-beeper
endef
TARGET_DEVICES += compex_wpq864
define Device/edgecore_ecw5410
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Edgecore
DEVICE_MODEL := ECW5410
SOC := qcom-ipq8068
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@v2.0-ap160
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ipq-wifi-edgecore_ecw5410
endef
TARGET_DEVICES += edgecore_ecw5410
define Device/linksys_ea7500-v1
$(call Device/LegacyImage)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := EA7500
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
PAGESIZE := 2048
BLOCKSIZE := 128k
KERNEL_SIZE := 3072k
KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem
UBINIZE_OPTS := -E 5
IMAGES := factory.bin sysupgrade.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | pad-to $$$$(PAGESIZE)
DEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers ath10k-firmware-qca99x0-ct luci-app-advanced-reboot
endef
TARGET_DEVICES += linksys_ea7500-v1
define Device/linksys_e8350-v1
$(call Device/LegacyImage)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := E8350
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
FW_VERSION := v1.0.03.003
FW_DEVICE_ID := 8350
PAGESIZE := 2048
BLOCKSIZE := 128k
KERNEL_IN_UBI := 1
IMAGES = factory.bin sysupgrade.ubi
IMAGE/sysupgrade.ubi := append-ubi | check-size 0x08000000 | append-metadata
IMAGE/factory.bin := append-ubi | check-size 0x08000000 | linksys-addfwhdr | linksys-bin
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct qtn-utils qtn-firmware qtn-proto kmod-qtn-pcie2
endef
TARGET_DEVICES += linksys_e8350-v1
define Device/linksys_ea8500
$(call Device/LegacyImage)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := EA8500
SOC := qcom-ipq8064
PAGESIZE := 2048
BLOCKSIZE := 128k
KERNEL_SIZE := 3072k
KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem
BOARD_NAME := ea8500
SUPPORTED_DEVICES += ea8500
UBINIZE_OPTS := -E 5
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct luci-app-advanced-reboot
endef
TARGET_DEVICES += linksys_ea8500
define Device/nec_wg2600hp
$(call Device/LegacyImage)
DEVICE_VENDOR := NEC
DEVICE_MODEL := Aterm WG2600HP
SOC := qcom-ipq8064
BLOCKSIZE := 64k
BOARD_NAME := wg2600hp
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += nec_wg2600hp
define Device/nec_wg2600hp3
$(call Device/LegacyImage)
DEVICE_VENDOR := NEC Platforms
DEVICE_MODEL := Aterm WG2600HP3
SOC := qcom-ipq8062
BLOCKSIZE := 64k
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
DEVICE_PACKAGES := -kmod-ata-ahci -kmod-ata-ahci-platform -kmod-usb-ohci -kmod-usb2 \
-kmod-usb-ledtrig-usbport -kmod-usb-phy-qcom-dwc3 -kmod-usb3 -kmod-usb-dwc3-qcom \
ath10k-firmware-qca9984-ct ipq-wifi-nec_wg2600hp3
endef
TARGET_DEVICES += nec_wg2600hp3
define Device/netgear_d7800
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4 D7800
SOC := qcom-ipq8064
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := D7800
NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := d7800
SUPPORTED_DEVICES += d7800
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += netgear_d7800
define Device/netgear_r7500
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4 R7500
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := R7500
NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := r7500
SUPPORTED_DEVICES += r7500
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct qtn-utils qtn-firmware qtn-proto kmod-qtn-pcie2
endef
TARGET_DEVICES += netgear_r7500
define Device/netgear_r7500v2
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4 R7500
DEVICE_VARIANT := v2
SOC := qcom-ipq8064
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := R7500v2
NETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := r7500v2
SUPPORTED_DEVICES += r7500v2
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct ath10k-firmware-qca988x-ct
endef
TARGET_DEVICES += netgear_r7500v2
define Device/netgear_r7800
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4S R7800
SOC := qcom-ipq8065
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := R7800
NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := r7800
SUPPORTED_DEVICES += r7800
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
endef
TARGET_DEVICES += netgear_r7800
define Device/netgear_xr500
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk Pro Gaming XR500
SOC := qcom-ipq8065
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := XR500
NETGEAR_HW_ID := 29764958+0+256+512+4x4+4x4+cascade
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
endef
TARGET_DEVICES += netgear_xr500
define Device/qcom_ipq8064-ap148
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := AP148
DEVICE_VARIANT := standard
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-ap148
KERNEL_INSTALL := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap148
SUPPORTED_DEVICES += ap148
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-ap148
define Device/qcom_ipq8064-ap148-legacy
$(call Device/LegacyImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := AP148
DEVICE_VARIANT := legacy
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-ap148
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap148
SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-ap148-legacy
define Device/qcom_ipq8064-ap161
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := AP161
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-ap161
KERNEL_INSTALL := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap161
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-ap161
define Device/qcom_ipq8064-db149
$(call Device/FitImage)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := DB149
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-db149
KERNEL_INSTALL := 1
BOARD_NAME := db149
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-db149
define Device/ruijie_rg-mtfi-m520
DEVICE_VENDOR := Ruijie
DEVICE_MODEL := RG-MTFi-M520
SOC := qcom-ipq8064
BLOCKSIZE := 64k
KERNEL_SIZE := 4096k
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE)
KERNEL_NAME := zImage
IMAGES += factory.bin
IMAGE/factory.bin := qsdk-ipq-factory-mmc
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct e2fsprogs kmod-hwmon-lm75 \
kmod-fs-ext4 kmod-fs-f2fs kmod-rtc-pcf8563 losetup mkf2fs
endef
TARGET_DEVICES += ruijie_rg-mtfi-m520
define Device/norton_core-518
DEVICE_TITLE := Norton Core 518
BOARD_NAME := core-518
SOC := qcom-ipq8065
DEVICE_DTS := qcom-ipq8065-core-518
BLOCKSIZE := 64k
KERNEL_SIZE := 4096k
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none | pad-to $${KERNEL_SIZE}
KERNEL_NAME := zImage
SUPPORTED_DEVICES += core-518
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup f2fs-tools
IMAGES := mmcblk0p10-rootfs.bin mmcblk0p9-kernel.bin sysupgrade.bin
IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$${BLOCKSIZE} | sysupgrade-tar rootfs=$$$$@ | append-metadata
IMAGE/mmcblk0p9-kernel.bin := pad-extra 40 | append-kernel | pad-to $$$${KERNEL_SIZE}
IMAGE/mmcblk0p10-rootfs.bin := append-rootfs | pad-rootfs
endef
TARGET_DEVICES += norton_core-518
define Device/surf_g-nat200
$(call Device/LegacyImage)
DEVICE_VENDOR := SURF
DEVICE_MODEL := G-NAT200
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 26624k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += surf_g-nat200
define Device/tplink_ad7200
$(call Device/TpSafeImage)
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := AD7200
DEVICE_VARIANT := v1/v2
DEVICE_ALT0_VENDOR := TP-Link
DEVICE_ALT0_MODEL := Talon AD7200
DEVICE_ALT0_VARIANT := v1/v2
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
TPLINK_BOARD_ID := AD7200
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-wil6210
endef
TARGET_DEVICES += tplink_ad7200
define Device/tplink_c2600
$(call Device/TpSafeImage)
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := Archer C2600
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := c2600
SUPPORTED_DEVICES += c2600
TPLINK_BOARD_ID := C2600
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += tplink_c2600
define Device/tplink_vr2600v
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := Archer VR2600v
DEVICE_VARIANT := v1
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none
KERNEL_NAME := zImage
KERNEL_SIZE := 3072k
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := vr2600v
SUPPORTED_DEVICES += vr2600v
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += tplink_vr2600v
define Device/ubnt_unifi-ac-hd
$(call Device/FitImageLzma)
DEVICE_VENDOR := Ubiquiti
DEVICE_MODEL := UniFi AC HD
SOC := qcom-ipq8064
BLOCKSIZE := 64k
IMAGE_SIZE := 14784k
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | append-metadata | check-size
endef
TARGET_DEVICES += ubnt_unifi-ac-hd
define Device/zyxel_nbg6817
DEVICE_VENDOR := ZyXEL
DEVICE_MODEL := NBG6817
SOC := qcom-ipq8065
KERNEL_SIZE := 4096k
BLOCKSIZE := 64k
BOARD_NAME := nbg6817
RAS_BOARD := NBG6817
RAS_ROOTFS_SIZE := 20934k
RAS_VERSION := "V1.99(OWRT.9999)C0"
SUPPORTED_DEVICES += nbg6817
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup
$(call Device/ZyXELImage)
endef
TARGET_DEVICES += zyxel_nbg6817
include $(SUBTARGET).mk
$(eval $(call BuildImage))

508
target/linux/ipq806x/image/generic.mk Normal file
View File

@ -0,0 +1,508 @@
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
DEVICE_VARS += TPLINK_BOARD_ID
define Device/kernel-size-migration
DEVICE_COMPAT_VERSION := 2.0
DEVICE_COMPAT_MESSAGE := *** Kernel partition size has changed from earlier \
versions. You need to sysupgrade with the OpenWrt factory image and \
use the force flag when image check fails. Settings will be lost. ***
endef
define Build/buffalo-rootfs-cksum
( \
echo -ne "\x$$(od -A n -t u1 $@ | tr -s ' ' '\n' | \
$(STAGING_DIR_HOST)/bin/awk '{s+=$$0}END{printf "%x", 255-s%256}')"; \
) >> $@
endef
define Build/edimax-header
$(eval edimax_model=$(word 1,$(1)))
$(STAGING_DIR_HOST)/bin/mkedimaximg \
-b -s CSYS -m $(edimax_model) \
-f 0x70000 -S 0x1200000 \
-i $@ -o $@.new
@mv $@.new $@
endef
define Device/DniImage
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none
KERNEL_NAME := zImage
NETGEAR_BOARD_ID :=
NETGEAR_HW_ID :=
UBINIZE_OPTS := -E 5
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \
append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | \
append-ubi | netgear-dni
IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \
append-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | \
append-metadata
endef
define Device/TpSafeImage
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none
KERNEL_NAME := zImage
TPLINK_BOARD_ID :=
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | tplink-safeloader factory
IMAGE/sysupgrade.bin := append-rootfs | \
tplink-safeloader sysupgrade | append-metadata
endef
define Device/ZyXELImage
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none | \
pad-to $$(KERNEL_SIZE)
KERNEL_NAME := zImage
IMAGES += factory.bin
IMAGE/factory.bin := append-rootfs | pad-rootfs | \
pad-to $$$$(BLOCKSIZE) | zyxel-ras-image separate-kernel
IMAGE/sysupgrade.bin/squashfs := append-rootfs | \
pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | \
append-metadata
endef
define Device/arris_tr4400-v2
$(call Device/LegacyImage)
DEVICE_VENDOR := Arris
DEVICE_MODEL := TR4400
DEVICE_VARIANT := v2
SOC := qcom-ipq8065
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_IN_UBI := 1
SUPPORTED_DEVICES += arris,rac2v1a
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += arris_tr4400-v2
define Device/askey_rt4230w-rev6
$(call Device/LegacyImage)
DEVICE_VENDOR := Askey
DEVICE_MODEL := RT4230W
DEVICE_VARIANT := REV6
SOC := qcom-ipq8065
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
KERNEL_IN_UBI := 1
endef
TARGET_DEVICES += askey_rt4230w-rev6
define Device/asrock_g10
$(call Device/FitImage)
$(call Device/UbiFit)
SOC := qcom-ipq8064
DEVICE_VENDOR := ASRock
DEVICE_MODEL := G10
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 5332k
DEVICE_PACKAGES := kmod-i2c-gpio ath10k-firmware-qca99x0-ct
IMAGE/nand-factory.bin := append-ubi | edimax-header RN67
endef
TARGET_DEVICES += asrock_g10
define Device/buffalo_wxr-2533dhp
$(call Device/LegacyImage)
SOC := qcom-ipq8064
DEVICE_VENDOR := Buffalo
DEVICE_MODEL := WXR-2533DHP
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := append-rootfs | buffalo-rootfs-cksum | \
sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += buffalo_wxr-2533dhp
define Device/compex_wpq864
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Compex
DEVICE_MODEL := WPQ864
BLOCKSIZE := 128k
PAGESIZE := 2048
SOC := qcom-ipq8064
DEVICE_PACKAGES := kmod-gpio-beeper
endef
TARGET_DEVICES += compex_wpq864
define Device/edgecore_ecw5410
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Edgecore
DEVICE_MODEL := ECW5410
SOC := qcom-ipq8068
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_CONFIG := config@v2.0-ap160
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
endef
TARGET_DEVICES += edgecore_ecw5410
define Device/linksys_ea7500-v1
$(call Device/LegacyImage)
$(Device/kernel-size-migration)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := EA7500
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
PAGESIZE := 2048
BLOCKSIZE := 128k
KERNEL_SIZE := 4096k
KERNEL = kernel-bin | append-dtb | uImage none | \
append-uImage-fakehdr filesystem
UBINIZE_OPTS := -E 5
IMAGES := factory.bin sysupgrade.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
append-ubi | pad-to $$$$(PAGESIZE)
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += linksys_ea7500-v1
define Device/linksys_ea8500
$(call Device/LegacyImage)
$(Device/kernel-size-migration)
DEVICE_VENDOR := Linksys
DEVICE_MODEL := EA8500
SOC := qcom-ipq8064
PAGESIZE := 2048
BLOCKSIZE := 128k
KERNEL_SIZE := 4096k
KERNEL = kernel-bin | append-dtb | uImage none | \
append-uImage-fakehdr filesystem
BOARD_NAME := ea8500
SUPPORTED_DEVICES += ea8500
UBINIZE_OPTS := -E 5
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \
append-ubi
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += linksys_ea8500
define Device/meraki_mr42
$(call Device/FitImage)
DEVICE_VENDOR := Cisco Meraki
DEVICE_MODEL := MR42
SOC := qcom-ipq8068
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_LOADADDR = 0x44208000
DEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \
-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \
-kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \
-uboot-envtools ath10k-firmware-qca9887-ct \
ath10k-firmware-qca99x0-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \
kmod-leds-tlc591xx
endef
TARGET_DEVICES += meraki_mr42
define Device/meraki_mr52
$(call Device/FitImage)
DEVICE_VENDOR := Cisco Meraki
DEVICE_MODEL := MR52
SOC := qcom-ipq8068
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_LOADADDR = 0x44208000
DEVICE_DTS_CONFIG := config@2
DEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \
-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \
-kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \
-uboot-envtools ath10k-firmware-qca9887-ct \
ath10k-firmware-qca9984-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \
kmod-leds-tlc591xx
endef
TARGET_DEVICES += meraki_mr52
define Device/nec_wg2600hp
$(call Device/LegacyImage)
DEVICE_VENDOR := NEC
DEVICE_MODEL := Aterm WG2600HP
SOC := qcom-ipq8064
BLOCKSIZE := 64k
BOARD_NAME := wg2600hp
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
pad-rootfs | append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += nec_wg2600hp
define Device/nec_wg2600hp3
$(call Device/LegacyImage)
DEVICE_VENDOR := NEC Platforms
DEVICE_MODEL := Aterm WG2600HP3
SOC := qcom-ipq8062
BLOCKSIZE := 64k
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
pad-rootfs | append-metadata
DEVICE_PACKAGES := -kmod-ata-ahci -kmod-ata-ahci-platform \
-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \
-kmod-usb-phy-qcom-dwc3 -kmod-usb3 -kmod-usb-dwc3-qcom \
ath10k-firmware-qca9984-ct
endef
TARGET_DEVICES += nec_wg2600hp3
define Device/netgear_d7800
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4 D7800
SOC := qcom-ipq8064
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := D7800
NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := d7800
SUPPORTED_DEVICES += d7800
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
DEVICE_COMPAT_VERSION := 2.0
DEVICE_COMPAT_MESSAGE := Sysupgrade does not work due to rootfs ubi partition size change. \
Use factory image with the TFTP recovery flash routine.
endef
TARGET_DEVICES += netgear_d7800
define Device/netgear_r7500
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4 R7500
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := R7500
NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := r7500
SUPPORTED_DEVICES += r7500
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct
endef
TARGET_DEVICES += netgear_r7500
define Device/netgear_r7500v2
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4 R7500
DEVICE_VARIANT := v2
SOC := qcom-ipq8064
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := R7500v2
NETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := r7500v2
SUPPORTED_DEVICES += r7500v2
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct \
ath10k-firmware-qca988x-ct
endef
TARGET_DEVICES += netgear_r7500v2
define Device/netgear_r7800
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk X4S R7800
SOC := qcom-ipq8065
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := R7800
NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := r7800
SUPPORTED_DEVICES += r7800
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-ramoops
endef
TARGET_DEVICES += netgear_r7800
define Device/netgear_xr500
$(call Device/DniImage)
DEVICE_VENDOR := NETGEAR
DEVICE_MODEL := Nighthawk XR500
SOC := qcom-ipq8065
KERNEL_SIZE := 4096k
NETGEAR_BOARD_ID := XR500
NETGEAR_HW_ID := 29764958+0+256+512+4x4+4x4+cascade
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-ramoops
endef
TARGET_DEVICES += netgear_xr500
define Device/qcom_ipq8064-ap148
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := AP148
DEVICE_VARIANT := standard
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-ap148
KERNEL_INSTALL := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap148
SUPPORTED_DEVICES += ap148
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-ap148
define Device/qcom_ipq8064-ap148-legacy
$(call Device/LegacyImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := AP148
DEVICE_VARIANT := legacy
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-ap148
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap148
SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-ap148-legacy
define Device/qcom_ipq8064-ap161
$(call Device/FitImage)
$(call Device/UbiFit)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := AP161
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-ap161
KERNEL_INSTALL := 1
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := ap161
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-ap161
define Device/qcom_ipq8064-db149
$(call Device/FitImage)
DEVICE_VENDOR := Qualcomm
DEVICE_MODEL := DB149
SOC := qcom-ipq8064
DEVICE_DTS := qcom-ipq8064-db149
KERNEL_INSTALL := 1
BOARD_NAME := db149
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += qcom_ipq8064-db149
define Device/ruijie_rg-mtfi-m520
DEVICE_VENDOR := Ruijie
DEVICE_MODEL := RG-MTFi-M520
SOC := qcom-ipq8064
BLOCKSIZE := 64k
KERNEL_SIZE := 4096k
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE)
KERNEL_NAME := zImage
IMAGES += factory.bin
IMAGE/factory.bin := qsdk-ipq-factory-mmc
IMAGE/sysupgrade.bin/squashfs := append-rootfs | \
pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | \
append-metadata
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct e2fsprogs kmod-hwmon-lm75 \
kmod-fs-ext4 kmod-fs-f2fs kmod-rtc-pcf8563 losetup mkf2fs
endef
TARGET_DEVICES += ruijie_rg-mtfi-m520
define Device/surf_g-nat200
$(call Device/LegacyImage)
DEVICE_VENDOR := SURF
DEVICE_MODEL := G-NAT200
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
IMAGE_SIZE := 26624k
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \
pad-rootfs | append-metadata
endef
TARGET_DEVICES += surf_g-nat200
define Device/tplink_ad7200
$(call Device/TpSafeImage)
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := AD7200
DEVICE_VARIANT := v1/v2
DEVICE_ALT0_VENDOR := TP-Link
DEVICE_ALT0_MODEL := Talon AD7200
DEVICE_ALT0_VARIANT := v1/v2
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
TPLINK_BOARD_ID := AD7200
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-wil6210
endef
TARGET_DEVICES += tplink_ad7200
define Device/tplink_c2600
$(call Device/TpSafeImage)
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := Archer C2600
DEVICE_VARIANT := v1
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := c2600
SUPPORTED_DEVICES += c2600
TPLINK_BOARD_ID := C2600
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
endef
TARGET_DEVICES += tplink_c2600
define Device/tplink_vr2600v
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := Archer VR2600v
DEVICE_VARIANT := v1
KERNEL_SUFFIX := -uImage
KERNEL = kernel-bin | append-dtb | uImage none
KERNEL_NAME := zImage
IMAGE_SIZE := 12672k
SOC := qcom-ipq8064
BLOCKSIZE := 128k
PAGESIZE := 2048
BOARD_NAME := vr2600v
SUPPORTED_DEVICES += vr2600v
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | \
append-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += tplink_vr2600v
define Device/ubnt_unifi-ac-hd
$(call Device/FitImageLzma)
DEVICE_VENDOR := Ubiquiti
DEVICE_MODEL := UniFi AC HD
SOC := qcom-ipq8064
BLOCKSIZE := 64k
IMAGE_SIZE := 14784k
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct
IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | check-size | append-metadata
endef
TARGET_DEVICES += ubnt_unifi-ac-hd
define Device/zyxel_nbg6817
DEVICE_VENDOR := ZyXEL
DEVICE_MODEL := NBG6817
SOC := qcom-ipq8065
KERNEL_SIZE := 4096k
BLOCKSIZE := 64k
BOARD_NAME := nbg6817
RAS_BOARD := NBG6817
RAS_ROOTFS_SIZE := 20934k
RAS_VERSION := "V1.99(OWRT.9999)C0"
SUPPORTED_DEVICES += nbg6817
DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs \
kmod-fs-ext4 losetup
$(call Device/ZyXELImage)
endef
TARGET_DEVICES += zyxel_nbg6817

0
target/linux/ipq806x/patches-5.4/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch → target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch
View File

0
target/linux/ipq806x/patches-5.4/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch → target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch
View File

6
target/linux/ipq806x/patches-5.4/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch → target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch
View File

@ -33,8 +33,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -319,7 +319,7 @@ config ARCH_MULTIPLATFORM
depends on MMU
@@ -323,7 +323,7 @@ config ARCH_MULTIPLATFORM
select ARCH_SELECT_MEMORY_MODEL
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
- select AUTO_ZRELADDR
@ -44,7 +44,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
select GENERIC_CLOCKEVENTS
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -258,9 +258,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac
@@ -251,9 +251,11 @@ MACHINE := arch/arm/mach-$(word 1,$(mac
else
MACHINE :=
endif

2
target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch → target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch
View File

@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -67,7 +67,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i
@@ -61,7 +61,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m

22
target/linux/ipq806x/patches-5.4/0067-generic-Mangle-bootloader-s-kernel-arguments.patch → target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch
View File

@ -22,7 +22,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1824,6 +1824,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
@@ -1778,6 +1778,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
The command-line arguments provided by the boot loader will be
appended to the the device tree bootargs property.
@ -42,7 +42,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
config CMDLINE
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -4,6 +4,8 @@
@@ -5,6 +5,8 @@
#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
#define do_extend_cmdline 1
@ -51,7 +51,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
#else
#define do_extend_cmdline 0
#endif
@@ -67,6 +69,80 @@ static uint32_t get_cell_size(const void
@@ -69,6 +71,80 @@ static uint32_t get_cell_size(const void
return cell_size;
}
@ -132,7 +132,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
{
char cmdline[COMMAND_LINE_SIZE];
@@ -86,12 +162,21 @@ static void merge_fdt_bootargs(void *fdt
@@ -88,12 +164,21 @@ static void merge_fdt_bootargs(void *fdt
/* and append the ATAG_CMDLINE */
if (fdt_cmdline) {
@ -154,7 +154,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
}
*ptr = '\0';
@@ -166,7 +251,9 @@ int atags_to_fdt(void *atag_list, void *
@@ -168,7 +253,9 @@ int atags_to_fdt(void *atag_list, void *
else
setprop_string(fdt, "/chosen", "bootargs",
atag->u.cmdline.cmdline);
@ -165,7 +165,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
if (memcount >= sizeof(mem_reg_property)/4)
continue;
if (!atag->u.mem.size)
@@ -210,6 +297,10 @@ int atags_to_fdt(void *atag_list, void *
@@ -212,6 +299,10 @@ int atags_to_fdt(void *atag_list, void *
setprop(fdt, "/memory", "reg", mem_reg_property,
4 * memcount * memsize);
}
@ -178,9 +178,9 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
}
--- a/init/main.c
+++ b/init/main.c
@@ -102,6 +102,10 @@
#define CREATE_TRACE_POINTS
#include <trace/events/initcall.h>
@@ -108,6 +108,10 @@
#include <kunit/test.h>
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+#include <linux/of.h>
@ -189,8 +189,8 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
static int kernel_init(void *);
extern void init_IRQ(void);
@@ -630,6 +634,18 @@ asmlinkage __visible void __init start_k
pr_notice("Kernel command line: %s\n", boot_command_line);
@@ -903,6 +907,18 @@ asmlinkage __visible void __init __no_sa
pr_notice("Kernel command line: %s\n", saved_command_line);
/* parameters may set static keys */
jump_label_init();
+

12
target/linux/ipq806x/patches-5.4/0069-arm-boot-add-dts-files.patch → target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch
View File

@ -10,18 +10,18 @@ Signed-off-by: John Crispin <john@phrozen.org>
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -842,7 +842,32 @@ dtb-$(CONFIG_ARCH_QCOM) += \
@@ -909,8 +909,32 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
+ qcom-ipq8062-wg2600hp3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
+ qcom-ipq8064-c2600.dtb \
+ qcom-ipq8064-d7800.dtb \
+ qcom-ipq8064-db149.dtb \
+ qcom-ipq8064-ap161.dtb \
+ qcom-ipq8064-ea7500-v1.dtb \
+ qcom-ipq8064-e8350-v1.dtb \
+ qcom-ipq8064-ea8500.dtb \
+ qcom-ipq8064-g10.dtb \
+ qcom-ipq8064-g-nat200.dtb \
@ -33,13 +33,13 @@ Signed-off-by: John Crispin <john@phrozen.org>
+ qcom-ipq8064-wpq864.dtb \
+ qcom-ipq8064-wxr-2533dhp.dtb \
+ qcom-ipq8065-nbg6817.dtb \
+ qcom-ipq8065-core-518.dtb \
+ qcom-ipq8065-r7800.dtb \
+ qcom-ipq8065-xr500.dtb \
+ qcom-ipq8065-rac2v1a.dtb \
+ qcom-ipq8065-rt4230w-rev6.dtb \
+ qcom-ipq8065-rt4230w-rev9.3.dtb \
+ qcom-ipq8065-tr4400-v2.dtb \
+ qcom-ipq8065-xr500.dtb \
+ qcom-ipq8068-ecw5410.dtb \
+ qcom-ipq8068-mr42.dtb \
+ qcom-ipq8068-mr52.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \

2
target/linux/ipq806x/patches-5.4/0072-add-ipq806x-with-no-clocks.patch → target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -597,6 +597,7 @@ static const struct of_device_id qcom_sc
@@ -1268,6 +1268,7 @@ static const struct of_device_id qcom_sc
SCM_HAS_BUS_CLK)
},
{ .compatible = "qcom,scm-ipq4019" },

106
target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch → target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch
View File

@ -27,7 +27,15 @@
reg = <0x41000000 0x200000>;
no-map;
};
@@ -155,6 +155,7 @@
@@ -128,6 +128,7 @@
gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -155,6 +156,7 @@
function = "pcie3_rst";
drive-strength = <12>;
bias-disable;
@ -35,7 +43,15 @@
};
};
@@ -219,21 +220,23 @@
@@ -190,6 +192,7 @@
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
@@ -219,21 +222,23 @@
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
@ -61,7 +77,7 @@
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
@@ -251,7 +254,7 @@
@@ -251,7 +256,7 @@
syscon-tcsr = <&tcsr>;
@ -70,7 +86,16 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12490000 0x1000>,
<0x12480000 0x1000>;
@@ -326,7 +329,7 @@
@@ -261,7 +266,7 @@
status = "disabled";
};
- i2c@124a0000 {
+ gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,7 +331,7 @@
syscon-tcsr = <&tcsr>;
@ -79,7 +104,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x1000>,
<0x1a200000 0x1000>;
@@ -397,7 +400,7 @@
@@ -397,7 +402,7 @@
status = "disabled";
};
@ -88,15 +113,80 @@
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
@@ -430,6 +433,7 @@
@@ -430,13 +435,35 @@
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ tsens_calib: calib@400 {
+ reg = <0x400 0xb>;
+ };
+ tsens_backup: backup@410 {
+ reg = <0x410 0xb>;
+ };
+ speedbin_efuse: speedbin@0c0 {
+ reg = <0x0c0 0x4>;
+ };
};
gcc: clock-controller@900000 {
- compatible = "qcom,gcc-ipq8064";
+ compatible = "qcom,gcc-ipq8064", "syscon";
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+ #thermal-sensor-cells = <1>;
+ #qcom,sensors = <11>;
+ };
};
tcsr: syscon@1a400000 {
@@ -625,13 +629,13 @@
@@ -622,7 +649,7 @@
gmac0: ethernet@37000000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -645,7 +672,7 @@
gmac1: ethernet@37200000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -668,7 +695,7 @@
gmac2: ethernet@37400000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -691,7 +718,7 @@
gmac3: ethernet@37600000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -740,13 +767,13 @@
qcom,ee = <0>;
};
@ -113,7 +203,7 @@
status = "disabled";
compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
@@ -645,13 +649,12 @@
@@ -760,13 +787,12 @@
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;

590
target/linux/ipq806x/patches-5.4/083-ipq8064-dtsi-additions.patch → target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch
View File

@ -26,7 +26,7 @@
};
cpu1: cpu@1 {
@@ -38,11 +50,476 @@
@@ -38,14 +50,350 @@
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
@ -40,22 +40,22 @@
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
};
- L2: l2-cache {
- compatible = "cache";
- cache-level = <2>;
+ };
+
+ idle-states {
+ CPU_SPC: spc {
+ compatible = "qcom,idle-state-spc", "arm,idle-state";
+ compatible = "qcom,idle-state-spc";
+ status = "disabled";
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <3000>;
+ };
+ };
};
+ };
+
- L2: l2-cache {
- compatible = "cache";
- cache-level = <2>;
+ opp_table_l2: opp_table_l2 {
+ compatible = "operating-points-v2";
+
@ -78,19 +78,22 @@
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
+ };
+ };
+
+ opp_table0: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1000000>;
+ opp-microvolt-speed0-pvs1-v0 = <925000>;
+ opp-microvolt-speed0-pvs2-v0 = <875000>;
+ opp-microvolt-speed0-pvs3-v0 = <800000>;
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
@ -98,10 +101,10 @@
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <975000>;
+ opp-microvolt-speed0-pvs2-v0 = <925000>;
+ opp-microvolt-speed0-pvs3-v0 = <850000>;
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
@ -109,10 +112,10 @@
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1100000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000>;
+ opp-microvolt-speed0-pvs2-v0 = <995000>;
+ opp-microvolt-speed0-pvs3-v0 = <900000>;
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
@ -120,10 +123,10 @@
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1150000>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000>;
+ opp-microvolt-speed0-pvs3-v0 = <950000>;
+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
@ -131,27 +134,27 @@
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1200000>;
+ opp-microvolt-speed0-pvs1-v0 = <1125000>;
+ opp-microvolt-speed0-pvs2-v0 = <1075000>;
+ opp-microvolt-speed0-pvs3-v0 = <1000000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1250000>;
+ opp-microvolt-speed0-pvs1-v0 = <1175000>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000>;
+ opp-microvolt-speed0-pvs3-v0 = <1050000>;
+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
};
};
+ thermal-zones {
+ tsens_tz_sensor0 {
+ polling-delay-passive = <0>;
@ -159,28 +162,16 @@
+ thermal-sensors = <&tsens 0>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -191,28 +182,16 @@
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -223,28 +202,16 @@
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -255,28 +222,16 @@
+ thermal-sensors = <&tsens 3>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -287,28 +242,16 @@
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -319,28 +262,16 @@
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -351,28 +282,16 @@
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -383,28 +302,16 @@
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -415,28 +322,16 @@
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -447,28 +342,16 @@
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
+ };
@ -479,34 +362,25 @@
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ cpu-critical-hi {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical_high";
+ };
+
+ cpu-config-hi {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "configurable_hi";
+ type = "critical";
+ };
+
+ cpu-config-lo {
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "configurable_lo";
+ };
+
+ cpu-critical-low {
+ temperature = <0>;
+ hysteresis = <2000>;
+ type = "critical_low";
+ type = "hot";
+ };
+ };
};
};
@@ -93,6 +570,15 @@
+ };
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x0>;
@@ -93,6 +441,15 @@
};
};
@ -522,7 +396,7 @@
firmware {
scm {
compatible = "qcom,scm-ipq806x", "qcom,scm";
@@ -120,6 +606,95 @@
@@ -120,6 +477,78 @@
reg-names = "lpass-lpaif";
};
@ -537,23 +411,6 @@
+ operating-points-v2 = <&opp_table_l2>;
+ };
+
+ qfprom: qfprom@700000 {
+ compatible = "qcom,qfprom", "syscon";
+ reg = <0x700000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+ tsens_calib: calib@400 {
+ reg = <0x400 0xb>;
+ };
+ tsens_backup: backup@410 {
+ reg = <0x410 0xb>;
+ };
+ speedbin_efuse: speedbin@0c0 {
+ reg = <0x0c0 0x4>;
+ };
+ };
+
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x108000 0x1000>;
@ -618,7 +475,7 @@
qcom_pinmux: pinmux@800000 {
compatible = "qcom,ipq8064-pinctrl";
reg = <0x800000 0x4000>;
@@ -159,6 +734,15 @@
@@ -160,6 +589,15 @@
};
};
@ -634,7 +491,7 @@
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -168,6 +752,53 @@
@@ -169,6 +607,53 @@
};
};
@ -688,7 +545,7 @@
leds_pins: leds_pins {
mux {
pins = "gpio7", "gpio8", "gpio9",
@@ -229,6 +860,17 @@
@@ -231,6 +716,17 @@
clock-output-names = "acpu1_aux";
};
@ -706,7 +563,7 @@
saw0: regulator@2089000 {
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
@@ -241,6 +883,17 @@
@@ -243,6 +739,52 @@
regulator;
};
@ -720,27 +577,100 @@
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
+ };
+
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <1>;
+ reg = <0x12440000 0x100>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -436,6 +1089,15 @@
#power-domain-cells = <1>;
@@ -368,6 +910,33 @@
};
};
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+ reg = <0x900000 0x3680>;
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ gsbi6: gsbi@16500000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <6>;
+ reg = <0x16500000 0x100>;
+ clocks = <&gcc GSBI6_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi6_i2c: i2c@16580000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-ipq8064", "syscon";
reg = <0x1a400000 0x100>;
@@ -448,6 +1110,95 @@
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
@@ -389,6 +958,19 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
sata_phy: sata-phy@1b400000 {
@@ -478,6 +1060,95 @@
#reset-cells = <1>;
};
@ -751,7 +681,7 @@
+
+ hs_phy_0: hs_phy_0 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x110f8800 0x30>;
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
@ -759,17 +689,17 @@
+
+ ss_phy_0: ss_phy_0 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x110f8830 0x30>;
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_0: usb3@110f8800 {
+ usb3_0: usb3@100f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x110f8800 0x8000>;
+ reg = <0x100f8800 0x8000>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
@ -780,10 +710,10 @@
+
+ status = "disabled";
+
+ dwc3_0: dwc3@11000000 {
+ dwc3_0: dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0xcd00>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x10000000 0xcd00>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
@ -793,7 +723,7 @@
+
+ hs_phy_1: hs_phy_1 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x100f8800 0x30>;
+ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
@ -801,17 +731,17 @@
+
+ ss_phy_1: ss_phy_1 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x100f8830 0x30>;
+ reg = <0x110f8830 0x30>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_1: usb3@100f8800 {
+ usb3_1: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x100f8800 0x8000>;
+ reg = <0x110f8800 0x8000>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
@ -822,10 +752,10 @@
+
+ status = "disabled";
+
+ dwc3_1: dwc3@10000000 {
+ dwc3_1: dwc3@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x11000000 0xcd00>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
@ -836,8 +766,8 @@
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
@@ -601,6 +1352,167 @@
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
@@ -739,6 +1410,59 @@
status = "disabled";
};
+ adm_dma: dma@18300000 {
@ -879,22 +809,6 @@
+ #size-cells = <0>;
+ };
+
+ nss_common: syscon@03000000 {
+ compatible = "syscon";
+ reg = <0x03000000 0x0000FFFF>;
+ };
+
+ qsgmii_csr: syscon@1bb00000 {
+ compatible = "syscon";
+ reg = <0x1bb00000 0x000001FF>;
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <7>;
+ snps,rd_osr_lmt = <7>;
+ snps,blen = <16 0 0 0 0 0 0>;
+ };
+
+ mdio0: mdio@37000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
@ -908,103 +822,11 @@
+
+ status = "disabled";
+ };
+
+ gmac0: ethernet@37000000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ reg = <0x37000000 0x200000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE1_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE1_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
+ gmac1: ethernet@37200000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ reg = <0x37200000 0x200000>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE2_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE2_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
+ gmac2: ethernet@37400000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ reg = <0x37400000 0x200000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE3_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE3_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
+ gmac3: ethernet@37600000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
+ reg = <0x37600000 0x200000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,pbl = <32>;
+ snps,aal = <1>;
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE4_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE4_RESET>;
+ reset-names = "stmmaceth";
+
+ status = "disabled";
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
@@ -676,4 +1588,17 @@
@@ -814,4 +1538,17 @@
};
};
};

0
target/linux/ipq806x/patches-5.4/084-ipq8064-v1.0-dtsi-cleanup.patch → target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch
View File

0
target/linux/ipq806x/patches-5.4/085-ipq8064-v1.0-dtsi-additions.patch → target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch
View File

145
target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch Normal file
View File

@ -0,0 +1,145 @@
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -24,73 +24,6 @@
device_type = "memory";
};
- mdio0: mdio-0 {
- status = "okay";
- compatible = "virtual,mdio-gpio";
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch0: switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
-
- dsa,member = <0 0>;
-
- pinctrl-0 = <&sw0_reset_pin>;
- pinctrl-names = "default";
-
- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- switch0cpu: port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii-id";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "sw1";
- };
-
- port@2 {
- reg = <2>;
- label = "sw2";
- };
-
- port@3 {
- reg = <3>;
- label = "sw3";
- };
-
- port@4 {
- reg = <4>;
- label = "sw4";
- };
-
- port@5 {
- reg = <5>;
- label = "sw5";
- };
- };
- };
- };
-
mdio1: mdio-1 {
status = "okay";
compatible = "virtual,mdio-gpio";
@@ -216,6 +149,68 @@
};
};
+&mdio0 {
+ status = "okay";
+
+ pinctrl-0 = <&mdio0_pins>;
+ pinctrl-names = "default";
+
+ switch0: switch@10 {
+ compatible = "qca,qca8337";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsa,member = <0 0>;
+
+ pinctrl-0 = <&sw0_reset_pin>;
+ pinctrl-names = "default";
+
+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
+ reg = <0x10>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch0cpu: port@0 {
+ reg = <0>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "sw1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "sw2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "sw3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "sw4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "sw5";
+ };
+ };
+ };
+};
+
&gmac0 {
status = "okay";

4
target/linux/ipq806x/patches-5.4/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch → target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch
View File

@ -21,7 +21,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
};
struct qcom_cpufreq_drv {
@@ -250,6 +251,7 @@ static const struct qcom_cpufreq_match_d
@@ -253,6 +254,7 @@ static const struct qcom_cpufreq_match_d
static const struct qcom_cpufreq_match_data match_data_krait = {
.get_version = qcom_cpufreq_krait_name_version,
@ -29,7 +29,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
};
static const char *qcs404_genpd_names[] = { "cpr", NULL };
@@ -385,6 +387,19 @@ static int qcom_cpufreq_probe(struct pla
@@ -389,6 +391,19 @@ static int qcom_cpufreq_probe(struct pla
}
}

99
target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch Normal file
View File

@ -0,0 +1,99 @@
From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sun, 7 Feb 2021 16:52:56 +0100
Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag
Some flag are missing from the original code.
These clk can't be set using the protected-clock proprities as they
cause the malfunction of the serial interface.
These clks are needed for the rpm interface to work proprely or the
cpu regulators starts to fail as soon as they are disabled by the
kernel.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -65,6 +65,7 @@ static struct clk_pll pll3 = {
.parent_names = (const char *[]){ "pxo" },
.num_parents = 1,
.ops = &clk_pll_ops,
+ .flags = CLK_IS_CRITICAL,
},
};
@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =
.parent_names = (const char *[]){ "gsbi4_qup_src" },
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =
.parent_names = (const char *[]){ "gsbi7_qup_src" },
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
+ .flags = CLK_IGNORE_UNUSED,
},
},
};
@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
+ .flags = CLK_SET_RATE_GATE,
},
}
};
@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr
.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
+ CLK_IGNORE_UNUSED,
},
},
};
@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr
.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
+ CLK_IGNORE_UNUSED,
},
},
};

59
target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch Normal file
View File

@ -0,0 +1,59 @@
From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sun, 7 Feb 2021 17:00:07 +0100
Subject: [PATCH 2/4] ipq806x: lcc: add missing reset
Add missing reset for ipq806x lcc clk
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/lcc-ipq806x.c | 8 ++++++++
include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 +
2 files changed, 9 insertions(+)
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -12,6 +12,7 @@
#include <linux/of_device.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
+#include <linux/reset-controller.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
@@ -22,6 +23,7 @@
#include "clk-branch.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
+#include "reset.h"
static struct clk_pll pll4 = {
.l_reg = 0x4,
@@ -39,6 +41,10 @@ static struct clk_pll pll4 = {
},
};
+static const struct qcom_reset_map lcc_ipq806x_resets[] = {
+ [LCC_PCM_RESET] = { 0x54, 13 },
+};
+
static const struct pll_config pll4_config = {
.l = 0xf,
.m = 0x91,
@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq
.config = &lcc_ipq806x_regmap_config,
.clks = lcc_ipq806x_clks,
.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
+ .resets = lcc_ipq806x_resets,
+ .num_resets = ARRAY_SIZE(lcc_ipq806x_resets),
};
static const struct of_device_id lcc_ipq806x_match_table[] = {
--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -19,4 +19,5 @@
#define SPDIF_CLK 10
#define AHBIX_CLK 11
+#define LCC_PCM_RESET 0
#endif

57
target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch Normal file
View File

@ -0,0 +1,57 @@
From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sun, 7 Feb 2021 17:08:16 +0100
Subject: [PATCH 3/4] clk: qcom: krait: add missing enable disable
Add missing enable disable mux function. Add extra check to
div2_round_rate.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -73,7 +73,25 @@ static u8 krait_mux_get_parent(struct cl
return clk_mux_val_to_index(hw, mux->parent_map, 0, sel);
}
+static int krait_mux_enable(struct clk_hw *hw)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+
+ __krait_mux_set_sel(mux, mux->en_mask);
+
+ return 0;
+}
+
+static void krait_mux_disable(struct clk_hw *hw)
+{
+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
+
+ __krait_mux_set_sel(mux, mux->safe_sel);
+}
+
const struct clk_ops krait_mux_clk_ops = {
+ .enable = krait_mux_enable,
+ .disable = krait_mux_disable,
.set_parent = krait_mux_set_parent,
.get_parent = krait_mux_get_parent,
.determine_rate = __clk_mux_determine_rate_closest,
@@ -84,8 +102,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
- return DIV_ROUND_UP(*parent_rate, 2);
+ struct clk_hw *hw_parent = clk_hw_get_parent(hw);
+
+ if (hw_parent) {
+ *parent_rate = clk_hw_round_rate(hw_parent, rate * 2);
+ return DIV_ROUND_UP(*parent_rate, 2);
+ } else
+ return -1;
}
static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,

289
target/linux/ipq806x/patches-5.4/999-02-nss-core-and-crypto-clocks.patch → target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch
View File

@ -1,51 +1,21 @@
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -240,7 +240,7 @@
#define PLL14 232
#define PLL14_VOTE 233
#define PLL18 234
-#define CE5_SRC 235
+#define CE5_A_CLK 235
#define CE5_H_CLK 236
#define CE5_CORE_CLK 237
#define CE3_SLEEP_CLK 238
@@ -283,5 +283,9 @@
#define EBI2_AON_CLK 281
#define NSSTCM_CLK_SRC 282
#define NSSTCM_CLK 283
+#define NSS_CORE_CLK 284 /* Virtual */
+#define CE5_A_CLK_SRC 285
+#define CE5_H_CLK_SRC 286
+#define CE5_CORE_CLK_SRC 287
#endif
--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -163,5 +163,10 @@
#define NSS_CAL_PRBS_RST_N_RESET 154
#define NSS_LCKDT_RST_N_RESET 155
#define NSS_SRDS_N_RESET 156
+#define CRYPTO_ENG1_RESET 157
+#define CRYPTO_ENG2_RESET 158
+#define CRYPTO_ENG3_RESET 159
+#define CRYPTO_ENG4_RESET 160
+#define CRYPTO_AHB_RESET 161
#endif
From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sun, 7 Feb 2021 17:23:38 +0100
Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
Add missing clk and reset needed for nss additional core and crypto
engine.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +-
include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +
3 files changed, 259 insertions(+), 1 deletion(-)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -24,6 +24,10 @@
#include "clk-branch.h"
#include "clk-hfpll.h"
#include "reset.h"
+#include <linux/regulator/nss-volt-ipq806x.h>
+
+/* NSS safe parent index which will be used during NSS PLL rate change */
+static int gcc_ipq806x_nss_safe_parent;
static struct clk_pll pll0 = {
.l_reg = 0x30c4,
@@ -222,7 +226,9 @@ static struct clk_regmap pll14_vote = {
@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
static struct pll_freq_tbl pll18_freq_tbl[] = {
NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
@ -55,7 +25,7 @@
};
static struct clk_pll pll18 = {
@@ -244,6 +250,22 @@ static struct clk_pll pll18 = {
@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
},
};
@ -78,7 +48,7 @@
enum {
P_PXO,
P_PLL8,
@@ -252,6 +274,7 @@ enum {
@@ -253,6 +271,7 @@ enum {
P_CXO,
P_PLL14,
P_PLL18,
@ -86,7 +56,7 @@
};
static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -319,6 +342,42 @@ static const char * const gcc_pxo_pll8_p
@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p
"pll18",
};
@ -129,7 +99,15 @@
static struct freq_tbl clk_tbl_gsbi_uart[] = {
{ 1843200, P_PLL8, 2, 6, 625 },
{ 3686400, P_PLL8, 2, 12, 625 },
@@ -2643,7 +2702,9 @@ static const struct freq_tbl clk_tbl_nss
@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 48000000, P_PLL8, 4, 1, 2 },
+ { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */
{ 64000000, P_PLL8, 3, 1, 2 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss
{ 110000000, P_PLL18, 1, 1, 5 },
{ 275000000, P_PLL18, 2, 0, 0 },
{ 550000000, P_PLL18, 1, 0, 0 },
@ -139,7 +117,7 @@
{ }
};
@@ -2753,6 +2814,319 @@ static struct clk_dyn_rcg ubi32_core2_sr
@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
},
};
@ -322,144 +300,11 @@
+ },
+ },
+};
+
+static int nss_core_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int ret;
+
+ /*
+ * When ramping up voltage, it needs to be done first. This ensures that
+ * the volt required will be available when you step up the frequency.
+ */
+ ret = nss_ramp_voltage(rate, true);
+ if (ret)
+ return ret;
+
+ ret = clk_dyn_rcg_ops.set_rate(&ubi32_core1_src_clk.clkr.hw, rate,
+ parent_rate);
+ if (ret)
+ return ret;
+
+ ret = clk_dyn_rcg_ops.set_rate(&ubi32_core2_src_clk.clkr.hw, rate,
+ parent_rate);
+
+ if (ret)
+ return ret;
+
+ /*
+ * When ramping down voltage, it needs to be set first. This ensures
+ * that the volt required will be available until you step down the
+ * frequency.
+ */
+ ret = nss_ramp_voltage(rate, false);
+
+ return ret;
+}
+
+static int
+nss_core_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate, u8 index)
+{
+ int ret;
+
+ /*
+ * When ramping up voltage needs to be done first. This ensures that
+ * the voltage required will be available when you step up the
+ * frequency.
+ */
+ ret = nss_ramp_voltage(rate, true);
+ if (ret)
+ return ret;
+
+ ret = clk_dyn_rcg_ops.set_rate_and_parent(
+ &ubi32_core1_src_clk.clkr.hw, rate, parent_rate, index);
+ if (ret)
+ return ret;
+
+ ret = clk_dyn_rcg_ops.set_rate_and_parent(
+ &ubi32_core2_src_clk.clkr.hw, rate, parent_rate, index);
+
+ if (ret)
+ return ret;
+
+ /*
+ * When ramping down voltage needs to be done last. This ensures that
+ * the voltage required will be available when you step down the
+ * frequency.
+ */
+ ret = nss_ramp_voltage(rate, false);
+
+ return ret;
+}
+
+static int nss_core_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_dyn_rcg_ops.determine_rate(&ubi32_core1_src_clk.clkr.hw,
+ req);
+}
+
+static unsigned long
+nss_core_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ return clk_dyn_rcg_ops.recalc_rate(&ubi32_core1_src_clk.clkr.hw,
+ parent_rate);
+}
+
+static u8 nss_core_clk_get_parent(struct clk_hw *hw)
+{
+ return clk_dyn_rcg_ops.get_parent(&ubi32_core1_src_clk.clkr.hw);
+}
+
+static int nss_core_clk_set_parent(struct clk_hw *hw, u8 i)
+{
+ int ret;
+ struct clk_dyn_rcg *rcg;
+ struct freq_tbl f = { 200000000, P_PLL0, 2, 1, 2 };
+
+ /* P_PLL0 is 800 Mhz which needs to be divided for 200 Mhz */
+ if (i == gcc_ipq806x_nss_safe_parent) {
+ rcg = to_clk_dyn_rcg(&ubi32_core1_src_clk.clkr.hw);
+ clk_dyn_configure_bank(rcg, &f);
+
+ rcg = to_clk_dyn_rcg(&ubi32_core2_src_clk.clkr.hw);
+ clk_dyn_configure_bank(rcg, &f);
+
+ return 0;
+ }
+
+ ret = clk_dyn_rcg_ops.set_parent(&ubi32_core1_src_clk.clkr.hw, i);
+ if (ret)
+ return ret;
+
+ return clk_dyn_rcg_ops.set_parent(&ubi32_core2_src_clk.clkr.hw, i);
+}
+
+static const struct clk_ops clk_ops_nss_core = {
+ .set_rate = nss_core_clk_set_rate,
+ .set_rate_and_parent = nss_core_clk_set_rate_and_parent,
+ .determine_rate = nss_core_clk_determine_rate,
+ .recalc_rate = nss_core_clk_recalc_rate,
+ .get_parent = nss_core_clk_get_parent,
+ .set_parent = nss_core_clk_set_parent,
+};
+
+/* Virtual clock for nss core clocks */
+static struct clk_regmap nss_core_clk = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_core_clk",
+ .ops = &clk_ops_nss_core,
+ .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .num_parents = 5,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static struct clk_regmap *gcc_ipq806x_clks[] = {
[PLL0] = &pll0.clkr,
[PLL0_VOTE] = &pll0_vote,
@@ -2760,6 +3134,7 @@ static struct clk_regmap *gcc_ipq806x_cl
@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl
[PLL4_VOTE] = &pll4_vote,
[PLL8] = &pll8.clkr,
[PLL8_VOTE] = &pll8_vote,
@ -467,11 +312,7 @@
[PLL14] = &pll14.clkr,
[PLL14_VOTE] = &pll14_vote,
[PLL18] = &pll18.clkr,
@@ -2871,9 +3246,16 @@ static struct clk_regmap *gcc_ipq806x_cl
[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
[NSSTCM_CLK] = &nss_tcm_clk.clkr,
+ [NSS_CORE_CLK] = &nss_core_clk,
@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl
[PLL9] = &hfpll0.clkr,
[PLL10] = &hfpll1.clkr,
[PLL12] = &hfpll_l2.clkr,
@ -484,7 +325,7 @@
};
static const struct qcom_reset_map gcc_ipq806x_resets[] = {
@@ -3005,6 +3387,11 @@ static const struct qcom_reset_map gcc_i
@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i
[GMAC_CORE3_RESET] = { 0x3cfc, 0 },
[GMAC_CORE4_RESET] = { 0x3d1c, 0 },
[GMAC_AHB_RESET] = { 0x3e24, 0 },
@ -496,40 +337,36 @@
[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
@@ -3080,6 +3467,12 @@ static int gcc_ipq806x_probe(struct plat
if (!regmap)
return -ENODEV;
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -240,7 +240,7 @@
#define PLL14 232
#define PLL14_VOTE 233
#define PLL18 234
-#define CE5_SRC 235
+#define CE5_A_CLK 235
#define CE5_H_CLK 236
#define CE5_CORE_CLK 237
#define CE3_SLEEP_CLK 238
@@ -283,5 +283,8 @@
#define EBI2_AON_CLK 281
#define NSSTCM_CLK_SRC 282
#define NSSTCM_CLK 283
+#define CE5_A_CLK_SRC 285
+#define CE5_H_CLK_SRC 286
+#define CE5_CORE_CLK_SRC 287
#endif
--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -163,5 +163,10 @@
#define NSS_CAL_PRBS_RST_N_RESET 154
#define NSS_LCKDT_RST_N_RESET 155
#define NSS_SRDS_N_RESET 156
+#define CRYPTO_ENG1_RESET 157
+#define CRYPTO_ENG2_RESET 158
+#define CRYPTO_ENG3_RESET 159
+#define CRYPTO_ENG4_RESET 160
+#define CRYPTO_AHB_RESET 161
+ gcc_ipq806x_nss_safe_parent = qcom_find_src_index(&nss_core_clk.hw,
+ gcc_pxo_pll8_pll14_pll18_pll0_map,
+ P_PLL0);
+ if (gcc_ipq806x_nss_safe_parent < 0)
+ return gcc_ipq806x_nss_safe_parent;
+
/* Setup PLL18 static bits */
regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
regmap_write(regmap, 0x31b0, 0x3080);
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -805,6 +805,11 @@ static int clk_dyn_rcg_set_rate_and_pare
return __clk_dyn_rcg_set_rate(hw, rate);
}
+void clk_dyn_configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
+{
+ configure_bank(rcg, f);
+}
+
const struct clk_ops clk_rcg_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -173,4 +173,7 @@ struct clk_rcg_dfs_data {
extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
const struct clk_rcg_dfs_data *rcgs,
size_t len);
+
+extern void clk_dyn_configure_bank(struct clk_dyn_rcg *rcg,
+ const struct freq_tbl *f);
#endif

12
target/linux/ipq806x/patches-5.4/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch → target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch
View File

@ -29,7 +29,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -155,6 +155,18 @@ config ARM_QCOM_CPUFREQ_HW
@@ -150,6 +150,18 @@ config ARM_QCOM_CPUFREQ_HW
The driver implements the cpufreq interface for this HW engine.
Say Y if you want to support CPUFreq HW.
@ -48,7 +48,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
config ARM_RASPBERRYPI_CPUFREQ
tristate "Raspberry Pi cpufreq support"
depends on CLK_RASPBERRYPI || COMPILE_TEST
@@ -338,4 +350,4 @@ config ARM_PXA2xx_CPUFREQ
@@ -339,4 +351,4 @@ config ARM_PXA2xx_CPUFREQ
help
This add the CPUFreq driver support for Intel PXA2xx SOCs.
@ -57,7 +57,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
\ No newline at end of file
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2
@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o
obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o
@ -65,8 +65,8 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
@@ -87,6 +88,7 @@ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += te
obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
@@ -86,6 +87,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += te
obj-$(CONFIG_ARM_TEGRA194_CPUFREQ) += tegra194-cpufreq.o
obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o
obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
+obj-$(CONFIG_ARM_KRAIT_CPUFREQ) += krait-cpufreq.o
@ -387,7 +387,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+ policy->cpuinfo.transition_latency = transition_latency;
+ policy->dvfs_possible_from_any_cpu = true;
+
+ dev_pm_opp_of_register_em(policy->cpus);
+ dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
+
+ return 0;
+

0
target/linux/ipq806x/patches-5.4/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch → target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch
View File

0
target/linux/ipq806x/patches-5.4/098-3-add-fab-scaling-support-with-cpufreq.patch → target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch
View File

6
target/linux/ipq806x/patches-5.4/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch → target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch
View File

@ -203,7 +203,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
host->use_ecc = true;
clear_bam_transaction(nandc);
@@ -2781,6 +2840,7 @@ static int qcom_nand_host_init_and_regis
@@ -2805,6 +2864,7 @@ static int qcom_nand_host_init_and_regis
struct nand_chip *chip = &host->chip;
struct mtd_info *mtd = nand_to_mtd(chip);
struct device *dev = nandc->dev;
@ -211,7 +211,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
int ret;
ret = of_property_read_u32(dn, "reg", &host->cs);
@@ -2841,6 +2901,17 @@ static int qcom_nand_host_init_and_regis
@@ -2865,6 +2925,17 @@ static int qcom_nand_host_init_and_regis
if (ret)
nand_cleanup(chip);
@ -229,7 +229,7 @@ Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
return ret;
}
@@ -3001,6 +3072,7 @@ static int qcom_nandc_remove(struct plat
@@ -3030,6 +3101,7 @@ static int qcom_nandc_remove(struct plat
static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,

0
target/linux/ipq806x/patches-5.4/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch → target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch
View File

0
target/linux/ipq806x/patches-5.4/100-v5.11-dmaengine-qcom-add_ADM_driver.patch → target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch
View File

10
target/linux/ipq806x/patches-5.4/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch → target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch
View File

@ -19,9 +19,9 @@ Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadha
--- a/drivers/mtd/parsers/Kconfig
+++ b/drivers/mtd/parsers/Kconfig
@@ -205,6 +205,14 @@ config MTD_SERCOMM_PARTS
offsets, which may differ from device to device depending on the
number and location of bad blocks on NAND.
@@ -211,6 +211,14 @@ config MTD_REDBOOT_PARTS_READONLY
endif # MTD_REDBOOT_PARTS
+config MTD_QCOMSMEM_PARTS
+ tristate "Qualcomm SMEM NAND flash partition parser"
@ -36,8 +36,8 @@ Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadha
depends on MTD && OF
--- a/drivers/mtd/parsers/Makefile
+++ b/drivers/mtd/parsers/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_MTD_PARSER_TRX) += parser_
obj-$(CONFIG_MTD_SERCOMM_PARTS) += scpart.o
@@ -14,4 +14,5 @@ obj-$(CONFIG_MTD_PARSER_TPLINK_SAFELOADE
obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o
obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o
obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o
+obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o

6
target/linux/ipq806x/patches-5.4/100-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch → target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch
View File

@ -18,7 +18,7 @@
#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
@@ -241,6 +252,36 @@ static void ipq806x_gmac_fix_mac_speed(v
@@ -242,6 +253,36 @@ static void ipq806x_gmac_fix_mac_speed(v
ipq806x_gmac_set_speed(gmac, speed);
}
@ -55,7 +55,7 @@
static int ipq806x_gmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
@@ -249,6 +290,7 @@ static int ipq806x_gmac_probe(struct pla
@@ -250,6 +291,7 @@ static int ipq806x_gmac_probe(struct pla
struct ipq806x_gmac *gmac;
int val;
int err;
@ -63,7 +63,7 @@
val = stmmac_get_platform_resources(pdev, &stmmac_res);
if (val)
@@ -338,6 +380,17 @@ static int ipq806x_gmac_probe(struct pla
@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla
0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);

0
target/linux/ipq806x/patches-5.4/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch → target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
View File

285
target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch Normal file
View File

@ -0,0 +1,285 @@
From 5c7d1181056feef0b58fb2f556f55e170ba5b479 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sat, 25 Jul 2020 19:14:59 +0200
Subject: [PATCH 01/10] drivers: thermal: tsens: Add VER_0 tsens version
VER_0 is used to describe device based on tsens version before v0.1.
These device are devices based on msm8960 for example apq8064 or
ipq806x.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
---
drivers/thermal/qcom/tsens.c | 150 ++++++++++++++++++++++++++++-------
drivers/thermal/qcom/tsens.h | 4 +-
2 files changed, 124 insertions(+), 30 deletions(-)
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -12,6 +12,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/regmap.h>
@@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int
dev_dbg(priv->dev, "[%u] %s: no violation: %d\n",
hw_id, __func__, temp);
}
+
+ if (tsens_version(priv) < VER_0_1) {
+ /* Constraint: There is only 1 interrupt control register for all
+ * 11 temperature sensor. So monitoring more than 1 sensor based
+ * on interrupts will yield inconsistent result. To overcome this
+ * issue we will monitor only sensor 0 which is the master sensor.
+ */
+ break;
+ }
}
return IRQ_HANDLED;
@@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor
int high_val, low_val, cl_high, cl_low;
u32 hw_id = s->hw_id;
+ if (tsens_version(priv) < VER_0_1) {
+ /* Pre v0.1 IP had a single register for each type of interrupt
+ * and thresholds
+ */
+ hw_id = 0;
+ }
+
dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
hw_id, __func__, low, high);
@@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct ts
u32 valid;
int ret;
- ret = regmap_field_read(priv->rf[valid_idx], &valid);
- if (ret)
- return ret;
- while (!valid) {
- /* Valid bit is 0 for 6 AHB clock cycles.
- * At 19.2MHz, 1 AHB clock is ~60ns.
- * We should enter this loop very, very rarely.
- */
- ndelay(400);
+ /* VER_0 doesn't have VALID bit */
+ if (tsens_version(priv) >= VER_0_1) {
ret = regmap_field_read(priv->rf[valid_idx], &valid);
if (ret)
return ret;
+ while (!valid) {
+ /* Valid bit is 0 for 6 AHB clock cycles.
+ * At 19.2MHz, 1 AHB clock is ~60ns.
+ * We should enter this loop very, very rarely.
+ */
+ ndelay(400);
+ ret = regmap_field_read(priv->rf[valid_idx], &valid);
+ if (ret)
+ return ret;
+ }
}
/* Valid bit is set, OK to read the temperature */
@@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_s
{
struct tsens_priv *priv = s->priv;
int hw_id = s->hw_id;
- int last_temp = 0, ret;
+ int last_temp = 0, ret, trdy;
+ unsigned long timeout;
- ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
- if (ret)
- return ret;
+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+ do {
+ if (tsens_version(priv) == VER_0) {
+ ret = regmap_field_read(priv->rf[TRDY], &trdy);
+ if (ret)
+ return ret;
+ if (!trdy)
+ continue;
+ }
- *temp = code_to_degc(last_temp, s) * 1000;
+ ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
+ if (ret)
+ return ret;
- return 0;
+ *temp = code_to_degc(last_temp, s) * 1000;
+
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -ETIMEDOUT;
}
#ifdef CONFIG_DEBUG_FS
@@ -738,19 +772,34 @@ int __init init_common(struct tsens_priv
priv->tm_offset = 0x1000;
}
- res = platform_get_resource(op, IORESOURCE_MEM, 0);
- tm_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(tm_base)) {
- ret = PTR_ERR(tm_base);
- goto err_put_device;
+ if (tsens_version(priv) >= VER_0_1) {
+ res = platform_get_resource(op, IORESOURCE_MEM, 0);
+ tm_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(tm_base)) {
+ ret = PTR_ERR(tm_base);
+ goto err_put_device;
+ }
+
+ priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
+ } else { /* VER_0 share the same gcc regs using a syscon */
+ struct device *parent = priv->dev->parent;
+
+ if (parent)
+ priv->tm_map = syscon_node_to_regmap(parent->of_node);
}
- priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
- if (IS_ERR(priv->tm_map)) {
- ret = PTR_ERR(priv->tm_map);
+ if (IS_ERR_OR_NULL(priv->tm_map)) {
+ if (!priv->tm_map)
+ ret = -ENODEV;
+ else
+ ret = PTR_ERR(priv->tm_map);
goto err_put_device;
}
+ /* VER_0 have only tm_map */
+ if (!priv->srot_map)
+ priv->srot_map = priv->tm_map;
+
if (tsens_version(priv) > VER_0_1) {
for (i = VER_MAJOR; i <= VER_STEP; i++) {
priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
@@ -771,6 +820,10 @@ int __init init_common(struct tsens_priv
ret = PTR_ERR(priv->rf[TSENS_EN]);
goto err_put_device;
}
+ /* in VER_0 TSENS need to be explicitly enabled */
+ if (tsens_version(priv) == VER_0)
+ regmap_field_write(priv->rf[TSENS_EN], 1);
+
ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
if (ret)
goto err_put_device;
@@ -793,6 +846,19 @@ int __init init_common(struct tsens_priv
goto err_put_device;
}
+ priv->rf[TSENS_SW_RST] =
+ devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]);
+ if (IS_ERR(priv->rf[TSENS_SW_RST])) {
+ ret = PTR_ERR(priv->rf[TSENS_SW_RST]);
+ goto err_put_device;
+ }
+
+ priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]);
+ if (IS_ERR(priv->rf[TRDY])) {
+ ret = PTR_ERR(priv->rf[TRDY]);
+ goto err_put_device;
+ }
+
/* This loop might need changes if enum regfield_ids is reordered */
for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
for (i = 0; i < priv->feat->max_sensors; i++) {
@@ -808,7 +874,7 @@ int __init init_common(struct tsens_priv
}
}
- if (priv->feat->crit_int) {
+ if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) {
/* Loop might need changes if enum regfield_ids is reordered */
for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {
for (i = 0; i < priv->feat->max_sensors; i++) {
@@ -846,7 +912,11 @@ int __init init_common(struct tsens_priv
}
spin_lock_init(&priv->ul_lock);
- tsens_enable_irq(priv);
+
+ /* VER_0 interrupt doesn't need to be enabled */
+ if (tsens_version(priv) >= VER_0_1)
+ tsens_enable_irq(priv);
+
tsens_debug_init(op);
err_put_device:
@@ -951,10 +1021,19 @@ static int tsens_register_irq(struct tse
if (irq == -ENXIO)
ret = 0;
} else {
- ret = devm_request_threaded_irq(&pdev->dev, irq,
- NULL, thread_fn,
- IRQF_ONESHOT,
- dev_name(&pdev->dev), priv);
+ /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */
+ if (tsens_version(priv) == VER_0)
+ ret = devm_request_threaded_irq(&pdev->dev, irq,
+ thread_fn, NULL,
+ IRQF_TRIGGER_RISING,
+ dev_name(&pdev->dev),
+ priv);
+ else
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ thread_fn, IRQF_ONESHOT,
+ dev_name(&pdev->dev),
+ priv);
+
if (ret)
dev_err(&pdev->dev, "%s: failed to get irq\n",
__func__);
@@ -983,6 +1062,19 @@ static int tsens_register(struct tsens_p
priv->ops->enable(priv, i);
}
+ /* VER_0 require to set MIN and MAX THRESH
+ * These 2 regs are set using the:
+ * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C
+ * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C
+ */
+ if (tsens_version(priv) < VER_0_1) {
+ regmap_field_write(priv->rf[CRIT_THRESH_0],
+ tsens_mC_to_hw(priv->sensor, 120000));
+
+ regmap_field_write(priv->rf[CRIT_THRESH_1],
+ tsens_mC_to_hw(priv->sensor, 0));
+ }
+
ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
if (ret < 0)
return ret;
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -13,6 +13,7 @@
#define CAL_DEGC_PT2 120
#define SLOPE_FACTOR 1000
#define SLOPE_DEFAULT 3200
+#define TIMEOUT_US 100
#define THRESHOLD_MAX_ADC_CODE 0x3ff
#define THRESHOLD_MIN_ADC_CODE 0x0
@@ -25,7 +26,8 @@ struct tsens_priv;
/* IP version numbers in ascending order */
enum tsens_ver {
- VER_0_1 = 0,
+ VER_0 = 0,
+ VER_0_1,
VER_1_X,
VER_2_X,
};

28
target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch Normal file
View File

@ -0,0 +1,28 @@
From efa0d50a6c5ec7619371dfe4d3e6ca54b73787d5 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 25 Nov 2020 16:47:21 +0100
Subject: [PATCH 02/10] drivers: thermal: tsens: Don't hardcode sensor slope
Function compute_intercept_slope hardcode the sensor slope to
SLOPE_DEFAULT. Change this and use the default value only if a slope is
not defined. This is needed for tsens VER_0 that has a hardcoded slope
table.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsen
"%s: sensor%d - data_point1:%#x data_point2:%#x\n",
__func__, i, p1[i], p2[i]);
- priv->sensor[i].slope = SLOPE_DEFAULT;
+ if (!priv->sensor[i].slope)
+ priv->sensor[i].slope = SLOPE_DEFAULT;
if (mode == TWO_PT_CALIB) {
/*
* slope (m) = adc_code2 - adc_code1 (y2 - y1)/

119
target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch Normal file
View File

@ -0,0 +1,119 @@
From 6bac2e2fa36c2d7c304768a689d8b73155b90aa2 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 25 Nov 2020 17:15:51 +0100
Subject: [PATCH 03/10] drivers: thermal: tsens: Convert msm8960 to reg_field
Convert msm9860 driver to reg_field to use the init_common
function.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 80 ++++++++++++++++++++++++++++++-
1 file changed, 79 insertions(+), 1 deletion(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -51,11 +51,22 @@
#define MIN_LIMIT_TH 0x0
#define MAX_LIMIT_TH 0xff
-#define S0_STATUS_ADDR 0x3628
#define INT_STATUS_ADDR 0x363c
#define TRDY_MASK BIT(7)
#define TIMEOUT_US 100
+#define S0_STATUS_OFF 0x3628
+#define S1_STATUS_OFF 0x362c
+#define S2_STATUS_OFF 0x3630
+#define S3_STATUS_OFF 0x3634
+#define S4_STATUS_OFF 0x3638
+#define S5_STATUS_OFF 0x3664 /* Sensors 5-10 found on apq8064/msm8960 */
+#define S6_STATUS_OFF 0x3668
+#define S7_STATUS_OFF 0x366c
+#define S8_STATUS_OFF 0x3670
+#define S9_STATUS_OFF 0x3674
+#define S10_STATUS_OFF 0x3678
+
static int suspend_8960(struct tsens_priv *priv)
{
int ret;
@@ -269,6 +280,71 @@ static int get_temp_8960(const struct ts
return -ETIMEDOUT;
}
+static struct tsens_features tsens_8960_feat = {
+ .ver_major = VER_0,
+ .crit_int = 0,
+ .adc = 1,
+ .srot_split = 0,
+ .max_sensors = 11,
+};
+
+static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {
+ /* ----- SROT ------ */
+ /* No VERSION information */
+
+ /* CNTL */
+ [TSENS_EN] = REG_FIELD(CNTL_ADDR, 0, 0),
+ [TSENS_SW_RST] = REG_FIELD(CNTL_ADDR, 1, 1),
+ /* 8960 has 5 sensors, 8660 has 11, we only handle 5 */
+ [SENSOR_EN] = REG_FIELD(CNTL_ADDR, 3, 7),
+
+ /* ----- TM ------ */
+ /* INTERRUPT ENABLE */
+ /* NO INTERRUPT ENABLE */
+
+ /* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */
+ [LOW_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 0, 7),
+ [UP_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 8, 15),
+ /* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield
+ * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp
+ * MIN_THRESH_0 -> CRIT_THRESH_1
+ * MAX_THRESH_0 -> CRIT_THRESH_0
+ */
+ [CRIT_THRESH_1] = REG_FIELD(THRESHOLD_ADDR, 16, 23),
+ [CRIT_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 24, 31),
+
+ /* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */
+ /* 1 == clear, 0 == normal operation */
+ [LOW_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 9, 9),
+ [UP_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 10, 10),
+
+ /* NO CRITICAL INTERRUPT SUPPORT on 8960 */
+
+ /* Sn_STATUS */
+ [LAST_TEMP_0] = REG_FIELD(S0_STATUS_OFF, 0, 7),
+ [LAST_TEMP_1] = REG_FIELD(S1_STATUS_OFF, 0, 7),
+ [LAST_TEMP_2] = REG_FIELD(S2_STATUS_OFF, 0, 7),
+ [LAST_TEMP_3] = REG_FIELD(S3_STATUS_OFF, 0, 7),
+ [LAST_TEMP_4] = REG_FIELD(S4_STATUS_OFF, 0, 7),
+ [LAST_TEMP_5] = REG_FIELD(S5_STATUS_OFF, 0, 7),
+ [LAST_TEMP_6] = REG_FIELD(S6_STATUS_OFF, 0, 7),
+ [LAST_TEMP_7] = REG_FIELD(S7_STATUS_OFF, 0, 7),
+ [LAST_TEMP_8] = REG_FIELD(S8_STATUS_OFF, 0, 7),
+ [LAST_TEMP_9] = REG_FIELD(S9_STATUS_OFF, 0, 7),
+ [LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0, 7),
+
+ /* No VALID field on 8960 */
+ /* TSENS_INT_STATUS bits: 1 == threshold violated */
+ [MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0),
+ [LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1),
+ [UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2),
+ /* No CRITICAL field on 8960 */
+ [MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3),
+
+ /* TRDY: 1=ready, 0=in progress */
+ [TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7),
+};
+
static const struct tsens_ops ops_8960 = {
.init = init_8960,
.calibrate = calibrate_8960,
@@ -282,4 +358,6 @@ static const struct tsens_ops ops_8960 =
struct tsens_plat_data data_8960 = {
.num_sensors = 11,
.ops = &ops_8960,
+ .feat = &tsens_8960_feat,
+ .fields = tsens_8960_regfields,
};

81
target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch Normal file
View File

@ -0,0 +1,81 @@
From c04f98a496929f75d75c65115d5717423c3d0634 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 25 Nov 2020 17:16:36 +0100
Subject: [PATCH 04/10] drivers: thermal: tsens: Use init_common for msm8960
Use init_common and drop custom init for msm8960.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------
1 file changed, 1 insertion(+), 51 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -173,56 +173,6 @@ static void disable_8960(struct tsens_pr
regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
}
-static int init_8960(struct tsens_priv *priv)
-{
- int ret, i;
- u32 reg_cntl;
-
- priv->tm_map = dev_get_regmap(priv->dev, NULL);
- if (!priv->tm_map)
- return -ENODEV;
-
- /*
- * The status registers for each sensor are discontiguous
- * because some SoCs have 5 sensors while others have more
- * but the control registers stay in the same place, i.e
- * directly after the first 5 status registers.
- */
- for (i = 0; i < priv->num_sensors; i++) {
- if (i >= 5)
- priv->sensor[i].status = S0_STATUS_ADDR + 40;
- priv->sensor[i].status += i * 4;
- }
-
- reg_cntl = SW_RST;
- ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
- if (ret)
- return ret;
-
- if (priv->num_sensors > 1) {
- reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
- reg_cntl &= ~SW_RST;
- ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
- CONFIG_MASK, CONFIG);
- } else {
- reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
- reg_cntl &= ~CONFIG_MASK_8660;
- reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
- }
-
- reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
- ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
- if (ret)
- return ret;
-
- reg_cntl |= EN;
- ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
- if (ret)
- return ret;
-
- return 0;
-}
-
static int calibrate_8960(struct tsens_priv *priv)
{
int i;
@@ -346,7 +296,7 @@ static const struct reg_field tsens_8960
};
static const struct tsens_ops ops_8960 = {
- .init = init_8960,
+ .init = init_common,
.calibrate = calibrate_8960,
.get_temp = get_temp_8960,
.enable = enable_8960,

66
target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch Normal file
View File

@ -0,0 +1,66 @@
From b3e8bd33b84a6b6c863bd1733bd15b5f1483b8ab Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 25 Nov 2020 17:06:55 +0100
Subject: [PATCH 05/10] drivers: thermal: tsens: Fix bug in sensor enable for
msm8960
Device based on tsens VER_0 contains a hardware bug that results in some
problem with sensor enablement. Sensor id 6-11 can't be enabled
selectively and all of them must be enabled in one step.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -27,9 +27,9 @@
#define EN BIT(0)
#define SW_RST BIT(1)
#define SENSOR0_EN BIT(3)
+#define MEASURE_PERIOD BIT(18)
#define SLP_CLK_ENA BIT(26)
#define SLP_CLK_ENA_8660 BIT(24)
-#define MEASURE_PERIOD 1
#define SENSOR0_SHIFT 3
/* INT_STATUS_ADDR bitmasks */
@@ -126,17 +126,34 @@ static int resume_8960(struct tsens_priv
static int enable_8960(struct tsens_priv *priv, int id)
{
int ret;
- u32 reg, mask;
+ u32 reg, mask = BIT(id);
ret = regmap_read(priv->tm_map, CNTL_ADDR, &reg);
if (ret)
return ret;
- mask = BIT(id + SENSOR0_SHIFT);
+ /* HARDWARE BUG:
+ * On platforms with more than 6 sensors, all remaining sensors
+ * must be enabled together, otherwise undefined results are expected.
+ * (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver,
+ * all the sensors are enabled in one step hence this bug is not
+ * triggered.
+ */
+ if (id > 5)
+ mask = GENMASK(10, 6);
+
+ mask <<= SENSOR0_SHIFT;
+
+ /* Sensors already enabled. Skip. */
+ if ((reg & mask) == mask)
+ return 0;
+
ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);
if (ret)
return ret;
+ reg |= MEASURE_PERIOD;
+
if (priv->num_sensors > 1)
reg |= mask | SLP_CLK_ENA | EN;
else

109
target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch Normal file
View File

@ -0,0 +1,109 @@
From 1ff9f982051759e0387e8c7e793b49c48eae291d Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 25 Nov 2020 17:11:05 +0100
Subject: [PATCH 06/10] drivers: thermal: tsens: Replace custom 8960 apis with
generic apis
Rework calibrate function to use common function. Derive the offset from
a missing hardcoded slope table and the data from the nvmem calib
efuses.
Drop custom get_temp function and use generic api.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 56 +++++++++----------------------
1 file changed, 15 insertions(+), 41 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -67,6 +67,13 @@
#define S9_STATUS_OFF 0x3674
#define S10_STATUS_OFF 0x3678
+/* Original slope - 200 to compensate mC to C inaccuracy */
+static u32 tsens_msm8960_slope[] = {
+ 976, 976, 954, 976,
+ 911, 932, 932, 999,
+ 932, 999, 932
+ };
+
static int suspend_8960(struct tsens_priv *priv)
{
int ret;
@@ -194,9 +201,7 @@ static int calibrate_8960(struct tsens_p
{
int i;
char *data;
-
- ssize_t num_read = priv->num_sensors;
- struct tsens_sensor *s = priv->sensor;
+ u32 p1[11];
data = qfprom_read(priv->dev, "calib");
if (IS_ERR(data))
@@ -204,49 +209,18 @@ static int calibrate_8960(struct tsens_p
if (IS_ERR(data))
return PTR_ERR(data);
- for (i = 0; i < num_read; i++, s++)
- s->offset = data[i];
+ for (i = 0; i < priv->num_sensors; i++) {
+ p1[i] = data[i];
+ priv->sensor[i].slope = tsens_msm8960_slope[i];
+ }
+
+ compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB);
kfree(data);
return 0;
}
-/* Temperature on y axis and ADC-code on x-axis */
-static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)
-{
- int slope, offset;
-
- slope = thermal_zone_get_slope(s->tzd);
- offset = CAL_MDEGC - slope * s->offset;
-
- return adc_code * slope + offset;
-}
-
-static int get_temp_8960(const struct tsens_sensor *s, int *temp)
-{
- int ret;
- u32 code, trdy;
- struct tsens_priv *priv = s->priv;
- unsigned long timeout;
-
- timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
- do {
- ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
- if (ret)
- return ret;
- if (!(trdy & TRDY_MASK))
- continue;
- ret = regmap_read(priv->tm_map, s->status, &code);
- if (ret)
- return ret;
- *temp = code_to_mdegC(code, s);
- return 0;
- } while (time_before(jiffies, timeout));
-
- return -ETIMEDOUT;
-}
-
static struct tsens_features tsens_8960_feat = {
.ver_major = VER_0,
.crit_int = 0,
@@ -315,7 +289,7 @@ static const struct reg_field tsens_8960
static const struct tsens_ops ops_8960 = {
.init = init_common,
.calibrate = calibrate_8960,
- .get_temp = get_temp_8960,
+ .get_temp = get_temp_common,
.enable = enable_8960,
.disable = disable_8960,
.suspend = suspend_8960,

65
target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch Normal file
View File

@ -0,0 +1,65 @@
From 5716a61239c6ac9ceb137e825e93c3aea06c4634 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Fri, 19 Mar 2021 00:48:23 +0100
Subject: [PATCH 07/10] drivers: thermal: tsens: Drop unused define for msm8960
Drop unused define for msm8960 replaced by generic api and reg_field.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens-8960.c | 24 +-----------------------
1 file changed, 1 insertion(+), 23 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -10,8 +10,6 @@
#include <linux/thermal.h>
#include "tsens.h"
-#define CAL_MDEGC 30000
-
#define CONFIG_ADDR 0x3640
#define CONFIG_ADDR_8660 0x3620
/* CONFIG_ADDR bitmasks */
@@ -21,39 +19,19 @@
#define CONFIG_SHIFT_8660 28
#define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660)
-#define STATUS_CNTL_ADDR_8064 0x3660
#define CNTL_ADDR 0x3620
/* CNTL_ADDR bitmasks */
#define EN BIT(0)
#define SW_RST BIT(1)
-#define SENSOR0_EN BIT(3)
+
#define MEASURE_PERIOD BIT(18)
#define SLP_CLK_ENA BIT(26)
#define SLP_CLK_ENA_8660 BIT(24)
#define SENSOR0_SHIFT 3
-/* INT_STATUS_ADDR bitmasks */
-#define MIN_STATUS_MASK BIT(0)
-#define LOWER_STATUS_CLR BIT(1)
-#define UPPER_STATUS_CLR BIT(2)
-#define MAX_STATUS_MASK BIT(3)
-
#define THRESHOLD_ADDR 0x3624
-/* THRESHOLD_ADDR bitmasks */
-#define THRESHOLD_MAX_LIMIT_SHIFT 24
-#define THRESHOLD_MIN_LIMIT_SHIFT 16
-#define THRESHOLD_UPPER_LIMIT_SHIFT 8
-#define THRESHOLD_LOWER_LIMIT_SHIFT 0
-
-/* Initial temperature threshold values */
-#define LOWER_LIMIT_TH 0x50
-#define UPPER_LIMIT_TH 0xdf
-#define MIN_LIMIT_TH 0x0
-#define MAX_LIMIT_TH 0xff
#define INT_STATUS_ADDR 0x363c
-#define TRDY_MASK BIT(7)
-#define TIMEOUT_US 100
#define S0_STATUS_OFF 0x3628
#define S1_STATUS_OFF 0x362c

26
target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch Normal file
View File

@ -0,0 +1,26 @@
From 0d0c22a59bf2672b57e23da9a9ea743e91b71f54 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Sat, 25 Jul 2020 19:55:57 +0200
Subject: [PATCH 08/10] drivers: thermal: tsens: Add support for ipq8064-tsens
Add support for tsens present in ipq806x SoCs based on generic msm8960
tsens driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens.c | 3 +++
1 file changed, 3 insertions(+)
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -968,6 +968,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t
static const struct of_device_id tsens_table[] = {
{
+ .compatible = "qcom,ipq8064-tsens",
+ .data = &data_8960,
+ }, {
.compatible = "qcom,msm8916-tsens",
.data = &data_8916,
}, {

112
target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch Normal file
View File

@ -0,0 +1,112 @@
From ac369071920d427dd484cf74cddba2774bba45f5 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Thu, 9 Jul 2020 22:35:54 +0200
Subject: [PATCH 09/10] dt-bindings: thermal: tsens: Document ipq8064 bindings
Document the use of bindings used for msm8960 tsens based devices.
msm8960 use the same gcc regs and is set as a child of the qcom gcc.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/thermal/qcom-tsens.yaml | 56 ++++++++++++++++---
1 file changed, 48 insertions(+), 8 deletions(-)
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -19,6 +19,11 @@ description: |
properties:
compatible:
oneOf:
+ - description: msm9860 TSENS based
+ items:
+ - enum:
+ - qcom,ipq8064-tsens
+
- description: v0.1 of TSENS
items:
- enum:
@@ -73,7 +78,9 @@ properties:
maxItems: 2
items:
- const: calib
- - const: calib_sel
+ - enum:
+ - calib_backup
+ - calib_sel
"#qcom,sensors":
description:
@@ -88,12 +95,20 @@ properties:
Number of cells required to uniquely identify the thermal sensors. Since
we have multiple sensors this is set to 1
+required:
+ - compatible
+ - interrupts
+ - interrupt-names
+ - "#thermal-sensor-cells"
+ - "#qcom,sensors"
+
allOf:
- if:
properties:
compatible:
contains:
enum:
+ - qcom,ipq8064-tsens
- qcom,msm8916-tsens
- qcom,msm8974-tsens
- qcom,msm8976-tsens
@@ -114,19 +129,44 @@ allOf:
interrupt-names:
minItems: 2
-required:
- - compatible
- - reg
- - "#qcom,sensors"
- - interrupts
- - interrupt-names
- - "#thermal-sensor-cells"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,tsens-v0_1
+ - qcom,tsens-v1
+ - qcom,tsens-v2
+
+ then:
+ required:
+ - reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
+ // Example msm9860 based SoC (ipq8064):
+ gcc: clock-controller {
+
+ /* ... */
+
+ tsens: thermal-sensor {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 1 (legacy: for pre v1 IP):
tsens1: thermal-sensor@900000 {
compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";

32
target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch Normal file
View File

@ -0,0 +1,32 @@
From 68e720ed73c8f038c8c500e4c49c1e65a993a448 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Tue, 6 Apr 2021 04:45:31 +0200
Subject: [PATCH 10/10] drivers: thermal: tsens: Fix wrong slope on msm-8960
Some user using some stats with the old legacy implementation and the
new implementation using the compute_intercept_slope reported an offset
of 3C. Fix the slope table to reflect the original temp.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/thermal/qcom/tsens-8960.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -45,11 +45,11 @@
#define S9_STATUS_OFF 0x3674
#define S10_STATUS_OFF 0x3678
-/* Original slope - 200 to compensate mC to C inaccuracy */
+/* Original slope - 350 to compensate mC to C inaccuracy */
static u32 tsens_msm8960_slope[] = {
- 976, 976, 954, 976,
- 911, 932, 932, 999,
- 932, 999, 932
+ 826, 826, 804, 826,
+ 761, 782, 782, 849,
+ 782, 849, 782
};
static int suspend_8960(struct tsens_priv *priv)

41
target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch Normal file
View File

@ -0,0 +1,41 @@
From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 19 Apr 2021 03:01:53 +0200
Subject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with
successful probe
calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
double or a wrong init of the debugfs information. Init debugfs only
with successful probe fixing warning about directory already present.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
if (tsens_version(priv) >= VER_0_1)
tsens_enable_irq(priv);
- tsens_debug_init(op);
-
err_put_device:
put_device(&op->dev);
return ret;
@@ -1161,7 +1159,12 @@ static int tsens_probe(struct platform_d
}
}
- return tsens_register(priv);
+ ret = tsens_register(priv);
+
+ if (!ret)
+ tsens_debug_init(pdev);
+
+ return ret;
}
static int tsens_remove(struct platform_device *pdev)

54
target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch Normal file
View File

@ -0,0 +1,54 @@
From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Mon, 19 Apr 2021 03:08:37 +0200
Subject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init
function
Simplify debugfs init function.
- Add check for existing dev directory.
- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was
incorrectly reported)
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
---
drivers/thermal/qcom/tsens.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
return ret;
seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
} else {
- seq_puts(s, "0.1.0\n");
+ seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
}
return 0;
@@ -704,21 +704,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
static void tsens_debug_init(struct platform_device *pdev)
{
struct tsens_priv *priv = platform_get_drvdata(pdev);
- struct dentry *root, *file;
- root = debugfs_lookup("tsens", NULL);
- if (!root)
+ priv->debug_root = debugfs_lookup("tsens", NULL);
+ if (!priv->debug_root)
priv->debug_root = debugfs_create_dir("tsens", NULL);
- else
- priv->debug_root = root;
- file = debugfs_lookup("version", priv->debug_root);
- if (!file)
+ if (!debugfs_lookup("version", priv->debug_root))
debugfs_create_file("version", 0444, priv->debug_root,
pdev, &dbg_version_fops);
/* A directory for each instance of the TSENS IP */
- priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
+ priv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root);
debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
}
#else

75
target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch Normal file
View File

@ -0,0 +1,75 @@
From e67f325e9cd67562b761e884680c0fec03a6f404 Mon Sep 17 00:00:00 2001
From: Matthew Hagan <mnhagan88@gmail.com>
Date: Tue, 8 Jun 2021 19:59:06 +0100
Subject: net: stmmac: explicitly deassert GMAC_AHB_RESET
We are currently assuming that GMAC_AHB_RESET will already be deasserted
by the bootloader. However if this has not been done, probing of the GMAC
will fail. To remedy this we must ensure GMAC_AHB_RESET has been deasserted
prior to probing.
v2 changes:
- remove NULL condition check for stmmac_ahb_rst in stmmac_main.c
- unwrap dev_err() message in stmmac_main.c
- add PTR_ERR() around plat->stmmac_ahb_rst in stmmac_platform.c
v3 changes:
- add error pointer to dev_err() output
- add reset_control_assert(stmmac_ahb_rst) in stmmac_dvr_remove
- revert PTR_ERR() around plat->stmmac_ahb_rst since this is performed
on the returned value of ret by the calling function
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++++
include/linux/stmmac.h | 1 +
3 files changed, 12 insertions(+)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -5052,6 +5052,10 @@ int stmmac_dvr_probe(struct device *devi
reset_control_reset(priv->plat->stmmac_rst);
}
+ ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
+ if (ret == -ENOTSUPP)
+ dev_err(priv->device, "unable to bring out of ahb reset\n");
+
/* Init MAC and get the capabilities */
ret = stmmac_hw_init(priv);
if (ret)
@@ -5260,6 +5264,7 @@ int stmmac_dvr_remove(struct device *dev
phylink_destroy(priv->phylink);
if (priv->plat->stmmac_rst)
reset_control_assert(priv->plat->stmmac_rst);
+ reset_control_assert(priv->plat->stmmac_ahb_rst);
pm_runtime_put(dev);
pm_runtime_disable(dev);
if (priv->hw->pcs != STMMAC_PCS_TBI &&
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -616,6 +616,12 @@ stmmac_probe_config_dt(struct platform_d
plat->stmmac_rst = NULL;
}
+ plat->stmmac_ahb_rst = devm_reset_control_get_optional_shared(
+ &pdev->dev, "ahb");
+ if (IS_ERR(plat->stmmac_ahb_rst))
+ if (PTR_ERR(plat->stmmac_ahb_rst) == -EPROBE_DEFER)
+ goto error_hw_init;
+
return plat;
error_hw_init:
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -192,6 +192,7 @@ struct plat_stmmacenet_data {
unsigned int clk_ref_rate;
s32 ptp_max_adj;
struct reset_control *stmmac_rst;
+ struct reset_control *stmmac_ahb_rst;
struct stmmac_axi *axi;
int has_gmac4;
bool has_sun8i;

64
target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch Normal file
View File

@ -0,0 +1,64 @@
From f95c4c56d65225a537a2d88735fde7ec4d37641d Mon Sep 17 00:00:00 2001
From: Matthew Hagan <mnhagan88@gmail.com>
Date: Sat, 5 Jun 2021 18:35:38 +0100
Subject: ARM: dts: qcom: add ahb reset to ipq806x-gmac
Add GMAC_AHB_RESET to the resets property of each gmac node.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Link: https://lore.kernel.org/r/20210605173546.4102455-2-mnhagan88@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1335,8 +1335,9 @@
clocks = <&gcc GMAC_CORE1_CLK>;
clock-names = "stmmaceth";
- resets = <&gcc GMAC_CORE1_RESET>;
- reset-names = "stmmaceth";
+ resets = <&gcc GMAC_CORE1_RESET>,
+ <&gcc GMAC_AHB_RESET>;
+ reset-names = "stmmaceth", "ahb";
status = "disabled";
};
@@ -1358,8 +1359,9 @@
clocks = <&gcc GMAC_CORE2_CLK>;
clock-names = "stmmaceth";
- resets = <&gcc GMAC_CORE2_RESET>;
- reset-names = "stmmaceth";
+ resets = <&gcc GMAC_CORE2_RESET>,
+ <&gcc GMAC_AHB_RESET>;
+ reset-names = "stmmaceth", "ahb";
status = "disabled";
};
@@ -1381,8 +1383,9 @@
clocks = <&gcc GMAC_CORE3_CLK>;
clock-names = "stmmaceth";
- resets = <&gcc GMAC_CORE3_RESET>;
- reset-names = "stmmaceth";
+ resets = <&gcc GMAC_CORE3_RESET>,
+ <&gcc GMAC_AHB_RESET>;
+ reset-names = "stmmaceth", "ahb";
status = "disabled";
};
@@ -1404,8 +1407,9 @@
clocks = <&gcc GMAC_CORE4_CLK>;
clock-names = "stmmaceth";
- resets = <&gcc GMAC_CORE4_RESET>;
- reset-names = "stmmaceth";
+ resets = <&gcc GMAC_CORE4_RESET>,
+ <&gcc GMAC_AHB_RESET>;
+ reset-names = "stmmaceth", "ahb";
status = "disabled";
};

4
target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch → target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch
View File

@ -2,7 +2,7 @@ From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
@ -12,7 +12,7 @@ Subject: SoC: add qualcomm syscon
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -176,6 +176,13 @@ config QCOM_SOCINFO
@@ -191,6 +191,13 @@ config QCOM_SOCINFO
Say yes here to support the Qualcomm socinfo driver, providing
information about the SoC to user space.

4
target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch → target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1837,6 +1837,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
@@ -1791,6 +1791,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL
endchoice
@ -19,7 +19,7 @@
+++ b/drivers/of/fdt.c
@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns
if (p != NULL && l > 0)
strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));
+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
+ * device tree option of chosen/bootargs-override. This is

40
target/linux/ipq806x/patches-5.4/0030-clk-Disable-i2c-device-on-gsbi4.patch
View File

@ -1,40 +0,0 @@
From 0c974b87829e007dc4fae94e20d488204e20e662 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 9 Mar 2017 08:16:10 +0100
Subject: [PATCH 30/69] clk: Disable i2c device on gsbi4
This patch was not annotated and comes from the v4.4 tree.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -365,7 +365,7 @@ static struct clk_rcg gsbi1_uart_src = {
.parent_names = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -383,7 +383,7 @@ static struct clk_branch gsbi1_uart_clk
},
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -961,6 +961,7 @@ static struct clk_branch gsbi1_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_h_clk",
.ops = &clk_branch_ops,
+ .flags = CLK_IGNORE_UNUSED,
},
},
};

29
target/linux/ipq806x/patches-5.4/0059-ARM-cpuidle-Add-cpuidle-support-for-QCOM-cpus.patch
View File

@ -1,29 +0,0 @@
From 04ca10340f1b4d92e849724d322a7ca225d11539 Mon Sep 17 00:00:00 2001
From: Lina Iyer <lina.iyer@linaro.org>
Date: Wed, 25 Mar 2015 14:25:29 -0600
Subject: [PATCH 59/69] ARM: cpuidle: Add cpuidle support for QCOM cpus
Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
drivers/cpuidle/Kconfig.arm | 7 +++++++
1 file changed, 7 insertions(+)
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -86,3 +86,10 @@ config ARM_MVEBU_V7_CPUIDLE
depends on ARCH_MVEBU && !ARM64
help
Select this to enable cpuidle on Armada 370, 38x and XP processors.
+
+config ARM_QCOM_CPUIDLE
+ bool "CPU Idle Driver for QCOM processors"
+ depends on ARCH_QCOM
+ select ARM_CPUIDLE
+ help
+ Select this to enable cpuidle on QCOM processors.

616
target/linux/ipq806x/patches-5.4/0063-1-ipq806x-tsens-driver.patch
View File

@ -1,616 +0,0 @@
From 3302e1e1a3cfa4e67fda2a61d6f0c42205d40932 Mon Sep 17 00:00:00 2001
From: Rajith Cherian <rajith@codeaurora.org>
Date: Tue, 14 Feb 2017 18:30:43 +0530
Subject: [PATCH] ipq8064: tsens: Base tsens driver for IPQ8064
Add TSENS driver template to support IPQ8064.
This is a base file copied from tsens-8960.c
Change-Id: I47c573fdfa2d898243c6a6ba952d1632f91391f7
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
ipq8064: tsens: TSENS driver support for IPQ8064
Support for IPQ8064 tsens driver. The driver works
with the thermal framework. The driver overrides the
following fucntionalities:
1. Get current temperature.
2. Get/Set trip temperatures.
3. Enabled/Disable trip points.
4. ISR for threshold generated interrupt.
5. Notify userspace when trip points are hit.
Change-Id: I8bc7204fd627d10875ab13fc1de8cb6c2ed7a918
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
---
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -2,5 +2,5 @@
obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \
- tsens-8960.o tsens-v2.o tsens-v1.o
+ tsens-8960.o tsens-v2.o tsens-v1.o tsens-ipq8064.o
obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
--- /dev/null
+++ b/drivers/thermal/qcom/tsens-ipq8064.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/regmap.h>
+#include <linux/thermal.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include "tsens.h"
+
+#define CAL_MDEGC 30000
+
+#define CONFIG_ADDR 0x3640
+/* CONFIG_ADDR bitmasks */
+#define CONFIG 0x9b
+#define CONFIG_MASK 0xf
+#define CONFIG_SHIFT 0
+
+#define STATUS_CNTL_8064 0x3660
+#define CNTL_ADDR 0x3620
+/* CNTL_ADDR bitmasks */
+#define EN BIT(0)
+#define SW_RST BIT(1)
+#define SENSOR0_EN BIT(3)
+#define SLP_CLK_ENA BIT(26)
+#define MEASURE_PERIOD 1
+#define SENSOR0_SHIFT 3
+
+/* INT_STATUS_ADDR bitmasks */
+#define MIN_STATUS_MASK BIT(0)
+#define LOWER_STATUS_CLR BIT(1)
+#define UPPER_STATUS_CLR BIT(2)
+#define MAX_STATUS_MASK BIT(3)
+
+#define THRESHOLD_ADDR 0x3624
+/* THRESHOLD_ADDR bitmasks */
+#define THRESHOLD_MAX_CODE 0x20000
+#define THRESHOLD_MIN_CODE 0
+#define THRESHOLD_MAX_LIMIT_SHIFT 24
+#define THRESHOLD_MIN_LIMIT_SHIFT 16
+#define THRESHOLD_UPPER_LIMIT_SHIFT 8
+#define THRESHOLD_LOWER_LIMIT_SHIFT 0
+#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_MAX_LIMIT_SHIFT)
+#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_MIN_LIMIT_SHIFT)
+#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_UPPER_LIMIT_SHIFT)
+#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \
+ THRESHOLD_LOWER_LIMIT_SHIFT)
+
+/* Initial temperature threshold values */
+#define LOWER_LIMIT_TH 0x9d /* 95C */
+#define UPPER_LIMIT_TH 0xa6 /* 105C */
+#define MIN_LIMIT_TH 0x0
+#define MAX_LIMIT_TH 0xff
+
+#define S0_STATUS_ADDR 0x3628
+#define STATUS_ADDR_OFFSET 2
+#define SENSOR_STATUS_SIZE 4
+#define INT_STATUS_ADDR 0x363c
+#define TRDY_MASK BIT(7)
+#define TIMEOUT_US 100
+
+#define TSENS_EN BIT(0)
+#define TSENS_SW_RST BIT(1)
+#define TSENS_ADC_CLK_SEL BIT(2)
+#define SENSOR0_EN BIT(3)
+#define SENSOR1_EN BIT(4)
+#define SENSOR2_EN BIT(5)
+#define SENSOR3_EN BIT(6)
+#define SENSOR4_EN BIT(7)
+#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \
+ SENSOR2_EN | SENSOR3_EN | SENSOR4_EN)
+#define TSENS_8064_SENSOR5_EN BIT(8)
+#define TSENS_8064_SENSOR6_EN BIT(9)
+#define TSENS_8064_SENSOR7_EN BIT(10)
+#define TSENS_8064_SENSOR8_EN BIT(11)
+#define TSENS_8064_SENSOR9_EN BIT(12)
+#define TSENS_8064_SENSOR10_EN BIT(13)
+#define TSENS_8064_SENSORS_EN (SENSORS_EN | \
+ TSENS_8064_SENSOR5_EN | \
+ TSENS_8064_SENSOR6_EN | \
+ TSENS_8064_SENSOR7_EN | \
+ TSENS_8064_SENSOR8_EN | \
+ TSENS_8064_SENSOR9_EN | \
+ TSENS_8064_SENSOR10_EN)
+
+#define TSENS_8064_SEQ_SENSORS 5
+#define TSENS_8064_S4_S5_OFFSET 40
+#define TSENS_FACTOR 1
+
+/* Trips: from very hot to very cold */
+enum tsens_trip_type {
+ TSENS_TRIP_STAGE3 = 0,
+ TSENS_TRIP_STAGE2,
+ TSENS_TRIP_STAGE1,
+ TSENS_TRIP_STAGE0,
+ TSENS_TRIP_NUM,
+};
+
+u32 tsens_8064_slope[] = {
+ 1176, 1176, 1154, 1176,
+ 1111, 1132, 1132, 1199,
+ 1132, 1199, 1132
+ };
+
+/* Temperature on y axis and ADC-code on x-axis */
+static inline int code_to_degC(u32 adc_code, const struct tsens_sensor *s)
+{
+ int degcbeforefactor, degc;
+
+ degcbeforefactor = (adc_code * s->slope) + s->offset;
+
+ if (degcbeforefactor == 0)
+ degc = degcbeforefactor;
+ else if (degcbeforefactor > 0)
+ degc = (degcbeforefactor + TSENS_FACTOR/2)
+ / TSENS_FACTOR;
+ else
+ degc = (degcbeforefactor - TSENS_FACTOR/2)
+ / TSENS_FACTOR;
+
+ return degc;
+}
+
+static int degC_to_code(int degC, const struct tsens_sensor *s)
+{
+ int code = ((degC * TSENS_FACTOR - s->offset) + (s->slope/2))
+ / s->slope;
+
+ if (code > THRESHOLD_MAX_CODE)
+ code = THRESHOLD_MAX_CODE;
+ else if (code < THRESHOLD_MIN_CODE)
+ code = THRESHOLD_MIN_CODE;
+ return code;
+}
+
+static int suspend_ipq8064(struct tsens_priv *priv)
+{
+ int ret;
+ unsigned int mask;
+ struct regmap *map = priv->tm_map;
+
+ ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
+ if (ret)
+ return ret;
+
+ mask = SLP_CLK_ENA | EN;
+
+ ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int resume_ipq8064(struct tsens_priv *priv)
+{
+ int ret;
+ struct regmap *map = priv->tm_map;
+
+ ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void notify_uspace_tsens_fn(struct work_struct *work)
+{
+ struct tsens_sensor *s = container_of(work, struct tsens_sensor,
+ notify_work);
+
+ sysfs_notify(&s->tzd->device.kobj, NULL, "type");
+}
+
+static void tsens_scheduler_fn(struct work_struct *work)
+{
+ struct tsens_priv *priv = container_of(work, struct tsens_priv,
+ tsens_work);
+ unsigned int threshold, threshold_low, code, reg, sensor, mask;
+ unsigned int sensor_addr;
+ bool upper_th_x, lower_th_x;
+ int adc_code, ret;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
+ if (ret)
+ return;
+ reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR;
+ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, reg);
+ if (ret)
+ return;
+
+ mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR);
+ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold);
+ if (ret)
+ return;
+ threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK)
+ >> THRESHOLD_LOWER_LIMIT_SHIFT;
+ threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK)
+ >> THRESHOLD_UPPER_LIMIT_SHIFT;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
+ if (ret)
+ return;
+
+ ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor);
+ if (ret)
+ return;
+ sensor &= (uint32_t) TSENS_8064_SENSORS_EN;
+ sensor >>= SENSOR0_SHIFT;
+
+ /* Constraint: There is only 1 interrupt control register for all
+ * 11 temperature sensor. So monitoring more than 1 sensor based
+ * on interrupts will yield inconsistent result. To overcome this
+ * issue we will monitor only sensor 0 which is the master sensor.
+ */
+
+ /* Skip if the sensor is disabled */
+ if (sensor & 1) {
+ ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code);
+ if (ret)
+ return;
+ upper_th_x = code >= threshold;
+ lower_th_x = code <= threshold_low;
+ if (upper_th_x)
+ mask |= UPPER_STATUS_CLR;
+ if (lower_th_x)
+ mask |= LOWER_STATUS_CLR;
+ if (upper_th_x || lower_th_x) {
+ /* Notify user space */
+ schedule_work(&priv->sensor[0].notify_work);
+ regmap_read(priv->tm_map, sensor_addr, &adc_code);
+ pr_debug("Trigger (%d degrees) for sensor %d\n",
+ code_to_degC(adc_code, &priv->sensor[0]), 0);
+ }
+ }
+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
+
+ /* force memory to sync */
+ mb();
+}
+
+static irqreturn_t tsens_isr(int irq, void *data)
+{
+ struct tsens_priv *priv = data;
+
+ schedule_work(&priv->tsens_work);
+ return IRQ_HANDLED;
+}
+
+static void hw_init(struct tsens_priv *priv)
+{
+ int ret;
+ unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0;
+ unsigned int reg_status_cntl = 0;
+
+ regmap_read(priv->tm_map, CNTL_ADDR, &reg_cntl);
+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST);
+
+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18)
+ | (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT);
+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_status_cntl);
+ reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR
+ | MIN_STATUS_MASK | MAX_STATUS_MASK;
+ regmap_write(priv->tm_map, STATUS_CNTL_8064, reg_status_cntl);
+ reg_cntl |= TSENS_EN;
+ regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+
+ regmap_read(priv->tm_map, CONFIG_ADDR, &reg_cfg);
+ reg_cfg = (reg_cfg & ~CONFIG_MASK) | (CONFIG << CONFIG_SHIFT);
+ regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg);
+
+ reg_thr |= (LOWER_LIMIT_TH << THRESHOLD_LOWER_LIMIT_SHIFT)
+ | (UPPER_LIMIT_TH << THRESHOLD_UPPER_LIMIT_SHIFT)
+ | (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT)
+ | (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT);
+
+ regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr);
+
+ ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr,
+ IRQF_TRIGGER_RISING, "tsens_interrupt", priv);
+ if (ret < 0) {
+ pr_err("%s: request_irq FAIL: %d\n", __func__, ret);
+ return;
+ }
+
+ INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
+}
+
+static int init_ipq8064(struct tsens_priv *priv)
+{
+ int ret, i;
+ u32 reg_cntl, offset = 0;
+
+ init_common(priv);
+ if (!priv->tm_map)
+ return -ENODEV;
+
+ /*
+ * The status registers for each sensor are discontiguous
+ * because some SoCs have 5 sensors while others have more
+ * but the control registers stay in the same place, i.e
+ * directly after the first 5 status registers.
+ */
+ for (i = 0; i < priv->num_sensors; i++) {
+ if (i >= TSENS_8064_SEQ_SENSORS)
+ offset = TSENS_8064_S4_S5_OFFSET;
+
+ priv->sensor[i].status = S0_STATUS_ADDR + offset
+ + (i << STATUS_ADDR_OFFSET);
+ priv->sensor[i].slope = tsens_8064_slope[i];
+ INIT_WORK(&priv->sensor[i].notify_work,
+ notify_uspace_tsens_fn);
+ }
+
+ reg_cntl = SW_RST;
+ ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
+ if (ret)
+ return ret;
+
+ reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
+ reg_cntl &= ~SW_RST;
+ ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
+ CONFIG_MASK, CONFIG);
+
+ reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
+ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ if (ret)
+ return ret;
+
+ reg_cntl |= EN;
+ ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int calibrate_ipq8064(struct tsens_priv *priv)
+{
+ int i;
+ char *data, *data_backup;
+
+ ssize_t num_read = priv->num_sensors;
+ struct tsens_sensor *s = priv->sensor;
+
+ data = qfprom_read(priv->dev, "calib");
+ if (IS_ERR(data)) {
+ pr_err("Calibration not found.\n");
+ return PTR_ERR(data);
+ }
+
+ data_backup = qfprom_read(priv->dev, "calib_backup");
+ if (IS_ERR(data_backup)) {
+ pr_err("Backup calibration not found.\n");
+ return PTR_ERR(data_backup);
+ }
+
+ for (i = 0; i < num_read; i++) {
+ s[i].calib_data = readb_relaxed(data + i);
+ s[i].calib_data_backup = readb_relaxed(data_backup + i);
+
+ if (s[i].calib_data_backup)
+ s[i].calib_data = s[i].calib_data_backup;
+ if (!s[i].calib_data) {
+ pr_err("QFPROM TSENS calibration data not present\n");
+ return -ENODEV;
+ }
+ s[i].slope = tsens_8064_slope[i];
+ s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
+ }
+
+ hw_init(priv);
+
+ return 0;
+}
+
+static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)
+{
+ int ret;
+ u32 code, trdy;
+ const struct tsens_sensor *s = &priv->sensor[id];
+ unsigned long timeout;
+
+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
+ do {
+ ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);
+ if (ret)
+ return ret;
+ if (!(trdy & TRDY_MASK))
+ continue;
+ ret = regmap_read(priv->tm_map, s->status, &code);
+ if (ret)
+ return ret;
+ *temp = code_to_degC(code, s);
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -ETIMEDOUT;
+}
+
+static int set_trip_temp_ipq8064(void *data, int trip, int temp)
+{
+ unsigned int reg_th, reg_cntl;
+ int ret, code, code_chk, hi_code, lo_code;
+ const struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ code_chk = code = degC_to_code(temp, s);
+
+ if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE)
+ return -EINVAL;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_cntl);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &reg_th);
+ if (ret)
+ return ret;
+
+ hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK)
+ >> THRESHOLD_UPPER_LIMIT_SHIFT;
+ lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK)
+ >> THRESHOLD_LOWER_LIMIT_SHIFT;
+
+ switch (trip) {
+ case TSENS_TRIP_STAGE3:
+ code <<= THRESHOLD_MAX_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_MAX_LIMIT_MASK;
+ break;
+ case TSENS_TRIP_STAGE2:
+ if (code_chk <= lo_code)
+ return -EINVAL;
+ code <<= THRESHOLD_UPPER_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK;
+ break;
+ case TSENS_TRIP_STAGE1:
+ if (code_chk >= hi_code)
+ return -EINVAL;
+ code <<= THRESHOLD_LOWER_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK;
+ break;
+ case TSENS_TRIP_STAGE0:
+ code <<= THRESHOLD_MIN_LIMIT_SHIFT;
+ reg_th &= ~THRESHOLD_MIN_LIMIT_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int set_trip_activate_ipq8064(void *data, int trip,
+ enum thermal_trip_activation_mode mode)
+{
+ unsigned int reg_cntl, mask, val;
+ const struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+ int ret;
+
+ if (!priv || trip < 0)
+ return -EINVAL;
+
+ ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg_cntl);
+ if (ret)
+ return ret;
+
+ switch (trip) {
+ case TSENS_TRIP_STAGE3:
+ mask = MAX_STATUS_MASK;
+ break;
+ case TSENS_TRIP_STAGE2:
+ mask = UPPER_STATUS_CLR;
+ break;
+ case TSENS_TRIP_STAGE1:
+ mask = LOWER_STATUS_CLR;
+ break;
+ case TSENS_TRIP_STAGE0:
+ mask = MIN_STATUS_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mode == THERMAL_TRIP_ACTIVATION_DISABLED)
+ val = reg_cntl | mask;
+ else
+ val = reg_cntl & ~mask;
+
+ ret = regmap_write(priv->tm_map, STATUS_CNTL_8064, val);
+ if (ret)
+ return ret;
+
+ /* force memory to sync */
+ mb();
+ return 0;
+}
+
+const struct tsens_ops ops_ipq8064 = {
+ .init = init_ipq8064,
+ .calibrate = calibrate_ipq8064,
+ .get_temp = get_temp_ipq8064,
+ .suspend = suspend_ipq8064,
+ .resume = resume_ipq8064,
+ .set_trip_temp = set_trip_temp_ipq8064,
+ .set_trip_activate = set_trip_activate_ipq8064,
+};
+
+const struct tsens_plat_data data_ipq8064 = {
+ .num_sensors = 11,
+ .ops = &ops_ipq8064,
+};
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -69,8 +69,11 @@ static const struct of_device_id tsens_t
}, {
.compatible = "qcom,tsens-v2",
.data = &data_tsens_v2,
+ }, {
+ .compatible = "qcom,ipq8064-tsens",
+ .data = &data_ipq8064,
},
- {}
+ {}
};
MODULE_DEVICE_TABLE(of, tsens_table);
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -324,7 +324,7 @@ extern const struct tsens_plat_data data
extern const struct tsens_plat_data data_8916, data_8974;
/* TSENS v1 targets */
-extern const struct tsens_plat_data data_tsens_v1;
+extern const struct tsens_plat_data data_tsens_v1, data_ipq8064;
/* TSENS v2 targets */
extern const struct tsens_plat_data data_8996, data_tsens_v2;

437
target/linux/ipq806x/patches-5.4/0063-2-tsens-support-configurable-interrupts.patch
View File

@ -1,437 +0,0 @@
From 4e87400732c77765afae2ea89ed43837457aa604 Mon Sep 17 00:00:00 2001
From: Rajith Cherian <rajith@codeaurora.org>
Date: Wed, 1 Feb 2017 19:00:26 +0530
Subject: [PATCH] ipq8064: tsens: Support for configurable interrupts
Provide support for adding configurable high and
configurable low trip temperatures. An interrupts is
also triggerred when these trip points are hit. The
interrupts can be activated or deactivated from sysfs.
This functionality is made available only if
CONFIG_THERMAL_WRITABLE_TRIPS is defined.
Change-Id: Ib73f3f9459de4fffce7bb985a0312a88291f4934
Signed-off-by: Rajith Cherian <rajith@codeaurora.org>
---
.../devicetree/bindings/thermal/qcom-tsens.txt | 4 ++
drivers/thermal/of-thermal.c | 63 ++++++++++++++++++----
drivers/thermal/qcom/tsens.c | 43 ++++++++++++---
drivers/thermal/qcom/tsens.h | 11 ++++
drivers/thermal/thermal_core.c | 44 ++++++++++++++-
include/linux/thermal.h | 14 +++++
6 files changed, 162 insertions(+), 17 deletions(-)
--- a/drivers/thermal/of-thermal.c
+++ b/drivers/thermal/of-thermal.c
@@ -91,7 +91,7 @@ static int of_thermal_get_temp(struct th
{
struct __thermal_zone *data = tz->devdata;
- if (!data->ops || !data->ops->get_temp)
+ if (!data->ops || !data->ops->get_temp || (data->mode == THERMAL_DEVICE_DISABLED))
return -EINVAL;
return data->ops->get_temp(data->sensor_data, temp);
@@ -102,7 +102,8 @@ static int of_thermal_set_trips(struct t
{
struct __thermal_zone *data = tz->devdata;
- if (!data->ops || !data->ops->set_trips)
+ if (!data->ops || !data->ops->set_trips
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EINVAL;
return data->ops->set_trips(data->sensor_data, low, high);
@@ -191,6 +192,9 @@ static int of_thermal_set_emul_temp(stru
if (!data->ops || !data->ops->set_emul_temp)
return -EINVAL;
+ if (data->mode == THERMAL_DEVICE_DISABLED)
+ return -EINVAL;
+
return data->ops->set_emul_temp(data->sensor_data, temp);
}
@@ -199,7 +203,7 @@ static int of_thermal_get_trend(struct t
{
struct __thermal_zone *data = tz->devdata;
- if (!data->ops || !data->ops->get_trend)
+ if (!data->ops || !data->ops->get_trend || (data->mode == THERMAL_DEVICE_DISABLED))
return -EINVAL;
return data->ops->get_trend(data->sensor_data, trip, trend);
@@ -300,7 +304,9 @@ static int of_thermal_set_mode(struct th
mutex_unlock(&tz->lock);
data->mode = mode;
- thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
+
+ if (mode == THERMAL_DEVICE_ENABLED)
+ thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
return 0;
}
@@ -310,7 +316,8 @@ static int of_thermal_get_trip_type(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
*type = data->trips[trip].type;
@@ -318,12 +325,39 @@ static int of_thermal_get_trip_type(stru
return 0;
}
+static int of_thermal_activate_trip_type(struct thermal_zone_device *tz,
+ int trip, enum thermal_trip_activation_mode mode)
+{
+ struct __thermal_zone *data = tz->devdata;
+
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
+ return -EDOM;
+
+ /*
+ * The configurable_hi and configurable_lo trip points can be
+ * activated and deactivated.
+ */
+
+ if (data->ops->set_trip_activate) {
+ int ret;
+
+ ret = data->ops->set_trip_activate(data->sensor_data,
+ trip, mode);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int of_thermal_get_trip_temp(struct thermal_zone_device *tz, int trip,
int *temp)
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
*temp = data->trips[trip].temperature;
@@ -336,7 +370,8 @@ static int of_thermal_set_trip_temp(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
if (data->ops && data->ops->set_trip_temp) {
@@ -358,7 +393,8 @@ static int of_thermal_get_trip_hyst(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
*hyst = data->trips[trip].hysteresis;
@@ -371,7 +407,8 @@ static int of_thermal_set_trip_hyst(stru
{
struct __thermal_zone *data = tz->devdata;
- if (trip >= data->ntrips || trip < 0)
+ if (trip >= data->ntrips || trip < 0
+ || (data->mode == THERMAL_DEVICE_DISABLED))
return -EDOM;
/* thermal framework should take care of data->mask & (1 << trip) */
@@ -446,6 +483,9 @@ thermal_zone_of_add_sensor(struct device
if (ops->set_emul_temp)
tzd->ops->set_emul_temp = of_thermal_set_emul_temp;
+ if (ops->set_trip_activate)
+ tzd->ops->set_trip_activate = of_thermal_activate_trip_type;
+
mutex_unlock(&tzd->lock);
return tzd;
@@ -768,7 +808,10 @@ static const char * const trip_types[] =
[THERMAL_TRIP_ACTIVE] = "active",
[THERMAL_TRIP_PASSIVE] = "passive",
[THERMAL_TRIP_HOT] = "hot",
- [THERMAL_TRIP_CRITICAL] = "critical",
+ [THERMAL_TRIP_CRITICAL] = "critical_high",
+ [THERMAL_TRIP_CONFIGURABLE_HI] = "configurable_hi",
+ [THERMAL_TRIP_CONFIGURABLE_LOW] = "configurable_lo",
+ [THERMAL_TRIP_CRITICAL_LOW] = "critical_low",
};
/**
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -22,7 +22,7 @@ static int tsens_get_temp(void *data, in
static int tsens_get_trend(void *data, int trip, enum thermal_trend *trend)
{
- const struct tsens_sensor *s = data;
+ struct tsens_sensor *s = data;
struct tsens_priv *priv = s->priv;
if (priv->ops->get_trend)
@@ -31,9 +31,10 @@ static int tsens_get_trend(void *data, i
return -ENOTSUPP;
}
-static int __maybe_unused tsens_suspend(struct device *dev)
+static int __maybe_unused tsens_suspend(void *data)
{
- struct tsens_priv *priv = dev_get_drvdata(dev);
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
if (priv->ops && priv->ops->suspend)
return priv->ops->suspend(priv);
@@ -41,9 +42,10 @@ static int __maybe_unused tsens_suspend
return 0;
}
-static int __maybe_unused tsens_resume(struct device *dev)
+static int __maybe_unused tsens_resume(void *data)
{
- struct tsens_priv *priv = dev_get_drvdata(dev);
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
if (priv->ops && priv->ops->resume)
return priv->ops->resume(priv);
@@ -51,6 +53,30 @@ static int __maybe_unused tsens_resume(s
return 0;
}
+static int __maybe_unused tsens_set_trip_temp(void *data, int trip, int temp)
+{
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops && priv->ops->set_trip_temp)
+ return priv->ops->set_trip_temp(s, trip, temp);
+
+ return 0;
+}
+
+static int __maybe_unused tsens_activate_trip_type(void *data, int trip,
+ enum thermal_trip_activation_mode mode)
+{
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops && priv->ops->set_trip_activate)
+ return priv->ops->set_trip_activate(s, trip, mode);
+
+ return 0;
+}
+
+
static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
static const struct of_device_id tsens_table[] = {
@@ -80,6 +106,8 @@ MODULE_DEVICE_TABLE(of, tsens_table);
static const struct thermal_zone_of_device_ops tsens_of_ops = {
.get_temp = tsens_get_temp,
.get_trend = tsens_get_trend,
+ .set_trip_temp = tsens_set_trip_temp,
+ .set_trip_activate = tsens_activate_trip_type,
};
static int tsens_register(struct tsens_priv *priv)
@@ -123,7 +151,7 @@ static int tsens_probe(struct platform_d
if (id)
data = id->data;
else
- data = &data_8960;
+ return -EINVAL;
num_sensors = data->num_sensors;
@@ -144,6 +172,9 @@ static int tsens_probe(struct platform_d
priv->dev = dev;
priv->num_sensors = num_sensors;
priv->ops = data->ops;
+
+ priv->tsens_irq = platform_get_irq(pdev, 0);
+
for (i = 0; i < priv->num_sensors; i++) {
if (data->hw_ids)
priv->sensor[i].hw_id = data->hw_ids[i];
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -40,9 +40,12 @@ enum tsens_ver {
struct tsens_sensor {
struct tsens_priv *priv;
struct thermal_zone_device *tzd;
+ struct work_struct notify_work;
int offset;
unsigned int id;
unsigned int hw_id;
+ int calib_data;
+ int calib_data_backup;
int slope;
u32 status;
};
@@ -57,6 +60,9 @@ struct tsens_sensor {
* @suspend: Function to suspend the tsens device
* @resume: Function to resume the tsens device
* @get_trend: Function to get the thermal/temp trend
+ * @set_trip_temp: Function to set trip temp
+ * @get_trip_temp: Function to get trip temp
+ * @set_trip_activate: Function to activate trip points
*/
struct tsens_ops {
/* mandatory callbacks */
@@ -69,6 +75,9 @@ struct tsens_ops {
int (*suspend)(struct tsens_priv *priv);
int (*resume)(struct tsens_priv *priv);
int (*get_trend)(struct tsens_priv *priv, int i, enum thermal_trend *trend);
+ int (*set_trip_temp)(void *data, int trip, int temp);
+ int (*set_trip_activate)(void *data, int trip,
+ enum thermal_trip_activation_mode mode);
};
#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
@@ -300,6 +309,7 @@ struct tsens_context {
struct tsens_priv {
struct device *dev;
u32 num_sensors;
+ u32 tsens_irq;
struct regmap *tm_map;
struct regmap *srot_map;
u32 tm_offset;
@@ -308,6 +318,7 @@ struct tsens_priv {
const struct tsens_features *feat;
const struct reg_field *fields;
const struct tsens_ops *ops;
+ struct work_struct tsens_work;
struct tsens_sensor sensor[0];
};
--- a/drivers/thermal/thermal_sysfs.c
+++ b/drivers/thermal/thermal_sysfs.c
@@ -113,12 +113,48 @@ trip_point_type_show(struct device *dev,
return sprintf(buf, "passive\n");
case THERMAL_TRIP_ACTIVE:
return sprintf(buf, "active\n");
+ case THERMAL_TRIP_CONFIGURABLE_HI:
+ return sprintf(buf, "configurable_hi\n");
+ case THERMAL_TRIP_CONFIGURABLE_LOW:
+ return sprintf(buf, "configurable_low\n");
+ case THERMAL_TRIP_CRITICAL_LOW:
+ return sprintf(buf, "critical_low\n");
default:
return sprintf(buf, "unknown\n");
}
}
static ssize_t
+trip_point_type_activate(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct thermal_zone_device *tz = to_thermal_zone(dev);
+ int trip, ret;
+ char *enabled = "enabled";
+ char *disabled = "disabled";
+
+ if (!tz->ops->set_trip_activate)
+ return -EPERM;
+
+ if (!sscanf(attr->attr.name, "trip_point_%d_type", &trip))
+ return -EINVAL;
+
+ if (!strncmp(buf, enabled, strlen(enabled)))
+ ret = tz->ops->set_trip_activate(tz, trip,
+ THERMAL_TRIP_ACTIVATION_ENABLED);
+ else if (!strncmp(buf, disabled, strlen(disabled)))
+ ret = tz->ops->set_trip_activate(tz, trip,
+ THERMAL_TRIP_ACTIVATION_DISABLED);
+ else
+ ret = -EINVAL;
+
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+static ssize_t
trip_point_temp_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
@@ -559,6 +595,12 @@ static int create_trip_attrs(struct ther
tz->trip_type_attrs[indx].attr.show = trip_point_type_show;
attrs[indx] = &tz->trip_type_attrs[indx].attr.attr;
+ if (IS_ENABLED(CONFIG_THERMAL_WRITABLE_TRIPS)) {
+ tz->trip_type_attrs[indx].attr.store
+ = trip_point_type_activate;
+ tz->trip_type_attrs[indx].attr.attr.mode |= S_IWUSR;
+ }
+
/* create trip temp attribute */
snprintf(tz->trip_temp_attrs[indx].name, THERMAL_NAME_LENGTH,
"trip_point_%d_temp", indx);
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -63,11 +63,19 @@ enum thermal_device_mode {
THERMAL_DEVICE_ENABLED,
};
+enum thermal_trip_activation_mode {
+ THERMAL_TRIP_ACTIVATION_DISABLED = 0,
+ THERMAL_TRIP_ACTIVATION_ENABLED,
+};
+
enum thermal_trip_type {
THERMAL_TRIP_ACTIVE = 0,
THERMAL_TRIP_PASSIVE,
THERMAL_TRIP_HOT,
THERMAL_TRIP_CRITICAL,
+ THERMAL_TRIP_CONFIGURABLE_HI,
+ THERMAL_TRIP_CONFIGURABLE_LOW,
+ THERMAL_TRIP_CRITICAL_LOW,
};
enum thermal_trend {
@@ -105,6 +113,8 @@ struct thermal_zone_device_ops {
enum thermal_trip_type *);
int (*get_trip_temp) (struct thermal_zone_device *, int, int *);
int (*set_trip_temp) (struct thermal_zone_device *, int, int);
+ int (*set_trip_activate) (struct thermal_zone_device *, int,
+ enum thermal_trip_activation_mode);
int (*get_trip_hyst) (struct thermal_zone_device *, int, int *);
int (*set_trip_hyst) (struct thermal_zone_device *, int, int);
int (*get_crit_temp) (struct thermal_zone_device *, int *);
@@ -349,6 +359,8 @@ struct thermal_genl_event {
* temperature.
* @set_trip_temp: a pointer to a function that sets the trip temperature on
* hardware.
+ * @activate_trip_type: a pointer to a function to enable/disable trip
+ * temperature interrupts
*/
struct thermal_zone_of_device_ops {
int (*get_temp)(void *, int *);
@@ -356,6 +368,8 @@ struct thermal_zone_of_device_ops {
int (*set_trips)(void *, int, int);
int (*set_emul_temp)(void *, int);
int (*set_trip_temp)(void *, int, int);
+ int (*set_trip_activate)(void *, int,
+ enum thermal_trip_activation_mode);
};
/**

68
target/linux/ipq806x/patches-5.4/0063-3-tsens-fix-kernel-5_4.patch
View File

@ -1,68 +0,0 @@
--- a/drivers/thermal/qcom/tsens-ipq8064.c
+++ b/drivers/thermal/qcom/tsens-ipq8064.c
@@ -18,6 +18,7 @@
#include <linux/regmap.h>
#include <linux/thermal.h>
#include <linux/nvmem-consumer.h>
+#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include "tsens.h"
@@ -320,15 +321,42 @@ static void hw_init(struct tsens_priv *p
INIT_WORK(&priv->tsens_work, tsens_scheduler_fn);
}
+static const struct regmap_config tsens_config = {
+ .name = "tm",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
static int init_ipq8064(struct tsens_priv *priv)
{
- int ret, i;
+ struct device *dev = priv->dev;
u32 reg_cntl, offset = 0;
+ struct resource *res;
+ resource_size_t size;
+ void __iomem *base;
+ int ret, i;
+ struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
+
+ if (!op)
+ return -EINVAL;
- init_common(priv);
- if (!priv->tm_map)
- return -ENODEV;
+ /* old DTs where SROT and TM were in a contiguous 2K block */
+ priv->tm_offset = 0x1000;
+ res = platform_get_resource(op, IORESOURCE_MEM, 0);
+ size = resource_size(res);
+ base = devm_ioremap(&op->dev, res->start, size);
+ if (IS_ERR(base)) {
+ ret = PTR_ERR(base);
+ goto err_put_device;
+ }
+
+ priv->tm_map = devm_regmap_init_mmio(dev, base, &tsens_config);
+ if (IS_ERR(priv->tm_map)) {
+ ret = PTR_ERR(priv->tm_map);
+ goto err_put_device;
+ }
/*
* The status registers for each sensor are discontiguous
* because some SoCs have 5 sensors while others have more
@@ -367,6 +395,10 @@ static int init_ipq8064(struct tsens_pri
return ret;
return 0;
+
+err_put_device:
+ put_device(&op->dev);
+ return ret;
}
static int calibrate_ipq8064(struct tsens_priv *priv)

107
target/linux/ipq806x/patches-5.4/0063-4-ip806x-tsense-rework-driver.patch
View File

@ -1,107 +0,0 @@
--- a/drivers/thermal/qcom/tsens-ipq8064.c
+++ b/drivers/thermal/qcom/tsens-ipq8064.c
@@ -13,10 +13,12 @@
*/
#include <linux/platform_device.h>
+#include <linux/err.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/thermal.h>
+#include <linux/slab.h>
#include <linux/nvmem-consumer.h>
#include <linux/of_platform.h>
#include <linux/io.h>
@@ -211,9 +213,8 @@ static void tsens_scheduler_fn(struct wo
struct tsens_priv *priv = container_of(work, struct tsens_priv,
tsens_work);
unsigned int threshold, threshold_low, code, reg, sensor, mask;
- unsigned int sensor_addr;
bool upper_th_x, lower_th_x;
- int adc_code, ret;
+ int ret;
ret = regmap_read(priv->tm_map, STATUS_CNTL_8064, &reg);
if (ret)
@@ -262,9 +263,8 @@ static void tsens_scheduler_fn(struct wo
if (upper_th_x || lower_th_x) {
/* Notify user space */
schedule_work(&priv->sensor[0].notify_work);
- regmap_read(priv->tm_map, sensor_addr, &adc_code);
pr_debug("Trigger (%d degrees) for sensor %d\n",
- code_to_degC(adc_code, &priv->sensor[0]), 0);
+ code_to_degC(code, &priv->sensor[0]), 0);
}
}
regmap_write(priv->tm_map, STATUS_CNTL_8064, reg & mask);
@@ -404,40 +404,55 @@ err_put_device:
static int calibrate_ipq8064(struct tsens_priv *priv)
{
int i;
- char *data, *data_backup;
-
+ int ret = 0;
+ u8 *data, *data_backup;
+ struct device *dev = priv->dev;
ssize_t num_read = priv->num_sensors;
struct tsens_sensor *s = priv->sensor;
- data = qfprom_read(priv->dev, "calib");
+ data = qfprom_read(dev, "calib");
if (IS_ERR(data)) {
- pr_err("Calibration not found.\n");
- return PTR_ERR(data);
+ ret = PTR_ERR(data);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Calibration not found.");
+ goto exit;
}
- data_backup = qfprom_read(priv->dev, "calib_backup");
+ data_backup = qfprom_read(dev, "calib_backup");
if (IS_ERR(data_backup)) {
- pr_err("Backup calibration not found.\n");
- return PTR_ERR(data_backup);
+ ret = PTR_ERR(data_backup);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Backup Calibration not found.");
+ goto free_data;
}
for (i = 0; i < num_read; i++) {
s[i].calib_data = readb_relaxed(data + i);
- s[i].calib_data_backup = readb_relaxed(data_backup + i);
+
+ if (!s[i].calib_data) {
+ s[i].calib_data_backup = readb_relaxed(data_backup + i);
+
+ if (!s[i].calib_data_backup) {
+ dev_err(dev, "QFPROM TSENS calibration data not present");
+ ret = -ENODEV;
+ goto free_backup;
+ }
- if (s[i].calib_data_backup)
s[i].calib_data = s[i].calib_data_backup;
- if (!s[i].calib_data) {
- pr_err("QFPROM TSENS calibration data not present\n");
- return -ENODEV;
}
+
s[i].slope = tsens_8064_slope[i];
s[i].offset = CAL_MDEGC - (s[i].calib_data * s[i].slope);
}
hw_init(priv);
- return 0;
+free_backup:
+ kfree(data_backup);
+free_data:
+ kfree(data);
+exit:
+ return ret;
}
static int get_temp_ipq8064(struct tsens_priv *priv, int id, int *temp)

70
target/linux/ipq806x/patches-5.4/080-v5.7-ARM-dts-qcom-add-gpio-ranges-property.patch
View File

@ -1,70 +0,0 @@
From patchwork Mon May 21 20:57:38 2018
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Subject: [v5,3/4] ARM: dts: qcom: add gpio-ranges property
X-Patchwork-Submitter: Christian Lamparter <chunkeey@gmail.com>
X-Patchwork-Id: 917856
Message-Id: <0ae3376606a89bcdf3fe753a5c967f7103699e09.1526935804.git.chunkeey@gmail.com>
To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Stephen Boyd <sboyd@kernel.org>, David Brown <david.brown@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
Andy Gross <andy.gross@linaro.org>,
Sven Eckelmann <sven.eckelmann@openmesh.com>
Date: Mon, 21 May 2018 22:57:38 +0200
From: Christian Lamparter <chunkeey@gmail.com>
List-Id: <linux-gpio.vger.kernel.org>
This patch adds the gpio-ranges property to almost all of
the Qualcomm ARM platforms that utilize the pinctrl-msm
framework.
The gpio-ranges property is part of the gpiolib subsystem.
As a result, the binding text is available in section
"2.1 gpio- and pin-controller interaction" of
Documentation/devicetree/bindings/gpio/gpio.txt
For more information please see the patch titled:
"pinctrl: msm: fix gpio-hog related boot issues" from
this series.
Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
To help with git bisect, the DT update patch has been intentionally
placed after the "pinctrl: msm: fix gpio-hog related boot issues".
Otherwise - if the order was reveresed - and bisect decides to split
between these two patches, the gpiochip_add_pin_ranges() function
will be executed twice with the same parameters for the same pinctrl.
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 1 +
arch/arm/boot/dts/qcom-apq8084.dtsi | 1 +
arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 +
arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8960.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8974.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8992.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 +
arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 +
13 files changed, 14 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -119,6 +119,7 @@
reg = <0x800000 0x4000>;
gpio-controller;
+ gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;

29
target/linux/ipq806x/patches-5.4/081-v5.8-ARM-dts-qcom-add-scm-definition-to-ipq806x.patch
View File

@ -1,29 +0,0 @@
From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Thu, 19 Mar 2020 23:44:24 +0100
Subject: ARM: dts: qcom: add scm definition to ipq806x
Add missing scm definition for ipq806x soc
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -93,6 +93,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq806x", "qcom,scm";
+ };
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;

104
target/linux/ipq806x/patches-5.4/086-v5.8-pinctrl-qom-use-scm_call-to-route-GPIO-irq-to-Apps.patch
View File

@ -1,104 +0,0 @@
From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
From: Ajay Kishore <akisho@codeaurora.org>
Date: Fri, 27 Mar 2020 23:32:08 +0100
Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
For IPQ806x targets, TZ protects the registers that are used to
configure the routing of interrupts to a target processor.
To resolve this, this patch uses scm call to route GPIO interrupts
to application processor. Also the scm call interface is changed.
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
1 file changed, 37 insertions(+), 6 deletions(-)
(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -22,6 +22,8 @@
#include <linux/reboot.h>
#include <linux/pm.h>
#include <linux/log2.h>
+#include <linux/qcom_scm.h>
+#include <linux/io.h>
#include "../core.h"
#include "../pinconf.h"
@@ -57,6 +59,8 @@ struct msm_pinctrl {
struct irq_chip irq_chip;
int irq;
+ bool intr_target_use_scm;
+
raw_spinlock_t lock;
DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
@@ -64,6 +68,7 @@ struct msm_pinctrl {
const struct msm_pinctrl_soc_data *soc;
void __iomem *regs[MAX_NR_TILES];
+ u32 phys_base[MAX_NR_TILES];
};
#define MSM_ACCESSOR(name) \
@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
else
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
- /* Route interrupts to application cpu */
- val = msm_readl_intr_target(pctrl, g);
- val &= ~(7 << g->intr_target_bit);
- val |= g->intr_target_kpss_val << g->intr_target_bit;
- msm_writel_intr_target(val, pctrl, g);
+ /* Route interrupts to application cpu.
+ * With intr_target_use_scm interrupts are routed to
+ * application cpu using scm calls.
+ */
+ if (pctrl->intr_target_use_scm) {
+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
+ int ret;
+
+ qcom_scm_io_readl(addr, &val);
+
+ val &= ~(7 << g->intr_target_bit);
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
+
+ ret = qcom_scm_io_writel(addr, val);
+ if (ret)
+ dev_err(pctrl->dev,
+ "Failed routing %lu interrupt to Apps proc",
+ d->hwirq);
+ } else {
+ val = msm_readl_intr_target(pctrl, g);
+ val &= ~(7 << g->intr_target_bit);
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
+ msm_writel_intr_target(val, pctrl, g);
+ }
/* Update configuration for gpio.
* RAW_STATUS_EN is left on for all gpio irqs. Due to the
@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
pctrl->dev = &pdev->dev;
pctrl->soc = soc_data;
pctrl->chip = msm_gpio_template;
+ pctrl->intr_target_use_scm = of_device_is_compatible(
+ pctrl->dev->of_node,
+ "qcom,ipq8064-pinctrl");
raw_spin_lock_init(&pctrl->lock);
@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pctrl->regs[0]))
return PTR_ERR(pctrl->regs[0]);
+
+ pctrl->phys_base[0] = res->start;
}
msm_pinctrl_setup_pm_reset(pctrl);

56
target/linux/ipq806x/patches-5.4/087-v5.8-ipq8064-pinctrl-Fixed-missing-RGMII-pincontrol-defin.patch
View File

@ -1,56 +0,0 @@
From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
From: Ansuel Smith <ansuelsmth@gmail.com>
Date: Wed, 19 Feb 2020 18:59:39 +0100
Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
Add missing gpio definition for mdio and rgmii2.
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -299,7 +299,7 @@ static const char * const gpio_groups[]
};
static const char * const mdio_groups[] = {
- "gpio0", "gpio1", "gpio10", "gpio11",
+ "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
};
static const char * const mi2s_groups[] = {
@@ -403,8 +403,8 @@ static const char * const usb2_hsic_grou
};
static const char * const rgmii2_groups[] = {
- "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
+ "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
};
static const char * const sata_groups[] = {
@@ -539,7 +539,7 @@ static const struct msm_function ipq8064
static const struct msm_pingroup ipq8064_groups[] = {
PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
@@ -603,7 +603,7 @@ static const struct msm_pingroup ipq8064
PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
- PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),

Some files were not shown because too many files have changed in this diff Show More