kernel: bump to 4.9.214, 4.14.171, 4.19.106 (#3375)

include/kernel-version.mk

@@ -6,13 +6,13 @@ ifdef CONFIG_TESTING_KERNEL
   KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)
 endif
 
-LINUX_VERSION-4.9 = .212
-LINUX_VERSION-4.14 = .169
-LINUX_VERSION-4.19 = .101
+LINUX_VERSION-4.9 = .214
+LINUX_VERSION-4.14 = .171
+LINUX_VERSION-4.19 = .106
 
-LINUX_KERNEL_HASH-4.9.212 = ade738a606c9b52ecf764e94b4e77116caa3a2b8abd30f4534d220ac6894be30
-LINUX_KERNEL_HASH-4.14.169 = d88ea97993c56b1fa0b0a05061bcde476c6be4fc3bb2de8bd97a8f8ff7278249
-LINUX_KERNEL_HASH-4.19.101 = be26156abdb38ac0576a34a235ef456bb8ca67fbbe56fc6649b8d069159f8bc4
+LINUX_KERNEL_HASH-4.9.214 = b47f093dac7034c7c4722e80042c05e4ef53c14a4f28aa992117a127d2b1e483
+LINUX_KERNEL_HASH-4.14.171 = 4fe02489e4b4a187eccf0ef87df6100534c9d485e76d876b1fa247c7635332a0
+LINUX_KERNEL_HASH-4.19.106 = 63c8bd76a9b282e18112f8ff9e3fd41e3d1df9f9b7248ea1a370b05a827e9cda
 
 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
 sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

target/linux/ar71xx/patches-4.14/450-gpio-nxp-74hc153-gpio-chip-driver.patch

@@ -1,6 +1,6 @@
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
-@@ -1299,4 +1299,12 @@ config GPIO_VIPERBOARD
+@@ -1300,4 +1300,12 @@ config GPIO_VIPERBOARD
  
  endmenu
  

target/linux/ar71xx/patches-4.14/451-gpio-74x164-improve-platform-device-support.patch

@@ -109,7 +109,7 @@
 +#endif
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
-@@ -1251,7 +1251,6 @@ menu "SPI GPIO expanders"
+@@ -1252,7 +1252,6 @@ menu "SPI GPIO expanders"
  
  config GPIO_74X164
  	tristate "74x164 serial-in/parallel-out 8-bits shift register"

target/linux/ar71xx/patches-4.14/452-gpio-add-gpio-latch-driver.patch

@@ -1,6 +1,6 @@
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
-@@ -1306,4 +1306,9 @@ config GPIO_NXP_74HC153
+@@ -1307,4 +1307,9 @@ config GPIO_NXP_74HC153
  	  Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
  	  provides a GPIO interface supporting input mode only.
  

target/linux/ar71xx/patches-4.14/525-MIPS-ath79-enable-qca-usb-quirks.patch

@@ -77,7 +77,7 @@
 +
 +	switch (pdev->id) {
 +	case 0:
-+		base = 0x18116c94;
++		base = 0x18116d94;
 +		break;
 +
 +	case 1:

target/linux/ar71xx/patches-4.14/910-unaligned_access_hacks.patch

@@ -831,7 +831,7 @@
   * No flags defined yet.
 --- a/net/core/utils.c
 +++ b/net/core/utils.c
-@@ -424,8 +424,14 @@ void inet_proto_csum_replace16(__sum16 *
+@@ -441,8 +441,14 @@ void inet_proto_csum_replace16(__sum16 *
  			       bool pseudohdr)
  {
  	__be32 diff[] = {

target/linux/ar71xx/patches-4.14/953-qca955x-pci-reset-fixes.patch

@@ -0,0 +1,120 @@
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -153,6 +153,24 @@ void ath79_device_reset_clear(u32 mask)
+ }
+ EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
+ 
++void ath79_device_reset2_clear(u32 mask)
++{
++	unsigned long flags;
++	u32 reg;
++	u32 t;
++
++	if (soc_is_qca955x())
++		reg = QCA955X_RESET_REG_RESET2_MODULE;
++	else
++		panic("Reset register not defined for this SOC");
++
++	spin_lock_irqsave(&ath79_device_reset_lock, flags);
++	t = ath79_reset_rr(reg);
++	ath79_reset_wr(reg, t & ~mask);
++	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
++}
++EXPORT_SYMBOL_GPL(ath79_device_reset2_clear);
++
+ u32 ath79_device_reset_get(u32 mask)
+ {
+ 	unsigned long flags;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -411,6 +411,7 @@
+ #define QCA955X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA955X_PLL_DDR_CONFIG_REG		0x04
+ #define QCA955X_PLL_CLK_CTRL_REG		0x08
++#define QCA955X_PLL_PCIE_CONFIG_REG		0x0c
+ #define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
+ #define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
+ #define QCA955X_PLL_ETH_SGMII_SERDES_REG	0x4c
+@@ -565,6 +566,7 @@
+ #define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
+ 
+ #define QCA955X_RESET_REG_RESET_MODULE		0x1c
++#define QCA955X_RESET_REG_RESET2_MODULE		0xc4
+ #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
+ #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
+ 
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
+@@ -178,6 +178,7 @@ static inline u32 ath79_reset_rr(unsigne
+ 
+ void ath79_device_reset_set(u32 mask);
+ void ath79_device_reset_clear(u32 mask);
++void ath79_device_reset2_clear(u32 mask);
+ u32 ath79_device_reset_get(u32 mask);
+ 
+ void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
+--- a/arch/mips/pci/pci-ar724x.c
++++ b/arch/mips/pci/pci-ar724x.c
+@@ -335,18 +335,37 @@ static void ar724x_pci_hw_init(struct ar
+ 	int wait = 0;
+ 
+ 	/* deassert PCIe host controller and PCIe PHY reset */
+-	ath79_device_reset_clear(AR724X_RESET_PCIE);
+-	ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
++	if (soc_is_qca955x()) {
++		ath79_device_reset_clear(QCA955X_RESET_PCIE);
++		mdelay(10);
++		ath79_device_reset_clear(QCA955X_RESET_PCIE_PHY);
++		mdelay(10);
++		ath79_device_reset2_clear(QCA955X_RESET_PCIE);
++		mdelay(10);
++		ath79_device_reset2_clear(QCA955X_RESET_PCIE_PHY);
++		mdelay(10);
++	} else {
++		ath79_device_reset_clear(AR724X_RESET_PCIE);
++		ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
++	}
+ 
+ 	/* remove the reset of the PCIE PLL */
+-	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+-	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
+-	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++	if (!soc_is_qca955x()) {
++		ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
++		ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++	}
+ 
+ 	/* deassert bypass for the PCIE PLL */
+-	ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+-	ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
+-	ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++	if (soc_is_qca955x()) {
++		ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
++		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
++		ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
++	} else {
++		ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
++		ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
++		ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
++	}
+ 
+ 	/* set PCIE Application Control to ready */
+ 	app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
+@@ -422,8 +441,14 @@ static int ar724x_pci_probe(struct platf
+ 	 * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+ 	 * host controller is in reset.
+ 	 */
+-	if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
+-		ar724x_pci_hw_init(apc);
++	if (soc_is_qca955x()) {
++		if (ath79_reset_rr(QCA955X_RESET_REG_RESET_MODULE) & QCA955X_RESET_PCIE ||
++		    ath79_reset_rr(QCA955X_RESET_REG_RESET2_MODULE) & QCA955X_RESET_PCIE)
++			ar724x_pci_hw_init(apc);
++	} else {
++		if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
++			ar724x_pci_hw_init(apc);
++	}
+ 
+ 	apc->link_up = ar724x_pci_check_link(apc);
+ 	if (!apc->link_up)

target/linux/ar71xx/patches-4.14/955-qca953x-fix-potential-missing-irq-dispatch.patch

@@ -0,0 +1,27 @@
+--- a/arch/mips/ath79/irq.c
++++ b/arch/mips/ath79/irq.c
+@@ -69,15 +69,21 @@ static void qca953x_ip2_irq_dispatch(str
+ 	u32 status;
+ 
+ 	status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
++	status &= QCA953X_PCIE_WMAC_INT_PCIE_ALL | QCA953X_PCIE_WMAC_INT_WMAC_ALL;
++
++	if (status == 0) {
++		spurious_interrupt();
++		return;
++	}
+ 
+ 	if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
+ 		ath79_ddr_wb_flush(3);
+ 		generic_handle_irq(ATH79_IP2_IRQ(0));
+-	} else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
++	}
++
++	if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
+ 		ath79_ddr_wb_flush(4);
+ 		generic_handle_irq(ATH79_IP2_IRQ(1));
+-	} else {
+-		spurious_interrupt();
+ 	}
+ }
+ 

target/linux/ar71xx/patches-4.9/450-gpio-nxp-74hc153-gpio-chip-driver.patch

@@ -1,6 +1,6 @@
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
-@@ -1214,4 +1214,12 @@ config GPIO_VIPERBOARD
+@@ -1215,4 +1215,12 @@ config GPIO_VIPERBOARD
  
  endmenu
  

target/linux/ar71xx/patches-4.9/451-gpio-74x164-improve-platform-device-support.patch

@@ -109,7 +109,7 @@
 +#endif
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
-@@ -1155,7 +1155,6 @@ menu "SPI GPIO expanders"
+@@ -1156,7 +1156,6 @@ menu "SPI GPIO expanders"
  
  config GPIO_74X164
  	tristate "74x164 serial-in/parallel-out 8-bits shift register"

target/linux/ar71xx/patches-4.9/452-gpio-add-gpio-latch-driver.patch

@@ -1,6 +1,6 @@
 --- a/drivers/gpio/Kconfig
 +++ b/drivers/gpio/Kconfig
-@@ -1221,4 +1221,9 @@ config GPIO_NXP_74HC153
+@@ -1222,4 +1222,9 @@ config GPIO_NXP_74HC153
  	  Platform driver for NXP 74HC153 Dual 4-input Multiplexer. This
  	  provides a GPIO interface supporting input mode only.
  

target/linux/ar71xx/patches-4.9/910-unaligned_access_hacks.patch

@@ -869,7 +869,7 @@
   * No flags defined yet.
 --- a/net/core/utils.c
 +++ b/net/core/utils.c
-@@ -321,8 +321,14 @@ void inet_proto_csum_replace16(__sum16 *
+@@ -338,8 +338,14 @@ void inet_proto_csum_replace16(__sum16 *
  			       bool pseudohdr)
  {
  	__be32 diff[] = {

target/linux/ath25/patches-4.14/130-watchdog.patch

@@ -212,7 +212,7 @@
 +MODULE_ALIAS("platform:" DRIVER_NAME);
 --- a/drivers/watchdog/Kconfig
 +++ b/drivers/watchdog/Kconfig
-@@ -1646,6 +1646,13 @@ config PIC32_DMT
+@@ -1647,6 +1647,13 @@ config PIC32_DMT
  	  To compile this driver as a loadable module, choose M here.
  	  The module will be called pic32-dmt.
  

target/linux/ath79/config-4.19

@@ -211,6 +211,7 @@ CONFIG_SERIAL_AR933X_CONSOLE=y
 CONFIG_SERIAL_AR933X_NR_UARTS=2
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SPI=y
+CONFIG_SPI_AR934X=y
 CONFIG_SPI_ATH79=y
 CONFIG_SPI_BITBANG=y
 CONFIG_SPI_GPIO=y

target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts

@@ -18,7 +18,6 @@
 	partition@50000 {
 		label = "u-boot-env";
 		reg = <0x050000 0x020000>;
-		read-only;
 	};
 
 	partition@70000 {

target/linux/ath79/dts/ar7161_netgear_wndr3700.dts

@@ -18,7 +18,6 @@
 	partition@50000 {
 		label = "u-boot-env";
 		reg = <0x050000 0x020000>;
-		read-only;
 	};
 
 	partition@70000 {

target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts

@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar7100.dtsi"
+
+/ {
+	compatible = "siemens,ws-ap3610", "qca,ar7161";
+	model = "Siemens WS-AP3610";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+		label-mac-device = &eth0;
+	};
+
+	extosc: ref {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "ref";
+		clock-frequency = <40000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_power_green: led_power_green {
+			label = "ws-ap3610:green:power";
+			gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: led_power_red {
+			label = "ws-ap3610:red:power";
+			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+		};
+
+		led_wlan5_blue {
+			label = "ws-ap3610:blue:wlan5";
+			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy0tpt";
+		};
+
+		led_wlan5_green {
+			label = "ws-ap3610:green:wlan5";
+			gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+		};
+
+		led_wlan2_blue {
+			label = "ws-ap3610:blue:wlan2";
+			gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+
+		led_wlan2_green {
+			label = "ws-ap3610:green:wlan2";
+			gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&pcie0 {
+	status = "okay";
+};
+
+&uart {
+	status = "okay";
+};
+
+&mdio0 {
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		/*
+		 * When the compatible-is missing, PHY autodetection
+		 * is performed, but the PHY-ID reads all 0xff.
+		 *
+		 * Linux does not create the device in this case,
+		 * and the reset is never even de-asserted.
+		 */
+		compatible = "ethernet-phy-id0143.bca2",
+				"ethernet-phy-ieee802.3-c22";
+		reg = <0>;
+
+		resets = <&rst 8>;
+		reset-names = "phy";
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-mode = "rgmii-id";
+	phy-handle = <&phy0>;
+};
+
+&spi {
+	status = "okay";
+
+	num-cs = <1>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "u-boot-bak";
+				reg = <0x40000 0x40000>;
+				read-only;
+			};
+
+			partition@80000 {
+				compatible = "denx,uimage";
+				label = "firmware";
+				reg = <0x80000 0xe00000>;
+			};
+
+			partition@e80000 {
+				label = "cfg1";
+				reg = <0xe80000 0x40000>;
+				read-only;
+			};
+
+			partition@ec0000 {
+				label = "cfg2";
+				reg = <0xec0000 0x40000>;
+				read-only;
+			};
+
+			partition@f00000 {
+				label = "nvram1";
+				reg = <0xf00000 0x40000>;
+				read-only;
+			};
+
+			partition@f40000 {
+				label = "nvram2";
+				reg = <0xf40000 0x40000>;
+				read-only;
+			};
+
+			partition@f80000 {
+				label = "rsvd1";
+				reg = <0xf80000 0x40000>;
+				read-only;
+			};
+
+			partition@fc0000 {
+				label = "rsvd2";
+				reg = <0xfc0000 0x40000>;
+				read-only;
+			};
+		};
+	};
+};

target/linux/ath79/dts/ar7240_tplink.dtsi

@@ -32,10 +32,11 @@
 		};
 	};
 
-	leds {
+	leds: leds {
 		compatible = "gpio-leds";
+
 		pinctrl-names = "default";
-		pinctrl-0 = <&switch_led_pins>;
+		pinctrl-0 = <&pinmux_switch_led_pins>;
 
 		led_system: system {
 			label = "tp-link:green:system";
@@ -46,31 +47,6 @@
 			label = "tp-link:green:qss";
 			gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 		};
-
-		lan1 {
-			label = "tp-link:green:lan1";
-			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
-		};
-
-		lan2 {
-			label = "tp-link:green:lan2";
-			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
-		};
-
-		lan3 {
-			label = "tp-link:green:lan3";
-			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
-		};
-
-		lan4 {
-			label = "tp-link:green:lan4";
-			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
-		};
-
-		wan {
-			label = "tp-link:green:wan";
-			gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
-		};
 	};
 
 	ath9k-leds {
@@ -105,7 +81,7 @@
 				read-only;
 			};
 
-			firmware: partition@20000 {
+			partition@20000 {
 				compatible = "tplink,firmware";
 				reg = <0x20000 0x3d0000>;
 				label = "firmware";
@@ -120,25 +96,14 @@
 	};
 };
 
-&eth0 {
-	status = "okay";
-
-	mtd-mac-address = <&uboot 0x1fc00>;
-	mtd-mac-address-increment = <(-1)>;
-};
-
 &eth1 {
 	status = "okay";
-
-	mtd-mac-address = <&uboot 0x1fc00>;
-	mtd-mac-address-increment = <1>;
 };
 
 &pcie {
 	status = "okay";
 
 	ath9k: wifi@0,0 {
-		compatible = "pci168c,002b";
 		reg = <0x0000 0 0 0 0>;
 		qca,no-eeprom;
 		mtd-mac-address = <&uboot 0x1fc00>;
@@ -148,7 +113,7 @@
 };
 
 &pinmux {
-	switch_led_pins: pinmux_switch_led_pins {
+	pinmux_switch_led_pins: switch_led_pins {
 		pinctrl-single,bits = <0x0 0x0 0xf8>;
 	};
 };

target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "ar7240_tplink.dtsi"
+
+&leds {
+	lan {
+		label = "tp-link:green:lan";
+		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&eth1 {
+	mtd-mac-address = <&uboot 0x1fc00>;
+};
+
+&ath9k {
+	compatible = "pci168c,002a";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wa701nd-v1.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7240_tplink_tl-wa.dtsi"
+
+/ {
+	model = "TP-Link TL-WA701ND v1";
+	compatible = "tplink,tl-wa701nd-v1", "qca,ar7240";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wa730re-v1.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7240_tplink_tl-wa.dtsi"
+
+/ {
+	model = "TP-Link TL-WA730RE v1";
+	compatible = "tplink,tl-wa730re-v1", "qca,ar7240";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wa801nd-v1.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7240_tplink_tl-wa.dtsi"
+
+/ {
+	model = "TP-Link TL-WA801ND v1";
+	compatible = "tplink,tl-wa801nd-v1", "qca,ar7240";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wa830re-v1.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7240_tplink_tl-wa.dtsi"
+
+/ {
+	model = "TP-Link TL-WA830RE v1";
+	compatible = "tplink,tl-wa830re-v1", "qca,ar7240";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wa901nd-v1.dts

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7240_tplink_tl-wa.dtsi"
+
+/ {
+	model = "TP-Link TL-WA901ND v1";
+	compatible = "tplink,tl-wa901nd-v1", "qca,ar7240";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi

@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "ar7240_tplink.dtsi"
+
+&leds {
+	lan1 {
+		label = "tp-link:green:lan1";
+		gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+	};
+
+	lan2 {
+		label = "tp-link:green:lan2";
+		gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+	};
+
+	lan3 {
+		label = "tp-link:green:lan3";
+		gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+	};
+
+	lan4 {
+		label = "tp-link:green:lan4";
+		gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+	};
+
+	wan {
+		label = "tp-link:green:wan";
+		gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	mtd-mac-address = <&uboot 0x1fc00>;
+	mtd-mac-address-increment = <(-1)>;
+};
+
+&eth1 {
+	mtd-mac-address = <&uboot 0x1fc00>;
+	mtd-mac-address-increment = <1>;
+};
+
+&ath9k {
+	compatible = "pci168c,002b";
+};

target/linux/ath79/dts/ar7240_tplink_tl-wr740n-v1.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include "ar7240_tplink_tl-wr74xn-v1.dtsi"
+#include "ar7240_tplink_tl-wr.dtsi"
 
 / {
 	model = "TP-Link TL-WR740N v1/v2";

target/linux/ath79/dts/ar7240_tplink_tl-wr740n-v3.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include "ar7240_tplink_tl-wr74xn-v1.dtsi"
+#include "ar7240_tplink_tl-wr.dtsi"
 
 / {
 	model = "TP-Link TL-WR740N v3";

target/linux/ath79/dts/ar7240_tplink_tl-wr741-v1.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include "ar7240_tplink_tl-wr74xn-v1.dtsi"
+#include "ar7240_tplink_tl-wr.dtsi"
 
 / {
 	model = "TP-Link TL-WR741N/ND v1/v2";

target/linux/ath79/dts/ar7240_tplink_tl-wr743nd-v1.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include "ar7240_tplink_tl-wr74xn-v1.dtsi"
+#include "ar7240_tplink_tl-wr.dtsi"
 
 / {
 	model = "TP-Link TL-WR743ND v1";

target/linux/ath79/dts/ar7240_tplink_tl-wr841-v5.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include "ar7240_tplink_tl-wr74xn-v1.dtsi"
+#include "ar7240_tplink_tl-wr.dtsi"
 
 / {
 	model = "TP-Link TL-WR841N/ND v5/v6";

target/linux/ath79/dts/ar7240_tplink_tl-wr941-v4.dts

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include "ar7240_tplink_tl-wr74xn-v1.dtsi"
+#include "ar7240_tplink_tl-wr.dtsi"
 
 / {
 	model = "TP-Link TL-WR941N/ND v4";

target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7241_ubnt_xm_outdoor.dtsi"
+
+/ {
+	compatible = "ubnt,nanostation-loco-m", "ubnt,xm", "qca,ar7241";
+	model = "Ubiquiti Nanostation Loco M";
+};
+
+&eth1 {
+	compatible = "syscon", "simple-mfd";
+};

target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts

@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "ar7241_ubnt_xm_outdoor.dtsi"
+
+/ {
+	compatible = "ubnt,picostation-m", "ubnt,xm", "qca,ar7241";
+	model = "Ubiquiti Picostation M";
+};
+
+&eth1 {
+	compatible = "syscon", "simple-mfd";
+};

target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts

@@ -113,6 +113,12 @@
 	phy12: ethernet-phy@c {
 		reg = <0xc>;
 		phy-mode = "mii";
+
+		resets = <&rst 8>;
+		reset-names = "phy";
+
+		reset-assert-us = <10000>;
+		reset-deassert-us = <10000>;
 	};
 };
 

target/linux/ath79/dts/ar9330.dtsi

@@ -119,11 +119,10 @@
 		};
 
 		spi: spi@1f000000 {
-			compatible = "qca,ar7100-spi";
-			reg = <0x1f000000 0x10>;
+			compatible = "qca,ar934x-spi";
+			reg = <0x1f000000 0x1c>;
 
 			clocks = <&pll ATH79_CLK_AHB>;
-			clock-names = "ahb";
 
 			#address-cells = <1>;
 			#size-cells = <0>;

target/linux/ath79/dts/ar9341_tplink.dtsi

@@ -18,9 +18,6 @@
 	keys: keys {
 		compatible = "gpio-keys";
 
-		pinctrl-names = "default";
-		pinctrl-0 = <&jtag_disable_pins>;
-
 		rfkill {
 			label = "WiFi";
 			linux,code = <KEY_RFKILL>;
@@ -85,7 +82,14 @@
 };
 
 &gpio {
-	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&jtag_disable_pins &pmx_usb_power>;
+};
+
+&pinmux {
+	pmx_usb_power: usb_power {
+		pinctrl-single,bits = <0x4 0x0 0xff>;
+	};
 };
 
 &eth0 {

target/linux/ath79/dts/ar9342_ubnt_bullet-m-xw.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_xw.dtsi"
 
 / {

target/linux/ath79/dts/ar9342_ubnt_lap-120.dts

@@ -1,8 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_wa.dtsi"
 
 / {

target/linux/ath79/dts/ar9342_ubnt_litebeam-ac-gen2.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_wa.dtsi"
 
 / {

target/linux/ath79/dts/ar9342_ubnt_nanobeam-ac.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_wa.dtsi"
 
 / {

target/linux/ath79/dts/ar9342_ubnt_nanostation-ac-loco.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_wa.dtsi"
 
 / {

target/linux/ath79/dts/ar9342_ubnt_nanostation-ac.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_wa.dtsi"
 
 / {

target/linux/ath79/dts/ar9342_ubnt_nanostation-loco-m-xw.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_xw.dtsi"
 
 / {
@@ -19,6 +16,7 @@
 	phy1: ethernet-phy@1 {
 		reg = <1>;
 		phy-mode = "mii";
+		reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
 	};
 };
 

target/linux/ath79/dts/ar9342_ubnt_nanostation-m-xw.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "ar9342_ubnt_xw.dtsi"
 
 / {

target/linux/ath79/dts/ar9344_qihoo_c301.dts

@@ -110,7 +110,6 @@
 	status = "okay";
 
 	num-cs = <2>;
-	cs-gpios= <0>, <0>;
 
 	flash@0 {
 		#address-cells = <1>;

target/linux/ath79/dts/ar9344_teltonika_rut955.dts

@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "ar9344.dtsi"
+
+/ {
+	model = "Teltonika RUT955";
+	compatible = "teltonika,rut955", "qca,ar9344";
+
+	aliases {
+		serial0 = &uart;
+		serial1 = &hs_uart;
+		led-boot = &led_system_green;
+		led-failsafe = &led_system_red;
+		led-running = &led_system_green;
+		led-upgrade = &led_system_red;
+		label-mac-device = &eth1;
+	};
+
+	i2c {
+		compatible = "i2c-gpio";
+		scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+		sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		hwmon@4d {
+			compatible = "microchip,mcp3221";
+			reg = <0x4d>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		signal1 {
+			label = "rut955:green:signal1";
+			gpios = <&gpio_ext 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		signal2 {
+			label = "rut955:green:signal2";
+			gpios = <&gpio_ext 1 GPIO_ACTIVE_HIGH>;
+		};
+
+		signal3 {
+			label = "rut955:green:signal3";
+			gpios = <&gpio_ext 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		signal4 {
+			label = "rut955:green:signal4";
+			gpios = <&gpio_ext 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		signal5 {
+			label = "rut955:green:signal5";
+			gpios = <&gpio_ext 4 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_system_red: system_red {
+			label = "rut955:red:system";
+			gpios = <&gpio_ext 5 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_system_green: system_green {
+			label = "rut955:green:system";
+			gpios = <&gpio_ext 6 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+			debounce-interval = <60>;
+		};
+	};
+};
+
+&gpio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&jtag_disable_pins>;
+
+	gpio-line-names = "RS485_D", "led_wan", "DIN3", "mmc_cs",
+		"ext_sck", "", "", "",
+		"", "", "", "",
+		"ext_mosi", "led_lan2", "led_lan1", "",
+		"i2c_scl", "i2c_sda", "", "DIN2",
+		"ext_cs", "DIN1", "led_lan3", "",
+		"", "", "", "",
+		"", "", "", "";
+
+	ext_sck {
+		gpio-hog;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:ext:sck";
+	};
+
+	ext_mosi {
+		gpio-hog;
+		gpios = <12 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:ext:mosi";
+	};
+
+	ext_cs {
+		gpio-hog;
+		gpios = <20 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "rut955:ext:cs";
+	};
+
+	mmc_cs {
+		gpio-hog;
+		gpios = <3 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:mmc:cs";
+	};
+
+	uart1_td {
+		gpio-hog;
+		gpios = <18 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:uart1:td";
+	};
+
+	uart1_rd {
+		gpio-hog;
+		gpios = <11 GPIO_ACTIVE_LOW>;
+		input;
+		line-name = "rut955:uart1:rd";
+	};
+
+	led_wan {
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:led:wan";
+	};
+
+	led_lan2 {
+		gpio-hog;
+		gpios = <13 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:led:lan2";
+	};
+
+	led_lan1 {
+		gpio-hog;
+		gpios = <14 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:led:lan1";
+	};
+
+	led_lan3 {
+		gpio-hog;
+		gpios = <22 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "rut955:led:lan3";
+	};
+};
+
+&ref {
+	clock-frequency = <40000000>;
+};
+
+&uart {
+	status = "okay";
+};
+
+&hs_uart {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmx_uart2>;
+
+	rts-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+	rs485-rts-active-low;
+	linux,rs485-enabled-at-boot-time;
+};
+
+&spi {
+	status = "okay";
+
+	num-cs = <3>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmx_spi>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "u-boot";
+				reg = <0x0 0x20000>;
+				read-only;
+			};
+
+			config: partition@20000 {
+				label = "config";
+				reg = <0x20000 0x10000>;
+				read-only;
+			};
+
+			art: partition@30000 {
+				label = "art";
+				reg = <0x30000 0x10000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "firmware";
+				reg = <0x40000 0xf30000>;
+				compatible = "tplink,firmware";
+			};
+
+			partition@f70000 {
+				label = "event-log";
+				reg = <0xf70000 0x90000>;
+				read-only;
+			};
+		};
+	};
+
+	microsd@1 {
+		status = "disabled";
+
+		compatible = "mmc-spi-slot";
+		spi-max-frequency = <25000000>;
+		reg = <1>;
+		voltage-ranges = <3200 3400>;
+		broken-cd;
+	};
+
+	gpio_ext: gpio_ext@2 {
+		compatible = "fairchild,74hc595";
+		reg = <2>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		registers-number = <2>;
+		spi-max-frequency = <10000000>;
+		gpio-line-names = "led_signal_bar1", "led_signal_bar2", "led_signal_bar3", "led_signal_bar4",
+			"led_signal_bar5", "led_status_red", "led_status_green", "sim_sel",
+			"DOUT1", "DOUT2", "modem_vbus", "modem_rst",
+			"DOUT3", "RS485_R", "SDCS", "HWRST";
+	};
+};
+
+&usb {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	port@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+
+		port@1 {
+			compatible = "usb-a-connector";
+			reg = <1>;
+		};
+
+		port@3 {
+			label = "RS-232 serial adapter";
+			reg = <3>;
+		};
+
+		port@4 {
+			label = "internal wwan modem";
+			reg = <4>;
+		};
+	};
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&wmac {
+	status = "okay";
+
+	mtd-cal-data = <&art 0x1000>;
+	mtd-mac-address = <&config 0x0>;
+	mtd-mac-address-increment = <2>;
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&swphy4>;
+
+	mtd-mac-address = <&config 0x0>;
+	mtd-mac-address-increment = <1>;
+};
+
+&eth1 {
+	status = "okay";
+
+	mtd-mac-address = <&config 0x0>;
+};
+
+&builtin_switch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pmx_leds_switch>;
+};
+
+&pinmux {
+	pmx_spi: spi {
+		// SPI_CS1 on GPIO 3, 2nd SCK on GPIO 4
+		// 2nd MOSI on GPIO 12, SPI_CS2 on GPIO 20
+		pinctrl-single,bits = <0x0 0x07000000 0xff000000>,
+					<0x4 0x0a 0xff>,
+					<0xc 0x0b 0xff>,
+					<0x14 0x08 0xff>;
+	};
+
+	pmx_leds_switch: leds_switch {
+		// switch port LEDs on GPIO 1, GPIO 13, GPIO 14 and GPIO 22
+		pinctrl-single,bits =  <0x0 0x00002d00 0x0000ff00>,
+					<0xc 0x002c2b00 0x00ffff00>,
+					<0x14 0x002a0000 0x00ff0000>;
+	};
+
+	pmx_uart2: uart2 {
+		// UART1_DTR on GPIO 0, UART1_RD on GPIO 11, UART1_TD on GPIO 18
+		pinctrl-single,bits = <0x0 0x0 0xff>,
+				<0x10 0x4f000000 0xff000000>,
+				<0x3c 0x000b0000 0x00ff0000>;
+	};
+};

target/linux/ath79/dts/ar934x.dtsi

@@ -133,6 +133,19 @@
 
 				#reset-cells = <1>;
 			};
+
+			hs_uart: uart@18500000 {
+				compatible = "qca,ar9330-uart";
+				reg = <0x18500000 0x14>;
+
+				interrupts = <6>;
+				interrupt-parent = <&miscintc>;
+
+				clocks = <&pll ATH79_CLK_UART1>;
+				clock-names = "uart";
+
+				status = "disabled";
+			};
 		};
 
 		nand: nand@1b000200 {
@@ -183,11 +196,10 @@
 		};
 
 		spi: spi@1f000000 {
-			compatible = "qca,ar9340-spi", "qca,ar7100-spi";
+			compatible = "qca,ar934x-spi";
 			reg = <0x1f000000 0x1c>;
 
 			clocks = <&pll ATH79_CLK_AHB>;
-			clock-names = "ahb";
 
 			#address-cells = <1>;
 			#size-cells = <0>;

target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi

@@ -1,3 +1,4 @@
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
@@ -75,7 +76,6 @@
 	status = "okay";
 
 	num-cs = <2>;
-	cs-gpios = <0>, <0>;
 
 	flash@0 {
 		compatible = "jedec,spi-nor";

target/linux/ath79/dts/qca953x.dtsi

@@ -201,11 +201,10 @@
 		};
 
 		spi: spi@1f000000 {
-			compatible = "qca,ar9530-spi", "qca,ar7100-spi";
-			reg = <0x1f000000 0x10>;
+			compatible = "qca,ar934x-spi";
+			reg = <0x1f000000 0x1c>;
 
 			clocks = <&pll ATH79_CLK_AHB>;
-			clock-names = "ahb";
 
 			status = "disabled";
 

target/linux/ath79/dts/qca9557.dtsi

@@ -292,11 +292,10 @@
 		};
 
 		spi: spi@1f000000 {
-			compatible = "qca,ar9557-spi", "qca,ar7100-spi";
-			reg = <0x1f000000 0x10>;
+			compatible = "qca,ar934x-spi";
+			reg = <0x1f000000 0x1c>;
 
 			clocks = <&pll ATH79_CLK_AHB>;
-			clock-names = "ahb";
 
 			status = "disabled";
 

target/linux/ath79/dts/qca9557_iodata_wn-ac1167dgr.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9557_iodata_wn-ac-dgr.dtsi"
 
 / {

target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9557_iodata_wn-ac-dgr.dtsi"
 
 / {

target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr2.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9557_iodata_wn-ac-dgr.dtsi"
 
 / {

target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9558_comfast_cf-wr650ac.dtsi"
 
 / {

target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9558_comfast_cf-wr650ac.dtsi"
 
 / {

target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd-v2.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9558_tplink_tl-wr1043nd.dtsi"
 
 / {

target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd-v3.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9558_tplink_tl-wr1043nd.dtsi"
 
 / {

target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9563_elecom_wrc-ghbk2-i.dtsi"
 
 / {

target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts

@@ -1,9 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /dts-v1/;
 
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
 #include "qca9563_elecom_wrc-ghbk2-i.dtsi"
 
 / {

target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi

@@ -75,7 +75,6 @@
 	status = "okay";
 
 	num-cs = <2>;
-	cs-gpios = <0>, <0>;
 
 	flash_nor: flash@0 {
 		compatible = "jedec,spi-nor";

target/linux/ath79/dts/qca9563_netgear_wndr.dtsi

@@ -100,7 +100,6 @@
 	status = "okay";
 
 	num-cs = <2>;
-	cs-gpios = <0>, <0>;
 
 	flash@0 {
 		compatible = "jedec,spi-nor";

target/linux/ath79/dts/qca956x.dtsi

@@ -215,11 +215,10 @@
 		};
 
 		spi: spi@1f000000 {
-			compatible = "qca,qca9560-spi", "qca,ar7100-spi";
-			reg = <0x1f000000 0x10>;
+			compatible = "qca,ar934x-spi";
+			reg = <0x1f000000 0x1c>;
 
 			clocks = <&pll ATH79_CLK_AHB>;
-			clock-names = "ahb";
 
 			status = "disabled";
 

target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/dts-v1/;
+
+#include "tp9343_tplink_tl-wr94x.dtsi"
+
+/ {
+	compatible = "tplink,tl-wr940n-v6", "qca,tp9343";
+	model = "TP-Link TL-WR940N v6";
+
+	aliases {
+		led-boot = &led_diag_orange;
+		led-failsafe = &led_diag_orange;
+		led-running = &led_diag_orange;
+		led-upgrade = &led_diag_orange;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wan_blue {
+			label = "tp-link:blue:wan";
+			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+		};
+
+		led_diag_orange: diag_orange {
+			label = "tp-link:orange:diag";
+			gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+};
+
+&eth1 {
+	mtd-mac-address = <&uboot 0x1fc00>;
+};

target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

@@ -1214,14 +1214,22 @@ static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 	unsigned int offset = ag->rx_buf_offset;
 	int ring_mask = BIT(ring->order) - 1;
 	int ring_size = BIT(ring->order);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
+	struct list_head rx_list;
+	struct sk_buff *next;
+#else
 	struct sk_buff_head queue;
+#endif
 	struct sk_buff *skb;
 	int done = 0;
 
 	DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 			dev->name, limit, ring->curr, ring->dirty);
-
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
+	INIT_LIST_HEAD(&rx_list);
+#else
 	skb_queue_head_init(&queue);
+#endif
 
 	while (done < limit) {
 		unsigned int i = ring->curr & ring_mask;
@@ -1263,7 +1271,11 @@ static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 		} else {
 			skb->dev = dev;
 			skb->ip_summed = CHECKSUM_NONE;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
+			list_add_tail(&skb->list, &rx_list);
+#else
 			__skb_queue_tail(&queue, skb);
+#endif
 		}
 
 next:
@@ -1275,10 +1287,16 @@ next:
 
 	ag71xx_ring_rx_refill(ag);
 
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,19,0))
+	list_for_each_entry_safe(skb, next, &rx_list, list)
+		skb->protocol = eth_type_trans(skb, dev);
+	netif_receive_skb_list(&rx_list);
+#else
 	while ((skb = __skb_dequeue(&queue)) != NULL) {
 		skb->protocol = eth_type_trans(skb, dev);
 		netif_receive_skb(skb);
 	}
+#endif
 
 	DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 		dev->name, ring->curr, ring->dirty, done);

target/linux/ath79/generic/base-files/etc/board.d/01_leds

@@ -219,6 +219,7 @@ tplink,cpe510-v3)
 tplink,cpe610-v1|\
 tplink,tl-wr902ac-v1)
 	ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0"
+	ucidef_set_led_netdev "internet" "Internet" "tp-link:green:internet" "eth0"
 	;;
 tplink,re355-v1|\
 tplink,re450-v1|\
@@ -243,9 +244,11 @@ trendnet,tew-823dru)
 	;;
 ubnt,bullet-m|\
 ubnt,bullet-m-xw|\
+ubnt,nanostation-loco-m|\
 ubnt,nanostation-loco-m-xw|\
 ubnt,nanostation-m|\
 ubnt,nanostation-m-xw|\
+ubnt,picostation-m|\
 ubnt,rocket-m)
 	ucidef_set_rssimon "wlan0" "200000" "1"
 	ucidef_set_led_rssi "rssilow" "RSSILOW" "ubnt:red:link1" "wlan0" "1" "100"

target/linux/ath79/generic/base-files/etc/board.d/02_network

@@ -30,6 +30,7 @@ ath79_setup_interfaces()
 	pisen,ts-d084|\
 	pisen,wmb001n|\
 	pisen,wmm003n|\
+	siemens,ws-ap3610|\
 	tplink,cpe210-v2|\
 	tplink,cpe210-v3|\
 	tplink,cpe510-v2|\
@@ -46,7 +47,9 @@ ath79_setup_interfaces()
 	ubnt,litebeam-ac-gen2|\
 	ubnt,nanobeam-ac|\
 	ubnt,nanostation-ac-loco|\
+	ubnt,nanostation-loco-m|\
 	ubnt,nanostation-loco-m-xw|\
+	ubnt,picostation-m|\
 	ubnt,rocket-m|\
 	ubnt,unifiac-lite|\
 	ubnt,unifiac-lr|\
@@ -217,6 +220,11 @@ ath79_setup_interfaces()
 		ucidef_add_switch "switch0" \
 			"0@eth0" "1:lan" "2:lan" "3:wan"
 		;;
+	teltonika,rut955)
+		ucidef_set_interface_wan "eth1"
+		ucidef_add_switch "switch0" \
+			"0@eth0" "2:lan:3" "3:lan:2" "4:lan:1"
+		;;
 	tplink,archer-a7-v5|\
 	tplink,archer-c6-v2|\
 	tplink,archer-c6-v2-us|\
@@ -425,7 +433,9 @@ ath79_setup_macs()
 		;;
 	ubnt,airrouter|\
 	ubnt,bullet-m|\
+	ubnt,nanostation-loco-m|\
 	ubnt,nanostation-m|\
+	ubnt,picostation-m|\
 	ubnt,rocket-m|\
 	ubnt,unifi)
 		label_mac=$(cat /sys/class/ieee80211/phy0/macaddress)

target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches

@@ -38,6 +38,14 @@ dlink,dir-835-a1)
 librerouter,librerouter-v1)
 	ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "1" "0"
 	;;
+teltonika,rut955)
+	ucidef_add_gpio_switch "sim_sel" "SIM select" "503" "1"
+	ucidef_add_gpio_switch "DOUT1" "DOUT1 (OC)" "504" "0"
+	ucidef_add_gpio_switch "DOUT2" "DOUT2 (Relay)" "505" "0"
+	ucidef_add_gpio_switch "modem_vbus" "Modem enable" "506" "1"
+	ucidef_add_gpio_switch "modem_rst" "Modem reset" "507" "0"
+	ucidef_add_gpio_switch "DOUT3" "DOUT3" "508" "0"
+	;;
 tplink,archer-c25-v1)
 	ucidef_add_gpio_switch "led_control" "LED control" "21" "0"
 	ucidef_add_gpio_switch "led_reset" "LED reset" "19" "1"

target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom

@@ -163,7 +163,9 @@ case "$FIRMWARE" in
 	tplink,tl-wr842n-v1|\
 	ubnt,airrouter|\
 	ubnt,bullet-m|\
+	ubnt,nanostation-loco-m|\
 	ubnt,nanostation-m|\
+	ubnt,picostation-m|\
 	ubnt,rocket-m)
 		ath9k_eeprom_extract "art" 0x1000 0x1000
 		;;

target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac

@@ -34,6 +34,9 @@ case "$board" in
 		[ "$PHYNBR" -eq 1 ] && \
 			k2t_get_mac "lan_mac" > /sys${DEVPATH}/macaddress
 		;;
+	siemens,ws-ap3610)
+		mtd_get_mac_ascii cfg1 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress
+		;;
 	trendnet,tew-823dru)
 		# set the 2.4G interface mac address to LAN MAC
 		[ "$PHYNBR" -eq 1 ] && \

target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh

@@ -0,0 +1,13 @@
+#!/bin/sh
+
+. /lib/functions.sh
+
+preinit_set_mac_address() {
+	case $(board_name) in
+	siemens,ws-ap3610)
+		ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr)
+		;;
+	esac
+}
+
+boot_hook_add preinit_main preinit_set_mac_address

target/linux/ath79/generic/config-default

@@ -1,4 +1,5 @@
 CONFIG_AT803X_PHY=y
+CONFIG_BROADCOM_PHY=y
 CONFIG_GPIO_WATCHDOG=y
 CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
 CONFIG_INTEL_XWAY_PHY=y

target/linux/ath79/generic/target.mk

@@ -1,7 +1,7 @@
 BOARDNAME:=Generic
 FEATURES += minor squashfs
 
-DEFAULT_PACKAGES += wpad
+DEFAULT_PACKAGES += wpad-basic
 
 define Target/Description
 	Build firmware images for generic Atheros AR71xx/AR913x/AR934x based boards.

target/linux/ath79/image/common-tp-link.mk

@@ -11,6 +11,7 @@ endef
 
 define Device/tplink-v1
   DEVICE_VENDOR := TP-Link
+  TPLINK_HWID := 0x0
   TPLINK_HWREV := 0x1
   TPLINK_HEADER_VERSION := 1
   LOADER_TYPE := gz
@@ -23,6 +24,7 @@ endef
 
 define Device/tplink-v2
   DEVICE_VENDOR := TP-Link
+  TPLINK_HWID := 0x0
   TPLINK_HWREV := 0x1
   TPLINK_HWREVADD := 0x0
   TPLINK_HVERSION := 3
@@ -74,9 +76,10 @@ endef
 
 define Device/tplink-safeloader
   $(Device/tplink-v1)
+  TPLINK_HWREV := 0x0
   KERNEL := kernel-bin | append-dtb | lzma | tplink-v1-header -O
   IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | \
-    append-metadata | check-size $$$$(IMAGE_SIZE)
+	append-metadata | check-size $$$$(IMAGE_SIZE)
   IMAGE/factory.bin := append-rootfs | tplink-safeloader factory
 endef
 

target/linux/ath79/image/generic-tp-link.mk

@@ -320,8 +320,6 @@ define Device/tplink_re350k-v1
   DEVICE_VARIANT := v1
   DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct
   TPLINK_BOARD_ID := RE350K-V1
-  TPLINK_HWID := 0x0
-  TPLINK_HWREV := 0
 endef
 TARGET_DEVICES += tplink_re350k-v1
 
@@ -330,8 +328,6 @@ define Device/tplink_rex5x-v1
   SOC := qca9558
   IMAGE_SIZE := 6016k
   DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
-  TPLINK_HWID := 0x0
-  TPLINK_HWREV := 0
 endef
 
 define Device/tplink_re355-v1
@@ -359,8 +355,6 @@ define Device/tplink_re450-v2
   DEVICE_MODEL := RE450
   DEVICE_VARIANT := v2
   DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
-  TPLINK_HWID := 0x0
-  TPLINK_HWREV := 0
   TPLINK_BOARD_ID := RE450-V2
   LOADER_TYPE := elf
 endef
@@ -585,8 +579,6 @@ define Device/tplink_tl-wr902ac-v1
 	-swconfig -uboot-envtools
   TPLINK_BOARD_ID := TL-WR902AC-V1
   IMAGE_SIZE := 7360k
-  TPLINK_HWID := 0x0
-  TPLINK_HWREV := 0
   SUPPORTED_DEVICES += tl-wr902ac-v1
 endef
 TARGET_DEVICES += tplink_tl-wr902ac-v1

target/linux/ath79/image/generic-ubnt.mk

@@ -179,6 +179,14 @@ define Device/ubnt_nanostation-ac-loco
 endef
 TARGET_DEVICES += ubnt_nanostation-ac-loco
 
+define Device/ubnt_nanostation-loco-m
+  $(Device/ubnt-xm)
+  DEVICE_MODEL := Nanostation Loco M
+  DEVICE_PACKAGES += rssileds
+  SUPPORTED_DEVICES += bullet-m
+endef
+TARGET_DEVICES += ubnt_nanostation-loco-m
+
 define Device/ubnt_nanostation-loco-m-xw
   $(Device/ubnt-xw)
   DEVICE_MODEL := Nanostation Loco M
@@ -203,6 +211,14 @@ define Device/ubnt_nanostation-m-xw
 endef
 TARGET_DEVICES += ubnt_nanostation-m-xw
 
+define Device/ubnt_picostation-m
+  $(Device/ubnt-xm)
+  DEVICE_MODEL := Picostation M
+  DEVICE_PACKAGES += rssileds
+  SUPPORTED_DEVICES += bullet-m
+endef
+TARGET_DEVICES += ubnt_picostation-m
+
 define Device/ubnt_rocket-m
   $(Device/ubnt-xm)
   DEVICE_MODEL := Rocket-M

target/linux/ath79/image/generic.mk

@@ -36,6 +36,11 @@ define Build/addpattern
 	-mv "$@.new" "$@"
 endef
 
+define Build/append-md5sum-bin
+	$(STAGING_DIR_HOST)/bin/mkhash md5 $@ | sed 's/../\\\\x&/g' |\
+		xargs echo -ne >> $@
+endef
+
 define Build/cybertan-trx
 	@echo -n '' > $@-empty.bin
 	-$(STAGING_DIR_HOST)/bin/trx -o $@.new \
@@ -73,6 +78,17 @@ define Build/pisen_wmb001n-factory
   rm -rf "$@.tmp"
 endef
 
+define Build/teltonika-fw-fake-checksum
+	# Teltonika U-Boot web based firmware upgrade/recovery routine compares
+	# 16 bytes from md5sum1[16] field in TP-Link v1 header (offset: 76 bytes
+	# from begin of the firmware file) with 16 bytes stored just before
+	# 0xdeadc0de marker. Values are only compared, MD5 sum is not verified.
+	let \
+		offs="$$(stat -c%s $@) - 20"; \
+		dd if=$@ bs=1 count=16 skip=76 |\
+		dd of=$@ bs=1 count=16 seek=$$offs conv=notrunc
+endef
+
 define Device/seama
   KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma
   KERNEL_INITRAMFS := $$(KERNEL) | seama
@@ -158,6 +174,7 @@ define Device/avm_fritz300e
 	append-squashfs-fakeroot-be | pad-to 256 | append-rootfs | pad-rootfs | \
 	append-metadata | check-size $$$$(IMAGE_SIZE)
   DEVICE_PACKAGES := fritz-tffs rssileds -swconfig
+  SUPPORTED_DEVICES += fritz300e
 endef
 TARGET_DEVICES += avm_fritz300e
 
@@ -1040,6 +1057,21 @@ define Device/rosinson_wr818
 endef
 TARGET_DEVICES += rosinson_wr818
 
+define Device/siemens_ws-ap3610
+  SOC := ar7161
+  DEVICE_VENDOR := Siemens
+  DEVICE_MODEL := WS-AP3610
+  IMAGE_SIZE := 14336k
+  BLOCKSIZE := 256k
+  LOADER_TYPE := bin
+  LOADER_FLASH_OFFS := 0x82000
+  COMPILE := loader-$(1).bin
+  COMPILE/loader-$(1).bin := loader-okli-compile
+  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49 | loader-okli $(1) 8128 | uImage none
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none
+endef
+TARGET_DEVICES += siemens_ws-ap3610
+
 define Device/sitecom_wlr-7100
   SOC := ar1022
   DEVICE_VENDOR := Sitecom
@@ -1054,6 +1086,28 @@ define Device/sitecom_wlr-7100
 endef
 TARGET_DEVICES += sitecom_wlr-7100
 
+define Device/teltonika_rut955
+  SOC := ar9344
+  DEVICE_VENDOR := Teltonika
+  DEVICE_MODEL := RUT955
+  DEVICE_PACKAGES := kmod-usb2 kmod-usb-acm kmod-usb-net-qmi-wwan \
+	kmod-usb-serial-option kmod-hwmon-mcp3021 uqmi -uboot-envtools
+  IMAGE_SIZE := 15552k
+  TPLINK_HWID := 0x35000001
+  TPLINK_HWREV := 0x1
+  TPLINK_HEADER_VERSION := 1
+  KERNEL := kernel-bin | append-dtb | lzma | tplink-v1-header
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs |\
+	pad-rootfs | teltonika-fw-fake-checksum | append-string master |\
+	append-md5sum-bin | check-size $$$$(IMAGE_SIZE)
+  IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) |\
+	append-rootfs | pad-rootfs | append-metadata |\
+	check-size $$$$(IMAGE_SIZE)
+endef
+TARGET_DEVICES += teltonika_rut955
+
 define Device/trendnet_tew-823dru
   SOC := qca9558
   DEVICE_VENDOR := Trendnet

target/linux/ath79/image/tiny-tp-link.mk

@@ -66,6 +66,46 @@ define Device/tplink_tl-mr3420-v2
 endef
 TARGET_DEVICES += tplink_tl-mr3420-v2
 
+define Device/tplink_tl-wa701nd-v1
+  $(Device/tplink-4m)
+  SOC := ar7240
+  DEVICE_MODEL := TL-WA701ND
+  DEVICE_VARIANT := v1
+  TPLINK_HWID := 0x07010001
+  SUPPORTED_DEVICES += tl-wa901nd
+endef
+TARGET_DEVICES += tplink_tl-wa701nd-v1
+
+define Device/tplink_tl-wa730re-v1
+  $(Device/tplink-4m)
+  SOC := ar7240
+  DEVICE_MODEL := TL-WA730RE
+  DEVICE_VARIANT := v1
+  TPLINK_HWID := 0x07300001
+  SUPPORTED_DEVICES += tl-wa901nd
+endef
+TARGET_DEVICES += tplink_tl-wa730re-v1
+
+define Device/tplink_tl-wa801nd-v1
+  $(Device/tplink-4m)
+  SOC := ar7240
+  DEVICE_MODEL := TL-WA801ND
+  DEVICE_VARIANT := v1
+  TPLINK_HWID := 0x08010001
+  SUPPORTED_DEVICES += tl-wa901nd
+endef
+TARGET_DEVICES += tplink_tl-wa801nd-v1
+
+define Device/tplink_tl-wa830re-v1
+  $(Device/tplink-4m)
+  SOC := ar7240
+  DEVICE_MODEL := TL-WA830RE
+  DEVICE_VARIANT := v1
+  TPLINK_HWID := 0x08300010
+  SUPPORTED_DEVICES += tl-wa901nd
+endef
+TARGET_DEVICES += tplink_tl-wa830re-v1
+
 define Device/tplink_tl-wa850re-v1
   $(Device/tplink-4mlzma)
   SOC := ar9341
@@ -85,12 +125,21 @@ define Device/tplink_tl-wa850re-v2
   DEVICE_VARIANT := v2
   TPLINK_BOARD_ID := TLWA850REV2
   TPLINK_HWID := 0x08500002
-  TPLINK_HWREV := 0x0
   DEVICE_PACKAGES := rssileds
   SUPPORTED_DEVICES += tl-wa850re-v2
 endef
 TARGET_DEVICES += tplink_tl-wa850re-v2
 
+define Device/tplink_tl-wa901nd-v1
+  $(Device/tplink-4m)
+  SOC := ar7240
+  DEVICE_MODEL := TL-WA901ND
+  DEVICE_VARIANT := v1
+  TPLINK_HWID := 0x09010001
+  SUPPORTED_DEVICES += tl-wa901nd
+endef
+TARGET_DEVICES += tplink_tl-wa901nd-v1
+
 define Device/tplink_tl-wa901nd-v2
   $(Device/tplink-4m)
   SOC := ar9132
@@ -264,6 +313,20 @@ define Device/tplink_tl-wr940n-v4
 endef
 TARGET_DEVICES += tplink_tl-wr940n-v4
 
+define Device/tplink_tl-wr940n-v6
+  $(Device/tplink-4mlzma)
+  SOC := tp9343
+  DEVICE_MODEL := TL-WR940N
+  DEVICE_VARIANT := v6
+  TPLINK_HWID := 0x09400006
+  SUPPORTED_DEVICES += tl-wr940n-v6
+  IMAGES += factory-us.bin factory-eu.bin factory-br.bin
+  IMAGE/factory-us.bin := tplink-v1-image factory -C US
+  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU
+  IMAGE/factory-br.bin := tplink-v1-image factory -C BR
+endef
+TARGET_DEVICES += tplink_tl-wr940n-v6
+
 define Device/tplink_tl-wr941-v2
   $(Device/tplink-4m)
   SOC := ar9132

target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch

@@ -811,7 +811,7 @@
   * No flags defined yet.
 --- a/net/core/utils.c
 +++ b/net/core/utils.c
-@@ -424,8 +424,14 @@ void inet_proto_csum_replace16(__sum16 *
+@@ -441,8 +441,14 @@ void inet_proto_csum_replace16(__sum16 *
  			       bool pseudohdr)
  {
  	__be32 diff[] = {

target/linux/ath79/patches-4.19/0039-MIPS-ath79-export-UART1-reference-clock.patch

@@ -0,0 +1,52 @@
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
+ 	[ATH79_CLK_AHB] = "ahb",
+ 	[ATH79_CLK_REF] = "ref",
+ 	[ATH79_CLK_MDIO] = "mdio",
++	[ATH79_CLK_UART1] = "uart1",
+ };
+ 
+ static const char * __init ath79_clk_name(int type)
+@@ -346,6 +347,9 @@ static void __init ar934x_clocks_init(vo
+ 	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
+ 		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
+ 
++	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
++		ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
++
+ 	iounmap(dpll_base);
+ }
+ 
+@@ -651,6 +655,9 @@ static void __init ath79_clocks_init_dt(
+ 	if (!clks[ATH79_CLK_MDIO])
+ 		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+ 
++	if (!clks[ATH79_CLK_UART1])
++		clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
++
+ 	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
+ 		pr_err("%pOF: could not register clk provider\n", np);
+ 		goto err_iounmap;
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+@@ -351,6 +351,7 @@
+ #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
+ 
+ #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL	BIT(7)
+ 
+ #define QCA953X_PLL_CPU_CONFIG_REG		0x00
+ #define QCA953X_PLL_DDR_CONFIG_REG		0x04
+--- a/include/dt-bindings/clock/ath79-clk.h
++++ b/include/dt-bindings/clock/ath79-clk.h
+@@ -15,7 +15,8 @@
+ #define ATH79_CLK_AHB		2
+ #define ATH79_CLK_REF		3
+ #define ATH79_CLK_MDIO		4
++#define ATH79_CLK_UART1		5
+ 
+-#define ATH79_CLK_END		5
++#define ATH79_CLK_END		6
+ 
+ #endif /* __DT_BINDINGS_ATH79_CLK_H */

target/linux/ath79/patches-4.19/0050-v5.1-drivers-provide-devm_platform_ioremap_resource.patch

@@ -0,0 +1,61 @@
+From 7945f929f1a77a1c8887a97ca07f87626858ff42 Mon Sep 17 00:00:00 2001
+From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Date: Wed, 20 Feb 2019 11:12:39 +0000
+Subject: [PATCH] drivers: provide devm_platform_ioremap_resource()
+
+There are currently 1200+ instances of using platform_get_resource()
+and devm_ioremap_resource() together in the kernel tree.
+
+This patch wraps these two calls in a single helper. Thanks to that
+we don't have to declare a local variable for struct resource * and can
+omit the redundant argument for resource type. We also have one
+function call less.
+
+Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
+Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/base/platform.c         | 18 ++++++++++++++++++
+ include/linux/platform_device.h |  3 +++
+ 2 files changed, 21 insertions(+)
+
+--- a/drivers/base/platform.c
++++ b/drivers/base/platform.c
+@@ -81,6 +81,24 @@ struct resource *platform_get_resource(s
+ EXPORT_SYMBOL_GPL(platform_get_resource);
+ 
+ /**
++ * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform
++ *				    device
++ *
++ * @pdev: platform device to use both for memory resource lookup as well as
++ *        resource managemend
++ * @index: resource index
++ */
++void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev,
++					     unsigned int index)
++{
++	struct resource *res;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
++	return devm_ioremap_resource(&pdev->dev, res);
++}
++EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource);
++
++/**
+  * platform_get_irq - get an IRQ for a device
+  * @dev: platform device
+  * @num: IRQ number index
+--- a/include/linux/platform_device.h
++++ b/include/linux/platform_device.h
+@@ -51,6 +51,9 @@ extern struct device platform_bus;
+ extern void arch_setup_pdev_archdata(struct platform_device *);
+ extern struct resource *platform_get_resource(struct platform_device *,
+ 					      unsigned int, unsigned int);
++extern void __iomem *
++devm_platform_ioremap_resource(struct platform_device *pdev,
++			       unsigned int index);
+ extern int platform_get_irq(struct platform_device *, unsigned int);
+ extern int platform_irq_count(struct platform_device *);
+ extern struct resource *platform_get_resource_byname(struct platform_device *,

target/linux/ath79/patches-4.19/0051-spi-add-driver-for-ar934x-spi-controller.patch

@@ -0,0 +1,283 @@
+From 7e161c423a232ef7ddf6c11b09ebe471dd5a23cf Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Wed, 5 Feb 2020 18:25:37 +0800
+Subject: [PATCH v4 1/2] spi: add driver for ar934x spi controller
+
+This patch adds driver for SPI controller found in Qualcomm Atheros
+AR934x/QCA95xx SoCs.
+This controller is a superset of the already supported qca,ar7100-spi.
+Besides the bit-bang mode in spi-ath79.c, this new controller added
+a new "shift register" mode, allowing faster spi operations.
+
+Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
+---
+ drivers/spi/Kconfig      |   7 ++
+ drivers/spi/Makefile     |   1 +
+ drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 243 insertions(+)
+ create mode 100644 drivers/spi/spi-ar934x.c
+
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -61,6 +61,13 @@ config SPI_ALTERA
+ 	help
+ 	  This is the driver for the Altera SPI Controller.
+ 
++config SPI_AR934X
++	tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
++	depends on ATH79 || COMPILE_TEST
++	help
++	  This enables support for the SPI controller present on the
++	  Qualcomm Atheros AR934X/QCA95XX SoCs.
++
+ config SPI_ATH79
+ 	tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
+ 	depends on ATH79 && GPIOLIB
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST)		+= spi-
+ 
+ # SPI master controller drivers (bus)
+ obj-$(CONFIG_SPI_ALTERA)		+= spi-altera.o
++obj-$(CONFIG_SPI_AR934X)		+= spi-ar934x.o
+ obj-$(CONFIG_SPI_ARMADA_3700)		+= spi-armada-3700.o
+ obj-$(CONFIG_SPI_ATMEL)			+= spi-atmel.o
+ obj-$(CONFIG_SPI_ATH79)			+= spi-ath79.o
+--- /dev/null
++++ b/drivers/spi/spi-ar934x.c
+@@ -0,0 +1,235 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
++//
++// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
++//
++// Based on spi-mt7621.c:
++// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
++// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
++
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/spi/spi.h>
++
++#define DRIVER_NAME "spi-ar934x"
++
++#define AR934X_SPI_REG_FS		0x00
++#define AR934X_SPI_ENABLE		BIT(0)
++
++#define AR934X_SPI_REG_IOC		0x08
++#define AR934X_SPI_IOC_INITVAL		0x70000
++
++#define AR934X_SPI_REG_CTRL		0x04
++#define AR934X_SPI_CLK_MASK		GENMASK(5, 0)
++
++#define AR934X_SPI_DATAOUT		0x10
++
++#define AR934X_SPI_REG_SHIFT_CTRL	0x14
++#define AR934X_SPI_SHIFT_EN		BIT(31)
++#define AR934X_SPI_SHIFT_CS(n)		BIT(28 + (n))
++#define AR934X_SPI_SHIFT_TERM		26
++#define AR934X_SPI_SHIFT_VAL(cs, term, count)			\
++	(AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |	\
++	(term) << AR934X_SPI_SHIFT_TERM | (count))
++
++#define AR934X_SPI_DATAIN 0x18
++
++struct ar934x_spi {
++	struct spi_controller *ctlr;
++	void __iomem *base;
++	struct clk *clk;
++	unsigned int clk_freq;
++};
++
++static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
++{
++	int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
++
++	if (div < 0)
++		return 0;
++	else if (div > AR934X_SPI_CLK_MASK)
++		return -EINVAL;
++	else
++		return div;
++}
++
++static int ar934x_spi_setup(struct spi_device *spi)
++{
++	struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
++
++	if ((spi->max_speed_hz == 0) ||
++	    (spi->max_speed_hz > (sp->clk_freq / 2))) {
++		spi->max_speed_hz = sp->clk_freq / 2;
++	} else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
++		dev_err(&spi->dev, "spi clock is too low\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ar934x_spi_transfer_one_message(struct spi_controller *master,
++					   struct spi_message *m)
++{
++	struct ar934x_spi *sp = spi_controller_get_devdata(master);
++	struct spi_transfer *t = NULL;
++	struct spi_device *spi = m->spi;
++	unsigned long trx_done, trx_cur;
++	int stat = 0;
++	u8 term = 0;
++	int div, i;
++	u32 reg;
++	const u8 *tx_buf;
++	u8 *buf;
++
++	m->actual_length = 0;
++	list_for_each_entry(t, &m->transfers, transfer_list) {
++		if (t->speed_hz)
++			div = ar934x_spi_clk_div(sp, t->speed_hz);
++		else
++			div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
++		if (div < 0) {
++			stat = -EIO;
++			goto msg_done;
++		}
++
++		reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
++		reg &= ~AR934X_SPI_CLK_MASK;
++		reg |= div;
++		iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
++		iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
++
++		for (trx_done = 0; trx_done < t->len; trx_done += 4) {
++			trx_cur = t->len - trx_done;
++			if (trx_cur > 4)
++				trx_cur = 4;
++			else if (list_is_last(&t->transfer_list, &m->transfers))
++				term = 1;
++
++			if (t->tx_buf) {
++				tx_buf = t->tx_buf + trx_done;
++				reg = tx_buf[0];
++				for (i = 1; i < trx_cur; i++)
++					reg = reg << 8 | tx_buf[i];
++				iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
++			}
++
++			reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
++						   trx_cur * 8);
++			iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
++			stat = readl_poll_timeout(
++				sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
++				!(reg & AR934X_SPI_SHIFT_EN), 0, 5);
++			if (stat < 0)
++				goto msg_done;
++
++			if (t->rx_buf) {
++				reg = ioread32(sp->base + AR934X_SPI_DATAIN);
++				buf = t->rx_buf + trx_done;
++				for (i = 0; i < trx_cur; i++) {
++					buf[trx_cur - i - 1] = reg & 0xff;
++					reg >>= 8;
++				}
++			}
++		}
++		m->actual_length += t->len;
++	}
++
++msg_done:
++	m->status = stat;
++	spi_finalize_current_message(master);
++
++	return 0;
++}
++
++static const struct of_device_id ar934x_spi_match[] = {
++	{ .compatible = "qca,ar934x-spi" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ar934x_spi_match);
++
++static int ar934x_spi_probe(struct platform_device *pdev)
++{
++	struct spi_controller *ctlr;
++	struct ar934x_spi *sp;
++	void __iomem *base;
++	struct clk *clk;
++	int ret;
++
++	base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(clk)) {
++		dev_err(&pdev->dev, "failed to get clock\n");
++		return PTR_ERR(clk);
++	}
++
++	ret = clk_prepare_enable(clk);
++	if (ret)
++		return ret;
++
++	ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
++	if (!ctlr) {
++		dev_info(&pdev->dev, "failed to allocate spi controller\n");
++		return -ENOMEM;
++	}
++
++	/* disable flash mapping and expose spi controller registers */
++	iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
++	/* restore pins to default state: CSn=1 DO=CLK=0 */
++	iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
++
++	ctlr->mode_bits = SPI_LSB_FIRST;
++	ctlr->setup = ar934x_spi_setup;
++	ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
++	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
++	ctlr->dev.of_node = pdev->dev.of_node;
++	ctlr->num_chipselect = 3;
++
++	dev_set_drvdata(&pdev->dev, ctlr);
++
++	sp = spi_controller_get_devdata(ctlr);
++	sp->base = base;
++	sp->clk = clk;
++	sp->clk_freq = clk_get_rate(clk);
++	sp->ctlr = ctlr;
++
++	return devm_spi_register_controller(&pdev->dev, ctlr);
++}
++
++static int ar934x_spi_remove(struct platform_device *pdev)
++{
++	struct spi_controller *ctlr;
++	struct ar934x_spi *sp;
++
++	ctlr = dev_get_drvdata(&pdev->dev);
++	sp = spi_controller_get_devdata(ctlr);
++
++	clk_disable_unprepare(sp->clk);
++
++	return 0;
++}
++
++static struct platform_driver ar934x_spi_driver = {
++	.driver = {
++		.name = DRIVER_NAME,
++		.of_match_table = ar934x_spi_match,
++	},
++	.probe = ar934x_spi_probe,
++	.remove = ar934x_spi_remove,
++};
++
++module_platform_driver(ar934x_spi_driver);
++
++MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
++MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:" DRIVER_NAME);

target/linux/ath79/patches-4.19/0060-serial-ar933x_uart-set-UART_CS_-RX-TX-_READY_ORIDE.patch

@@ -0,0 +1,64 @@
+From patchwork Fri Feb  7 09:53:35 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 1190470
+Date: Fri, 7 Feb 2020 11:53:35 +0200
+From: Daniel Golle <daniel@makrotopia.org>
+To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
+        Jiri Slaby <jslaby@suse.com>,
+        Chuanhong Guo <gch981213@gmail.com>,
+        Eitan Cohen <eitan@neot-semadar.com>,
+        Ori Gofen <origofen@gmail.com>
+Subject: [PATCH] serial: ar933x_uart: set UART_CS_{RX,TX}_READY_ORIDE
+Message-ID: <20200207095335.GA179836@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+Sender: linux-kernel-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-kernel.vger.kernel.org>
+X-Mailing-List: linux-kernel@vger.kernel.org
+
+On AR934x this UART is usually not initialized by the bootloader
+as it is only used as a secondary serial port while the primary
+UART is a newly introduced NS16550-compatible.
+In order to make use of the ar933x-uart on AR934x without RTS/CTS
+hardware flow control, one needs to set the
+UART_CS_{RX,TX}_READY_ORIDE bits as other than on AR933x where this
+UART is used as primary/console, the bootloader on AR934x typically
+doesn't set those bits.
+Setting them explicitely on AR933x should not do any harm, so just
+set them unconditionally.
+
+Tested-by: Chuanhong Guo <gch981213@gmail.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/tty/serial/ar933x_uart.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/tty/serial/ar933x_uart.c
++++ b/drivers/tty/serial/ar933x_uart.c
+@@ -286,6 +286,10 @@ static void ar933x_uart_set_termios(stru
+ 	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+ 			    AR933X_UART_CS_HOST_INT_EN);
+ 
++	/* enable RX and TX ready overide */
++	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
++		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
++
+ 	/* reenable the UART */
+ 	ar933x_uart_rmw(up, AR933X_UART_CS_REG,
+ 			AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S,
+@@ -418,6 +422,10 @@ static int ar933x_uart_startup(struct ua
+ 	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
+ 			    AR933X_UART_CS_HOST_INT_EN);
+ 
++	/* enable RX and TX ready overide */
++	ar933x_uart_rmw_set(up, AR933X_UART_CS_REG,
++		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
++
+ 	/* Enable RX interrupts */
+ 	up->ier = AR933X_UART_INT_RX_VALID;
+ 	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);

target/linux/ath79/patches-4.19/0061-tty-serial-ar933x-uart-rs485-gpio.patch

@@ -0,0 +1,267 @@
+From patchwork Fri Feb 21 21:23:31 2020
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 1198835
+Date: Fri, 21 Feb 2020 22:23:31 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org
+Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
+ Jiri Slaby <jslaby@suse.com>, Petr =?utf-8?q?=C5=A0tetiar?= <ynezz@true.cz>,
+ Chuanhong Guo <gch981213@gmail.com>, Piotr Dymacz <pepe2k@gmail.com>
+Subject: [PATCH v2] serial: ar933x_uart: add RS485 support
+Message-ID: <20200221212331.GA21467@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+Sender: linux-kernel-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-kernel.vger.kernel.org>
+X-Mailing-List: linux-kernel@vger.kernel.org
+
+Emulate half-duplex operation and use mctrl_gpio to add support for
+RS485 tranceiver with transmit/receive switch hooked to RTS GPIO line.
+This is needed to make use of the RS485 port found on Teltonika RUT955.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+v2: use bool to indicate ongoing half-duplex send, use it afterwards
+    to decide whether we've just been in a send operation.
+
+ drivers/tty/serial/Kconfig       |   1 +
+ drivers/tty/serial/ar933x_uart.c | 113 +++++++++++++++++++++++++++++--
+ 2 files changed, 108 insertions(+), 6 deletions(-)
+
+--- a/drivers/tty/serial/Kconfig
++++ b/drivers/tty/serial/Kconfig
+@@ -1296,6 +1296,7 @@ config SERIAL_AR933X
+ 	tristate "AR933X serial port support"
+ 	depends on HAVE_CLK && ATH79
+ 	select SERIAL_CORE
++	select SERIAL_MCTRL_GPIO if GPIOLIB
+ 	help
+ 	  If you have an Atheros AR933X SOC based board and want to use the
+ 	  built-in UART of the SoC, say Y to this option.
+--- a/drivers/tty/serial/ar933x_uart.c
++++ b/drivers/tty/serial/ar933x_uart.c
+@@ -13,6 +13,7 @@
+ #include <linux/console.h>
+ #include <linux/sysrq.h>
+ #include <linux/delay.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/platform_device.h>
+ #include <linux/of.h>
+ #include <linux/of_platform.h>
+@@ -29,6 +30,8 @@
+ 
+ #include <asm/mach-ath79/ar933x_uart.h>
+ 
++#include "serial_mctrl_gpio.h"
++
+ #define DRIVER_NAME "ar933x-uart"
+ 
+ #define AR933X_UART_MAX_SCALE	0xff
+@@ -47,6 +50,8 @@ struct ar933x_uart_port {
+ 	unsigned int		min_baud;
+ 	unsigned int		max_baud;
+ 	struct clk		*clk;
++	struct mctrl_gpios	*gpios;
++	struct gpio_desc	*rts_gpiod;
+ };
+ 
+ static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
+@@ -100,6 +105,18 @@ static inline void ar933x_uart_stop_tx_i
+ 	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
+ }
+ 
++static inline void ar933x_uart_start_rx_interrupt(struct ar933x_uart_port *up)
++{
++	up->ier |= AR933X_UART_INT_RX_VALID;
++	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++}
++
++static inline void ar933x_uart_stop_rx_interrupt(struct ar933x_uart_port *up)
++{
++	up->ier &= ~AR933X_UART_INT_RX_VALID;
++	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++}
++
+ static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch)
+ {
+ 	unsigned int rdata;
+@@ -125,11 +142,21 @@ static unsigned int ar933x_uart_tx_empty
+ 
+ static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
+ {
+-	return TIOCM_CAR;
++	struct ar933x_uart_port *up =
++		container_of(port, struct ar933x_uart_port, port);
++	int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
++
++	mctrl_gpio_get(up->gpios, &ret);
++
++	return ret;
+ }
+ 
+ static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+ {
++	struct ar933x_uart_port *up =
++		container_of(port, struct ar933x_uart_port, port);
++
++	mctrl_gpio_set(up->gpios, mctrl);
+ }
+ 
+ static void ar933x_uart_start_tx(struct uart_port *port)
+@@ -140,6 +167,37 @@ static void ar933x_uart_start_tx(struct
+ 	ar933x_uart_start_tx_interrupt(up);
+ }
+ 
++static void ar933x_uart_wait_tx_complete(struct ar933x_uart_port *up)
++{
++	unsigned int status;
++	unsigned int timeout = 60000;
++
++	/* Wait up to 60ms for the character(s) to be sent. */
++	do {
++		status = ar933x_uart_read(up, AR933X_UART_CS_REG);
++		if (--timeout == 0)
++			break;
++		udelay(1);
++	} while (status & AR933X_UART_CS_TX_BUSY);
++
++	if (timeout == 0)
++		dev_err(up->port.dev, "waiting for TX timed out\n");
++}
++
++static void ar933x_uart_rx_flush(struct ar933x_uart_port *up)
++{
++	unsigned int status;
++
++	/* clear RX_VALID interrupt */
++	ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_RX_VALID);
++
++	/* remove characters from the RX FIFO */
++	do {
++		ar933x_uart_write(up, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
++		status = ar933x_uart_read(up, AR933X_UART_DATA_REG);
++	} while (status & AR933X_UART_DATA_RX_CSR);
++}
++
+ static void ar933x_uart_stop_tx(struct uart_port *port)
+ {
+ 	struct ar933x_uart_port *up =
+@@ -153,8 +211,7 @@ static void ar933x_uart_stop_rx(struct u
+ 	struct ar933x_uart_port *up =
+ 		container_of(port, struct ar933x_uart_port, port);
+ 
+-	up->ier &= ~AR933X_UART_INT_RX_VALID;
+-	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++	ar933x_uart_stop_rx_interrupt(up);
+ }
+ 
+ static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
+@@ -336,11 +393,20 @@ static void ar933x_uart_rx_chars(struct
+ static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
+ {
+ 	struct circ_buf *xmit = &up->port.state->xmit;
++	struct serial_rs485 *rs485conf = &up->port.rs485;
+ 	int count;
++	bool half_duplex_send = false;
+ 
+ 	if (uart_tx_stopped(&up->port))
+ 		return;
+ 
++	if ((rs485conf->flags & SER_RS485_ENABLED) &&
++	    (up->port.x_char || !uart_circ_empty(xmit))) {
++		ar933x_uart_stop_rx_interrupt(up);
++		gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_ON_SEND));
++		half_duplex_send = true;
++	}
++
+ 	count = up->port.fifosize;
+ 	do {
+ 		unsigned int rdata;
+@@ -368,8 +434,14 @@ static void ar933x_uart_tx_chars(struct
+ 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ 		uart_write_wakeup(&up->port);
+ 
+-	if (!uart_circ_empty(xmit))
++	if (!uart_circ_empty(xmit)) {
+ 		ar933x_uart_start_tx_interrupt(up);
++	} else if (half_duplex_send) {
++		ar933x_uart_wait_tx_complete(up);
++		ar933x_uart_rx_flush(up);
++		ar933x_uart_start_rx_interrupt(up);
++		gpiod_set_value(up->rts_gpiod, !!(rs485conf->flags & SER_RS485_RTS_AFTER_SEND));
++	}
+ }
+ 
+ static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
+@@ -427,8 +499,7 @@ static int ar933x_uart_startup(struct ua
+ 		AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE);
+ 
+ 	/* Enable RX interrupts */
+-	up->ier = AR933X_UART_INT_RX_VALID;
+-	ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier);
++	ar933x_uart_start_rx_interrupt(up);
+ 
+ 	spin_unlock_irqrestore(&up->port.lock, flags);
+ 
+@@ -511,6 +582,21 @@ static const struct uart_ops ar933x_uart
+ 	.verify_port	= ar933x_uart_verify_port,
+ };
+ 
++static int ar933x_config_rs485(struct uart_port *port,
++				struct serial_rs485 *rs485conf)
++{
++	struct ar933x_uart_port *up =
++		container_of(port, struct ar933x_uart_port, port);
++
++	if ((rs485conf->flags & SER_RS485_ENABLED) &&
++	    !up->rts_gpiod) {
++		dev_err(port->dev, "RS485 needs rts-gpio\n");
++		return 1;
++	}
++	port->rs485 = *rs485conf;
++	return 0;
++}
++
+ #ifdef CONFIG_SERIAL_AR933X_CONSOLE
+ static struct ar933x_uart_port *
+ ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
+@@ -680,6 +766,8 @@ static int ar933x_uart_probe(struct plat
+ 		goto err_disable_clk;
+ 	}
+ 
++	uart_get_rs485_mode(&pdev->dev, &port->rs485);
++
+ 	port->mapbase = mem_res->start;
+ 	port->line = id;
+ 	port->irq = irq_res->start;
+@@ -690,6 +778,7 @@ static int ar933x_uart_probe(struct plat
+ 	port->regshift = 2;
+ 	port->fifosize = AR933X_UART_FIFO_SIZE;
+ 	port->ops = &ar933x_uart_ops;
++	port->rs485_config = ar933x_config_rs485;
+ 
+ 	baud = ar933x_uart_get_baud(port->uartclk, AR933X_UART_MAX_SCALE, 1);
+ 	up->min_baud = max_t(unsigned int, baud, AR933X_UART_MIN_BAUD);
+@@ -697,6 +786,18 @@ static int ar933x_uart_probe(struct plat
+ 	baud = ar933x_uart_get_baud(port->uartclk, 0, AR933X_UART_MAX_STEP);
+ 	up->max_baud = min_t(unsigned int, baud, AR933X_UART_MAX_BAUD);
+ 
++	up->gpios = mctrl_gpio_init(port, 0);
++	if (IS_ERR(up->gpios) && PTR_ERR(up->gpios) != -ENOSYS)
++		return PTR_ERR(up->gpios);
++
++	up->rts_gpiod = mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS);
++
++	if ((port->rs485.flags & SER_RS485_ENABLED) &&
++	    !up->rts_gpiod) {
++		dev_err(&pdev->dev, "lacking rts-gpio, disabling RS485\n");
++		port->rs485.flags &= ~SER_RS485_ENABLED;
++	}
++
+ #ifdef CONFIG_SERIAL_AR933X_CONSOLE
+ 	ar933x_console_ports[up->port.line] = up;
+ #endif

target/linux/ath79/patches-4.19/700-net-phy-add-reset-controller-support.patch

@@ -0,0 +1,107 @@
+From 71dd6c0dff51b5f1fef2e9dfa6f6a948aac975f3 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Wed, 17 Apr 2019 23:59:21 +0200
+Subject: [PATCH] net: phy: add support for reset-controller
+
+This commit adds support for PHY reset pins handled by a reset controller.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/mdio_bus.c    | 27 +++++++++++++++++++++++++--
+ drivers/net/phy/mdio_device.c | 13 +++++++++++--
+ include/linux/mdio.h          |  1 +
+ 3 files changed, 37 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -29,6 +29,7 @@
+ #include <linux/of_gpio.h>
+ #include <linux/netdevice.h>
+ #include <linux/etherdevice.h>
++#include <linux/reset.h>
+ #include <linux/skbuff.h>
+ #include <linux/spinlock.h>
+ #include <linux/mm.h>
+@@ -65,8 +66,23 @@ static int mdiobus_register_gpiod(struct
+ 
+ 	mdiodev->reset = gpiod;
+ 
+-	/* Assert the reset signal again */
+-	mdio_device_reset(mdiodev, 1);
++	return 0;
++}
++
++static int mdiobus_register_reset(struct mdio_device *mdiodev)
++{
++	struct reset_control *reset = NULL;
++
++	if (mdiodev->dev.of_node)
++		reset = devm_reset_control_get_exclusive(&mdiodev->dev,
++							 "phy");
++	if (PTR_ERR(reset) == -ENOENT ||
++	    PTR_ERR(reset) == -ENOTSUPP)
++		reset = NULL;
++	else if (IS_ERR(reset))
++		return PTR_ERR(reset);
++
++	mdiodev->reset_ctrl = reset;
+ 
+ 	return 0;
+ }
+@@ -82,6 +98,13 @@ int mdiobus_register_device(struct mdio_
+ 		err = mdiobus_register_gpiod(mdiodev);
+ 		if (err)
+ 			return err;
++
++		err = mdiobus_register_reset(mdiodev);
++		if (err)
++			return err;
++
++		/* Assert the reset signal */
++		mdio_device_reset(mdiodev, 1);
+ 	}
+ 
+ 	mdiodev->bus->mdio_map[mdiodev->addr] = mdiodev;
+--- a/drivers/net/phy/mdio_device.c
++++ b/drivers/net/phy/mdio_device.c
+@@ -21,6 +21,7 @@
+ #include <linux/mii.h>
+ #include <linux/module.h>
+ #include <linux/phy.h>
++#include <linux/reset.h>
+ #include <linux/slab.h>
+ #include <linux/string.h>
+ #include <linux/unistd.h>
+@@ -121,10 +122,18 @@ void mdio_device_reset(struct mdio_devic
+ {
+ 	unsigned int d;
+ 
+-	if (!mdiodev->reset)
++	if (!mdiodev->reset && !mdiodev->reset_ctrl)
+ 		return;
+ 
+-	gpiod_set_value(mdiodev->reset, value);
++	if (mdiodev->reset)
++		gpiod_set_value(mdiodev->reset, value);
++
++	if (mdiodev->reset_ctrl) {
++		if (value)
++			reset_control_assert(mdiodev->reset_ctrl);
++		else
++			reset_control_deassert(mdiodev->reset_ctrl);
++	}
+ 
+ 	d = value ? mdiodev->reset_assert_delay : mdiodev->reset_deassert_delay;
+ 	if (d)
+--- a/include/linux/mdio.h
++++ b/include/linux/mdio.h
+@@ -40,6 +40,7 @@ struct mdio_device {
+ 	int addr;
+ 	int flags;
+ 	struct gpio_desc *reset;
++	struct reset_control *reset_ctrl;
+ 	unsigned int reset_assert_delay;
+ 	unsigned int reset_deassert_delay;
+ };

target/linux/ath79/patches-4.19/701-mdio-bus-dont-use-managed-reset-controller.patch

@@ -0,0 +1,44 @@
+From 32085f25d7b68404055f3525c780142fc72e543f Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 22 Nov 2019 22:44:51 +0100
+Subject: [PATCH] mdio_bus: don't use managed reset-controller
+
+Geert Uytterhoeven reported that using devm_reset_controller_get leads
+to a WARNING when probing a reset-controlled PHY. This is because the
+device devm_reset_controller_get gets supplied is not actually the
+one being probed.
+
+Acquire an unmanaged reset-control as well as free the reset_control on
+unregister to fix this.
+
+Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
+CC: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David Bauer <mail@david-bauer.net>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/mdio_bus.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -74,8 +74,8 @@ static int mdiobus_register_reset(struct
+ 	struct reset_control *reset = NULL;
+ 
+ 	if (mdiodev->dev.of_node)
+-		reset = devm_reset_control_get_exclusive(&mdiodev->dev,
+-							 "phy");
++		reset = of_reset_control_get_exclusive(mdiodev->dev.of_node,
++						       "phy");
+ 	if (PTR_ERR(reset) == -ENOENT ||
+ 	    PTR_ERR(reset) == -ENOTSUPP)
+ 		reset = NULL;
+@@ -118,6 +118,8 @@ int mdiobus_unregister_device(struct mdi
+ 	if (mdiodev->bus->mdio_map[mdiodev->addr] != mdiodev)
+ 		return -EINVAL;
+ 
++	reset_control_put(mdiodev->reset_ctrl);
++
+ 	mdiodev->bus->mdio_map[mdiodev->addr] = NULL;
+ 
+ 	return 0;

target/linux/ath79/patches-4.19/910-unaligned_access_hacks.patch

@@ -802,7 +802,7 @@
   * No flags defined yet.
 --- a/net/core/utils.c
 +++ b/net/core/utils.c
-@@ -447,8 +447,14 @@ void inet_proto_csum_replace16(__sum16 *
+@@ -464,8 +464,14 @@ void inet_proto_csum_replace16(__sum16 *
  			       bool pseudohdr)
  {
  	__be32 diff[] = {

target/linux/ath79/tiny/base-files/etc/board.d/01_leds

@@ -41,7 +41,12 @@ on,n150r)
 	ucidef_set_led_switch "lan2" "LAN2" "netgear:green:lan2" "switch0" "0x04" "0x0f"
 	;;
 tplink,tl-mr3020-v1|\
-tplink,tl-mr3040-v2)
+tplink,tl-mr3040-v2|\
+tplink,tl-wa701nd-v1|\
+tplink,tl-wa730re-v1|\
+tplink,tl-wa801nd-v1|\
+tplink,tl-wa830re-v1|\
+tplink,tl-wa901nd-v1)
 	ucidef_set_led_netdev "lan" "LAN" "tp-link:green:lan" "eth0"
 	;;
 tplink,tl-mr3420-v2|\
@@ -95,6 +100,9 @@ tplink,tl-wr941nd-v6)
 	ucidef_set_led_switch "lan3" "LAN3" "tp-link:blue:lan3" "switch0" "0x04"
 	ucidef_set_led_switch "lan4" "LAN4" "tp-link:blue:lan4" "switch0" "0x02"
 	;;
+tplink,tl-wr940n-v6)
+	ucidef_set_led_netdev "wan" "WAN" "tp-link:blue:wan" "eth1"
+	;;
 esac
 
 board_config_flush

target/linux/ath79/tiny/base-files/etc/board.d/02_network

@@ -32,8 +32,13 @@ ath79_setup_interfaces()
 	tplink,tl-mr10u|\
 	tplink,tl-mr3020-v1|\
 	tplink,tl-mr3040-v2|\
+	tplink,tl-wa701nd-v1|\
+	tplink,tl-wa730re-v1|\
+	tplink,tl-wa801nd-v1|\
+	tplink,tl-wa830re-v1|\
 	tplink,tl-wa850re-v1|\
 	tplink,tl-wa850re-v2|\
+	tplink,tl-wa901nd-v1|\
 	tplink,tl-wa901nd-v2|\
 	tplink,tl-wr703n)
 		ucidef_set_interface_lan "eth0"
@@ -47,6 +52,7 @@ ath79_setup_interfaces()
 	tplink,tl-wr841-v12|\
 	tplink,tl-wr940n-v3|\
 	tplink,tl-wr940n-v4|\
+	tplink,tl-wr940n-v6|\
 	tplink,tl-wr941nd-v6)
 		ucidef_set_interface_wan "eth1"
 		ucidef_add_switch "switch0" \

target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom

@@ -65,6 +65,11 @@ case "$FIRMWARE" in
 "ath9k-eeprom-pci-0000:00:00.0.bin")
 	case $board in
 	buffalo,whr-g301n|\
+	tplink,tl-wa701nd-v1|\
+	tplink,tl-wa730re-v1|\
+	tplink,tl-wa801nd-v1|\
+	tplink,tl-wa830re-v1|\
+	tplink,tl-wa901nd-v1|\
 	tplink,tl-wr841-v5|\
 	tplink,tl-wr941-v4)
 		ath9k_eeprom_extract "art" 0x1000 0xeb8

target/linux/bcm27xx/patches-4.19/950-0029-mm-Remove-the-PFN-busy-warning.patch

@@ -14,7 +14,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
 
 --- a/mm/page_alloc.c
 +++ b/mm/page_alloc.c
-@@ -7977,8 +7977,6 @@ int alloc_contig_range(unsigned long sta
+@@ -8007,8 +8007,6 @@ int alloc_contig_range(unsigned long sta
  
  	/* Make sure the range is really isolated. */
  	if (test_pages_isolated(outer_start, end, false)) {

target/linux/bcm27xx/patches-4.19/950-0089-OF-DT-Overlay-configfs-interface.patch

@@ -90,8 +90,8 @@ configfs: New of_overlay API
 +make sense for developers (since it avoids problems with namespaces).
 --- a/drivers/of/Kconfig
 +++ b/drivers/of/Kconfig
-@@ -104,4 +104,11 @@ config OF_OVERLAY
- config OF_NUMA
+@@ -108,4 +108,11 @@ config OF_DMA_DEFAULT_COHERENT
+ 	# arches should select this if DMA is coherent by default for OF devices
  	bool
  
 +config OF_CONFIGFS

target/linux/bcm27xx/patches-4.19/950-0786-leds-pca963x-Fix-open-drain-initialization.patch

@@ -1,61 +0,0 @@
-From 1738aaf187e0c8e97fbdd9661960b835f45e8985 Mon Sep 17 00:00:00 2001
-From: Zahari Petkov <zahari@balena.io>
-Date: Mon, 18 Nov 2019 23:02:55 +0200
-Subject: [PATCH] leds: pca963x: Fix open-drain initialization
-
-commit 697529091ac7a0a90ca349b914bb30641c13c753 upstream.
-
-Before commit bb29b9cccd95 ("leds: pca963x: Add bindings to invert
-polarity") Mode register 2 was initialized directly with either 0x01
-or 0x05 for open-drain or totem pole (push-pull) configuration.
-
-Afterwards, MODE2 initialization started using bitwise operations on
-top of the default MODE2 register value (0x05). Using bitwise OR for
-setting OUTDRV with 0x01 and 0x05 does not produce correct results.
-When open-drain is used, instead of setting OUTDRV to 0, the driver
-keeps it as 1:
-
-Open-drain: 0x05 | 0x01 -> 0x05 (0b101 - incorrect)
-Totem pole: 0x05 | 0x05 -> 0x05 (0b101 - correct but still wrong)
-
-Now OUTDRV setting uses correct bitwise operations for initialization:
-
-Open-drain: 0x05 & ~0x04 -> 0x01 (0b001 - correct)
-Totem pole: 0x05 | 0x04 -> 0x05 (0b101 - correct)
-
-Additional MODE2 register definitions are introduced now as well.
-
-Fixes: bb29b9cccd95 ("leds: pca963x: Add bindings to invert polarity")
-Signed-off-by: Zahari Petkov <zahari@balena.io>
-Signed-off-by: Pavel Machek <pavel@ucw.cz>
----
- drivers/leds/leds-pca963x.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/leds/leds-pca963x.c
-+++ b/drivers/leds/leds-pca963x.c
-@@ -43,6 +43,8 @@
- #define PCA963X_LED_PWM		0x2	/* Controlled through PWM */
- #define PCA963X_LED_GRP_PWM	0x3	/* Controlled through PWM/GRPPWM */
- 
-+#define PCA963X_MODE2_OUTDRV	0x04	/* Open-drain or totem pole */
-+#define PCA963X_MODE2_INVRT	0x10	/* Normal or inverted direction */
- #define PCA963X_MODE2_DMBLNK	0x20	/* Enable blinking */
- 
- #define PCA963X_MODE1		0x00
-@@ -462,12 +464,12 @@ static int pca963x_probe(struct i2c_clie
- 						    PCA963X_MODE2);
- 		/* Configure output: open-drain or totem pole (push-pull) */
- 		if (pdata->outdrv == PCA963X_OPEN_DRAIN)
--			mode2 |= 0x01;
-+			mode2 &= ~PCA963X_MODE2_OUTDRV;
- 		else
--			mode2 |= 0x05;
-+			mode2 |= PCA963X_MODE2_OUTDRV;
- 		/* Configure direction: normal or inverted */
- 		if (pdata->dir == PCA963X_INVERTED)
--			mode2 |= 0x10;
-+			mode2 |= PCA963X_MODE2_INVRT;
- 		i2c_smbus_write_byte_data(pca963x->chip->client, PCA963X_MODE2,
- 					  mode2);
- 	}

target/linux/bcm53xx/patches-4.14/320-ARM-dts-BCM5301X-Add-serial-to-the-bootargs.patch

@@ -75,7 +75,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  
  	chosen {
 -		bootargs = "earlycon";
-+		bootargs = "console=ttyS0,115200 	earlycon";
++		bootargs = "console=ttyS0,115200 earlycon";
  	};
  
  	memory {

target/linux/bcm53xx/patches-4.14/400-mtd-spi-nor-detect-JEDEC-incompatible-w25q128-using-.patch

@@ -13,7 +13,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
 
 --- a/drivers/mtd/spi-nor/spi-nor.c
 +++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1226,6 +1226,18 @@ static const struct flash_info *spi_nor_
+@@ -1230,6 +1230,18 @@ static const struct flash_info *spi_nor_
  	}
  	dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  		id[0], id[1], id[2]);

target/linux/bcm53xx/patches-4.19/320-ARM-dts-BCM5301X-Add-serial-to-the-bootargs.patch

@@ -75,7 +75,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  
  	chosen {
 -		bootargs = "earlycon";
-+		bootargs = "console=ttyS0,115200 	earlycon";
++		bootargs = "console=ttyS0,115200 earlycon";
  	};
  
  	memory {

target/linux/bcm53xx/patches-4.19/400-mtd-spi-nor-detect-JEDEC-incompatible-w25q128-using-.patch

@@ -13,7 +13,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
 
 --- a/drivers/mtd/spi-nor/spi-nor.c
 +++ b/drivers/mtd/spi-nor/spi-nor.c
-@@ -1301,6 +1301,18 @@ static const struct flash_info *spi_nor_
+@@ -1305,6 +1305,18 @@ static const struct flash_info *spi_nor_
  	}
  	dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  		id[0], id[1], id[2]);

target/linux/brcm47xx/patches-4.14/209-b44-register-adm-switch.patch

@@ -19,7 +19,7 @@ Subject: [PATCH 210/210] b44: register adm switch
  
  #include <linux/uaccess.h>
  #include <asm/io.h>
-@@ -2248,6 +2250,69 @@ static void b44_adjust_link(struct net_d
+@@ -2251,6 +2253,69 @@ static void b44_adjust_link(struct net_d
  	}
  }
  
@@ -89,7 +89,7 @@ Subject: [PATCH 210/210] b44: register adm switch
  static int b44_register_phy_one(struct b44 *bp)
  {
  	struct mii_bus *mii_bus;
-@@ -2283,6 +2348,9 @@ static int b44_register_phy_one(struct b
+@@ -2286,6 +2351,9 @@ static int b44_register_phy_one(struct b
  	if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
  	    (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
  
@@ -99,7 +99,7 @@ Subject: [PATCH 210/210] b44: register adm switch
  		dev_info(sdev->dev,
  			 "could not find PHY at %i, use fixed one\n",
  			 bp->phy_addr);
-@@ -2477,6 +2545,7 @@ static void b44_remove_one(struct ssb_de
+@@ -2480,6 +2548,7 @@ static void b44_remove_one(struct ssb_de
  	unregister_netdev(dev);
  	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
  		b44_unregister_phy_one(bp);

target/linux/brcm47xx/patches-4.14/210-b44_phy_fix.patch

@@ -43,7 +43,7 @@
  
  	if (bp->flags & B44_FLAG_EXTERNAL_PHY)
  		return 0;
-@@ -2178,6 +2203,8 @@ static int b44_get_invariants(struct b44
+@@ -2181,6 +2206,8 @@ static int b44_get_invariants(struct b44
  	 * valid PHY address. */
  	bp->phy_addr &= 0x1F;
  

target/linux/brcm47xx/patches-4.14/831-old_gpio_wdt.patch

@@ -4,7 +4,7 @@ Signed-off-by: Mathias Adam <m.adam--openwrt@adamis.de>
 
 --- a/drivers/watchdog/Kconfig
 +++ b/drivers/watchdog/Kconfig
-@@ -1472,6 +1472,15 @@ config WDT_MTX1
+@@ -1473,6 +1473,15 @@ config WDT_MTX1
  	  Hardware driver for the MTX-1 boards. This is a watchdog timer that
  	  will reboot the machine after a 100 seconds timer expired.