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fix ramips mtk762x mmc/host/mtk-mmc/Kconfig drivers support

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This commit is contained in:
coolsnowwolf 2018-10-21 18:12:38 +08:00
parent 92d379f08b
commit 6906aa263a
44 changed files with 12404 additions and 19 deletions
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12
target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/Kconfig Normal file
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config MTK_MMC
tristate "MTK SD/MMC"
depends on !MTD_NAND_RALINK
config MTK_AEE_KDUMP
bool "MTK AEE KDUMP"
depends on MTK_MMC
config MTK_MMC_CD_POLL
bool "Card Detect with Polling"
depends on MTK_MMC

42
target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/Makefile Normal file
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# Copyright Statement:
#
# This software/firmware and related documentation ("MediaTek Software") are
# protected under relevant copyright laws. The information contained herein
# is confidential and proprietary to MediaTek Inc. and/or its licensors.
# Without the prior written permission of MediaTek inc. and/or its licensors,
# any reproduction, modification, use or disclosure of MediaTek Software,
# and information contained herein, in whole or in part, shall be strictly prohibited.
#
# MediaTek Inc. (C) 2010. All rights reserved.
#
# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
#
# The following software/firmware and/or related documentation ("MediaTek Software")
# have been modified by MediaTek Inc. All revisions are subject to any receiver's
# applicable license agreements with MediaTek Inc.
obj-$(CONFIG_MTK_MMC) += mtk_sd.o
mtk_sd-objs := sd.o dbg.o
ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
EXTRA_CFLAGS += -DMT6575_SD_DEBUG
endif
clean:
@rm -f *.o modules.order .*.cmd

63
target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/board.h Normal file
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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef __ARCH_ARM_MACH_BOARD_H
#define __ARCH_ARM_MACH_BOARD_H
#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
#define MSDC_REMOVABLE (1 << 5) /* removable slot */
#define MSDC_SMPL_RISING (0)
#define MSDC_SMPL_FALLING (1)
#define MSDC_CMD_PIN (0)
#define MSDC_DAT_PIN (1)
#define MSDC_CD_PIN (2)
#define MSDC_WP_PIN (3)
#define MSDC_RST_PIN (4)
struct msdc_hw {
unsigned char clk_src; /* host clock source */
unsigned long flags; /* hardware capability flags */
/* config gpio pull mode */
void (*config_gpio_pin)(int type, int pull);
};
extern struct msdc_hw msdc0_hw;
#endif /* __ARCH_ARM_MACH_BOARD_H */

306
target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/dbg.c Normal file
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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/string.h>
#include <linux/uaccess.h>
// #include <mach/mt6575_gpt.h> /* --- by chhung */
#include "dbg.h"
#include "mt6575_sd.h"
#include <linux/seq_file.h>
static char cmd_buf[256];
/* for debug zone */
unsigned int sd_debug_zone[4] = {
0,
0,
0,
0
};
#if defined(MT6575_SD_DEBUG)
/* for driver profile */
#define TICKS_ONE_MS (13000)
u32 gpt_enable;
u32 sdio_pro_enable; /* make sure gpt is enabled */
u32 sdio_pro_time; /* no more than 30s */
struct sdio_profile sdio_perfomance = {0};
#if 0 /* --- chhung */
void msdc_init_gpt(void)
{
GPT_CONFIG config;
config.num = GPT6;
config.mode = GPT_FREE_RUN;
config.clkSrc = GPT_CLK_SRC_SYS;
config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
if (GPT_Config(config) == FALSE)
return;
GPT_Start(GPT6);
}
#endif /* end of --- */
u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
{
u32 ret = 0;
if (new_H32 == old_H32) {
ret = new_L32 - old_L32;
} else if (new_H32 == (old_H32 + 1)) {
if (new_L32 > old_L32)
printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
ret = (0xffffffff - old_L32);
ret += new_L32;
} else {
printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
}
return ret;
}
void msdc_sdio_profile(struct sdio_profile *result)
{
struct cmd_profile *cmd;
u32 i;
printk("sdio === performance dump ===\n");
printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
result->total_tc, result->total_tc / TICKS_ONE_MS,
result->total_tx_bytes, result->total_rx_bytes);
/* CMD52 Dump */
cmd = &result->cmd52_rx;
printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
cmd = &result->cmd52_tx;
printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);
/* CMD53 Rx bytes + block mode */
for (i = 0; i < 512; i++) {
cmd = &result->cmd53_rx_byte[i];
if (cmd->count) {
printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
for (i = 0; i < 100; i++) {
cmd = &result->cmd53_rx_blk[i];
if (cmd->count) {
printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
/* CMD53 Tx bytes + block mode */
for (i = 0; i < 512; i++) {
cmd = &result->cmd53_tx_byte[i];
if (cmd->count) {
printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
for (i = 0; i < 100; i++) {
cmd = &result->cmd53_tx_blk[i];
if (cmd->count) {
printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,
cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));
}
}
printk("sdio === performance dump done ===\n");
}
//========= sdio command table ===========
void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
{
struct sdio_profile *result = &sdio_perfomance;
struct cmd_profile *cmd;
u32 block;
if (sdio_pro_enable == 0)
return;
if (opcode == 52) {
cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
} else if (opcode == 53) {
if (sizes < 512) {
cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
} else {
block = sizes / 512;
if (block >= 99) {
printk("cmd53 error blocks\n");
while (1)
;
}
cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
}
} else {
return;
}
/* update the members */
if (ticks > cmd->max_tc)
cmd->max_tc = ticks;
if (cmd->min_tc == 0 || ticks < cmd->min_tc)
cmd->min_tc = ticks;
cmd->tot_tc += ticks;
cmd->tot_bytes += sizes;
cmd->count++;
if (bRx)
result->total_rx_bytes += sizes;
else
result->total_tx_bytes += sizes;
result->total_tc += ticks;
/* dump when total_tc > 30s */
if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
msdc_sdio_profile(result);
memset(result, 0, sizeof(struct sdio_profile));
}
}
//========== driver proc interface ===========
static int msdc_debug_proc_read(struct seq_file *s, void *p)
{
seq_puts(s, "\n=========================================\n");
seq_puts(s, "Index<0> + Id + Zone\n");
seq_puts(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
seq_puts(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
seq_puts(s, "Index<3> + SDIO_PROFILE + TIME\n");
seq_puts(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
seq_puts(s, "=========================================\n\n");
return 0;
}
static ssize_t msdc_debug_proc_write(struct file *file,
const char __user *buf, size_t count, loff_t *data)
{
int ret;
int cmd, p1, p2;
int id, zone;
int mode, size;
if (count == 0)
return -1;
if (count > 255)
count = 255;
if (copy_from_user(cmd_buf, buf, count))
return -EFAULT;
cmd_buf[count] = '\0';
printk("msdc Write %s\n", cmd_buf);
sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
if (cmd == SD_TOOL_ZONE) {
id = p1;
zone = p2;
zone &= 0x3ff;
printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
if (id >= 0 && id <= 3) {
sd_debug_zone[id] = zone;
} else if (id == 4) {
sd_debug_zone[0] = sd_debug_zone[1] = zone;
sd_debug_zone[2] = sd_debug_zone[3] = zone;
} else {
printk("msdc host_id error when set debug zone\n");
}
} else if (cmd == SD_TOOL_SDIO_PROFILE) {
if (p1 == 1) { /* enable profile */
if (gpt_enable == 0) {
// msdc_init_gpt(); /* --- by chhung */
gpt_enable = 1;
}
sdio_pro_enable = 1;
if (p2 == 0)
p2 = 1;
if (p2 >= 30)
p2 = 30;
sdio_pro_time = p2;
} else if (p1 == 0) {
/* todo */
sdio_pro_enable = 0;
}
}
return count;
}
static int msdc_debug_show(struct inode *inode, struct file *file)
{
return single_open(file, msdc_debug_proc_read, NULL);
}
static const struct file_operations msdc_debug_fops = {
.owner = THIS_MODULE,
.open = msdc_debug_show,
.read = seq_read,
.write = msdc_debug_proc_write,
.llseek = seq_lseek,
.release = single_release,
};
void msdc_debug_proc_init(void)
{
proc_create("msdc_debug", 0660, NULL, &msdc_debug_fops);
}
EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
#endif

155
target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/dbg.h Normal file
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/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*
* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef __MT_MSDC_DEUBG__
#define __MT_MSDC_DEUBG__
//==========================
extern u32 sdio_pro_enable;
/* for a type command, e.g. CMD53, 2 blocks */
struct cmd_profile {
u32 max_tc; /* Max tick count */
u32 min_tc;
u32 tot_tc; /* total tick count */
u32 tot_bytes;
u32 count; /* the counts of the command */
};
/* dump when total_tc and total_bytes */
struct sdio_profile {
u32 total_tc; /* total tick count of CMD52 and CMD53 */
u32 total_tx_bytes; /* total bytes of CMD53 Tx */
u32 total_rx_bytes; /* total bytes of CMD53 Rx */
/*CMD52*/
struct cmd_profile cmd52_tx;
struct cmd_profile cmd52_rx;
/*CMD53 in byte unit */
struct cmd_profile cmd53_tx_byte[512];
struct cmd_profile cmd53_rx_byte[512];
/*CMD53 in block unit */
struct cmd_profile cmd53_tx_blk[100];
struct cmd_profile cmd53_rx_blk[100];
};
//==========================
enum msdc_dbg {
SD_TOOL_ZONE = 0,
SD_TOOL_DMA_SIZE = 1,
SD_TOOL_PM_ENABLE = 2,
SD_TOOL_SDIO_PROFILE = 3,
};
enum msdc_mode {
MODE_PIO = 0,
MODE_DMA = 1,
MODE_SIZE_DEP = 2,
};
/* Debug message event */
#define DBG_EVT_NONE (0) /* No event */
#define DBG_EVT_DMA (1 << 0) /* DMA related event */
#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
#define DBG_EVT_FUC (1 << 5) /* Function event */
#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
#define DBG_EVT_WRN (1 << 8) /* Warning event */
#define DBG_EVT_PWR (1 << 9) /* Power event */
#define DBG_EVT_ALL (0xffffffff)
#define DBG_EVT_MASK (DBG_EVT_ALL)
extern unsigned int sd_debug_zone[4];
#define TAG "msdc"
#if 0 /* +++ chhung */
#define BUG_ON(x) \
do { \
if (x) { \
printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
while (1) \
; \
} \
} while (0)
#endif /* end of +++ */
#define N_MSG(evt, fmt, args...)
/*
do { \
if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
} \
} while(0)
*/
#define ERR_MSG(fmt, args...) \
do { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
} while (0);
#if 1
//defined CONFIG_MTK_MMC_CD_POLL
#define INIT_MSG(fmt, args...)
#define IRQ_MSG(fmt, args...)
#else
#define INIT_MSG(fmt, args...) \
do { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
host->id, ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \
} while (0);
/* PID in ISR in not corrent */
#define IRQ_MSG(fmt, args...) \
do { \
printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
host->id, ##args, __FUNCTION__, __LINE__); \
} while (0);
#endif
void msdc_debug_proc_init(void);
#if 0 /* --- chhung */
void msdc_init_gpt(void);
extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
#endif /* end of --- */
u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
#endif

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@ -0,0 +1,986 @@
/* Copyright Statement:
*
* This software/firmware and related documentation ("MediaTek Software") are
* protected under relevant copyright laws. The information contained herein
* is confidential and proprietary to MediaTek Inc. and/or its licensors.
* Without the prior written permission of MediaTek inc. and/or its licensors,
* any reproduction, modification, use or disclosure of MediaTek Software,
* and information contained herein, in whole or in part, shall be strictly prohibited.
*/
/* MediaTek Inc. (C) 2010. All rights reserved.
*
* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
* THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
* CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
* SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
* CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* The following software/firmware and/or related documentation ("MediaTek Software")
* have been modified by MediaTek Inc. All revisions are subject to any receiver's
* applicable license agreements with MediaTek Inc.
*/
#ifndef MT6575_SD_H
#define MT6575_SD_H
#include <linux/bitops.h>
#include <linux/mmc/host.h>
// #include <mach/mt6575_reg_base.h> /* --- by chhung */
/*--------------------------------------------------------------------------*/
/* Common Macro */
/*--------------------------------------------------------------------------*/
#define REG_ADDR(x) (base + OFFSET_##x)
/*--------------------------------------------------------------------------*/
/* Common Definition */
/*--------------------------------------------------------------------------*/
#define MSDC_FIFO_SZ (128)
#define MSDC_FIFO_THD (64) // (128)
#define MSDC_NUM (4)
#define MSDC_MS (0)
#define MSDC_SDMMC (1)
#define MSDC_MODE_UNKNOWN (0)
#define MSDC_MODE_PIO (1)
#define MSDC_MODE_DMA_BASIC (2)
#define MSDC_MODE_DMA_DESC (3)
#define MSDC_MODE_DMA_ENHANCED (4)
#define MSDC_MODE_MMC_STREAM (5)
#define MSDC_BUS_1BITS (0)
#define MSDC_BUS_4BITS (1)
#define MSDC_BUS_8BITS (2)
#define MSDC_BRUST_8B (3)
#define MSDC_BRUST_16B (4)
#define MSDC_BRUST_32B (5)
#define MSDC_BRUST_64B (6)
#define MSDC_PIN_PULL_NONE (0)
#define MSDC_PIN_PULL_DOWN (1)
#define MSDC_PIN_PULL_UP (2)
#define MSDC_PIN_KEEP (3)
#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
#define MSDC_MIN_SCLK (260000)
#define MSDC_AUTOCMD12 (0x0001)
#define MSDC_AUTOCMD23 (0x0002)
#define MSDC_AUTOCMD19 (0x0003)
#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
enum {
RESP_NONE = 0,
RESP_R1,
RESP_R2,
RESP_R3,
RESP_R4,
RESP_R5,
RESP_R6,
RESP_R7,
RESP_R1B
};
/*--------------------------------------------------------------------------*/
/* Register Offset */
/*--------------------------------------------------------------------------*/
#define OFFSET_MSDC_CFG (0x0)
#define OFFSET_MSDC_IOCON (0x04)
#define OFFSET_MSDC_PS (0x08)
#define OFFSET_MSDC_INT (0x0c)
#define OFFSET_MSDC_INTEN (0x10)
#define OFFSET_MSDC_FIFOCS (0x14)
#define OFFSET_MSDC_TXDATA (0x18)
#define OFFSET_MSDC_RXDATA (0x1c)
#define OFFSET_SDC_CFG (0x30)
#define OFFSET_SDC_CMD (0x34)
#define OFFSET_SDC_ARG (0x38)
#define OFFSET_SDC_STS (0x3c)
#define OFFSET_SDC_RESP0 (0x40)
#define OFFSET_SDC_RESP1 (0x44)
#define OFFSET_SDC_RESP2 (0x48)
#define OFFSET_SDC_RESP3 (0x4c)
#define OFFSET_SDC_BLK_NUM (0x50)
#define OFFSET_SDC_CSTS (0x58)
#define OFFSET_SDC_CSTS_EN (0x5c)
#define OFFSET_SDC_DCRC_STS (0x60)
#define OFFSET_EMMC_CFG0 (0x70)
#define OFFSET_EMMC_CFG1 (0x74)
#define OFFSET_EMMC_STS (0x78)
#define OFFSET_EMMC_IOCON (0x7c)
#define OFFSET_SDC_ACMD_RESP (0x80)
#define OFFSET_SDC_ACMD19_TRG (0x84)
#define OFFSET_SDC_ACMD19_STS (0x88)
#define OFFSET_MSDC_DMA_SA (0x90)
#define OFFSET_MSDC_DMA_CA (0x94)
#define OFFSET_MSDC_DMA_CTRL (0x98)
#define OFFSET_MSDC_DMA_CFG (0x9c)
#define OFFSET_MSDC_DBG_SEL (0xa0)
#define OFFSET_MSDC_DBG_OUT (0xa4)
#define OFFSET_MSDC_PATCH_BIT (0xb0)
#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
#define OFFSET_MSDC_PAD_CTL0 (0xe0)
#define OFFSET_MSDC_PAD_CTL1 (0xe4)
#define OFFSET_MSDC_PAD_CTL2 (0xe8)
#define OFFSET_MSDC_PAD_TUNE (0xec)
#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
#define OFFSET_MSDC_HW_DBG (0xf8)
#define OFFSET_MSDC_VERSION (0x100)
#define OFFSET_MSDC_ECO_VER (0x104)
/*--------------------------------------------------------------------------*/
/* Register Address */
/*--------------------------------------------------------------------------*/
/* common register */
#define MSDC_CFG REG_ADDR(MSDC_CFG)
#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
#define MSDC_PS REG_ADDR(MSDC_PS)
#define MSDC_INT REG_ADDR(MSDC_INT)
#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
/* sdmmc register */
#define SDC_CFG REG_ADDR(SDC_CFG)
#define SDC_CMD REG_ADDR(SDC_CMD)
#define SDC_ARG REG_ADDR(SDC_ARG)
#define SDC_STS REG_ADDR(SDC_STS)
#define SDC_RESP0 REG_ADDR(SDC_RESP0)
#define SDC_RESP1 REG_ADDR(SDC_RESP1)
#define SDC_RESP2 REG_ADDR(SDC_RESP2)
#define SDC_RESP3 REG_ADDR(SDC_RESP3)
#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
#define SDC_CSTS REG_ADDR(SDC_CSTS)
#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
/* emmc register*/
#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
#define EMMC_STS REG_ADDR(EMMC_STS)
#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
/* auto command register */
#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
/* dma register */
#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
/* pad ctrl register */
#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
/* data read delay */
#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
/* debug register */
#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
/* misc register */
#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
/*--------------------------------------------------------------------------*/
/* Register Mask */
/*--------------------------------------------------------------------------*/
/* MSDC_CFG mask */
#define MSDC_CFG_MODE (0x1 << 0) /* RW */
#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
#define MSDC_CFG_RST (0x1 << 2) /* RW */
#define MSDC_CFG_PIO (0x1 << 3) /* RW */
#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
/* MSDC_IOCON mask */
#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
/* MSDC_PS mask */
#define MSDC_PS_CDEN (0x1 << 0) /* RW */
#define MSDC_PS_CDSTS (0x1 << 1) /* R */
#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
#define MSDC_PS_DAT (0xff << 16) /* R */
#define MSDC_PS_CMD (0x1 << 24) /* R */
#define MSDC_PS_WP (0x1UL << 31) /* R */
/* MSDC_INT mask */
#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
#define MSDC_INT_CSTA (0x1 << 11) /* R */
#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
/* MSDC_INTEN mask */
#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
/* MSDC_FIFOCS mask */
#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
#define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
/* SDC_CFG mask */
#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
#define SDC_CFG_SDIO (0x1 << 19) /* RW */
#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
/* SDC_CMD mask */
#define SDC_CMD_OPC (0x3f << 0) /* RW */
#define SDC_CMD_BRK (0x1 << 6) /* RW */
#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
#define SDC_CMD_DTYP (0x3 << 11) /* RW */
#define SDC_CMD_DTYP (0x3 << 11) /* RW */
#define SDC_CMD_RW (0x1 << 13) /* RW */
#define SDC_CMD_STOP (0x1 << 14) /* RW */
#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
#define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
/* SDC_STS mask */
#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
/* SDC_DCRC_STS mask */
#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
/* EMMC_CFG0 mask */
#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
/* EMMC_CFG1 mask */
#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
/* EMMC_STS mask */
#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
/* EMMC_IOCON mask */
#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
/* SDC_ACMD19_TRG mask */
#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
/* MSDC_DMA_CTRL mask */
#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
/* MSDC_DMA_CFG mask */
#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
/* MSDC_PATCH_BIT mask */
#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
/* MSDC_PATCH_BIT1 mask */
#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
/* MSDC_PAD_CTL0 mask */
#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
/* MSDC_PAD_CTL1 mask */
#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
/* MSDC_PAD_CTL2 mask */
#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
#define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
/* MSDC_PAD_TUNE mask */
#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
/* MSDC_DAT_RDDLY0/1 mask */
#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
#define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
#define CARD_READY_FOR_DATA (1 << 8)
#define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
/*--------------------------------------------------------------------------*/
/* Descriptor Structure */
/*--------------------------------------------------------------------------*/
struct gpd {
u32 hwo:1; /* could be changed by hw */
u32 bdp:1;
u32 rsv0:6;
u32 chksum:8;
u32 intr:1;
u32 rsv1:15;
void *next;
void *ptr;
u32 buflen:16;
u32 extlen:8;
u32 rsv2:8;
u32 arg;
u32 blknum;
u32 cmd;
};
struct bd {
u32 eol:1;
u32 rsv0:7;
u32 chksum:8;
u32 rsv1:1;
u32 blkpad:1;
u32 dwpad:1;
u32 rsv2:13;
void *next;
void *ptr;
u32 buflen:16;
u32 rsv3:16;
};
/*--------------------------------------------------------------------------*/
/* Register Debugging Structure */
/*--------------------------------------------------------------------------*/
struct msdc_cfg_reg {
u32 msdc:1;
u32 ckpwn:1;
u32 rst:1;
u32 pio:1;
u32 ckdrven:1;
u32 start18v:1;
u32 pass18v:1;
u32 ckstb:1;
u32 ckdiv:8;
u32 ckmod:2;
u32 pad:14;
};
struct msdc_iocon_reg {
u32 sdr104cksel:1;
u32 rsmpl:1;
u32 dsmpl:1;
u32 ddlysel:1;
u32 ddr50ckd:1;
u32 dsplsel:1;
u32 pad1:10;
u32 d0spl:1;
u32 d1spl:1;
u32 d2spl:1;
u32 d3spl:1;
u32 d4spl:1;
u32 d5spl:1;
u32 d6spl:1;
u32 d7spl:1;
u32 riscsz:1;
u32 pad2:7;
};
struct msdc_ps_reg {
u32 cden:1;
u32 cdsts:1;
u32 pad1:10;
u32 cddebounce:4;
u32 dat:8;
u32 cmd:1;
u32 pad2:6;
u32 wp:1;
};
struct msdc_int_reg {
u32 mmcirq:1;
u32 cdsc:1;
u32 pad1:1;
u32 atocmdrdy:1;
u32 atocmdtmo:1;
u32 atocmdcrc:1;
u32 dmaqempty:1;
u32 sdioirq:1;
u32 cmdrdy:1;
u32 cmdtmo:1;
u32 rspcrc:1;
u32 csta:1;
u32 xfercomp:1;
u32 dxferdone:1;
u32 dattmo:1;
u32 datcrc:1;
u32 atocmd19done:1;
u32 pad2:15;
};
struct msdc_inten_reg {
u32 mmcirq:1;
u32 cdsc:1;
u32 pad1:1;
u32 atocmdrdy:1;
u32 atocmdtmo:1;
u32 atocmdcrc:1;
u32 dmaqempty:1;
u32 sdioirq:1;
u32 cmdrdy:1;
u32 cmdtmo:1;
u32 rspcrc:1;
u32 csta:1;
u32 xfercomp:1;
u32 dxferdone:1;
u32 dattmo:1;
u32 datcrc:1;
u32 atocmd19done:1;
u32 pad2:15;
};
struct msdc_fifocs_reg {
u32 rxcnt:8;
u32 pad1:8;
u32 txcnt:8;
u32 pad2:7;
u32 clr:1;
};
struct msdc_txdat_reg {
u32 val;
};
struct msdc_rxdat_reg {
u32 val;
};
struct sdc_cfg_reg {
u32 sdiowkup:1;
u32 inswkup:1;
u32 pad1:14;
u32 buswidth:2;
u32 pad2:1;
u32 sdio:1;
u32 sdioide:1;
u32 intblkgap:1;
u32 pad4:2;
u32 dtoc:8;
};
struct sdc_cmd_reg {
u32 cmd:6;
u32 brk:1;
u32 rsptyp:3;
u32 pad1:1;
u32 dtype:2;
u32 rw:1;
u32 stop:1;
u32 goirq:1;
u32 blklen:12;
u32 atocmd:2;
u32 volswth:1;
u32 pad2:1;
};
struct sdc_arg_reg {
u32 arg;
};
struct sdc_sts_reg {
u32 sdcbusy:1;
u32 cmdbusy:1;
u32 pad:29;
u32 swrcmpl:1;
};
struct sdc_resp0_reg {
u32 val;
};
struct sdc_resp1_reg {
u32 val;
};
struct sdc_resp2_reg {
u32 val;
};
struct sdc_resp3_reg {
u32 val;
};
struct sdc_blknum_reg {
u32 num;
};
struct sdc_csts_reg {
u32 sts;
};
struct sdc_cstsen_reg {
u32 sts;
};
struct sdc_datcrcsts_reg {
u32 datcrcsts:8;
u32 ddrcrcsts:4;
u32 pad:20;
};
struct emmc_cfg0_reg {
u32 bootstart:1;
u32 bootstop:1;
u32 bootmode:1;
u32 pad1:9;
u32 bootwaidly:3;
u32 bootsupp:1;
u32 pad2:16;
};
struct emmc_cfg1_reg {
u32 bootcrctmc:16;
u32 pad:4;
u32 bootacktmc:12;
};
struct emmc_sts_reg {
u32 bootcrcerr:1;
u32 bootackerr:1;
u32 bootdattmo:1;
u32 bootacktmo:1;
u32 bootupstate:1;
u32 bootackrcv:1;
u32 bootdatrcv:1;
u32 pad:25;
};
struct emmc_iocon_reg {
u32 bootrst:1;
u32 pad:31;
};
struct msdc_acmd_resp_reg {
u32 val;
};
struct msdc_acmd19_trg_reg {
u32 tunesel:4;
u32 pad:28;
};
struct msdc_acmd19_sts_reg {
u32 val;
};
struct msdc_dma_sa_reg {
u32 addr;
};
struct msdc_dma_ca_reg {
u32 addr;
};
struct msdc_dma_ctrl_reg {
u32 start:1;
u32 stop:1;
u32 resume:1;
u32 pad1:5;
u32 mode:1;
u32 pad2:1;
u32 lastbuf:1;
u32 pad3:1;
u32 brustsz:3;
u32 pad4:1;
u32 xfersz:16;
};
struct msdc_dma_cfg_reg {
u32 status:1;
u32 decsen:1;
u32 pad1:2;
u32 bdcsen:1;
u32 gpdcsen:1;
u32 pad2:26;
};
struct msdc_dbg_sel_reg {
u32 sel:16;
u32 pad2:16;
};
struct msdc_dbg_out_reg {
u32 val;
};
struct msdc_pad_ctl0_reg {
u32 clkdrvn:3;
u32 rsv0:1;
u32 clkdrvp:3;
u32 rsv1:1;
u32 clksr:1;
u32 rsv2:7;
u32 clkpd:1;
u32 clkpu:1;
u32 clksmt:1;
u32 clkies:1;
u32 clktdsel:4;
u32 clkrdsel:8;
};
struct msdc_pad_ctl1_reg {
u32 cmddrvn:3;
u32 rsv0:1;
u32 cmddrvp:3;
u32 rsv1:1;
u32 cmdsr:1;
u32 rsv2:7;
u32 cmdpd:1;
u32 cmdpu:1;
u32 cmdsmt:1;
u32 cmdies:1;
u32 cmdtdsel:4;
u32 cmdrdsel:8;
};
struct msdc_pad_ctl2_reg {
u32 datdrvn:3;
u32 rsv0:1;
u32 datdrvp:3;
u32 rsv1:1;
u32 datsr:1;
u32 rsv2:7;
u32 datpd:1;
u32 datpu:1;
u32 datsmt:1;
u32 daties:1;
u32 dattdsel:4;
u32 datrdsel:8;
};
struct msdc_pad_tune_reg {
u32 wrrxdly:3;
u32 pad1:5;
u32 rdrxdly:8;
u32 pad2:16;
};
struct msdc_dat_rddly0 {
u32 dat0:5;
u32 rsv0:3;
u32 dat1:5;
u32 rsv1:3;
u32 dat2:5;
u32 rsv2:3;
u32 dat3:5;
u32 rsv3:3;
};
struct msdc_dat_rddly1 {
u32 dat4:5;
u32 rsv4:3;
u32 dat5:5;
u32 rsv5:3;
u32 dat6:5;
u32 rsv6:3;
u32 dat7:5;
u32 rsv7:3;
};
struct msdc_hw_dbg_reg {
u32 dbg0sel:8;
u32 dbg1sel:6;
u32 pad1:2;
u32 dbg2sel:6;
u32 pad2:2;
u32 dbg3sel:6;
u32 pad3:2;
};
struct msdc_version_reg {
u32 val;
};
struct msdc_eco_ver_reg {
u32 val;
};
struct msdc_regs {
struct msdc_cfg_reg msdc_cfg; /* base+0x00h */
struct msdc_iocon_reg msdc_iocon; /* base+0x04h */
struct msdc_ps_reg msdc_ps; /* base+0x08h */
struct msdc_int_reg msdc_int; /* base+0x0ch */
struct msdc_inten_reg msdc_inten; /* base+0x10h */
struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
struct msdc_txdat_reg msdc_txdat; /* base+0x18h */
struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
u32 rsv1[4];
struct sdc_cfg_reg sdc_cfg; /* base+0x30h */
struct sdc_cmd_reg sdc_cmd; /* base+0x34h */
struct sdc_arg_reg sdc_arg; /* base+0x38h */
struct sdc_sts_reg sdc_sts; /* base+0x3ch */
struct sdc_resp0_reg sdc_resp0; /* base+0x40h */
struct sdc_resp1_reg sdc_resp1; /* base+0x44h */
struct sdc_resp2_reg sdc_resp2; /* base+0x48h */
struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */
struct sdc_blknum_reg sdc_blknum; /* base+0x50h */
u32 rsv2[1];
struct sdc_csts_reg sdc_csts; /* base+0x58h */
struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
u32 rsv3[3];
struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
struct emmc_sts_reg emmc_sts; /* base+0x78h */
struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */
struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
u32 rsv4[1];
struct msdc_dma_sa_reg dma_sa; /* base+0x90h */
struct msdc_dma_ca_reg dma_ca; /* base+0x94h */
struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */
u32 rsv5[2];
u32 patch0; /* base+0xb0h */
u32 patch1; /* base+0xb4h */
u32 rsv6[10];
struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
struct msdc_pad_tune_reg pad_tune; /* base+0xech */
struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
u32 rsv7[1];
struct msdc_version_reg version; /* base+0x100h */
struct msdc_eco_ver_reg eco_ver; /* base+0x104h */
};
struct msdc_dma {
u32 sglen; /* size of scatter list */
struct scatterlist *sg; /* I/O scatter list */
u8 mode; /* dma mode */
struct gpd *gpd; /* pointer to gpd array */
struct bd *bd; /* pointer to bd array */
dma_addr_t gpd_addr; /* the physical address of gpd array */
dma_addr_t bd_addr; /* the physical address of bd array */
};
struct msdc_host {
struct msdc_hw *hw;
struct mmc_host *mmc; /* mmc structure */
struct mmc_command *cmd;
struct mmc_data *data;
struct mmc_request *mrq;
int cmd_rsp;
int error;
spinlock_t lock; /* mutex */
struct semaphore sem;
u32 blksz; /* host block size */
void __iomem *base; /* host base address */
int id; /* host id */
int pwr_ref; /* core power reference count */
u32 xfer_size; /* total transferred size */
struct msdc_dma dma; /* dma channel */
u32 dma_xfer_size; /* dma transfer size in bytes */
u32 timeout_ns; /* data timeout ns */
u32 timeout_clks; /* data timeout clks */
int irq; /* host interrupt */
struct delayed_work card_delaywork;
struct completion cmd_done;
struct completion xfer_done;
struct pm_message pm_state;
u32 mclk; /* mmc subsystem clock */
u32 hclk; /* host clock speed */
u32 sclk; /* SD/MS clock speed */
u8 core_clkon; /* Host core clock on ? */
u8 card_clkon; /* Card clock on ? */
u8 core_power; /* core power */
u8 power_mode; /* host power mode */
u8 card_inserted; /* card inserted ? */
u8 suspend; /* host suspended ? */
u8 app_cmd; /* for app command */
u32 app_cmd_arg;
};
#define sdr_read8(reg) readb(reg)
#define sdr_read32(reg) readl(reg)
#define sdr_write8(reg, val) writeb(val, reg)
#define sdr_write32(reg, val) writel(val, reg)
static inline void sdr_set_bits(void __iomem *reg, u32 bs)
{
u32 val = readl(reg);
val |= bs;
writel(val, reg);
}
static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
{
u32 val = readl(reg);
val &= ~bs;
writel(val, reg);
}
static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
{
unsigned int tv = readl(reg);
tv &= ~field;
tv |= ((val) << (ffs((unsigned int)field) - 1));
writel(tv, reg);
}
static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
{
unsigned int tv = readl(reg);
*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
}
#endif

2461
target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c Normal file
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70
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/Kconfig Normal file
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config NET_VENDOR_MEDIATEK
tristate "Mediatek/Ralink ethernet driver"
depends on RALINK
help
This driver supports the ethernet mac inside the Mediatek and Ralink WiSoCs
config NET_MEDIATEK_SOC
def_tristate NET_VENDOR_MEDIATEK
if NET_MEDIATEK_SOC
choice
prompt "MAC type"
config NET_MEDIATEK_RT2880
bool "RT2882"
depends on MIPS && SOC_RT288X
config NET_MEDIATEK_RT3050
bool "RT3050/MT7628"
depends on MIPS && (SOC_RT305X || SOC_MT7620)
config NET_MEDIATEK_RT3883
bool "RT3883"
depends on MIPS && SOC_RT3883
config NET_MEDIATEK_MT7620
bool "MT7620"
depends on MIPS && SOC_MT7620
config NET_MEDIATEK_MT7621
bool "MT7621"
depends on MIPS && SOC_MT7621
endchoice
config NET_MEDIATEK_OFFLOAD
def_bool NET_MEDIATEK_SOC
depends on NET_MEDIATEK_MT7621
config NET_MEDIATEK_HW_QOS
def_bool NET_MEDIATEK_SOC
depends on NET_MEDIATEK_MT7623
config NET_MEDIATEK_MDIO
def_bool NET_MEDIATEK_SOC
depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883 || NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621)
select PHYLIB
config NET_MEDIATEK_MDIO_RT2880
def_bool NET_MEDIATEK_SOC
depends on (NET_MEDIATEK_RT2880 || NET_MEDIATEK_RT3883)
select NET_MEDIATEK_MDIO
config NET_MEDIATEK_MDIO_MT7620
def_bool NET_MEDIATEK_SOC
depends on (NET_MEDIATEK_MT7620 || NET_MEDIATEK_MT7621)
select NET_MEDIATEK_MDIO
config NET_MEDIATEK_ESW_RT3050
def_tristate NET_MEDIATEK_SOC
depends on NET_MEDIATEK_RT3050
config NET_MEDIATEK_GSW_MT7620
def_tristate NET_MEDIATEK_SOC
depends on NET_MEDIATEK_MT7620
config NET_MEDIATEK_GSW_MT7621
def_tristate NET_MEDIATEK_SOC
depends on NET_MEDIATEK_MT7621
endif

22
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/Makefile Normal file
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#
# Makefile for the Ralink SoCs built-in ethernet macs
#
mtk-eth-soc-y += mtk_eth_soc.o ethtool.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO) += mdio.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_RT2880) += mdio_rt2880.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MDIO_MT7620) += mdio_mt7620.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_OFFLOAD) += mtk_offload.o mtk_debugfs.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT2880) += soc_rt2880.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3050) += soc_rt3050.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_RT3883) += soc_rt3883.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7620) += soc_mt7620.o
mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621) += soc_mt7621.o
obj-$(CONFIG_NET_MEDIATEK_ESW_RT3050) += esw_rt3050.o
obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o mt7530.o
obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o mt7530.o
obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk-eth-soc.o

1461
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/esw_rt3050.c Normal file
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29
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/esw_rt3050.h Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_ESW_RT3052_H__
#define _RALINK_ESW_RT3052_H__
#ifdef CONFIG_NET_MEDIATEK_ESW_RT3052
int __init mtk_switch_init(void);
void mtk_switch_exit(void);
#else
static inline int __init mtk_switch_init(void) { return 0; }
static inline void mtk_switch_exit(void) { }
#endif
#endif

230
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/ethtool.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include "mtk_eth_soc.h"
static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
#define _FE(x...) # x,
FE_STAT_REG_DECLARE
#undef _FE
};
static int fe_get_link_ksettings(struct net_device *ndev,
struct ethtool_link_ksettings *cmd)
{
struct fe_priv *priv = netdev_priv(ndev);
if (!priv->phy_dev)
return -ENODEV;
if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
if (phy_read_status(priv->phy_dev))
return -ENODEV;
}
phy_ethtool_ksettings_get(ndev->phydev, cmd);
return 0;
}
static int fe_set_link_ksettings(struct net_device *ndev,
const struct ethtool_link_ksettings *cmd)
{
struct fe_priv *priv = netdev_priv(ndev);
if (!priv->phy_dev)
goto out_sset;
if (cmd->base.phy_address != priv->phy_dev->mdio.addr) {
if (priv->phy->phy_node[cmd->base.phy_address]) {
priv->phy_dev = priv->phy->phy[cmd->base.phy_address];
priv->phy_flags = FE_PHY_FLAG_PORT;
} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address)) {
priv->phy_dev = mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address);
priv->phy_flags = FE_PHY_FLAG_ATTACH;
} else {
goto out_sset;
}
}
return phy_ethtool_ksettings_set(ndev->phydev, cmd);
out_sset:
return -ENODEV;
}
static void fe_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
struct fe_priv *priv = netdev_priv(dev);
struct fe_soc_data *soc = priv->soc;
strlcpy(info->driver, priv->dev->driver->name, sizeof(info->driver));
strlcpy(info->version, MTK_FE_DRV_VERSION, sizeof(info->version));
strlcpy(info->bus_info, dev_name(priv->dev), sizeof(info->bus_info));
if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
info->n_stats = ARRAY_SIZE(fe_gdma_str);
}
static u32 fe_get_msglevel(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
return priv->msg_enable;
}
static void fe_set_msglevel(struct net_device *dev, u32 value)
{
struct fe_priv *priv = netdev_priv(dev);
priv->msg_enable = value;
}
static int fe_nway_reset(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
if (!priv->phy_dev)
goto out_nway_reset;
return genphy_restart_aneg(priv->phy_dev);
out_nway_reset:
return -EOPNOTSUPP;
}
static u32 fe_get_link(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
int err;
if (!priv->phy_dev)
goto out_get_link;
if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
err = genphy_update_link(priv->phy_dev);
if (err)
goto out_get_link;
}
return priv->phy_dev->link;
out_get_link:
return ethtool_op_get_link(dev);
}
static int fe_set_ringparam(struct net_device *dev,
struct ethtool_ringparam *ring)
{
struct fe_priv *priv = netdev_priv(dev);
if ((ring->tx_pending < 2) ||
(ring->rx_pending < 2) ||
(ring->rx_pending > MAX_DMA_DESC) ||
(ring->tx_pending > MAX_DMA_DESC))
return -EINVAL;
dev->netdev_ops->ndo_stop(dev);
priv->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);
priv->rx_ring.rx_ring_size = BIT(fls(ring->rx_pending) - 1);
dev->netdev_ops->ndo_open(dev);
return 0;
}
static void fe_get_ringparam(struct net_device *dev,
struct ethtool_ringparam *ring)
{
struct fe_priv *priv = netdev_priv(dev);
ring->rx_max_pending = MAX_DMA_DESC;
ring->tx_max_pending = MAX_DMA_DESC;
ring->rx_pending = priv->rx_ring.rx_ring_size;
ring->tx_pending = priv->tx_ring.tx_ring_size;
}
static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
{
switch (stringset) {
case ETH_SS_STATS:
memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
break;
}
}
static int fe_get_sset_count(struct net_device *dev, int sset)
{
switch (sset) {
case ETH_SS_STATS:
return ARRAY_SIZE(fe_gdma_str);
default:
return -EOPNOTSUPP;
}
}
static void fe_get_ethtool_stats(struct net_device *dev,
struct ethtool_stats *stats, u64 *data)
{
struct fe_priv *priv = netdev_priv(dev);
struct fe_hw_stats *hwstats = priv->hw_stats;
u64 *data_src, *data_dst;
unsigned int start;
int i;
if (netif_running(dev) && netif_device_present(dev)) {
if (spin_trylock(&hwstats->stats_lock)) {
fe_stats_update(priv);
spin_unlock(&hwstats->stats_lock);
}
}
do {
data_src = &hwstats->tx_bytes;
data_dst = data;
start = u64_stats_fetch_begin_irq(&hwstats->syncp);
for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
*data_dst++ = *data_src++;
} while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
}
static struct ethtool_ops fe_ethtool_ops = {
.get_link_ksettings = fe_get_link_ksettings,
.set_link_ksettings = fe_set_link_ksettings,
.get_drvinfo = fe_get_drvinfo,
.get_msglevel = fe_get_msglevel,
.set_msglevel = fe_set_msglevel,
.nway_reset = fe_nway_reset,
.get_link = fe_get_link,
.set_ringparam = fe_set_ringparam,
.get_ringparam = fe_get_ringparam,
};
void fe_set_ethtool_ops(struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
struct fe_soc_data *soc = priv->soc;
if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
fe_ethtool_ops.get_strings = fe_get_strings;
fe_ethtool_ops.get_sset_count = fe_get_sset_count;
fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
}
netdev->ethtool_ops = &fe_ethtool_ops;
}

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef FE_ETHTOOL_H
#define FE_ETHTOOL_H
#include <linux/ethtool.h>
void fe_set_ethtool_ops(struct net_device *netdev);
#endif /* FE_ETHTOOL_H */

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <ralink_regs.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
{
iowrite32(val, gsw->base + reg);
}
u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
{
return ioread32(gsw->base + reg);
}
static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
{
struct fe_priv *priv = (struct fe_priv *)_priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
u32 status;
int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
status = mtk_switch_r32(gsw, GSW_REG_ISR);
if (status & PORT_IRQ_ST_CHG)
for (i = 0; i <= max; i++) {
u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
int link = status & 0x1;
if (link != priv->link[i])
mt7620_print_link_state(priv, i, link,
(status >> 2) & 3,
(status & 0x2));
priv->link[i] = link;
}
mt7620_handle_carrier(priv);
mtk_switch_w32(gsw, status, GSW_REG_ISR);
return IRQ_HANDLED;
}
static int mt7620_mdio_mode(struct device_node *eth_node)
{
struct device_node *phy_node, *mdiobus_node;
const __be32 *id;
int ret = 0;
mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
if (mdiobus_node) {
for_each_child_of_node(mdiobus_node, phy_node) {
id = of_get_property(phy_node, "reg", NULL);
if (id && (be32_to_cpu(*id) == 0x1f))
ret = 1;
}
of_node_put(mdiobus_node);
}
return ret;
}
static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
{
u32 i;
u32 val;
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
u32 val;
/* turn off ephy and set phy base addr to 12 */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(0x1f << 24) | (0xc << 16),
GSW_REG_GPC1);
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
} else {
/* global page 4 */
_mt7620_mii_write(gsw, 1, 31, 0x4000);
_mt7620_mii_write(gsw, 1, 17, 0x7444);
if (is_BGA)
_mt7620_mii_write(gsw, 1, 19, 0x0114);
else
_mt7620_mii_write(gsw, 1, 19, 0x0117);
_mt7620_mii_write(gsw, 1, 22, 0x10cf);
_mt7620_mii_write(gsw, 1, 25, 0x6212);
_mt7620_mii_write(gsw, 1, 26, 0x0777);
_mt7620_mii_write(gsw, 1, 29, 0x4000);
_mt7620_mii_write(gsw, 1, 28, 0xc077);
_mt7620_mii_write(gsw, 1, 24, 0x0000);
/* global page 3 */
_mt7620_mii_write(gsw, 1, 31, 0x3000);
_mt7620_mii_write(gsw, 1, 17, 0x4838);
/* global page 2 */
_mt7620_mii_write(gsw, 1, 31, 0x2000);
if (is_BGA) {
_mt7620_mii_write(gsw, 1, 21, 0x0515);
_mt7620_mii_write(gsw, 1, 22, 0x0053);
_mt7620_mii_write(gsw, 1, 23, 0x00bf);
_mt7620_mii_write(gsw, 1, 24, 0x0aaf);
_mt7620_mii_write(gsw, 1, 25, 0x0fad);
_mt7620_mii_write(gsw, 1, 26, 0x0fc1);
} else {
_mt7620_mii_write(gsw, 1, 21, 0x0517);
_mt7620_mii_write(gsw, 1, 22, 0x0fd2);
_mt7620_mii_write(gsw, 1, 23, 0x00bf);
_mt7620_mii_write(gsw, 1, 24, 0x0aab);
_mt7620_mii_write(gsw, 1, 25, 0x00ae);
_mt7620_mii_write(gsw, 1, 26, 0x0fff);
}
/* global page 1 */
_mt7620_mii_write(gsw, 1, 31, 0x1000);
_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
/* turn on all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, i, 0);
val &= ~BIT(11);
_mt7620_mii_write(gsw, i, 0, val);
}
}
/* global page 0 */
_mt7620_mii_write(gsw, 1, 31, 0x8000);
_mt7620_mii_write(gsw, 0, 30, 0xa000);
_mt7620_mii_write(gsw, 1, 30, 0xa000);
_mt7620_mii_write(gsw, 2, 30, 0xa000);
_mt7620_mii_write(gsw, 3, 30, 0xa000);
_mt7620_mii_write(gsw, 0, 4, 0x05e1);
_mt7620_mii_write(gsw, 1, 4, 0x05e1);
_mt7620_mii_write(gsw, 2, 4, 0x05e1);
_mt7620_mii_write(gsw, 3, 4, 0x05e1);
/* global page 2 */
_mt7620_mii_write(gsw, 1, 31, 0xa000);
_mt7620_mii_write(gsw, 0, 16, 0x1111);
_mt7620_mii_write(gsw, 1, 16, 0x1010);
_mt7620_mii_write(gsw, 2, 16, 0x1515);
_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
/* CPU Port6 Force Link 1G, FC ON */
mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
/* Set Port 6 as CPU Port */
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
if (gsw->port4 == PORT4_EPHY) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
val |= 3 << 14;
rt_sysc_w32(val, SYSC_REG_CFG1);
_mt7620_mii_write(gsw, 4, 30, 0xa000);
_mt7620_mii_write(gsw, 4, 4, 0x05e1);
_mt7620_mii_write(gsw, 4, 16, 0x1313);
pr_info("gsw: setting port4 to ephy mode\n");
} else if (!mdio_mode) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
val &= ~(3 << 14);
rt_sysc_w32(val, SYSC_REG_CFG1);
pr_info("gsw: setting port4 to gmac mode\n");
}
}
static const struct of_device_id mediatek_gsw_match[] = {
{ .compatible = "mediatek,mt7620-gsw" },
{},
};
MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
int mtk_gsw_init(struct fe_priv *priv)
{
struct device_node *np = priv->switch_np;
struct platform_device *pdev = of_find_device_by_node(np);
struct mt7620_gsw *gsw;
if (!pdev)
return -ENODEV;
if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
return -EINVAL;
gsw = platform_get_drvdata(pdev);
priv->soc->swpriv = gsw;
mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node));
if (gsw->irq) {
request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
"gsw", priv);
mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
}
return 0;
}
static int mt7620_gsw_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
const char *port4 = NULL;
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
if (!gsw)
return -ENOMEM;
gsw->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(gsw->base))
return PTR_ERR(gsw->base);
gsw->dev = &pdev->dev;
of_property_read_string(np, "mediatek,port4", &port4);
if (port4 && !strcmp(port4, "ephy"))
gsw->port4 = PORT4_EPHY;
else if (port4 && !strcmp(port4, "gmac"))
gsw->port4 = PORT4_EXT;
else
gsw->port4 = PORT4_EPHY;
gsw->irq = platform_get_irq(pdev, 0);
platform_set_drvdata(pdev, gsw);
return 0;
}
static int mt7620_gsw_remove(struct platform_device *pdev)
{
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver gsw_driver = {
.probe = mt7620_gsw_probe,
.remove = mt7620_gsw_remove,
.driver = {
.name = "mt7620-gsw",
.owner = THIS_MODULE,
.of_match_table = mediatek_gsw_match,
},
};
module_platform_driver(gsw_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
MODULE_VERSION(MTK_FE_DRV_VERSION);

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_GSW_MT7620_H__
#define _RALINK_GSW_MT7620_H__
#define GSW_REG_PHY_TIMEOUT (5 * HZ)
#ifdef CONFIG_SOC_MT7621
#define MT7620A_GSW_REG_PIAC 0x0004
#else
#define MT7620A_GSW_REG_PIAC 0x7004
#endif
#define GSW_NUM_VLANS 16
#define GSW_NUM_VIDS 4096
#define GSW_NUM_PORTS 7
#define GSW_PORT6 6
#define GSW_MDIO_ACCESS BIT(31)
#define GSW_MDIO_READ BIT(19)
#define GSW_MDIO_WRITE BIT(18)
#define GSW_MDIO_START BIT(16)
#define GSW_MDIO_ADDR_SHIFT 20
#define GSW_MDIO_REG_SHIFT 25
#define GSW_REG_MIB_CNT_EN 0x4000
#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
#define GSW_REG_SMACCR0 0x3fE4
#define GSW_REG_SMACCR1 0x3fE8
#define GSW_REG_CKGCR 0x3ff0
#define GSW_REG_IMR 0x7008
#define GSW_REG_ISR 0x700c
#define GSW_REG_GPC1 0x7014
#define GSW_REG_MAC_P0_MCR 0x100
#define GSW_REG_MAC_P1_MCR 0x200
// Global MAC control register
#define GSW_REG_GMACCR 0x30E0
#define SYSC_REG_CHIP_REV_ID 0x0c
#define SYSC_REG_CFG1 0x14
#define RST_CTRL_MCM BIT(2)
#define SYSC_PAD_RGMII2_MDIO 0x58
#define SYSC_GPIO_MODE 0x60
#define PORT_IRQ_ST_CHG 0x7f
#ifdef CONFIG_SOC_MT7621
#define ESW_PHY_POLLING 0x0000
#else
#define ESW_PHY_POLLING 0x7000
#endif
#define PMCR_IPG BIT(18)
#define PMCR_MAC_MODE BIT(16)
#define PMCR_FORCE BIT(15)
#define PMCR_TX_EN BIT(14)
#define PMCR_RX_EN BIT(13)
#define PMCR_BACKOFF BIT(9)
#define PMCR_BACKPRES BIT(8)
#define PMCR_RX_FC BIT(5)
#define PMCR_TX_FC BIT(4)
#define PMCR_SPEED(_x) (_x << 2)
#define PMCR_DUPLEX BIT(1)
#define PMCR_LINK BIT(0)
#define PHY_AN_EN BIT(31)
#define PHY_PRE_EN BIT(30)
#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
enum {
/* Global attributes. */
GSW_ATTR_ENABLE_VLAN,
/* Port attributes. */
GSW_ATTR_PORT_UNTAG,
};
enum {
PORT4_EPHY = 0,
PORT4_EXT,
};
struct mt7620_gsw {
struct device *dev;
void __iomem *base;
int irq;
int port4;
unsigned long int autopoll;
};
void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
int mtk_gsw_init(struct fe_priv *priv);
int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
int mt7620_has_carrier(struct fe_priv *priv);
void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
int speed, int duplex);
void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
u32 phy_register, u32 write_data);
u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
void mt7620_handle_carrier(struct fe_priv *priv);
#endif

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <ralink_regs.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
{
iowrite32(val, gsw->base + reg);
}
u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
{
return ioread32(gsw->base + reg);
}
static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
{
struct fe_priv *priv = (struct fe_priv *)_priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
u32 reg, i;
reg = mt7530_mdio_r32(gsw, 0x700c);
mt7530_mdio_w32(gsw, 0x700c, reg);
for (i = 0; i < 5; i++)
if (reg & BIT(i)) {
unsigned int link;
link = mt7530_mdio_r32(gsw,
0x3008 + (i * 0x100)) & 0x1;
if (link != priv->link[i]) {
priv->link[i] = link;
if (link)
netdev_info(priv->netdev,
"port %d link up\n", i);
else
netdev_info(priv->netdev,
"port %d link down\n", i);
}
}
mt7620_handle_carrier(priv);
return IRQ_HANDLED;
}
static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
{
u32 i;
u32 val;
/* wardware reset the switch */
fe_reset(RST_CTRL_MCM);
mdelay(10);
/* reduce RGMII2 PAD driving strength */
rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
/* gpio mux - RGMII1=Normal mode */
rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
/* set GMAC1 RGMII mode */
rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
/* enable MDIO to control MT7530 */
rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
/* turn off all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, i, 0x0);
val |= BIT(11);
_mt7620_mii_write(gsw, i, 0x0, val);
}
/* reset the switch */
mt7530_mdio_w32(gsw, 0x7000, 0x3);
usleep_range(10, 20);
if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
/* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
mtk_switch_w32(gsw, 0x2305e30b, GSW_REG_MAC_P0_MCR);
mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
} else {
/* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
mtk_switch_w32(gsw, 0x2305e33b, GSW_REG_MAC_P0_MCR);
mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
}
/* (GE2, Link down) */
mtk_switch_w32(gsw, 0x8000, GSW_REG_MAC_P1_MCR);
/* Set switch max RX frame length to 2k */
mt7530_mdio_w32(gsw, GSW_REG_GMACCR, 0x3F0B);
/* Enable Port 6, P5 as GMAC5, P5 disable */
val = mt7530_mdio_r32(gsw, 0x7804);
val &= ~BIT(8);
val |= BIT(6) | BIT(13) | BIT(16);
mt7530_mdio_w32(gsw, 0x7804, val);
val = rt_sysc_r32(0x10);
val = (val >> 6) & 0x7;
if (val >= 6) {
/* 25Mhz Xtal - do nothing */
} else if (val >= 3) {
/* 40Mhz */
/* disable MT7530 core clock */
_mt7620_mii_write(gsw, 0, 13, 0x1f);
_mt7620_mii_write(gsw, 0, 14, 0x410);
_mt7620_mii_write(gsw, 0, 13, 0x401f);
_mt7620_mii_write(gsw, 0, 14, 0x0);
/* disable MT7530 PLL */
_mt7620_mii_write(gsw, 0, 13, 0x1f);
_mt7620_mii_write(gsw, 0, 14, 0x40d);
_mt7620_mii_write(gsw, 0, 13, 0x401f);
_mt7620_mii_write(gsw, 0, 14, 0x2020);
/* for MT7530 core clock = 500Mhz */
_mt7620_mii_write(gsw, 0, 13, 0x1f);
_mt7620_mii_write(gsw, 0, 14, 0x40e);
_mt7620_mii_write(gsw, 0, 13, 0x401f);
_mt7620_mii_write(gsw, 0, 14, 0x119);
/* enable MT7530 PLL */
_mt7620_mii_write(gsw, 0, 13, 0x1f);
_mt7620_mii_write(gsw, 0, 14, 0x40d);
_mt7620_mii_write(gsw, 0, 13, 0x401f);
_mt7620_mii_write(gsw, 0, 14, 0x2820);
usleep_range(20, 40);
/* enable MT7530 core clock */
_mt7620_mii_write(gsw, 0, 13, 0x1f);
_mt7620_mii_write(gsw, 0, 14, 0x410);
_mt7620_mii_write(gsw, 0, 13, 0x401f);
} else {
/* 20Mhz Xtal - TODO */
}
/* RGMII */
_mt7620_mii_write(gsw, 0, 14, 0x1);
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
val |= BIT(1);
mt7530_mdio_w32(gsw, 0x7830, val);
val = mt7530_mdio_r32(gsw, 0x7a40);
val &= ~BIT(30);
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
/* delay setting for 10/1000M */
mt7530_mdio_w32(gsw, 0x7b00, 0x102);
mt7530_mdio_w32(gsw, 0x7b04, 0x14);
/* lower Tx Driving*/
mt7530_mdio_w32(gsw, 0x7a54, 0x44);
mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
mt7530_mdio_w32(gsw, 0x7a64, 0x44);
mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
mt7530_mdio_w32(gsw, 0x7a74, 0x44);
mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
/* turn on all PHYs */
for (i = 0; i <= 4; i++) {
val = _mt7620_mii_read(gsw, i, 0);
val &= ~BIT(11);
_mt7620_mii_write(gsw, i, 0, val);
}
/* enable irq */
mt7530_mdio_w32(gsw, 0x7008, 0x1f);
val = mt7530_mdio_r32(gsw, 0x7808);
val |= 3 << 16;
mt7530_mdio_w32(gsw, 0x7808, val);
}
static const struct of_device_id mediatek_gsw_match[] = {
{ .compatible = "mediatek,mt7621-gsw" },
{},
};
MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
int mtk_gsw_init(struct fe_priv *priv)
{
struct device_node *np = priv->switch_np;
struct platform_device *pdev = of_find_device_by_node(np);
struct mt7620_gsw *gsw;
if (!pdev)
return -ENODEV;
if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
return -EINVAL;
gsw = platform_get_drvdata(pdev);
priv->soc->swpriv = gsw;
if (gsw->irq) {
request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
"gsw", priv);
disable_irq(gsw->irq);
}
mt7621_hw_init(gsw, np);
if (gsw->irq)
enable_irq(gsw->irq);
return 0;
}
static int mt7621_gsw_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
struct mt7620_gsw *gsw;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
if (!gsw)
return -ENOMEM;
gsw->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(gsw->base))
return PTR_ERR(gsw->base);
gsw->dev = &pdev->dev;
gsw->irq = platform_get_irq(pdev, 0);
platform_set_drvdata(pdev, gsw);
return 0;
}
static int mt7621_gsw_remove(struct platform_device *pdev)
{
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver gsw_driver = {
.probe = mt7621_gsw_probe,
.remove = mt7621_gsw_remove,
.driver = {
.name = "mt7621-gsw",
.owner = THIS_MODULE,
.of_match_table = mediatek_gsw_match,
},
};
module_platform_driver(gsw_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
MODULE_VERSION(MTK_FE_DRV_VERSION);

261
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mdio.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/phy.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include "mtk_eth_soc.h"
#include "mdio.h"
static int fe_mdio_reset(struct mii_bus *bus)
{
/* TODO */
return 0;
}
static void fe_phy_link_adjust(struct net_device *dev)
{
struct fe_priv *priv = netdev_priv(dev);
unsigned long flags;
int i;
spin_lock_irqsave(&priv->phy->lock, flags);
for (i = 0; i < 8; i++) {
if (priv->phy->phy_node[i]) {
struct phy_device *phydev = priv->phy->phy[i];
int status_change = 0;
if (phydev->link)
if (priv->phy->duplex[i] != phydev->duplex ||
priv->phy->speed[i] != phydev->speed)
status_change = 1;
if (phydev->link != priv->link[i])
status_change = 1;
switch (phydev->speed) {
case SPEED_1000:
case SPEED_100:
case SPEED_10:
priv->link[i] = phydev->link;
priv->phy->duplex[i] = phydev->duplex;
priv->phy->speed[i] = phydev->speed;
if (status_change &&
priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
break;
}
}
}
spin_unlock_irqrestore(&priv->phy->lock, flags);
}
int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
{
const __be32 *_port = NULL;
struct phy_device *phydev;
int phy_mode, port;
_port = of_get_property(phy_node, "reg", NULL);
if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
pr_err("%s: invalid port id\n", phy_node->name);
return -EINVAL;
}
port = be32_to_cpu(*_port);
phy_mode = of_get_phy_mode(phy_node);
if (phy_mode < 0) {
dev_err(priv->dev, "incorrect phy-mode %d\n", phy_mode);
priv->phy->phy_node[port] = NULL;
return -EINVAL;
}
phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
0, phy_mode);
if (!phydev) {
dev_err(priv->dev, "could not connect to PHY\n");
priv->phy->phy_node[port] = NULL;
return -ENODEV;
}
phydev->supported &= PHY_GBIT_FEATURES;
phydev->advertising = phydev->supported;
phydev->no_auto_carrier_off = 1;
dev_info(priv->dev,
"connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
port, dev_name(&phydev->mdio.dev), phydev->phy_id,
phydev->drv->name);
priv->phy->phy[port] = phydev;
priv->link[port] = 0;
return 0;
}
static void phy_init(struct fe_priv *priv, struct phy_device *phy)
{
phy_attach(priv->netdev, dev_name(&phy->mdio.dev), PHY_INTERFACE_MODE_MII);
phy->autoneg = AUTONEG_ENABLE;
phy->speed = 0;
phy->duplex = 0;
phy->supported &= IS_ENABLED(CONFIG_NET_MEDIATEK_MDIO_MT7620) ?
PHY_GBIT_FEATURES : PHY_BASIC_FEATURES;
phy->advertising = phy->supported | ADVERTISED_Autoneg;
phy_start_aneg(phy);
}
static int fe_phy_connect(struct fe_priv *priv)
{
int i;
for (i = 0; i < 8; i++) {
if (priv->phy->phy_node[i]) {
if (!priv->phy_dev) {
priv->phy_dev = priv->phy->phy[i];
priv->phy_flags = FE_PHY_FLAG_PORT;
}
} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
phy_init(priv, mdiobus_get_phy(priv->mii_bus, i));
if (!priv->phy_dev) {
priv->phy_dev = mdiobus_get_phy(priv->mii_bus, i);
priv->phy_flags = FE_PHY_FLAG_ATTACH;
}
}
}
return 0;
}
static void fe_phy_disconnect(struct fe_priv *priv)
{
unsigned long flags;
int i;
for (i = 0; i < 8; i++)
if (priv->phy->phy_fixed[i]) {
spin_lock_irqsave(&priv->phy->lock, flags);
priv->link[i] = 0;
if (priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
spin_unlock_irqrestore(&priv->phy->lock, flags);
} else if (priv->phy->phy[i]) {
phy_disconnect(priv->phy->phy[i]);
} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {
phy_detach(mdiobus_get_phy(priv->mii_bus, i));
}
}
static void fe_phy_start(struct fe_priv *priv)
{
unsigned long flags;
int i;
for (i = 0; i < 8; i++) {
if (priv->phy->phy_fixed[i]) {
spin_lock_irqsave(&priv->phy->lock, flags);
priv->link[i] = 1;
if (priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
spin_unlock_irqrestore(&priv->phy->lock, flags);
} else if (priv->phy->phy[i]) {
phy_start(priv->phy->phy[i]);
}
}
}
static void fe_phy_stop(struct fe_priv *priv)
{
unsigned long flags;
int i;
for (i = 0; i < 8; i++)
if (priv->phy->phy_fixed[i]) {
spin_lock_irqsave(&priv->phy->lock, flags);
priv->link[i] = 0;
if (priv->soc->mdio_adjust_link)
priv->soc->mdio_adjust_link(priv, i);
spin_unlock_irqrestore(&priv->phy->lock, flags);
} else if (priv->phy->phy[i]) {
phy_stop(priv->phy->phy[i]);
}
}
static struct fe_phy phy_ralink = {
.connect = fe_phy_connect,
.disconnect = fe_phy_disconnect,
.start = fe_phy_start,
.stop = fe_phy_stop,
};
int fe_mdio_init(struct fe_priv *priv)
{
struct device_node *mii_np;
int err;
if (!priv->soc->mdio_read || !priv->soc->mdio_write)
return 0;
spin_lock_init(&phy_ralink.lock);
priv->phy = &phy_ralink;
mii_np = of_get_child_by_name(priv->dev->of_node, "mdio-bus");
if (!mii_np) {
dev_err(priv->dev, "no %s child node found", "mdio-bus");
return -ENODEV;
}
if (!of_device_is_available(mii_np)) {
err = 0;
goto err_put_node;
}
priv->mii_bus = mdiobus_alloc();
if (!priv->mii_bus) {
err = -ENOMEM;
goto err_put_node;
}
priv->mii_bus->name = "mdio";
priv->mii_bus->read = priv->soc->mdio_read;
priv->mii_bus->write = priv->soc->mdio_write;
priv->mii_bus->reset = fe_mdio_reset;
priv->mii_bus->priv = priv;
priv->mii_bus->parent = priv->dev;
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
err = of_mdiobus_register(priv->mii_bus, mii_np);
if (err)
goto err_free_bus;
return 0;
err_free_bus:
kfree(priv->mii_bus);
err_put_node:
of_node_put(mii_np);
priv->mii_bus = NULL;
return err;
}
void fe_mdio_cleanup(struct fe_priv *priv)
{
if (!priv->mii_bus)
return;
mdiobus_unregister(priv->mii_bus);
of_node_put(priv->mii_bus->dev.of_node);
kfree(priv->mii_bus);
}

27
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mdio.h Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_MDIO_H__
#define _RALINK_MDIO_H__
#ifdef CONFIG_NET_MEDIATEK_MDIO
int fe_mdio_init(struct fe_priv *priv);
void fe_mdio_cleanup(struct fe_priv *priv);
int fe_connect_phy_node(struct fe_priv *priv,
struct device_node *phy_node);
#else
static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
#endif
#endif

168
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mdio_mt7620.c Normal file
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@ -0,0 +1,168 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
#include "mdio.h"
static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
{
unsigned long t_start = jiffies;
while (1) {
if (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
return 0;
if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))
break;
}
dev_err(gsw->dev, "mdio: MDIO timeout\n");
return -1;
}
u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
u32 phy_register, u32 write_data)
{
if (mt7620_mii_busy_wait(gsw))
return -1;
write_data &= 0xffff;
mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
(phy_register << GSW_MDIO_REG_SHIFT) |
(phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
MT7620A_GSW_REG_PIAC);
if (mt7620_mii_busy_wait(gsw))
return -1;
return 0;
}
u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
{
u32 d;
if (mt7620_mii_busy_wait(gsw))
return 0xffff;
mtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
(phy_reg << GSW_MDIO_REG_SHIFT) |
(phy_addr << GSW_MDIO_ADDR_SHIFT),
MT7620A_GSW_REG_PIAC);
if (mt7620_mii_busy_wait(gsw))
return 0xffff;
d = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
return d;
}
int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
{
struct fe_priv *priv = bus->priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
}
int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
{
struct fe_priv *priv = bus->priv;
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
return _mt7620_mii_read(gsw, phy_addr, phy_reg);
}
void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
{
_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
_mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
_mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
}
u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
{
u16 high, low;
_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
high = _mt7620_mii_read(gsw, 0x1f, 0x10);
return (high << 16) | (low & 0xffff);
}
static unsigned char *fe_speed_str(int speed)
{
switch (speed) {
case 2:
case SPEED_1000:
return "1000";
case 1:
case SPEED_100:
return "100";
case 0:
case SPEED_10:
return "10";
}
return "? ";
}
int mt7620_has_carrier(struct fe_priv *priv)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
int i;
for (i = 0; i < GSW_PORT6; i++)
if (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
return 1;
return 0;
}
void mt7620_handle_carrier(struct fe_priv *priv)
{
if (!priv->phy)
return;
if (mt7620_has_carrier(priv))
netif_carrier_on(priv->netdev);
else
netif_carrier_off(priv->netdev);
}
void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
int speed, int duplex)
{
if (link)
netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
port, fe_speed_str(speed),
(duplex) ? "Full" : "Half");
else
netdev_info(priv->netdev, "port %d link down\n", port);
}
void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
{
mt7620_print_link_state(priv, port, priv->link[port],
priv->phy->speed[port],
(priv->phy->duplex[port] == DUPLEX_FULL));
mt7620_handle_carrier(priv);
}

222
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mdio_rt2880.c Normal file
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
#include "mdio.h"
#define FE_MDIO_RETRY 1000
static unsigned char *rt2880_speed_str(struct fe_priv *priv)
{
switch (priv->phy->speed[0]) {
case SPEED_1000:
return "1000";
case SPEED_100:
return "100";
case SPEED_10:
return "10";
}
return "?";
}
void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
{
u32 mdio_cfg;
if (!priv->link[0]) {
netif_carrier_off(priv->netdev);
netdev_info(priv->netdev, "link down\n");
return;
}
mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
FE_MDIO_CFG_RX_CLK_SKEW_200 |
FE_MDIO_CFG_GP1_FRC_EN;
if (priv->phy->duplex[0] == DUPLEX_FULL)
mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
if (priv->phy->tx_fc[0])
mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
if (priv->phy->rx_fc[0])
mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
switch (priv->phy->speed[0]) {
case SPEED_10:
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
break;
case SPEED_100:
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
break;
case SPEED_1000:
mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
break;
default:
BUG();
}
fe_w32(mdio_cfg, FE_MDIO_CFG);
netif_carrier_on(priv->netdev);
netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
rt2880_speed_str(priv),
(priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
}
static int rt2880_mdio_wait_ready(struct fe_priv *priv)
{
int retries;
retries = FE_MDIO_RETRY;
while (1) {
u32 t;
t = fe_r32(FE_MDIO_ACCESS);
if ((t & BIT(31)) == 0)
return 0;
if (retries-- == 0)
break;
udelay(1);
}
dev_err(priv->dev, "MDIO operation timed out\n");
return -ETIMEDOUT;
}
int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
{
struct fe_priv *priv = bus->priv;
int err;
u32 t;
err = rt2880_mdio_wait_ready(priv);
if (err)
return 0xffff;
t = (phy_addr << 24) | (phy_reg << 16);
fe_w32(t, FE_MDIO_ACCESS);
t |= BIT(31);
fe_w32(t, FE_MDIO_ACCESS);
err = rt2880_mdio_wait_ready(priv);
if (err)
return 0xffff;
pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
return fe_r32(FE_MDIO_ACCESS) & 0xffff;
}
int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
{
struct fe_priv *priv = bus->priv;
int err;
u32 t;
pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
err = rt2880_mdio_wait_ready(priv);
if (err)
return err;
t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
fe_w32(t, FE_MDIO_ACCESS);
t |= BIT(31);
fe_w32(t, FE_MDIO_ACCESS);
return rt2880_mdio_wait_ready(priv);
}
void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
{
const __be32 *id = of_get_property(np, "reg", NULL);
const __be32 *link;
int size;
int phy_mode;
if (!id || (be32_to_cpu(*id) != 0)) {
pr_err("%s: invalid port id\n", np->name);
return;
}
priv->phy->phy_fixed[0] = of_get_property(np,
"mediatek,fixed-link", &size);
if (priv->phy->phy_fixed[0] &&
(size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
pr_err("%s: invalid fixed link property\n", np->name);
priv->phy->phy_fixed[0] = NULL;
return;
}
phy_mode = of_get_phy_mode(np);
switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
break;
case PHY_INTERFACE_MODE_MII:
break;
case PHY_INTERFACE_MODE_RMII:
break;
default:
if (!priv->phy->phy_fixed[0])
dev_err(priv->dev, "port %d - invalid phy mode\n",
priv->phy->speed[0]);
break;
}
priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
return;
if (priv->phy->phy_fixed[0]) {
link = priv->phy->phy_fixed[0];
priv->phy->speed[0] = be32_to_cpup(link++);
priv->phy->duplex[0] = be32_to_cpup(link++);
priv->phy->tx_fc[0] = be32_to_cpup(link++);
priv->phy->rx_fc[0] = be32_to_cpup(link++);
priv->link[0] = 1;
switch (priv->phy->speed[0]) {
case SPEED_10:
break;
case SPEED_100:
break;
case SPEED_1000:
break;
default:
dev_err(priv->dev, "invalid link speed: %d\n",
priv->phy->speed[0]);
priv->phy->phy_fixed[0] = 0;
return;
}
dev_info(priv->dev, "using fixed link parameters\n");
rt2880_mdio_link_adjust(priv, 0);
return;
}
if (priv->phy->phy_node[0] && mdiobus_get_phy(priv->mii_bus, 0))
fe_connect_phy_node(priv, priv->phy->phy_node[0]);
}

23
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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef _RALINK_MDIO_RT2880_H__
#define _RALINK_MDIO_RT2880_H__
void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
#endif

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/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
* Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
*/
#include <linux/if.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/netlink.h>
#include <linux/bitops.h>
#include <net/genetlink.h>
#include <linux/switch.h>
#include <linux/delay.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/lockdep.h>
#include <linux/workqueue.h>
#include <linux/of_device.h>
#include "mt7530.h"
#define MT7530_CPU_PORT 6
#define MT7530_NUM_PORTS 8
#ifdef CONFIG_SOC_MT7621
#define MT7530_NUM_VLANS 4095
#else
#define MT7530_NUM_VLANS 16
#endif
#define MT7530_MAX_VID 4095
#define MT7530_MIN_VID 0
#define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
#define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
#define MT7621_PORT_MIB_TXB_ID 18 /* TxByte */
#define MT7621_PORT_MIB_RXB_ID 37 /* RxByte */
/* registers */
#define REG_ESW_VLAN_VTCR 0x90
#define REG_ESW_VLAN_VAWD1 0x94
#define REG_ESW_VLAN_VAWD2 0x98
#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
/* vlan egress mode */
enum {
ETAG_CTRL_UNTAG = 0,
ETAG_CTRL_TAG = 2,
ETAG_CTRL_SWAP = 1,
ETAG_CTRL_STACK = 3,
};
#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
#define REG_HWTRAP 0x7804
#define MIB_DESC(_s , _o, _n) \
{ \
.size = (_s), \
.offset = (_o), \
.name = (_n), \
}
struct mt7xxx_mib_desc {
unsigned int size;
unsigned int offset;
const char *name;
};
static const struct mt7xxx_mib_desc mt7620_mibs[] = {
MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
};
static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
};
static const struct mt7xxx_mib_desc mt7621_mibs[] = {
MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
};
enum {
/* Global attributes. */
MT7530_ATTR_ENABLE_VLAN,
};
struct mt7530_port_entry {
u16 pvid;
};
struct mt7530_vlan_entry {
u16 vid;
u8 member;
u8 etags;
};
struct mt7530_priv {
void __iomem *base;
struct mii_bus *bus;
struct switch_dev swdev;
bool global_vlan_enable;
struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
};
struct mt7530_mapping {
char *name;
u16 pvids[MT7530_NUM_PORTS];
u8 members[MT7530_NUM_VLANS];
u8 etags[MT7530_NUM_VLANS];
u16 vids[MT7530_NUM_VLANS];
} mt7530_defaults[] = {
{
.name = "llllw",
.pvids = { 1, 1, 1, 1, 2, 1, 1 },
.members = { 0, 0x6f, 0x50 },
.etags = { 0, 0x40, 0x40 },
.vids = { 0, 1, 2 },
}, {
.name = "wllll",
.pvids = { 2, 1, 1, 1, 1, 1, 1 },
.members = { 0, 0x7e, 0x41 },
.etags = { 0, 0x40, 0x40 },
.vids = { 0, 1, 2 },
}, {
.name = "lwlll",
.pvids = { 1, 2, 1, 1, 1, 1, 1 },
.members = { 0, 0x7d, 0x42 },
.etags = { 0, 0x40, 0x40 },
.vids = { 0, 1, 2 },
},
};
struct mt7530_mapping*
mt7530_find_mapping(struct device_node *np)
{
const char *map;
int i;
if (of_property_read_string(np, "mediatek,portmap", &map))
return NULL;
for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
if (!strcmp(map, mt7530_defaults[i].name))
return &mt7530_defaults[i];
return NULL;
}
static void
mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
{
int i = 0;
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530->port_entries[i].pvid = map->pvids[i];
for (i = 0; i < MT7530_NUM_VLANS; i++) {
mt7530->vlan_entries[i].member = map->members[i];
mt7530->vlan_entries[i].etags = map->etags[i];
mt7530->vlan_entries[i].vid = map->vids[i];
}
}
static int
mt7530_reset_switch(struct switch_dev *dev)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
int i;
memset(priv->port_entries, 0, sizeof(priv->port_entries));
memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
/* set default vid of each vlan to the same number of vlan, so the vid
* won't need be set explicitly.
*/
for (i = 0; i < MT7530_NUM_VLANS; i++) {
priv->vlan_entries[i].vid = i;
}
return 0;
}
static int
mt7530_get_vlan_enable(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
val->value.i = priv->global_vlan_enable;
return 0;
}
static int
mt7530_set_vlan_enable(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
priv->global_vlan_enable = val->value.i != 0;
return 0;
}
static u32
mt7530_r32(struct mt7530_priv *priv, u32 reg)
{
u32 val;
if (priv->bus) {
u16 high, low;
mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
high = mdiobus_read(priv->bus, 0x1f, 0x10);
return (high << 16) | (low & 0xffff);
}
val = ioread32(priv->base + reg);
pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
return val;
}
static void
mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
{
if (priv->bus) {
mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
return;
}
pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
iowrite32(val, priv->base + reg);
}
static void
mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
{
int i;
mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
for (i = 0; i < 20; i++) {
u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
if ((val & BIT(31)) == 0)
break;
udelay(1000);
}
if (i == 20)
printk("mt7530: vtcr timeout\n");
}
static int
mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
if (port >= MT7530_NUM_PORTS)
return -EINVAL;
*val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
*val &= 0xfff;
return 0;
}
static int
mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
if (port >= MT7530_NUM_PORTS)
return -EINVAL;
if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
return -EINVAL;
priv->port_entries[port].pvid = pvid;
return 0;
}
static int
mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
u32 member;
u32 etags;
int i;
val->len = 0;
if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
return -EINVAL;
mt7530_vtcr(priv, 0, val->port_vlan);
member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
member >>= 16;
member &= 0xff;
etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
for (i = 0; i < MT7530_NUM_PORTS; i++) {
struct switch_port *p;
int etag;
if (!(member & BIT(i)))
continue;
p = &val->value.ports[val->len++];
p->id = i;
etag = (etags >> (i * 2)) & 0x3;
if (etag == ETAG_CTRL_TAG)
p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
else if (etag != ETAG_CTRL_UNTAG)
printk("vlan egress tag control neither untag nor tag.\n");
}
return 0;
}
static int
mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
u8 member = 0;
u8 etags = 0;
int i;
if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
val->len > MT7530_NUM_PORTS)
return -EINVAL;
for (i = 0; i < val->len; i++) {
struct switch_port *p = &val->value.ports[i];
if (p->id >= MT7530_NUM_PORTS)
return -EINVAL;
member |= BIT(p->id);
if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
etags |= BIT(p->id);
}
priv->vlan_entries[val->port_vlan].member = member;
priv->vlan_entries[val->port_vlan].etags = etags;
return 0;
}
static int
mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
int vlan;
u16 vid;
vlan = val->port_vlan;
vid = (u16)val->value.i;
if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
return -EINVAL;
if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
return -EINVAL;
priv->vlan_entries[vlan].vid = vid;
return 0;
}
static int
mt7621_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
val->value.i = val->port_vlan;
return 0;
}
static int
mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
u32 vid;
int vlan;
vlan = val->port_vlan;
vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
if (vlan & 1)
vid = vid >> 12;
vid &= 0xfff;
val->value.i = vid;
return 0;
}
static void
mt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,
u8 ports, u8 etags)
{
int port;
u32 val;
#ifndef CONFIG_SOC_MT7621
/* vid of vlan */
val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
if (vlan % 2 == 0) {
val &= 0xfff000;
val |= vid;
} else {
val &= 0xfff;
val |= (vid << 12);
}
mt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);
#endif
/* vlan port membership */
if (ports)
mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
REG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |
REG_ESW_VLAN_VAWD1_VALID);
else
mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
/* egress mode */
val = 0;
for (port = 0; port < MT7530_NUM_PORTS; port++) {
if (etags & BIT(port))
val |= ETAG_CTRL_TAG << (port * 2);
else
val |= ETAG_CTRL_UNTAG << (port * 2);
}
mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
/* write to vlan table */
#ifdef CONFIG_SOC_MT7621
mt7530_vtcr(priv, 1, vid);
#else
mt7530_vtcr(priv, 1, vlan);
#endif
}
static int
mt7530_apply_config(struct switch_dev *dev)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
int i, j;
u8 tag_ports;
u8 untag_ports;
if (!priv->global_vlan_enable) {
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
return 0;
}
/* set all ports as security mode */
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
/* check if a port is used in tag/untag vlan egress mode */
tag_ports = 0;
untag_ports = 0;
for (i = 0; i < MT7530_NUM_VLANS; i++) {
u8 member = priv->vlan_entries[i].member;
u8 etags = priv->vlan_entries[i].etags;
if (!member)
continue;
for (j = 0; j < MT7530_NUM_PORTS; j++) {
if (!(member & BIT(j)))
continue;
if (etags & BIT(j))
tag_ports |= 1u << j;
else
untag_ports |= 1u << j;
}
}
/* set all untag-only ports as transparent and the rest as user port */
for (i = 0; i < MT7530_NUM_PORTS; i++) {
u32 pvc_mode = 0x81000000;
if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
pvc_mode = 0x810000c0;
mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
}
/* first clear the swtich vlan table */
for (i = 0; i < MT7530_NUM_VLANS; i++)
mt7530_write_vlan_entry(priv, i, i, 0, 0);
/* now program only vlans with members to avoid
clobbering remapped entries in later iterations */
for (i = 0; i < MT7530_NUM_VLANS; i++) {
u16 vid = priv->vlan_entries[i].vid;
u8 member = priv->vlan_entries[i].member;
u8 etags = priv->vlan_entries[i].etags;
if (member)
mt7530_write_vlan_entry(priv, i, vid, member, etags);
}
/* Port Default PVID */
for (i = 0; i < MT7530_NUM_PORTS; i++) {
int vlan = priv->port_entries[i].pvid;
u16 pvid = 0;
u32 val;
if (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)
pvid = priv->vlan_entries[vlan].vid;
val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
val &= ~0xfff;
val |= pvid;
mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
}
return 0;
}
static int
mt7530_get_port_link(struct switch_dev *dev, int port,
struct switch_port_link *link)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
u32 speed, pmsr;
if (port < 0 || port >= MT7530_NUM_PORTS)
return -EINVAL;
pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
link->link = pmsr & 1;
link->duplex = (pmsr >> 1) & 1;
speed = (pmsr >> 2) & 3;
switch (speed) {
case 0:
link->speed = SWITCH_PORT_SPEED_10;
break;
case 1:
link->speed = SWITCH_PORT_SPEED_100;
break;
case 2:
case 3: /* forced gige speed can be 2 or 3 */
link->speed = SWITCH_PORT_SPEED_1000;
break;
default:
link->speed = SWITCH_PORT_SPEED_UNKNOWN;
break;
}
return 0;
}
static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
{
unsigned int port_base;
u64 lo;
port_base = MT7621_MIB_COUNTER_BASE +
MT7621_MIB_COUNTER_PORT_OFFSET * port;
lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
if (mt7621_mibs[i].size == 2) {
u64 hi;
hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
lo |= hi << 32;
}
return lo;
}
static int mt7621_sw_get_port_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
static char buf[4096];
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
int i, len = 0;
if (val->port_vlan >= MT7530_NUM_PORTS)
return -EINVAL;
len += snprintf(buf + len, sizeof(buf) - len,
"Port %d MIB counters\n", val->port_vlan);
for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
u64 counter;
len += snprintf(buf + len, sizeof(buf) - len,
"%-11s: ", mt7621_mibs[i].name);
counter = get_mib_counter(priv, i, val->port_vlan);
len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
counter);
}
val->value.s = buf;
val->len = len;
return 0;
}
static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
{
return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
}
static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
{
return mt7530_r32(priv,
MT7620_MIB_COUNTER_BASE_PORT +
(MT7620_MIB_COUNTER_PORT_OFFSET * port) +
mt7620_port_mibs[i].offset);
}
static int mt7530_sw_get_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
static char buf[4096];
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
int i, len = 0;
len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
u64 counter;
len += snprintf(buf + len, sizeof(buf) - len,
"%-11s: ", mt7620_mibs[i].name);
counter = get_mib_counter_7620(priv, i);
len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
counter);
}
val->value.s = buf;
val->len = len;
return 0;
}
static int mt7530_sw_get_port_mib(struct switch_dev *dev,
const struct switch_attr *attr,
struct switch_val *val)
{
static char buf[4096];
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
int i, len = 0;
if (val->port_vlan >= MT7530_NUM_PORTS)
return -EINVAL;
len += snprintf(buf + len, sizeof(buf) - len,
"Port %d MIB counters\n", val->port_vlan);
for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
u64 counter;
len += snprintf(buf + len, sizeof(buf) - len,
"%-11s: ", mt7620_port_mibs[i].name);
counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
counter);
}
val->value.s = buf;
val->len = len;
return 0;
}
static int mt7530_get_port_stats(struct switch_dev *dev, int port,
struct switch_port_stats *stats)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
if (port < 0 || port >= MT7530_NUM_PORTS)
return -EINVAL;
stats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);
stats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);
return 0;
}
static int mt7621_get_port_stats(struct switch_dev *dev, int port,
struct switch_port_stats *stats)
{
struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
if (port < 0 || port >= MT7530_NUM_PORTS)
return -EINVAL;
stats->tx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_TXB_ID, port);
stats->rx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_RXB_ID, port);
return 0;
}
static const struct switch_attr mt7530_global[] = {
{
.type = SWITCH_TYPE_INT,
.name = "enable_vlan",
.description = "VLAN mode (1:enabled)",
.max = 1,
.id = MT7530_ATTR_ENABLE_VLAN,
.get = mt7530_get_vlan_enable,
.set = mt7530_set_vlan_enable,
}, {
.type = SWITCH_TYPE_STRING,
.name = "mib",
.description = "Get MIB counters for switch",
.get = mt7530_sw_get_mib,
.set = NULL,
},
};
static const struct switch_attr mt7621_port[] = {
{
.type = SWITCH_TYPE_STRING,
.name = "mib",
.description = "Get MIB counters for port",
.get = mt7621_sw_get_port_mib,
.set = NULL,
},
};
static const struct switch_attr mt7621_vlan[] = {
{
.type = SWITCH_TYPE_INT,
.name = "vid",
.description = "VLAN ID (0-4094)",
.set = mt7530_set_vid,
.get = mt7621_get_vid,
.max = 4094,
},
};
static const struct switch_attr mt7530_port[] = {
{
.type = SWITCH_TYPE_STRING,
.name = "mib",
.description = "Get MIB counters for port",
.get = mt7530_sw_get_port_mib,
.set = NULL,
},
};
static const struct switch_attr mt7530_vlan[] = {
{
.type = SWITCH_TYPE_INT,
.name = "vid",
.description = "VLAN ID (0-4094)",
.set = mt7530_set_vid,
.get = mt7530_get_vid,
.max = 4094,
},
};
static const struct switch_dev_ops mt7621_ops = {
.attr_global = {
.attr = mt7530_global,
.n_attr = ARRAY_SIZE(mt7530_global),
},
.attr_port = {
.attr = mt7621_port,
.n_attr = ARRAY_SIZE(mt7621_port),
},
.attr_vlan = {
.attr = mt7621_vlan,
.n_attr = ARRAY_SIZE(mt7621_vlan),
},
.get_vlan_ports = mt7530_get_vlan_ports,
.set_vlan_ports = mt7530_set_vlan_ports,
.get_port_pvid = mt7530_get_port_pvid,
.set_port_pvid = mt7530_set_port_pvid,
.get_port_link = mt7530_get_port_link,
.get_port_stats = mt7621_get_port_stats,
.apply_config = mt7530_apply_config,
.reset_switch = mt7530_reset_switch,
};
static const struct switch_dev_ops mt7530_ops = {
.attr_global = {
.attr = mt7530_global,
.n_attr = ARRAY_SIZE(mt7530_global),
},
.attr_port = {
.attr = mt7530_port,
.n_attr = ARRAY_SIZE(mt7530_port),
},
.attr_vlan = {
.attr = mt7530_vlan,
.n_attr = ARRAY_SIZE(mt7530_vlan),
},
.get_vlan_ports = mt7530_get_vlan_ports,
.set_vlan_ports = mt7530_set_vlan_ports,
.get_port_pvid = mt7530_get_port_pvid,
.set_port_pvid = mt7530_set_port_pvid,
.get_port_link = mt7530_get_port_link,
.get_port_stats = mt7530_get_port_stats,
.apply_config = mt7530_apply_config,
.reset_switch = mt7530_reset_switch,
};
int
mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
{
struct switch_dev *swdev;
struct mt7530_priv *mt7530;
struct mt7530_mapping *map;
int ret;
mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
if (!mt7530)
return -ENOMEM;
mt7530->base = base;
mt7530->bus = bus;
mt7530->global_vlan_enable = vlan;
swdev = &mt7530->swdev;
if (bus) {
swdev->alias = "mt7530";
swdev->name = "mt7530";
} else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
swdev->alias = "mt7621";
swdev->name = "mt7621";
} else {
swdev->alias = "mt7620";
swdev->name = "mt7620";
}
swdev->cpu_port = MT7530_CPU_PORT;
swdev->ports = MT7530_NUM_PORTS;
swdev->vlans = MT7530_NUM_VLANS;
if (IS_ENABLED(CONFIG_SOC_MT7621))
swdev->ops = &mt7621_ops;
else
swdev->ops = &mt7530_ops;
ret = register_switch(swdev, NULL);
if (ret) {
dev_err(dev, "failed to register mt7530\n");
return ret;
}
map = mt7530_find_mapping(dev->of_node);
if (map)
mt7530_apply_mapping(mt7530, map);
mt7530_apply_config(swdev);
/* magic vodoo */
if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
}
dev_info(dev, "loaded %s driver\n", swdev->name);
return 0;
}

186
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/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
* Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
*/
#ifndef _MT7530_H__
#define _MT7530_H__
#define MT7620_MIB_COUNTER_BASE_PORT 0x4000
#define MT7620_MIB_COUNTER_PORT_OFFSET 0x100
#define MT7620_MIB_COUNTER_BASE 0x1010
/* PPE Accounting Group #0 Byte Counter */
#define MT7620_MIB_STATS_PPE_AC_BCNT0 0x000
/* PPE Accounting Group #0 Packet Counter */
#define MT7620_MIB_STATS_PPE_AC_PCNT0 0x004
/* PPE Accounting Group #63 Byte Counter */
#define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8
/* PPE Accounting Group #63 Packet Counter */
#define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC
/* PPE Meter Group #0 */
#define MT7620_MIB_STATS_PPE_MTR_CNT0 0x200
/* PPE Meter Group #63 */
#define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC
/* Transmit good byte count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300
/* Transmit good packet count for CPU GDM (exclude flow control frames) */
#define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304
/* Transmit abort count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT 0x308
/* Transmit collision count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_TX_COLCNT 0x30C
/* Received good byte count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_GBCNT1 0x320
/* Received good packet count for CPU GDM (exclude flow control frame) */
#define MT7620_MIB_STATS_GDM1_RX_GPCNT1 0x324
/* Received overflow error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_OERCNT 0x328
/* Received FCS error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_FERCNT 0x32C
/* Received too short error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_SERCNT 0x330
/* Received too long error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_LERCNT 0x334
/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_CERCNT 0x338
/* Received flow control pkt count for CPU GDM */
#define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C
/* Transmit good byte count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340
/* Transmit good packet count for PPE GDM (exclude flow control frames) */
#define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344
/* Transmit abort count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT 0x348
/* Transmit collision count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_TX_COLCNT 0x34C
/* Received good byte count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360
/* Received good packet count for PPE GDM (exclude flow control frame) */
#define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364
/* Received overflow error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_OERCNT 0x368
/* Received FCS error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_FERCNT 0x36C
/* Received too short error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_SERCNT 0x370
/* Received too long error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_LERCNT 0x374
/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_CERCNT 0x378
/* Received flow control pkt count for PPE GDM */
#define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C
/* Tx Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TGPCN 0x10
/* Tx Bad Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TBOCN 0x14
/* Tx Good Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TGOCN 0x18
/* Tx Event Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_TEPCN 0x1C
/* Rx Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_RGPCN 0x20
/* Rx Bad Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_RBOCN 0x24
/* Rx Good Octet Counter of Port n */
#define MT7620_MIB_STATS_PORT_RGOCN 0x28
/* Rx Event Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_REPC1N 0x2C
/* Rx Event Packet Counter of Port n */
#define MT7620_MIB_STATS_PORT_REPC2N 0x30
#define MT7621_MIB_COUNTER_BASE 0x4000
#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
#define MT7621_STATS_TDPC 0x00
#define MT7621_STATS_TCRC 0x04
#define MT7621_STATS_TUPC 0x08
#define MT7621_STATS_TMPC 0x0C
#define MT7621_STATS_TBPC 0x10
#define MT7621_STATS_TCEC 0x14
#define MT7621_STATS_TSCEC 0x18
#define MT7621_STATS_TMCEC 0x1C
#define MT7621_STATS_TDEC 0x20
#define MT7621_STATS_TLCEC 0x24
#define MT7621_STATS_TXCEC 0x28
#define MT7621_STATS_TPPC 0x2C
#define MT7621_STATS_TL64PC 0x30
#define MT7621_STATS_TL65PC 0x34
#define MT7621_STATS_TL128PC 0x38
#define MT7621_STATS_TL256PC 0x3C
#define MT7621_STATS_TL512PC 0x40
#define MT7621_STATS_TL1024PC 0x44
#define MT7621_STATS_TOC 0x48
#define MT7621_STATS_RDPC 0x60
#define MT7621_STATS_RFPC 0x64
#define MT7621_STATS_RUPC 0x68
#define MT7621_STATS_RMPC 0x6C
#define MT7621_STATS_RBPC 0x70
#define MT7621_STATS_RAEPC 0x74
#define MT7621_STATS_RCEPC 0x78
#define MT7621_STATS_RUSPC 0x7C
#define MT7621_STATS_RFEPC 0x80
#define MT7621_STATS_ROSPC 0x84
#define MT7621_STATS_RJEPC 0x88
#define MT7621_STATS_RPPC 0x8C
#define MT7621_STATS_RL64PC 0x90
#define MT7621_STATS_RL65PC 0x94
#define MT7621_STATS_RL128PC 0x98
#define MT7621_STATS_RL256PC 0x9C
#define MT7621_STATS_RL512PC 0xA0
#define MT7621_STATS_RL1024PC 0xA4
#define MT7621_STATS_ROC 0xA8
#define MT7621_STATS_RDPC_CTRL 0xB0
#define MT7621_STATS_RDPC_ING 0xB4
#define MT7621_STATS_RDPC_ARL 0xB8
int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
#endif

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
* Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
*/
#include "mtk_offload.h"
static const char *mtk_foe_entry_state_str[] = {
"INVALID",
"UNBIND",
"BIND",
"FIN"
};
static const char *mtk_foe_packet_type_str[] = {
"IPV4_HNAPT",
"IPV4_HNAT",
"IPV6_1T_ROUTE",
"IPV4_DSLITE",
"IPV6_3T_ROUTE",
"IPV6_5T_ROUTE",
"IPV6_6RD",
};
#define IPV4_HNAPT 0
#define IPV4_HNAT 1
#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1: 0)
struct mtk_eth *_eth;
#define es(entry) (mtk_foe_entry_state_str[entry->bfib1.state])
//#define ei(entry, end) (MTK_PPE_TBL_SZ - (int)(end - entry))
#define ei(entry, end) (MTK_PPE_ENTRY_CNT - (int)(end - entry))
#define pt(entry) (mtk_foe_packet_type_str[entry->ipv4_hnapt.bfib1.pkt_type])
static int mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private)
{
struct mtk_eth *eth = _eth;
struct mtk_foe_entry *entry, *end;
int i = 0;
entry = eth->foe_table;
end = eth->foe_table + MTK_PPE_ENTRY_CNT;
while (entry < end) {
if (IS_IPV4_HNAPT(entry)) {
__be32 saddr = htonl(entry->ipv4_hnapt.sip);
__be32 daddr = htonl(entry->ipv4_hnapt.dip);
__be32 nsaddr = htonl(entry->ipv4_hnapt.new_sip);
__be32 ndaddr = htonl(entry->ipv4_hnapt.new_dip);
unsigned char h_dest[ETH_ALEN];
unsigned char h_source[ETH_ALEN];
*((u32*) h_source) = swab32(entry->ipv4_hnapt.smac_hi);
*((u16*) &h_source[4]) = swab16(entry->ipv4_hnapt.smac_lo);
*((u32*) h_dest) = swab32(entry->ipv4_hnapt.dmac_hi);
*((u16*) &h_dest[4]) = swab16(entry->ipv4_hnapt.dmac_lo);
seq_printf(m,
"(%x)0x%05x|state=%s|type=%s|"
"%pI4:%d->%pI4:%d=>%pI4:%d->%pI4:%d|%pM=>%pM|"
"etype=0x%04x|info1=0x%x|info2=0x%x|"
"vlan1=%d|vlan2=%d\n",
i,
ei(entry, end), es(entry), pt(entry),
&saddr, entry->ipv4_hnapt.sport,
&daddr, entry->ipv4_hnapt.dport,
&nsaddr, entry->ipv4_hnapt.new_sport,
&ndaddr, entry->ipv4_hnapt.new_dport, h_source,
h_dest, ntohs(entry->ipv4_hnapt.etype),
entry->ipv4_hnapt.info_blk1,
entry->ipv4_hnapt.info_blk2,
entry->ipv4_hnapt.vlan1,
entry->ipv4_hnapt.vlan2);
} else
seq_printf(m, "0x%05x state=%s\n",
ei(entry, end), es(entry));
entry++;
i++;
}
return 0;
}
static int mtk_ppe_debugfs_foe_open(struct inode *inode, struct file *file)
{
return single_open(file, mtk_ppe_debugfs_foe_show, file->private_data);
}
static const struct file_operations mtk_ppe_debugfs_foe_fops = {
.open = mtk_ppe_debugfs_foe_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
int mtk_ppe_debugfs_init(struct mtk_eth *eth)
{
struct dentry *root;
_eth = eth;
root = debugfs_create_dir("mtk_ppe", NULL);
if (!root)
return -ENOMEM;
debugfs_create_file("all_entry", S_IRUGO, root, eth, &mtk_ppe_debugfs_foe_fops);
return 0;
}

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#ifndef FE_ETH_H
#define FE_ETH_H
#include <linux/mii.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#include <linux/dma-mapping.h>
#include <linux/phy.h>
#include <linux/ethtool.h>
#include <linux/version.h>
enum fe_reg {
FE_REG_PDMA_GLO_CFG = 0,
FE_REG_PDMA_RST_CFG,
FE_REG_DLY_INT_CFG,
FE_REG_TX_BASE_PTR0,
FE_REG_TX_MAX_CNT0,
FE_REG_TX_CTX_IDX0,
FE_REG_TX_DTX_IDX0,
FE_REG_RX_BASE_PTR0,
FE_REG_RX_MAX_CNT0,
FE_REG_RX_CALC_IDX0,
FE_REG_RX_DRX_IDX0,
FE_REG_FE_INT_ENABLE,
FE_REG_FE_INT_STATUS,
FE_REG_FE_DMA_VID_BASE,
FE_REG_FE_COUNTER_BASE,
FE_REG_FE_RST_GL,
FE_REG_FE_INT_STATUS2,
FE_REG_COUNT
};
enum fe_work_flag {
FE_FLAG_RESET_PENDING,
FE_FLAG_MAX
};
#define MTK_FE_DRV_VERSION "0.1.2"
/* power of 2 to let NEXT_TX_DESP_IDX work */
#define NUM_DMA_DESC BIT(10)
#define MAX_DMA_DESC 0xfff
#define FE_DELAY_EN_INT 0x80
#define FE_DELAY_MAX_INT 0x04
#define FE_DELAY_MAX_TOUT 0x04
#define FE_DELAY_TIME 20
#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \
FE_DELAY_MAX_TOUT)
#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
#define FE_PSE_FQFC_CFG_INIT 0x80504000
#define FE_PSE_FQFC_CFG_256Q 0xff908000
/* interrupt bits */
#define FE_CNT_PPE_AF BIT(31)
#define FE_CNT_GDM_AF BIT(29)
#define FE_PSE_P2_FC BIT(26)
#define FE_PSE_BUF_DROP BIT(24)
#define FE_GDM_OTHER_DROP BIT(23)
#define FE_PSE_P1_FC BIT(22)
#define FE_PSE_P0_FC BIT(21)
#define FE_PSE_FQ_EMPTY BIT(20)
#define FE_GE1_STA_CHG BIT(18)
#define FE_TX_COHERENT BIT(17)
#define FE_RX_COHERENT BIT(16)
#define FE_TX_DONE_INT3 BIT(11)
#define FE_TX_DONE_INT2 BIT(10)
#define FE_TX_DONE_INT1 BIT(9)
#define FE_TX_DONE_INT0 BIT(8)
#define FE_RX_DONE_INT0 BIT(2)
#define FE_TX_DLY_INT BIT(1)
#define FE_RX_DLY_INT BIT(0)
#define FE_RX_DONE_INT FE_RX_DONE_INT0
#define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
#define RT5350_RX_DLY_INT BIT(30)
#define RT5350_TX_DLY_INT BIT(28)
#define RT5350_RX_DONE_INT1 BIT(17)
#define RT5350_RX_DONE_INT0 BIT(16)
#define RT5350_TX_DONE_INT3 BIT(3)
#define RT5350_TX_DONE_INT2 BIT(2)
#define RT5350_TX_DONE_INT1 BIT(1)
#define RT5350_TX_DONE_INT0 BIT(0)
#define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
#define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
/* registers */
#define FE_FE_OFFSET 0x0000
#define FE_GDMA_OFFSET 0x0020
#define FE_PSE_OFFSET 0x0040
#define FE_GDMA2_OFFSET 0x0060
#define FE_CDMA_OFFSET 0x0080
#define FE_DMA_VID0 0x00a8
#define FE_PDMA_OFFSET 0x0100
#define FE_PPE_OFFSET 0x0200
#define FE_CMTABLE_OFFSET 0x0400
#define FE_POLICYTABLE_OFFSET 0x1000
#define RT5350_PDMA_OFFSET 0x0800
#define RT5350_SDM_OFFSET 0x0c00
#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
#ifdef CONFIG_SOC_MT7621
#define MT7620A_GDMA_OFFSET 0x0500
#else
#define MT7620A_GDMA_OFFSET 0x0600
#endif
#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
/* Switch DMA configuration */
#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00)
#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04)
#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08)
#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C)
#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10)
#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100)
#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104)
#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108)
#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C)
#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110)
#define RT5350_SDM_ICS_EN BIT(16)
#define RT5350_SDM_TCS_EN BIT(17)
#define RT5350_SDM_UCS_EN BIT(18)
/* MDIO_CFG register bits */
#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
/* uni-cast port */
#define FE_GDM1_JMB_LEN_MASK 0xf
#define FE_GDM1_JMB_LEN_SHIFT 28
#define FE_GDM1_ICS_EN BIT(22)
#define FE_GDM1_TCS_EN BIT(21)
#define FE_GDM1_UCS_EN BIT(20)
#define FE_GDM1_JMB_EN BIT(19)
#define FE_GDM1_STRPCRC BIT(16)
#define FE_GDM1_UFRC_P_CPU (0 << 12)
#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
#define FE_GDM1_UFRC_P_PPE (6 << 12)
/* checksums */
#define FE_ICS_GEN_EN BIT(2)
#define FE_UCS_GEN_EN BIT(1)
#define FE_TCS_GEN_EN BIT(0)
/* dma ring */
#define FE_PST_DRX_IDX0 BIT(16)
#define FE_PST_DTX_IDX3 BIT(3)
#define FE_PST_DTX_IDX2 BIT(2)
#define FE_PST_DTX_IDX1 BIT(1)
#define FE_PST_DTX_IDX0 BIT(0)
#define FE_RX_2B_OFFSET BIT(31)
#define FE_TX_WB_DDONE BIT(6)
#define FE_RX_DMA_BUSY BIT(3)
#define FE_TX_DMA_BUSY BIT(1)
#define FE_RX_DMA_EN BIT(2)
#define FE_TX_DMA_EN BIT(0)
#define FE_PDMA_SIZE_4DWORDS (0 << 4)
#define FE_PDMA_SIZE_8DWORDS (1 << 4)
#define FE_PDMA_SIZE_16DWORDS (2 << 4)
#define FE_US_CYC_CNT_MASK 0xff
#define FE_US_CYC_CNT_SHIFT 0x8
#define FE_US_CYC_CNT_DIVISOR 1000000
/* rxd2 */
#define RX_DMA_DONE BIT(31)
#define RX_DMA_LSO BIT(30)
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
#define RX_DMA_TAG BIT(15)
/* rxd3 */
#define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
#define RX_DMA_VID(_x) ((_x) & 0xffff)
/* rxd4 */
#define RX_DMA_L4VALID BIT(30)
struct fe_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
unsigned int rxd3;
unsigned int rxd4;
} __packed __aligned(4);
#define TX_DMA_BUF_LEN 0x3fff
#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN)
#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
#define TX_DMA_LS1 BIT(14)
#define TX_DMA_LS0 BIT(30)
#define TX_DMA_DONE BIT(31)
#define TX_DMA_INS_VLAN_MT7621 BIT(16)
#define TX_DMA_INS_VLAN BIT(7)
#define TX_DMA_INS_PPPOE BIT(12)
#define TX_DMA_QN(_x) ((_x) << 16)
#define TX_DMA_PN(_x) ((_x) << 24)
#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
#define TX_DMA_UDF BIT(20)
#define TX_DMA_CHKSUM (0x7 << 29)
#define TX_DMA_TSO BIT(28)
/* frame engine counters */
#define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
#define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
#define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
/* phy device flags */
#define FE_PHY_FLAG_PORT BIT(0)
#define FE_PHY_FLAG_ATTACH BIT(1)
struct fe_tx_dma {
unsigned int txd1;
unsigned int txd2;
unsigned int txd3;
unsigned int txd4;
} __packed __aligned(4);
struct fe_priv;
struct fe_phy {
/* make sure that phy operations are atomic */
spinlock_t lock;
struct phy_device *phy[8];
struct device_node *phy_node[8];
const __be32 *phy_fixed[8];
int duplex[8];
int speed[8];
int tx_fc[8];
int rx_fc[8];
int (*connect)(struct fe_priv *priv);
void (*disconnect)(struct fe_priv *priv);
void (*start)(struct fe_priv *priv);
void (*stop)(struct fe_priv *priv);
};
struct fe_soc_data {
const u16 *reg_table;
void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
void (*reset_fe)(void);
void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
int (*fwd_config)(struct fe_priv *priv);
void (*tx_dma)(struct fe_tx_dma *txd);
int (*switch_init)(struct fe_priv *priv);
int (*switch_config)(struct fe_priv *priv);
void (*port_init)(struct fe_priv *priv, struct device_node *port);
int (*has_carrier)(struct fe_priv *priv);
int (*mdio_init)(struct fe_priv *priv);
void (*mdio_cleanup)(struct fe_priv *priv);
int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
u16 val);
int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
void (*mdio_adjust_link)(struct fe_priv *priv, int port);
void *swpriv;
u32 pdma_glo_cfg;
u32 rx_int;
u32 tx_int;
u32 status_int;
u32 checksum_bit;
};
#define FE_FLAG_PADDING_64B BIT(0)
#define FE_FLAG_PADDING_BUG BIT(1)
#define FE_FLAG_JUMBO_FRAME BIT(2)
#define FE_FLAG_RX_2B_OFFSET BIT(3)
#define FE_FLAG_RX_SG_DMA BIT(4)
#define FE_FLAG_RX_VLAN_CTAG BIT(5)
#define FE_FLAG_NAPI_WEIGHT BIT(6)
#define FE_FLAG_CALIBRATE_CLK BIT(7)
#define FE_FLAG_HAS_SWITCH BIT(8)
#define FE_STAT_REG_DECLARE \
_FE(tx_bytes) \
_FE(tx_packets) \
_FE(tx_skip) \
_FE(tx_collisions) \
_FE(rx_bytes) \
_FE(rx_packets) \
_FE(rx_overflow) \
_FE(rx_fcs_errors) \
_FE(rx_short_errors) \
_FE(rx_long_errors) \
_FE(rx_checksum_errors) \
_FE(rx_flow_control_packets)
struct fe_hw_stats {
/* make sure that stats operations are atomic */
spinlock_t stats_lock;
struct u64_stats_sync syncp;
#define _FE(x) u64 x;
FE_STAT_REG_DECLARE
#undef _FE
};
struct fe_tx_buf {
struct sk_buff *skb;
DEFINE_DMA_UNMAP_ADDR(dma_addr0);
DEFINE_DMA_UNMAP_ADDR(dma_addr1);
u16 dma_len0;
u16 dma_len1;
};
struct fe_tx_ring {
struct fe_tx_dma *tx_dma;
struct fe_tx_buf *tx_buf;
dma_addr_t tx_phys;
u16 tx_ring_size;
u16 tx_free_idx;
u16 tx_next_idx;
u16 tx_thresh;
};
struct fe_rx_ring {
struct page_frag_cache frag_cache;
struct fe_rx_dma *rx_dma;
u8 **rx_data;
dma_addr_t rx_phys;
u16 rx_ring_size;
u16 frag_size;
u16 rx_buf_size;
u16 rx_calc_idx;
};
struct fe_priv {
/* make sure that register operations are atomic */
spinlock_t page_lock;
struct fe_soc_data *soc;
struct net_device *netdev;
struct device_node *switch_np;
u32 msg_enable;
u32 flags;
struct device *dev;
unsigned long sysclk;
struct fe_rx_ring rx_ring;
struct napi_struct rx_napi;
struct fe_tx_ring tx_ring;
struct fe_phy *phy;
struct mii_bus *mii_bus;
struct phy_device *phy_dev;
u32 phy_flags;
int link[8];
struct fe_hw_stats *hw_stats;
unsigned long vlan_map;
struct work_struct pending_work;
DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
struct reset_control *rst_ppe;
struct mtk_foe_entry *foe_table;
dma_addr_t foe_table_phys;
struct flow_offload __rcu **foe_flow_table;
};
extern const struct of_device_id of_fe_match[];
void fe_w32(u32 val, unsigned reg);
void fe_m32(struct fe_priv *priv, u32 clear, u32 set, unsigned reg);
u32 fe_r32(unsigned reg);
int fe_set_clock_cycle(struct fe_priv *priv);
void fe_csum_config(struct fe_priv *priv);
void fe_stats_update(struct fe_priv *priv);
void fe_fwd_config(struct fe_priv *priv);
void fe_reg_w32(u32 val, enum fe_reg reg);
u32 fe_reg_r32(enum fe_reg reg);
void fe_reset(u32 reset_bits);
static inline void *priv_netdev(struct fe_priv *priv)
{
return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
}
int mtk_ppe_probe(struct fe_priv *eth);
void mtk_ppe_remove(struct fe_priv *eth);
int mtk_flow_offload(struct fe_priv *eth,
enum flow_offload_type type,
struct flow_offload *flow,
struct flow_offload_hw_path *src,
struct flow_offload_hw_path *dest);
int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4);
#endif /* FE_ETH_H */

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2018 John Crispin <john@phrozen.org>
*/
#include "mtk_offload.h"
#define INVALID 0
#define UNBIND 1
#define BIND 2
#define FIN 3
#define IPV4_HNAPT 0
#define IPV4_HNAT 1
static u32
mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
{
u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port);
u32 src = ntohl(tuple->dst_v4.s_addr);
u32 dst = ntohl(tuple->src_v4.s_addr);
u32 hash = (ports & src) | ((~ports) & dst);
u32 hash_23_0 = hash & 0xffffff;
u32 hash_31_24 = hash & 0xff000000;
hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
hash &= 0x7ff;
hash *= 2;;
return hash;
}
static int
mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
struct flow_offload_tuple *tuple,
struct flow_offload_tuple *dest_tuple,
struct flow_offload_hw_path *src,
struct flow_offload_hw_path *dest)
{
int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
if (tuple->l4proto == IPPROTO_UDP)
entry->ipv4_hnapt.bfib1.udp = 1;
entry->ipv4_hnapt.etype = htons(ETH_P_IP);
entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
entry->ipv4_hnapt.iblk2.fqos = 0;
entry->ipv4_hnapt.bfib1.ttl = 1;
entry->ipv4_hnapt.bfib1.cah = 1;
entry->ipv4_hnapt.bfib1.ka = 1;
entry->ipv4_hnapt.iblk2.mcast = is_mcast;
entry->ipv4_hnapt.iblk2.dscp = 0;
entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
#ifdef CONFIG_NET_MEDIATEK_HW_QOS
entry->ipv4_hnapt.iblk2.qid = 1;
entry->ipv4_hnapt.iblk2.fqos = 1;
#endif
#ifdef CONFIG_RALINK
entry->ipv4_hnapt.iblk2.dp = 1;
if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
entry->ipv4_hnapt.iblk2.qid += 8;
#else
entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
#endif
entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
entry->bfib1.state = BIND;
if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
entry->bfib1.psn = 1;
entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
}
if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
entry->ipv4_hnapt.vlan1 = dest->vlan_id;
entry->bfib1.vlan_layer = 1;
switch (dest->vlan_proto) {
case htons(ETH_P_8021Q):
entry->ipv4_hnapt.bfib1.vpm = 1;
break;
case htons(ETH_P_8021AD):
entry->ipv4_hnapt.bfib1.vpm = 2;
break;
default:
return -EINVAL;
}
}
return 0;
}
static void
mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
{
entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
}
static void
mtk_foe_write(struct mtk_eth *eth, u32 hash,
struct mtk_foe_entry *entry)
{
struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
memcpy(&table[hash], entry, sizeof(*entry));
}
int mtk_flow_offload(struct mtk_eth *eth,
enum flow_offload_type type,
struct flow_offload *flow,
struct flow_offload_hw_path *src,
struct flow_offload_hw_path *dest)
{
struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
u32 ohash, rhash;
struct mtk_foe_entry orig = {
.bfib1.time_stamp = time_stamp,
.bfib1.psn = 0,
};
struct mtk_foe_entry reply = {
.bfib1.time_stamp = time_stamp,
.bfib1.psn = 0,
};
if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
return -EINVAL;
switch (otuple->l3proto) {
case AF_INET:
if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
return -EINVAL;
ohash = mtk_flow_hash_v4(otuple);
rhash = mtk_flow_hash_v4(rtuple);
break;
case AF_INET6:
return -EINVAL;
default:
return -EINVAL;
}
if (type == FLOW_OFFLOAD_DEL) {
orig.bfib1.state = INVALID;
reply.bfib1.state = INVALID;
flow = NULL;
goto write;
}
mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
write:
mtk_foe_write(eth, ohash, &orig);
mtk_foe_write(eth, rhash, &reply);
rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
if (type == FLOW_OFFLOAD_DEL)
synchronize_rcu();
return 0;
}
#ifdef CONFIG_NET_MEDIATEK_HW_QOS
#define QDMA_TX_SCH_TX 0x1a14
static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
{
int exp = 0, shift = 0;
u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
u32 val = 0;
if (rate)
val = BIT(11);
while (rate > 127) {
rate /= 10;
exp++;
}
val |= (rate & 0x7f) << 4;
val |= exp & 0xf;
if (id)
shift = 16;
reg &= ~(0xffff << shift);
reg |= val << shift;
mtk_w32(eth, val, QDMA_TX_SCH_TX);
}
#define QTX_CFG(x) (0x1800 + (x * 0x10))
#define QTX_SCH(x) (0x1804 + (x * 0x10))
static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
{
int max_exp = 0, min_exp = 0;
u32 reg;
if (id >= 16)
return;
reg = mtk_r32(eth, QTX_SCH(id));
reg &= 0x70000000;
if (sched)
reg |= BIT(31);
if (min_rate)
reg |= BIT(27);
if (max_rate)
reg |= BIT(11);
while (max_rate > 127) {
max_rate /= 10;
max_exp++;
}
while (min_rate > 127) {
min_rate /= 10;
min_exp++;
}
reg |= (min_rate & 0x7f) << 20;
reg |= (min_exp & 0xf) << 16;
reg |= (weight & 0xf) << 12;
reg |= (max_rate & 0x7f) << 4;
reg |= max_exp & 0xf;
mtk_w32(eth, reg, QTX_SCH(id));
resv &= 0xff;
reg = mtk_r32(eth, QTX_CFG(id));
reg &= 0xffff0000;
reg |= (resv << 8) | resv;
mtk_w32(eth, reg, QTX_CFG(id));
}
#endif
static int mtk_init_foe_table(struct mtk_eth *eth)
{
if (eth->foe_table)
return 0;
eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
sizeof(*eth->foe_flow_table),
GFP_KERNEL);
if (!eth->foe_flow_table)
return -EINVAL;
/* map the FOE table */
eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
&eth->foe_table_phys, GFP_KERNEL);
if (!eth->foe_table) {
dev_err(eth->dev, "failed to allocate foe table\n");
kfree(eth->foe_flow_table);
return -ENOMEM;
}
return 0;
}
static int mtk_ppe_start(struct mtk_eth *eth)
{
int ret;
ret = mtk_init_foe_table(eth);
if (ret)
return ret;
/* tell the PPE about the tables base address */
mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
/* flush the table */
memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
/* setup hashing */
mtk_m32(eth,
MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
MTK_REG_PPE_TB_CFG);
/* set the default hashing seed */
mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
/* each foe entry is 64bytes and is setup by cpu forwarding*/
mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
MTK_PPE_TB_CFG_SMA_MASK,
MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU,
MTK_REG_PPE_TB_CFG);
/* set ip proto */
mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
/* setup caching */
mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
MTK_REG_PPE_CAH_CTRL);
/* enable FOE */
mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
MTK_REG_PPE_FLOW_CFG);
/* setup flow entry un/bind aging */
mtk_m32(eth, 0,
MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
MTK_PPE_TB_CFG_TCP_AGE,
MTK_REG_PPE_TB_CFG);
mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
MTK_REG_PPE_UNB_AGE);
mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
MTK_REG_PPE_BND_AGE0);
mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
MTK_REG_PPE_BND_AGE1);
/* setup flow entry keep alive */
mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK, MTK_PPE_TB_CFG_KA,
MTK_REG_PPE_TB_CFG);
mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
/* setup flow entry rate limit */
mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
mtk_w32(eth, MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 1, MTK_REG_PPE_BNDR);
/* enable the PPE */
mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
#ifdef CONFIG_RALINK
/* set the default forwarding port to QDMA */
mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
#else
/* set the default forwarding port to QDMA */
mtk_w32(eth, 0x55555555, MTK_REG_PPE_DFT_CPORT);
#endif
/* drop packets with TTL=0 */
mtk_m32(eth, 0, MTK_PPE_GLO_CFG_TTL0_DROP, MTK_REG_PPE_GLO_CFG);
/* send all traffic from gmac to the ppe */
mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
dev_info(eth->dev, "PPE started\n");
#ifdef CONFIG_NET_MEDIATEK_HW_QOS
mtk_ppe_scheduler(eth, 0, 500000);
mtk_ppe_scheduler(eth, 1, 500000);
mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
#endif
return 0;
}
static int mtk_ppe_busy_wait(struct mtk_eth *eth)
{
unsigned long t_start = jiffies;
u32 r = 0;
while (1) {
r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
if (!(r & MTK_PPE_GLO_CFG_BUSY))
return 0;
if (time_after(jiffies, t_start + HZ))
break;
usleep_range(10, 20);
}
dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
reset_control_reset(eth->rst_ppe);
return -ETIMEDOUT;
}
static int mtk_ppe_stop(struct mtk_eth *eth)
{
u32 r1 = 0, r2 = 0;
int i;
/* discard all traffic while we disable the PPE */
mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
if (mtk_ppe_busy_wait(eth))
return -ETIMEDOUT;
/* invalidate all flow table entries */
for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
/* disable caching */
mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
MTK_REG_PPE_CAH_CTRL);
/* flush cache has to be ahead of hnat diable --*/
mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
/* disable FOE */
mtk_m32(eth,
MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
0, MTK_REG_PPE_FLOW_CFG);
/* disable FOE aging */
mtk_m32(eth, 0,
MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
r1 = mtk_r32(eth, 0x100);
r2 = mtk_r32(eth, 0x10c);
dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
dev_info(eth->dev, "reset pse\n");
mtk_w32(eth, 0x1, 0x4);
}
/* set the foe entry base address to 0 */
mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
if (mtk_ppe_busy_wait(eth))
return -ETIMEDOUT;
/* send all traffic back to the DMA engine */
#ifdef CONFIG_RALINK
mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
#else
mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(0));
mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(1));
#endif
return 0;
}
static void mtk_offload_keepalive(struct fe_priv *eth, unsigned int hash)
{
struct flow_offload *flow;
rcu_read_lock();
flow = rcu_dereference(eth->foe_flow_table[hash]);
if (flow)
flow->timeout = jiffies + 30 * HZ;
rcu_read_unlock();
}
int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4)
{
unsigned int hash;
switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
mtk_offload_keepalive(eth, hash);
return -1;
case MTK_CPU_REASON_PACKET_SAMPLING:
return -1;
default:
return 0;
}
}
int mtk_ppe_probe(struct mtk_eth *eth)
{
int err;
err = mtk_ppe_start(eth);
if (err)
return err;
err = mtk_ppe_debugfs_init(eth);
if (err)
return err;
return 0;
}
void mtk_ppe_remove(struct mtk_eth *eth)
{
mtk_ppe_stop(eth);
}

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
* Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
*/
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/if.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/netfilter.h>
#include <linux/netdevice.h>
#include <net/netfilter/nf_flow_table.h>
#include <linux/debugfs.h>
#include <linux/etherdevice.h>
#include <linux/bitfield.h>
#include "mtk_eth_soc.h"
#ifdef CONFIG_RALINK
/* ramips compat */
#define mtk_eth fe_priv
#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
#define mtk_m32 fe_m32
static inline u32
mtk_r32(struct mtk_eth *eth, u32 reg)
{
return fe_r32(reg);
}
static inline void
mtk_w32(struct mtk_eth *eth, u32 val, u32 reg)
{
fe_w32(val, reg);
}
#endif
#define MTK_REG_PPE_GLO_CFG 0xe00
#define MTK_PPE_GLO_CFG_BUSY BIT(31)
#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
#define MTK_PPE_GLO_CFG_EN BIT(0)
#define MTK_REG_PPE_FLOW_CFG 0xe04
#define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19)
#define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17)
#define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13)
#define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12)
#define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2)
#define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1)
#define MTK_REG_PPE_IP_PROT_CHK 0xe08
#define MTK_REG_PPE_TB_BASE 0xe20
#define MTK_REG_PPE_BNDR 0xe28
#define MTK_PPE_BNDR_RATE_MASK 0xffff
#define MTK_REG_PPE_BIND_LMT_0 0xe2C
#define MTK_REG_PPE_BIND_LMT_1 0xe30
#define MTK_PPE_NTU_KA BIT(16)
#define MTK_REG_PPE_KA 0xe34
#define MTK_PPE_KA_T BIT(0)
#define MTK_PPE_KA_TCP BIT(16)
#define MTK_PPE_KA_UDP BIT(24)
#define MTK_REG_PPE_UNB_AGE 0xe38
#define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16)
#define MTK_PPE_UNB_AGE_MNP (1000 << 16)
#define MTK_PPE_UNB_AGE_DLTA_MASK 0xff
#define MTK_PPE_UNB_AGE_DLTA 3
#define MTK_REG_PPE_BND_AGE0 0xe3c
#define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16)
#define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16)
#define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff
#define MTK_PPE_BND_AGE0_UDP_DLTA 5
#define MTK_REG_PPE_BND_AGE1 0xe40
#define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16)
#define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16)
#define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff
#define MTK_PPE_BND_AGE1_TCP_DLTA 5
#define MTK_REG_PPE_DFT_CPORT 0xe48
#define MTK_REG_PPE_TB_CFG 0xe1c
#define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18)
#define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14)
#define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14)
#define MTK_PPE_TB_CFG_KA (3 << 12)
#define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12)
#define MTK_PPE_TB_CFG_FIN_AGE BIT(11)
#define MTK_PPE_TB_CFG_UDP_AGE BIT(10)
#define MTK_PPE_TB_CFG_TCP_AGE BIT(9)
#define MTK_PPE_TB_CFG_UNBD_AGE BIT(8)
#define MTK_PPE_TB_CFG_NTU_AGE BIT(7)
#define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4)
#define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4)
#define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0
#define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3)
#define MTK_PPE_TB_CFG_TBL_SZ_4K 2
#define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7
#define MTK_REG_PPE_HASH_SEED 0xe44
#define MTK_PPE_HASH_SEED 0x12345678
#define MTK_REG_PPE_CAH_CTRL 0xf20
#define MTK_PPE_CAH_CTRL_X_MODE BIT(9)
#define MTK_PPE_CAH_CTRL_EN BIT(0)
struct mtk_foe_unbind_info_blk {
u32 time_stamp:8;
u32 pcnt:16; /* packet count */
u32 preb:1;
u32 pkt_type:3;
u32 state:2;
u32 udp:1;
u32 sta:1; /* static entry */
} __attribute__ ((packed));
struct mtk_foe_bind_info_blk {
u32 time_stamp:15;
u32 ka:1; /* keep alive */
u32 vlan_layer:3;
u32 psn:1; /* egress packet has PPPoE session */
#ifdef CONFIG_RALINK
u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */
#else
u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */
u32 ps:1; /* packet sampling */
#endif
u32 cah:1; /* cacheable flag */
u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */
u32 ttl:1;
u32 pkt_type:3;
u32 state:2;
u32 udp:1;
u32 sta:1; /* static entry */
} __attribute__ ((packed));
struct mtk_foe_info_blk2 {
u32 qid:4; /* QID in Qos Port */
u32 fqos:1; /* force to PSE QoS port */
u32 dp:3; /* force to PSE port x
0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */
u32 mcast:1; /* multicast this packet to CPU */
u32 pcpl:1; /* OSBN */
u32 mlen:1; /* 0:post 1:pre packet length in meter */
u32 alen:1; /* 0:post 1:pre packet length in accounting */
u32 port_mg:6; /* port meter group */
u32 port_ag:6; /* port account group */
u32 dscp:8; /* DSCP value */
} __attribute__ ((packed));
struct mtk_foe_ipv4_hnapt {
union {
struct mtk_foe_bind_info_blk bfib1;
struct mtk_foe_unbind_info_blk udib1;
u32 info_blk1;
};
u32 sip;
u32 dip;
u16 dport;
u16 sport;
union {
struct mtk_foe_info_blk2 iblk2;
u32 info_blk2;
};
u32 new_sip;
u32 new_dip;
u16 new_dport;
u16 new_sport;
u32 resv1;
u32 resv2;
u32 resv3:26;
u32 act_dp:6; /* UDF */
u16 vlan1;
u16 etype;
u32 dmac_hi;
u16 vlan2;
u16 dmac_lo;
u32 smac_hi;
u16 pppoe_id;
u16 smac_lo;
} __attribute__ ((packed));
struct mtk_foe_entry {
union {
struct mtk_foe_unbind_info_blk udib1;
struct mtk_foe_bind_info_blk bfib1;
struct mtk_foe_ipv4_hnapt ipv4_hnapt;
};
};
enum mtk_foe_entry_state {
FOE_STATE_INVALID = 0,
FOE_STATE_UNBIND = 1,
FOE_STATE_BIND = 2,
FOE_STATE_FIN = 3
};
#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
#define MTK_RXD4_CPU_REASON GENMASK(18, 14)
#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
#define MTK_RXD4_ALG GENMASK(31, 22)
enum mtk_foe_cpu_reason {
MTK_CPU_REASON_TTL_EXCEEDED = 0x02,
MTK_CPU_REASON_OPTION_HEADER = 0x03,
MTK_CPU_REASON_NO_FLOW = 0x07,
MTK_CPU_REASON_IPV4_FRAG = 0x08,
MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
MTK_CPU_REASON_UN_HIT = 0x0d,
MTK_CPU_REASON_HIT_UNBIND = 0x0e,
MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
MTK_CPU_REASON_HIT_TTL_1 = 0x11,
MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18,
MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
MTK_CPU_REASON_HIT_PRE_BIND = 0x1a,
MTK_CPU_REASON_PACKET_SAMPLING = 0x1b,
MTK_CPU_REASON_EXCEED_MTU = 0x1c,
MTK_CPU_REASON_PPE_BYPASS = 0x1e,
MTK_CPU_REASON_INVALID = 0x1f,
};
/* our table size is 4K */
#define MTK_PPE_ENTRY_CNT 0x1000
#define MTK_PPE_TBL_SZ \
(MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry))
int mtk_ppe_debugfs_init(struct mtk_eth *eth);

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/if_vlan.h>
#include <linux/of_net.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <mt7620.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
#include "mt7530.h"
#include "mdio.h"
#define MT7620A_CDMA_CSG_CFG 0x400
#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
#define MT7620A_RESET_FE BIT(21)
#define MT7621_RESET_FE BIT(6)
#define MT7620A_RESET_ESW BIT(23)
#define MT7620_L4_VALID BIT(23)
#define MT7621_L4_VALID BIT(24)
#define MT7620_TX_DMA_UDF BIT(15)
#define MT7621_TX_DMA_UDF BIT(19)
#define TX_DMA_FP_BMAP ((0xff) << 19)
#define CDMA_ICS_EN BIT(2)
#define CDMA_UCS_EN BIT(1)
#define CDMA_TCS_EN BIT(0)
#define GDMA_ICS_EN BIT(22)
#define GDMA_TCS_EN BIT(21)
#define GDMA_UCS_EN BIT(20)
/* frame engine counters */
#define MT7620_REG_MIB_OFFSET 0x1000
#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
#define MT7621_REG_MIB_OFFSET 0x2000
#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
#define GSW_REG_GDMA1_MAC_ADRL 0x508
#define GSW_REG_GDMA1_MAC_ADRH 0x50C
#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
* but after test it should be BIT(13).
*/
#define MT7620_FE_GDM1_AF BIT(13)
#define MT7621_FE_GDM1_AF BIT(28)
#define MT7621_FE_GDM2_AF BIT(29)
static const u16 mt7620_reg_table[FE_REG_COUNT] = {
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
[FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
};
static int mt7620_gsw_config(struct fe_priv *priv)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
/* is the mt7530 internal or external */
if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
mt7530_probe(priv->dev, gsw->base, NULL, 0);
mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
} else {
mt7530_probe(priv->dev, gsw->base, NULL, 1);
}
return 0;
}
static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
unsigned long flags;
spin_lock_irqsave(&priv->page_lock, flags);
mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
GSW_REG_SMACCR0);
spin_unlock_irqrestore(&priv->page_lock, flags);
}
static void mt7620_auto_poll(struct mt7620_gsw *gsw)
{
int phy;
int lsb = -1, msb = 0;
for_each_set_bit(phy, &gsw->autopoll, 32) {
if (lsb < 0)
lsb = phy;
msb = phy;
}
if (lsb == msb)
lsb--;
mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
(msb << 8) | lsb, ESW_PHY_POLLING);
}
static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
{
struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
const __be32 *_id = of_get_property(np, "reg", NULL);
int phy_mode, size, id;
int shift = 12;
u32 val, mask = 0;
int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
if (_id)
pr_err("%s: invalid port id %d\n", np->name,
be32_to_cpu(*_id));
else
pr_err("%s: invalid port id\n", np->name);
return;
}
id = be32_to_cpu(*_id);
if (id == 4)
shift = 14;
priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
&size);
if (priv->phy->phy_fixed[id] &&
(size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
pr_err("%s: invalid fixed link property\n", np->name);
priv->phy->phy_fixed[id] = NULL;
return;
}
phy_mode = of_get_phy_mode(np);
switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
mask = 0;
break;
case PHY_INTERFACE_MODE_MII:
mask = 1;
break;
case PHY_INTERFACE_MODE_RMII:
mask = 2;
break;
default:
dev_err(priv->dev, "port %d - invalid phy mode\n", id);
return;
}
priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
return;
val = rt_sysc_r32(SYSC_REG_CFG1);
val &= ~(3 << shift);
val |= mask << shift;
rt_sysc_w32(val, SYSC_REG_CFG1);
if (priv->phy->phy_fixed[id]) {
const __be32 *link = priv->phy->phy_fixed[id];
int tx_fc, rx_fc;
u32 val = 0;
priv->phy->speed[id] = be32_to_cpup(link++);
tx_fc = be32_to_cpup(link++);
rx_fc = be32_to_cpup(link++);
priv->phy->duplex[id] = be32_to_cpup(link++);
priv->link[id] = 1;
switch (priv->phy->speed[id]) {
case SPEED_10:
val = 0;
break;
case SPEED_100:
val = 1;
break;
case SPEED_1000:
val = 2;
break;
default:
dev_err(priv->dev, "invalid link speed: %d\n",
priv->phy->speed[id]);
priv->phy->phy_fixed[id] = 0;
return;
}
val = PMCR_SPEED(val);
val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
if (tx_fc)
val |= PMCR_TX_FC;
if (rx_fc)
val |= PMCR_RX_FC;
if (priv->phy->duplex[id])
val |= PMCR_DUPLEX;
mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
dev_info(priv->dev, "using fixed link parameters\n");
return;
}
if (priv->phy->phy_node[id] && mdiobus_get_phy(priv->mii_bus, id)) {
u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
fe_connect_phy_node(priv, priv->phy->phy_node[id]);
gsw->autopoll |= BIT(id);
mt7620_auto_poll(gsw);
return;
}
}
static void mt7620_fe_reset(void)
{
fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
}
static void mt7620_rxcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
GDMA_TCS_EN | GDMA_UCS_EN),
MT7620A_GDMA1_FWD_CFG);
else
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
GDMA_TCS_EN | GDMA_UCS_EN),
MT7620A_GDMA1_FWD_CFG);
}
static void mt7620_txcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
CDMA_UCS_EN | CDMA_TCS_EN),
MT7620A_CDMA_CSG_CFG);
else
fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
CDMA_UCS_EN | CDMA_TCS_EN),
MT7620A_CDMA_CSG_CFG);
}
static int mt7620_fwd_config(struct fe_priv *priv)
{
struct net_device *dev = priv_netdev(priv);
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
return 0;
}
static void mt7620_tx_dma(struct fe_tx_dma *txd)
{
}
static void mt7620_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
NETIF_F_HW_VLAN_CTAG_TX;
if (mt7620_get_eco() >= 5)
netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
NETIF_F_IPV6_CSUM;
}
static struct fe_soc_data mt7620_data = {
.init_data = mt7620_init_data,
.reset_fe = mt7620_fe_reset,
.set_mac = mt7620_set_mac,
.fwd_config = mt7620_fwd_config,
.tx_dma = mt7620_tx_dma,
.switch_init = mtk_gsw_init,
.switch_config = mt7620_gsw_config,
.port_init = mt7620_port_init,
.reg_table = mt7620_reg_table,
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
.status_int = MT7620_FE_GDM1_AF,
.checksum_bit = MT7620_L4_VALID,
.has_carrier = mt7620_has_carrier,
.mdio_read = mt7620_mdio_read,
.mdio_write = mt7620_mdio_write,
.mdio_adjust_link = mt7620_mdio_link_adjust,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

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/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/if_vlan.h>
#include <linux/of_net.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "gsw_mt7620.h"
#include "mt7530.h"
#include "mdio.h"
#define MT7620A_CDMA_CSG_CFG 0x400
#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
#define MT7621_RESET_FE BIT(6)
#define MT7621_L4_VALID BIT(24)
#define MT7621_TX_DMA_UDF BIT(19)
#define MT7621_TX_DMA_FPORT BIT(25)
#define CDMA_ICS_EN BIT(2)
#define CDMA_UCS_EN BIT(1)
#define CDMA_TCS_EN BIT(0)
#define GDMA_ICS_EN BIT(22)
#define GDMA_TCS_EN BIT(21)
#define GDMA_UCS_EN BIT(20)
/* frame engine counters */
#define MT7621_REG_MIB_OFFSET 0x2000
#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
#define GSW_REG_GDMA1_MAC_ADRL 0x508
#define GSW_REG_GDMA1_MAC_ADRH 0x50C
#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
* but after test it should be BIT(13).
*/
#define MT7620_FE_GDM1_AF BIT(13)
#define MT7621_FE_GDM1_AF BIT(28)
#define MT7621_FE_GDM2_AF BIT(29)
static const u16 mt7621_reg_table[FE_REG_COUNT] = {
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_DMA_VID_BASE] = 0,
[FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
};
static int mt7621_gsw_config(struct fe_priv *priv)
{
if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f))
mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
return 0;
}
static void mt7621_fe_reset(void)
{
fe_reset(MT7621_RESET_FE);
}
static void mt7621_rxcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
GDMA_TCS_EN | GDMA_UCS_EN),
MT7620A_GDMA1_FWD_CFG);
else
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
GDMA_TCS_EN | GDMA_UCS_EN),
MT7620A_GDMA1_FWD_CFG);
}
static void mt7621_rxvlan_config(bool enable)
{
if (enable)
fe_w32(1, MT7621_CDMP_EG_CTRL);
else
fe_w32(0, MT7621_CDMP_EG_CTRL);
}
static int mt7621_fwd_config(struct fe_priv *priv)
{
struct net_device *dev = priv_netdev(priv);
fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff,
MT7620A_GDMA1_FWD_CFG);
/* mt7621 doesn't have txcsum config */
mt7621_rxcsum_config((dev->features & NETIF_F_RXCSUM));
mt7621_rxvlan_config(priv->flags & FE_FLAG_RX_VLAN_CTAG);
return 0;
}
static void mt7621_tx_dma(struct fe_tx_dma *txd)
{
txd->txd4 = MT7621_TX_DMA_FPORT;
}
static void mt7621_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT |
FE_FLAG_HAS_SWITCH | FE_FLAG_JUMBO_FRAME;
netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
NETIF_F_TSO6 | NETIF_F_IPV6_CSUM |
NETIF_F_TSO_MANGLEID;
}
static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
{
unsigned long flags;
spin_lock_irqsave(&priv->page_lock, flags);
fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
GSW_REG_GDMA1_MAC_ADRL);
spin_unlock_irqrestore(&priv->page_lock, flags);
}
static struct fe_soc_data mt7621_data = {
.init_data = mt7621_init_data,
.reset_fe = mt7621_fe_reset,
.set_mac = mt7621_set_mac,
.fwd_config = mt7621_fwd_config,
.tx_dma = mt7621_tx_dma,
.switch_init = mtk_gsw_init,
.switch_config = mt7621_gsw_config,
.reg_table = mt7621_reg_table,
.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
.status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
.checksum_bit = MT7621_L4_VALID,
.has_carrier = mt7620_has_carrier,
.mdio_read = mt7620_mdio_read,
.mdio_write = mt7620_mdio_write,
.mdio_adjust_link = mt7620_mdio_link_adjust,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

76
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/soc_rt2880.c Normal file
View File

@ -0,0 +1,76 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
#define RT2880_RESET_FE BIT(18)
static void rt2880_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
/* this should work according to the datasheet but actually does not*/
/* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
}
void rt2880_fe_reset(void)
{
fe_reset(RT2880_RESET_FE);
}
static int rt2880_fwd_config(struct fe_priv *priv)
{
int ret;
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
fe_fwd_config(priv);
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return ret;
}
struct fe_soc_data rt2880_data = {
.init_data = rt2880_init_data,
.reset_fe = rt2880_fe_reset,
.fwd_config = rt2880_fwd_config,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.status_int = FE_CNT_GDM_AF,
.mdio_read = rt2880_mdio_read,
.mdio_write = rt2880_mdio_write,
.mdio_adjust_link = rt2880_mdio_link_adjust,
.port_init = rt2880_port_init,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

158
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/soc_rt3050.c Normal file
View File

@ -0,0 +1,158 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
#define RT305X_RESET_FE BIT(21)
#define RT305X_RESET_ESW BIT(23)
static const u16 rt5350_reg_table[FE_REG_COUNT] = {
[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
[FE_REG_FE_RST_GL] = 0,
[FE_REG_FE_DMA_VID_BASE] = 0,
};
static void rt305x_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
FE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH;
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
}
static int rt3050_fwd_config(struct fe_priv *priv)
{
int ret;
if (ralink_soc != RT305X_SOC_RT3052) {
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
}
fe_fwd_config(priv);
if (ralink_soc != RT305X_SOC_RT3352)
fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return 0;
}
static void rt305x_fe_reset(void)
{
fe_reset(RT305X_RESET_FE);
}
static void rt5350_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_HAS_SWITCH;
netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
}
static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
{
unsigned long flags;
spin_lock_irqsave(&priv->page_lock, flags);
fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
RT5350_SDM_MAC_ADRL);
spin_unlock_irqrestore(&priv->page_lock, flags);
}
static void rt5350_rxcsum_config(bool enable)
{
if (enable)
fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
RT5350_SDM_CFG);
else
fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
RT5350_SDM_CFG);
}
static int rt5350_fwd_config(struct fe_priv *priv)
{
struct net_device *dev = priv_netdev(priv);
rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
return 0;
}
static void rt5350_tx_dma(struct fe_tx_dma *txd)
{
txd->txd4 = 0;
}
static void rt5350_fe_reset(void)
{
fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW);
}
static struct fe_soc_data rt3050_data = {
.init_data = rt305x_init_data,
.reset_fe = rt305x_fe_reset,
.fwd_config = rt3050_fwd_config,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.status_int = FE_CNT_GDM_AF,
};
static struct fe_soc_data rt5350_data = {
.init_data = rt5350_init_data,
.reg_table = rt5350_reg_table,
.reset_fe = rt5350_fe_reset,
.set_mac = rt5350_set_mac,
.fwd_config = rt5350_fwd_config,
.tx_dma = rt5350_tx_dma,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.checksum_bit = RX_DMA_L4VALID,
.rx_int = RT5350_RX_DONE_INT,
.tx_int = RT5350_TX_DONE_INT,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

75
target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/soc_rt3883.c Normal file
View File

@ -0,0 +1,75 @@
/* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
* Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
* Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
*/
#include <linux/module.h>
#include <asm/mach-ralink/ralink_regs.h>
#include "mtk_eth_soc.h"
#include "mdio_rt2880.h"
#define RT3883_RSTCTRL_FE BIT(21)
static void rt3883_fe_reset(void)
{
fe_reset(RT3883_RSTCTRL_FE);
}
static int rt3883_fwd_config(struct fe_priv *priv)
{
int ret;
ret = fe_set_clock_cycle(priv);
if (ret)
return ret;
fe_fwd_config(priv);
fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
fe_csum_config(priv);
return ret;
}
static void rt3883_init_data(struct fe_soc_data *data,
struct net_device *netdev)
{
struct fe_priv *priv = netdev_priv(netdev);
priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
}
static struct fe_soc_data rt3883_data = {
.init_data = rt3883_init_data,
.reset_fe = rt3883_fe_reset,
.fwd_config = rt3883_fwd_config,
.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
.rx_int = FE_RX_DONE_INT,
.tx_int = FE_TX_DONE_INT,
.status_int = FE_CNT_GDM_AF,
.checksum_bit = RX_DMA_L4VALID,
.mdio_read = rt2880_mdio_read,
.mdio_write = rt2880_mdio_write,
.mdio_adjust_link = rt2880_mdio_link_adjust,
.port_init = rt2880_port_init,
};
const struct of_device_id of_fe_match[] = {
{ .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
{},
};
MODULE_DEVICE_TABLE(of, of_fe_match);

8
target/linux/ramips/image/mt7620.mk
View File

@ -427,22 +427,22 @@ TARGET_DEVICES += oy-0001
define Device/psg1208
DTS := PSG1208
DEVICE_TITLE := Phicomm PSG1208 (K1)
DEVICE_TITLE := Phicomm PSG1208
DEVICE_PACKAGES := kmod-mt76
endef
TARGET_DEVICES += psg1208
define Device/psg1218a
DTS := PSG1218A
DEVICE_TITLE := Phicomm PSG1218 (K2)
DEVICE_PACKAGES := -luci-app-ipsec-vpnd kmod-mt76x2 luci-app-zerotier
DEVICE_TITLE := Phicomm PSG1218 rev.Ax
DEVICE_PACKAGES := kmod-mt76x2
SUPPORTED_DEVICES += psg1218
endef
TARGET_DEVICES += psg1218a
define Device/psg1218b
DTS := PSG1218B
DEVICE_TITLE := Phicomm PSG1218 (K2C)
DEVICE_TITLE := Phicomm PSG1218 rev.Bx
DEVICE_PACKAGES := kmod-mt76x2
SUPPORTED_DEVICES += psg1218
endef

2
target/linux/ramips/image/mt7621.mk
View File

@ -338,7 +338,7 @@ TARGET_DEVICES += re350-v1
define Device/re6500
DTS := RE6500
DEVICE_TITLE := Linksys RE6500
DEVICE_PACKAGES := -luci-app-ipsec-vpnd kmod-mt76x2 wpad-basic
DEVICE_PACKAGES := kmod-mt76x2 wpad-basic
endef
TARGET_DEVICES += re6500

2
target/linux/ramips/image/rt305x.mk
View File

@ -652,7 +652,7 @@ TARGET_DEVICES += rt-n10-plus
define Device/rt-n13u
DTS := RT-N13U
DEVICE_TITLE := Asus RT-N13U
DEVICE_PACKAGES := kmod-leds-gpio kmod-rt2800-pci wpad-mini kmod-usb-dwc2
DEVICE_PACKAGES := kmod-leds-gpio kmod-rt2800-pci kmod-usb-dwc2
endef
TARGET_DEVICES += rt-n13u

1
target/linux/ramips/mt7620/config-4.14
View File

@ -233,4 +233,3 @@ CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
CONFIG_MIPS_FPU_EMULATOR=y

1
target/linux/ramips/mt76x8/config-4.14
View File

@ -228,4 +228,3 @@ CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
CONFIG_MIPS_FPU_EMULATOR=y

2
target/linux/ramips/mt76x8/target.mk
View File

@ -7,7 +7,7 @@ BOARDNAME:=MT76x8 based boards
FEATURES+=usb
CPU_TYPE:=24kc
DEFAULT_PACKAGES += kmod-mt76 wpad-mini
DEFAULT_PACKAGES += kmod-mt76 wpad-basic
define Target/Description
Build firmware images for Ralink MT76x8 based boards.

12
target/linux/ramips/patches-4.14/0053-mtd-spi-nor-add-w25q256-3b-mode-switch.patch
View File

@ -116,7 +116,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
return ret;
@@ -1165,7 +1217,7 @@ static const struct flash_info spi_nor_i
@@ -1170,7 +1222,7 @@ static const struct flash_info spi_nor_i
{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
@ -125,7 +125,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
@@ -1225,6 +1277,9 @@ static int spi_nor_read(struct mtd_info
@@ -1230,6 +1282,9 @@ static int spi_nor_read(struct mtd_info
if (ret)
return ret;
@ -135,7 +135,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
while (len) {
loff_t addr = from;
@@ -1249,6 +1304,18 @@ static int spi_nor_read(struct mtd_info
@@ -1254,6 +1309,18 @@ static int spi_nor_read(struct mtd_info
ret = 0;
read_err:
@ -154,7 +154,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
return ret;
}
@@ -1350,6 +1417,10 @@ static int spi_nor_write(struct mtd_info
@@ -1355,6 +1422,10 @@ static int spi_nor_write(struct mtd_info
if (ret)
return ret;
@ -165,7 +165,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
@@ -1390,6 +1461,7 @@ static int spi_nor_write(struct mtd_info
@@ -1395,6 +1466,7 @@ static int spi_nor_write(struct mtd_info
}
write_err:
@ -173,7 +173,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
return ret;
}
@@ -2806,8 +2878,10 @@ int spi_nor_scan(struct spi_nor *nor, co
@@ -2811,8 +2883,10 @@ int spi_nor_scan(struct spi_nor *nor, co
} else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;

2
target/linux/ramips/patches-4.14/0054-mtd-spi-nor-w25q256-respect-default-mode.patch
View File

@ -33,7 +33,7 @@
/*
* Write status register 1 byte
* Returns negative if error occurred.
@@ -2878,9 +2887,16 @@ int spi_nor_scan(struct spi_nor *nor, co
@@ -2883,9 +2892,16 @@ int spi_nor_scan(struct spi_nor *nor, co
} else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;

1
target/linux/ramips/rt288x/config-4.14
View File

@ -220,4 +220,3 @@ CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
CONFIG_MIPS_FPU_EMULATOR=y

1
target/linux/ramips/rt305x/config-4.14
View File

@ -197,4 +197,3 @@ CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
CONFIG_MIPS_FPU_EMULATOR=y

1
target/linux/ramips/rt3883/config-4.14
View File

@ -223,4 +223,3 @@ CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
CONFIG_MIPS_FPU_EMULATOR=y