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kernel: 5.10: refresh all patches (#10005)

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target/linux/ipq807x/patches-5.10/147-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/clk/qcom/gcc-ipq8074.c?h=v5.10.138&id=6b90ab952401bd6c1a321dcfc0e0df080f2bc905

Signed-off-by: José Hwong <josehwong@hotmail.com>
This commit is contained in:
benihi 2022-08-26 09:11:29 -04:00 committed by GitHub
parent 3e87e5f41d
commit 6670876f72
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GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 16 additions and 48 deletions
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5
target/linux/generic/hack-5.10/952-net-conntrack-events-support-multiple-registrant.patch
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@ -274,7 +274,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
int nf_ct_expect_register_notifier(struct net *net, int nf_ct_expect_register_notifier(struct net *net,
--- a/net/netfilter/nf_conntrack_netlink.c --- a/net/netfilter/nf_conntrack_netlink.c
+++ b/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c
@@ -706,13 +706,20 @@ static size_t ctnetlink_nlmsg_size(const @@ -701,12 +701,19 @@ static size_t ctnetlink_nlmsg_size(const
} }
static int static int
@ -287,7 +287,6 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
const struct nf_conntrack_zone *zone; const struct nf_conntrack_zone *zone;
struct net *net; struct net *net;
struct nlmsghdr *nlh; struct nlmsghdr *nlh;
struct nfgenmsg *nfmsg;
struct nlattr *nest_parms; struct nlattr *nest_parms;
+#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS +#ifdef CONFIG_NF_CONNTRACK_CHAIN_EVENTS
+ struct nf_ct_event *item = (struct nf_ct_event *)ptr; + struct nf_ct_event *item = (struct nf_ct_event *)ptr;
@ -295,7 +294,7 @@ Signed-off-by: Zhi Chen <zhichen@codeaurora.org>
struct nf_conn *ct = item->ct; struct nf_conn *ct = item->ct;
struct sk_buff *skb; struct sk_buff *skb;
unsigned int type; unsigned int type;
@@ -3787,9 +3794,15 @@ static int ctnetlink_stat_exp_cpu(struct @@ -3752,9 +3759,15 @@ static int ctnetlink_stat_exp_cpu(struct
} }
#ifdef CONFIG_NF_CONNTRACK_EVENTS #ifdef CONFIG_NF_CONNTRACK_EVENTS

2
target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch
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@ -15,7 +15,7 @@ Acked-by: Stephen Boyd <sboyd@kernel.org>
--- a/drivers/clk/qcom/gcc-ipq8074.c --- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4789,6 +4789,7 @@ static const struct qcom_reset_map gcc_i @@ -4790,6 +4790,7 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },

4
target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch
View File

@ -34,7 +34,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
}; };
--- a/drivers/clk/qcom/gcc-ipq8074.c --- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref @@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref
}, },
}; };
@ -59,7 +59,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
static struct clk_branch gcc_nssnoc_ce_apb_clk = { static struct clk_branch gcc_nssnoc_ce_apb_clk = {
.halt_reg = 0x6830c, .halt_reg = 0x6830c,
.clkr = { .clkr = {
@@ -4607,6 +4625,7 @@ static struct clk_regmap *gcc_ipq8074_cl @@ -4608,6 +4626,7 @@ static struct clk_regmap *gcc_ipq8074_cl
[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,

14
target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch
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@ -37,7 +37,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
static struct clk_alpha_pll gpll0_main = { static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000, .offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
@@ -962,6 +978,12 @@ static const struct freq_tbl ftbl_pcie_a @@ -963,6 +979,12 @@ static const struct freq_tbl ftbl_pcie_a
{ } { }
}; };
@ -50,7 +50,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
static struct clk_rcg2 pcie0_axi_clk_src = { static struct clk_rcg2 pcie0_axi_clk_src = {
.cmd_rcgr = 0x75054, .cmd_rcgr = 0x75054,
.freq_tbl = ftbl_pcie_axi_clk_src, .freq_tbl = ftbl_pcie_axi_clk_src,
@@ -2021,6 +2043,78 @@ static struct clk_rcg2 gp3_clk_src = { @@ -2022,6 +2044,78 @@ static struct clk_rcg2 gp3_clk_src = {
}, },
}; };
@ -129,7 +129,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
static struct clk_branch gcc_blsp1_ahb_clk = { static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008, .halt_reg = 0x01008,
.clkr = { .clkr = {
@@ -4352,13 +4446,7 @@ static struct clk_branch gcc_gp3_clk = { @@ -4353,13 +4447,7 @@ static struct clk_branch gcc_gp3_clk = {
}, },
}; };
@ -144,7 +144,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
.cmd_rcgr = 0x75070, .cmd_rcgr = 0x75070,
.freq_tbl = ftbl_pcie_rchng_clk_src, .freq_tbl = ftbl_pcie_rchng_clk_src,
.hid_width = 5, .hid_width = 5,
@@ -4434,6 +4522,114 @@ static struct clk_branch gcc_pcie0_axi_s @@ -4435,6 +4523,114 @@ static struct clk_branch gcc_pcie0_axi_s
.alpha_en_mask = BIT(24), .alpha_en_mask = BIT(24),
}; };
@ -259,7 +259,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
static struct clk_hw *gcc_ipq8074_hws[] = { static struct clk_hw *gcc_ipq8074_hws[] = {
&gpll0_out_main_div2.hw, &gpll0_out_main_div2.hw,
&gpll6_out_main_div2.hw, &gpll6_out_main_div2.hw,
@@ -4442,6 +4638,7 @@ static struct clk_hw *gcc_ipq8074_hws[] @@ -4443,6 +4639,7 @@ static struct clk_hw *gcc_ipq8074_hws[]
&gcc_xo_div4_clk_src.hw, &gcc_xo_div4_clk_src.hw,
&nss_noc_clk_src.hw, &nss_noc_clk_src.hw,
&nss_ppe_cdiv_clk_src.hw, &nss_ppe_cdiv_clk_src.hw,
@ -267,7 +267,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
}; };
static struct clk_regmap *gcc_ipq8074_clks[] = { static struct clk_regmap *gcc_ipq8074_clks[] = {
@@ -4673,6 +4870,15 @@ static struct clk_regmap *gcc_ipq8074_cl @@ -4674,6 +4871,15 @@ static struct clk_regmap *gcc_ipq8074_cl
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
@ -283,7 +283,7 @@ Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
}; };
static const struct qcom_reset_map gcc_ipq8074_resets[] = { static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -4809,6 +5015,20 @@ static const struct qcom_reset_map gcc_i @@ -4810,6 +5016,20 @@ static const struct qcom_reset_map gcc_i
[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
[GCC_WCSSAON_RESET] = { 0x59010, 0 }, [GCC_WCSSAON_RESET] = { 0x59010, 0 },

4
target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch
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@ -16,7 +16,7 @@ Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
--- a/drivers/clk/qcom/gcc-ipq8074.c --- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4523,10 +4523,10 @@ static struct clk_branch gcc_pcie0_axi_s @@ -4524,10 +4524,10 @@ static struct clk_branch gcc_pcie0_axi_s
}; };
static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
@ -29,7 +29,7 @@ Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_snoc_bus_timeout2_ahb_clk", .name = "gcc_snoc_bus_timeout2_ahb_clk",
@@ -4541,10 +4541,10 @@ static struct clk_branch gcc_snoc_bus_ti @@ -4542,10 +4542,10 @@ static struct clk_branch gcc_snoc_bus_ti
}; };
static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = {

2
target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch
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@ -15,7 +15,7 @@ Change-Id: I17beca334be79d738a35587860847aa0b1f96fa9
--- a/drivers/clk/qcom/gcc-ipq8074.c --- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -5066,6 +5066,11 @@ static int gcc_ipq8074_probe(struct plat @@ -5067,6 +5067,11 @@ static int gcc_ipq8074_probe(struct plat
/* SW Workaround for UBI32 Huayra PLL */ /* SW Workaround for UBI32 Huayra PLL */
regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));

2
target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch
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@ -34,7 +34,7 @@ Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
--- a/drivers/clk/qcom/gcc-ipq8074.c --- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -5071,6 +5071,9 @@ static int gcc_ipq8074_probe(struct plat @@ -5072,6 +5072,9 @@ static int gcc_ipq8074_probe(struct plat
/* Disable SW_COLLAPSE for USB1 GDSCR */ /* Disable SW_COLLAPSE for USB1 GDSCR */
regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0);

31
target/linux/ipq807x/patches-5.10/147-clk-ipq8074-defer-from-disabling-gcc_sleep_clk_src.patch
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@ -1,31 +0,0 @@
From db9c60394765843f6a77833bc40c27fac8852e97 Mon Sep 17 00:00:00 2001
From: Balaji Prakash J <bjagadee@codeaurora.org>
Date: Mon, 20 Apr 2020 20:07:51 +0530
Subject: [PATCH] clk: ipq8074: defer from disabling gcc_sleep_clk_src
Added CLK_IS_CRITICAL flag in order to defer from
disabling the sleep clock source.
Once the usb sleep clocks are disabled, clock framework
is trying to disable the sleep clock source also and
the below warning is observed.
[ 28.235750] gcc_sleep_clk_src status stuck at 'on'
[ 28.235794] WARNING: CPU: 0 PID: 29 at drivers/clk/qcom/clk-branch.c:92 clk_branch_toggle+0x160/0x178
Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
Change-Id: I61fab902375716272ad9c426ce71581058f7bd35
---
drivers/clk/qcom/gcc-ipq8074.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -678,6 +678,7 @@ static struct clk_branch gcc_sleep_clk_s
},
.num_parents = 1,
.ops = &clk_branch2_ops,
+ .flags = CLK_IS_CRITICAL,
},
},
};