From 6586685561e587449671d36cc290891498a400e9 Mon Sep 17 00:00:00 2001 From: Lollipop907 <34392880+Lollipop907@users.noreply.github.com> Date: Fri, 5 Apr 2024 16:57:42 +0800 Subject: [PATCH] rockchip: Add support for Advantech RSB4810 (#12031) --- package/boot/uboot-rockchip/Makefile | 12 + ...68-Add-support-for-advantech-rsb4810.patch | 146 +++ .../armv8/base-files/etc/board.d/02_network | 2 + .../boot/dts/rockchip/rk3568-rsb4810.dts | 890 ++++++++++++++++++ target/linux/rockchip/image/armv8.mk | 10 + ...ip-rk356x-add-support-for-new-boards.patch | 3 +- ...ip-rk356x-add-support-for-new-boards.patch | 3 +- ...ip-rk356x-add-support-for-new-boards.patch | 3 +- 8 files changed, 1066 insertions(+), 3 deletions(-) create mode 100644 package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch create mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rsb4810.dts diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index e892c6620..54cc71af5 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -309,7 +309,19 @@ define U-Boot/station-p2-rk3568 DDR:=rk3568_ddr_1560MHz_v1.18.bin endef +define U-Boot/advantech-rsb4810-rk3568 + BUILD_SUBTARGET:=armv8 + NAME:=Advantech RSB4810 + BUILD_DEVICES:= \ + advantech_rsb4810 + DEPENDS:=+PACKAGE_u-boot-advantech-rsb4810-rk3568:arm-trusted-firmware-rk3568 + PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor + ATF:=rk3568_bl31_v1.43.elf + DDR:=rk3568_ddr_1560MHz_v1.18.bin +endef + UBOOT_TARGETS := \ + advantech-rsb4810-rk3568 \ lyt-t68m-rk3568 \ mrkaio-m68s-rk3568 \ opc-h68k-rk3568 \ diff --git a/package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch b/package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch new file mode 100644 index 000000000..3e1df8574 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch @@ -0,0 +1,146 @@ +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -184,7 +184,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ + rk3568-evb.dtb \ + rk3568-r66s.dtb \ + rk3568-rock-3a.dtb \ +- rk3568-radxa-e25.dtb ++ rk3568-radxa-e25.dtb \ ++ rk3568-rsb4810.dtb + + dtb-$(CONFIG_ROCKCHIP_RK3588) += \ + rk3588-edgeble-neu6a-io.dtb \ +--- /dev/null ++++ b/arch/arm/dts/rk3568-rsb4810.dts +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "Advantech RK3568 RSB4810 Board"; ++ compatible = "advantech-rsb4810", "rockchip,rk3568"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-rsb4810-u-boot.dtsi +@@ -0,0 +1,23 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2021 Rockchip Electronics Co., Ltd ++ */ ++ ++#include "rk356x-u-boot.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; ++ }; ++}; ++ ++&sdmmc0 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ clock-frequency = <24000000>; ++ u-boot,dm-spl; ++ status = "okay"; ++}; +--- /dev/null ++++ b/configs/advantech-rsb4810-rk3568_defconfig +@@ -0,0 +1,83 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_TEXT_BASE=0x00a00000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=2 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3568-rsb4810" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_STACK_R_ADDR=0x600000 ++CONFIG_SPL_STACK=0x400000 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rsb4810.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y ++CONFIG_SPL_BSS_START_ADDR=0x4000000 ++CONFIG_SPL_BSS_MAX_SIZE=0x4000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_ERRNO_STR=y diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 12ce6a781..7573d939c 100755 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -8,6 +8,7 @@ rockchip_setup_interfaces() local board="$1" case "$board" in + advantech,rsb4810|\ ariaboard,photonicat|\ dilusense,dlfr100|\ ezpro,mrkaio-m68s|\ @@ -77,6 +78,7 @@ rockchip_setup_macs() local label_mac="" case "$board" in + advantech,rsb4810|\ ariaboard,photonicat|\ codinge,xiaobao-nas-v1|\ dilusense,dlfr100|\ diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rsb4810.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rsb4810.dts new file mode 100644 index 000000000..139d2cd8c --- /dev/null +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-rsb4810.dts @@ -0,0 +1,890 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Advantech RK3568 RSB4810 Board"; + compatible = "advantech,rsb4810", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + +#ifdef DTS_NO_LEGACY + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +#endif + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&m2_pwr_h>; + pinctrl-names = "default"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc3v3_minipcie: vcc3v3-minipcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&minipcie_pwr_h>; + pinctrl-names = "default"; + regulator-name = "vcc3v3_minipcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usb_hub_en: usb-hub-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_hub_reset>; + pinctrl-names = "default"; + regulator-name = "usb_hub_en"; + regulator-always-on; + regulator-boot-on; + }; + + usb_m2_en: usb-m2-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_m2_reset>; + pinctrl-names = "default"; + regulator-name = "usb_m2_en"; + regulator-always-on; + regulator-boot-on; + }; + + cust_gpios_en: cust-gpios-en { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-0 = <&cust_gpios_h>; + pinctrl-names = "default"; + gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + regulator-name = "cust_gpio_en"; + regulator-always-on; + regulator-boot-on; + }; + + uart4_en: uart4-en { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-0 = <&uart4_en_h>; + pinctrl-names = "default"; + gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-name = "uart4_en"; + regulator-always-on; + regulator-boot-on; + }; + + uart7_en: uart7-en { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-0 = <&uart7_en_h>; + pinctrl-names = "default"; + gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + regulator-name = "uart7_en"; + regulator-always-on; + regulator-boot-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + rk809_sound: rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_reset + &gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + enable_phy_delay = <0>; + tx_delay = <0x37>; + rx_delay = <0x0d>; + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "input"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_reset + &gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + enable_phy_delay = <0>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +#ifdef DTS_NO_LEGACY +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; +#endif + +&i2c0 { + status = "okay"; + + vdd_cpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + mic-in-differential; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_reset_l>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_minipcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&m2_pcie_reset_l>; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + minipcie_pwr_h: minipcie-pwr-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + m2_pwr_h: m2-pwr-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + minipcie_reset_l: minipcie-reset-l { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + m2_pcie_reset_l: m2-pcie-reset-l { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_hub_reset: usb-hub-reset { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usb_m2_reset: usb-m2-reset { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac0 { + gmac0_reset: gmac0_reset { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gmac1 { + gmac1_reset: gmac1_reset { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + misc { + system_rst_h: system-rst-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + cust_gpios_h: cust-gpios-h { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + uart4_en_h: uart4-en-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + uart7_en_h: uart7-en-h { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + uart4m1_xfer_adv: uart4m1-xfer { + rockchip,pins = <3 RK_PB1 4 &pcfg_pull_down>, + <3 RK_PB2 4 &pcfg_pull_down>; + }; + + uart7m1_xfer_adv: uart7m1-xfer { + rockchip,pins = <3 RK_PC5 4 &pcfg_pull_down>, + <3 RK_PC4 4 &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m1_pins>; +}; + +&pwm4 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4m1_xfer_adv>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7m1_xfer_adv>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +#ifdef DTS_NO_LEGACY +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; +#endif diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 820d155e2..2faee8565 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -2,6 +2,16 @@ # # Copyright (C) 2020 Tobias Maedel +define Device/advantech_rsb4810 + DEVICE_VENDOR := Advantech + DEVICE_MODEL := RSB4810 + SOC := rk3568 + UBOOT_DEVICE_NAME := advantech-rsb4810-rk3568 + IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata + DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform -urngd +endef +TARGET_DEVICES += advantech_rsb4810 + define Device/ariaboard_photonicat DEVICE_VENDOR := Ariaboard DEVICE_MODEL := Photonicat diff --git a/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch index 40230634d..ed01e540d 100644 --- a/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch +++ b/target/linux/rockchip/patches-5.15/210-rockchip-rk356x-add-support-for-new-boards.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -59,3 +59,19 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa +@@ -59,3 +59,20 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb @@ -17,6 +17,7 @@ +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r68s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rsb4810.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-seewo-sv21.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-t68m.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-panther-x2.dtb diff --git a/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch index 371e3c9dd..6caa7a34a 100644 --- a/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch +++ b/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -79,3 +79,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so +@@ -79,3 +79,19 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb @@ -16,6 +16,7 @@ +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rsb4810.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-seewo-sv21.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-t68m.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-panther-x2.dtb diff --git a/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch index 699e7f5b9..139589e31 100644 --- a/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch +++ b/target/linux/rockchip/patches-6.6/210-rockchip-rk356x-add-support-for-new-boards.patch @@ -8,7 +8,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb -@@ -98,9 +99,19 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu +@@ -98,9 +99,20 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb @@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rsb4810.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-seewo-sv21.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb