From 61b7a5aa759f404b4b6902ce3ea942fa6a112fdb Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Fri, 14 Apr 2023 23:21:09 +0800 Subject: [PATCH] Revert "rockchip: rk3568 overclock to 2.2GHz" This reverts commit c28b7a562577c6b84e543f82ede8cff6ca925729. --- .../rockchip/rk3328-dram-nanopi2-timing.dtsi | 311 ------------------ .../boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi | 1 - .../boot/dts/rockchip/rk3568-opc-h66k.dts | 1 - .../boot/dts/rockchip/rk3568-opc-h68k.dts | 1 - .../boot/dts/rockchip/rk3568-pro-opp.dtsi | 18 - .../arm64/boot/dts/rockchip/rk3568-r66s.dts | 1 - .../arm64/boot/dts/rockchip/rk3568-r68s.dts | 1 - ...-dts-rockchip-rk3568-remove-scmi-clk.patch | 66 ---- ...-dts-rockchip-rk3568-remove-scmi-clk.patch | 66 ---- 9 files changed, 466 deletions(-) delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi delete mode 100644 target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi delete mode 100644 target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch delete mode 100644 target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi deleted file mode 100644 index a3f5ff4bd..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include -#include - -/ { - ddr_timing: ddr_timing { - compatible = "rockchip,ddr-timing"; - ddr3_speed_bin = ; - ddr4_speed_bin = ; - pd_idle = <0>; - sr_idle = <0>; - sr_mc_gate_idle = <0>; - srpd_lite_idle = <0>; - standby_idle = <0>; - - auto_pd_dis_freq = <1066>; - auto_sr_dis_freq = <800>; - ddr3_dll_dis_freq = <300>; - ddr4_dll_dis_freq = <625>; - phy_dll_dis_freq = <400>; - - ddr3_odt_dis_freq = <100>; - phy_ddr3_odt_dis_freq = <100>; - ddr3_drv = ; - ddr3_odt = ; - phy_ddr3_ca_drv = ; - phy_ddr3_ck_drv = ; - phy_ddr3_dq_drv = ; - phy_ddr3_odt = ; - - lpddr3_odt_dis_freq = <666>; - phy_lpddr3_odt_dis_freq = <666>; - lpddr3_drv = ; - lpddr3_odt = ; - phy_lpddr3_ca_drv = ; - phy_lpddr3_ck_drv = ; - phy_lpddr3_dq_drv = ; - phy_lpddr3_odt = ; - - lpddr4_odt_dis_freq = <800>; - phy_lpddr4_odt_dis_freq = <800>; - lpddr4_drv = ; - lpddr4_dq_odt = ; - lpddr4_ca_odt = ; - phy_lpddr4_ca_drv = ; - phy_lpddr4_ck_cs_drv = ; - phy_lpddr4_dq_drv = ; - phy_lpddr4_odt = ; - - ddr4_odt_dis_freq = <666>; - phy_ddr4_odt_dis_freq = <666>; - ddr4_drv = ; - ddr4_odt = ; - phy_ddr4_ca_drv = ; - phy_ddr4_ck_drv = ; - phy_ddr4_dq_drv = ; - phy_ddr4_odt = ; - - /* CA de-skew, one step is 47.8ps, range 0-15 */ - ddr3a1_ddr4a9_de-skew = <7>; - ddr3a0_ddr4a10_de-skew = <7>; - ddr3a3_ddr4a6_de-skew = <8>; - ddr3a2_ddr4a4_de-skew = <8>; - ddr3a5_ddr4a8_de-skew = <7>; - ddr3a4_ddr4a5_de-skew = <9>; - ddr3a7_ddr4a11_de-skew = <7>; - ddr3a6_ddr4a7_de-skew = <9>; - ddr3a9_ddr4a0_de-skew = <8>; - ddr3a8_ddr4a13_de-skew = <7>; - ddr3a11_ddr4a3_de-skew = <9>; - ddr3a10_ddr4cs0_de-skew = <7>; - ddr3a13_ddr4a2_de-skew = <8>; - ddr3a12_ddr4ba1_de-skew = <7>; - ddr3a15_ddr4odt0_de-skew = <7>; - ddr3a14_ddr4a1_de-skew = <8>; - ddr3ba1_ddr4a15_de-skew = <7>; - ddr3ba0_ddr4bg0_de-skew = <7>; - ddr3ras_ddr4cke_de-skew = <7>; - ddr3ba2_ddr4ba0_de-skew = <8>; - ddr3we_ddr4bg1_de-skew = <8>; - ddr3cas_ddr4a12_de-skew = <7>; - ddr3ckn_ddr4ckn_de-skew = <8>; - ddr3ckp_ddr4ckp_de-skew = <8>; - ddr3cke_ddr4a16_de-skew = <8>; - ddr3odt0_ddr4a14_de-skew = <7>; - ddr3cs0_ddr4act_de-skew = <8>; - ddr3reset_ddr4reset_de-skew = <7>; - ddr3cs1_ddr4cs1_de-skew = <7>; - ddr3odt1_ddr4odt1_de-skew = <7>; - - /* DATA de-skew - * RX one step is 25.1ps, range 0-15 - * TX one step is 47.8ps, range 0-15 - */ - cs0_dm0_rx_de-skew = <7>; - cs0_dm0_tx_de-skew = <8>; - cs0_dq0_rx_de-skew = <7>; - cs0_dq0_tx_de-skew = <8>; - cs0_dq1_rx_de-skew = <7>; - cs0_dq1_tx_de-skew = <8>; - cs0_dq2_rx_de-skew = <7>; - cs0_dq2_tx_de-skew = <8>; - cs0_dq3_rx_de-skew = <7>; - cs0_dq3_tx_de-skew = <8>; - cs0_dq4_rx_de-skew = <7>; - cs0_dq4_tx_de-skew = <8>; - cs0_dq5_rx_de-skew = <7>; - cs0_dq5_tx_de-skew = <8>; - cs0_dq6_rx_de-skew = <7>; - cs0_dq6_tx_de-skew = <8>; - cs0_dq7_rx_de-skew = <7>; - cs0_dq7_tx_de-skew = <8>; - cs0_dqs0_rx_de-skew = <6>; - cs0_dqs0p_tx_de-skew = <9>; - cs0_dqs0n_tx_de-skew = <9>; - - cs0_dm1_rx_de-skew = <7>; - cs0_dm1_tx_de-skew = <7>; - cs0_dq8_rx_de-skew = <7>; - cs0_dq8_tx_de-skew = <8>; - cs0_dq9_rx_de-skew = <7>; - cs0_dq9_tx_de-skew = <7>; - cs0_dq10_rx_de-skew = <7>; - cs0_dq10_tx_de-skew = <8>; - cs0_dq11_rx_de-skew = <7>; - cs0_dq11_tx_de-skew = <7>; - cs0_dq12_rx_de-skew = <7>; - cs0_dq12_tx_de-skew = <8>; - cs0_dq13_rx_de-skew = <7>; - cs0_dq13_tx_de-skew = <7>; - cs0_dq14_rx_de-skew = <7>; - cs0_dq14_tx_de-skew = <8>; - cs0_dq15_rx_de-skew = <7>; - cs0_dq15_tx_de-skew = <7>; - cs0_dqs1_rx_de-skew = <7>; - cs0_dqs1p_tx_de-skew = <9>; - cs0_dqs1n_tx_de-skew = <9>; - - cs0_dm2_rx_de-skew = <7>; - cs0_dm2_tx_de-skew = <8>; - cs0_dq16_rx_de-skew = <7>; - cs0_dq16_tx_de-skew = <8>; - cs0_dq17_rx_de-skew = <7>; - cs0_dq17_tx_de-skew = <8>; - cs0_dq18_rx_de-skew = <7>; - cs0_dq18_tx_de-skew = <8>; - cs0_dq19_rx_de-skew = <7>; - cs0_dq19_tx_de-skew = <8>; - cs0_dq20_rx_de-skew = <7>; - cs0_dq20_tx_de-skew = <8>; - cs0_dq21_rx_de-skew = <7>; - cs0_dq21_tx_de-skew = <8>; - cs0_dq22_rx_de-skew = <7>; - cs0_dq22_tx_de-skew = <8>; - cs0_dq23_rx_de-skew = <7>; - cs0_dq23_tx_de-skew = <8>; - cs0_dqs2_rx_de-skew = <6>; - cs0_dqs2p_tx_de-skew = <9>; - cs0_dqs2n_tx_de-skew = <9>; - - cs0_dm3_rx_de-skew = <7>; - cs0_dm3_tx_de-skew = <7>; - cs0_dq24_rx_de-skew = <7>; - cs0_dq24_tx_de-skew = <8>; - cs0_dq25_rx_de-skew = <7>; - cs0_dq25_tx_de-skew = <7>; - cs0_dq26_rx_de-skew = <7>; - cs0_dq26_tx_de-skew = <7>; - cs0_dq27_rx_de-skew = <7>; - cs0_dq27_tx_de-skew = <7>; - cs0_dq28_rx_de-skew = <7>; - cs0_dq28_tx_de-skew = <7>; - cs0_dq29_rx_de-skew = <7>; - cs0_dq29_tx_de-skew = <7>; - cs0_dq30_rx_de-skew = <7>; - cs0_dq30_tx_de-skew = <7>; - cs0_dq31_rx_de-skew = <7>; - cs0_dq31_tx_de-skew = <7>; - cs0_dqs3_rx_de-skew = <7>; - cs0_dqs3p_tx_de-skew = <9>; - cs0_dqs3n_tx_de-skew = <9>; - - cs1_dm0_rx_de-skew = <7>; - cs1_dm0_tx_de-skew = <8>; - cs1_dq0_rx_de-skew = <7>; - cs1_dq0_tx_de-skew = <8>; - cs1_dq1_rx_de-skew = <7>; - cs1_dq1_tx_de-skew = <8>; - cs1_dq2_rx_de-skew = <7>; - cs1_dq2_tx_de-skew = <8>; - cs1_dq3_rx_de-skew = <7>; - cs1_dq3_tx_de-skew = <8>; - cs1_dq4_rx_de-skew = <7>; - cs1_dq4_tx_de-skew = <8>; - cs1_dq5_rx_de-skew = <7>; - cs1_dq5_tx_de-skew = <8>; - cs1_dq6_rx_de-skew = <7>; - cs1_dq6_tx_de-skew = <8>; - cs1_dq7_rx_de-skew = <7>; - cs1_dq7_tx_de-skew = <8>; - cs1_dqs0_rx_de-skew = <6>; - cs1_dqs0p_tx_de-skew = <9>; - cs1_dqs0n_tx_de-skew = <9>; - - cs1_dm1_rx_de-skew = <7>; - cs1_dm1_tx_de-skew = <7>; - cs1_dq8_rx_de-skew = <7>; - cs1_dq8_tx_de-skew = <8>; - cs1_dq9_rx_de-skew = <7>; - cs1_dq9_tx_de-skew = <7>; - cs1_dq10_rx_de-skew = <7>; - cs1_dq10_tx_de-skew = <8>; - cs1_dq11_rx_de-skew = <7>; - cs1_dq11_tx_de-skew = <7>; - cs1_dq12_rx_de-skew = <7>; - cs1_dq12_tx_de-skew = <8>; - cs1_dq13_rx_de-skew = <7>; - cs1_dq13_tx_de-skew = <7>; - cs1_dq14_rx_de-skew = <7>; - cs1_dq14_tx_de-skew = <8>; - cs1_dq15_rx_de-skew = <7>; - cs1_dq15_tx_de-skew = <7>; - cs1_dqs1_rx_de-skew = <7>; - cs1_dqs1p_tx_de-skew = <9>; - cs1_dqs1n_tx_de-skew = <9>; - - cs1_dm2_rx_de-skew = <7>; - cs1_dm2_tx_de-skew = <8>; - cs1_dq16_rx_de-skew = <7>; - cs1_dq16_tx_de-skew = <8>; - cs1_dq17_rx_de-skew = <7>; - cs1_dq17_tx_de-skew = <8>; - cs1_dq18_rx_de-skew = <7>; - cs1_dq18_tx_de-skew = <8>; - cs1_dq19_rx_de-skew = <7>; - cs1_dq19_tx_de-skew = <8>; - cs1_dq20_rx_de-skew = <7>; - cs1_dq20_tx_de-skew = <8>; - cs1_dq21_rx_de-skew = <7>; - cs1_dq21_tx_de-skew = <8>; - cs1_dq22_rx_de-skew = <7>; - cs1_dq22_tx_de-skew = <8>; - cs1_dq23_rx_de-skew = <7>; - cs1_dq23_tx_de-skew = <8>; - cs1_dqs2_rx_de-skew = <6>; - cs1_dqs2p_tx_de-skew = <9>; - cs1_dqs2n_tx_de-skew = <9>; - - cs1_dm3_rx_de-skew = <7>; - cs1_dm3_tx_de-skew = <7>; - cs1_dq24_rx_de-skew = <7>; - cs1_dq24_tx_de-skew = <8>; - cs1_dq25_rx_de-skew = <7>; - cs1_dq25_tx_de-skew = <7>; - cs1_dq26_rx_de-skew = <7>; - cs1_dq26_tx_de-skew = <7>; - cs1_dq27_rx_de-skew = <7>; - cs1_dq27_tx_de-skew = <7>; - cs1_dq28_rx_de-skew = <7>; - cs1_dq28_tx_de-skew = <7>; - cs1_dq29_rx_de-skew = <7>; - cs1_dq29_tx_de-skew = <7>; - cs1_dq30_rx_de-skew = <7>; - cs1_dq30_tx_de-skew = <7>; - cs1_dq31_rx_de-skew = <7>; - cs1_dq31_tx_de-skew = <7>; - cs1_dqs3_rx_de-skew = <7>; - cs1_dqs3p_tx_de-skew = <9>; - cs1_dqs3n_tx_de-skew = <9>; - }; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi index 8babafdfa..c3e015937 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-mrkaio-m68s.dtsi @@ -5,7 +5,6 @@ #include #include #include "rk3568.dtsi" -#include "rk3568-pro-opp.dtsi" / { aliases { diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts index f290ff379..2d578dbcf 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h66k.dts @@ -4,7 +4,6 @@ /dts-v1/; #include "rk3568-hinlink-opc.dtsi" -#include "rk3568-pro-opp.dtsi" / { model = "HINLINK OPC-H66K Board"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts index ab93b7768..befa4ee8d 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-opc-h68k.dts @@ -4,7 +4,6 @@ /dts-v1/; #include "rk3568-hinlink-opc.dtsi" -#include "rk3568-pro-opp.dtsi" / { model = "HINLINK OPC-H68K Board"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi deleted file mode 100644 index 6a30ac5b5..000000000 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-pro-opp.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -&cpu0_opp_table { - opp-2088000000 { - opp-hz = /bits/ 64 <2088000000>; - opp-microvolt = <1200000>; - }; - - opp-2184000000 { - opp-hz = /bits/ 64 <2184000000>; - opp-microvolt = <1250000>; - }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1275000>; - }; -}; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts index 9b07bbdf7..60733c123 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts @@ -3,7 +3,6 @@ /dts-v1/; #include "rk3568-fastrhino.dtsi" -#include "rk3568-pro-opp.dtsi" / { model = "FastRhino R66S"; diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts index 64a4a5bb2..020b7f015 100644 --- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts +++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-r68s.dts @@ -3,7 +3,6 @@ /dts-v1/; #include "rk3568-fastrhino.dtsi" -#include "rk3568-pro-opp.dtsi" / { model = "FastRhino R68S"; diff --git a/target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch b/target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch deleted file mode 100644 index 7d4b1eb98..000000000 --- a/target/linux/rockchip/patches-5.15/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch +++ /dev/null @@ -1,66 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -53,7 +53,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; -- clocks = <&scmi_clk 0>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -63,6 +63,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -72,6 +73,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -81,6 +83,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -136,6 +139,7 @@ - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; -+ status = "disabled"; - - scmi_clk: protocol@14 { - reg = <0x14>; -@@ -193,6 +197,7 @@ - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; -+ status = "disabled"; - }; - }; - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -150,6 +150,12 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { - } - - static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { -+ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11), -+ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11), -+ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9), -+ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9), -+ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9), -+ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5), diff --git a/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch b/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch deleted file mode 100644 index a27b515d7..000000000 --- a/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3568-remove-scmi-clk.patch +++ /dev/null @@ -1,66 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -53,7 +53,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x0>; -- clocks = <&scmi_clk 0>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -63,6 +63,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x100>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -72,6 +73,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x200>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -81,6 +83,7 @@ - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0 0x300>; -+ clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - enable-method = "psci"; - operating-points-v2 = <&cpu0_opp_table>; -@@ -141,6 +144,7 @@ - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; -+ status = "disabled"; - - scmi_clk: protocol@14 { - reg = <0x14>; -@@ -248,6 +252,7 @@ - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; -+ status = "disabled"; - }; - }; - ---- a/drivers/clk/rockchip/clk-rk3568.c -+++ b/drivers/clk/rockchip/clk-rk3568.c -@@ -156,6 +156,12 @@ static struct rockchip_pll_rate_table rk - } - - static struct rockchip_cpuclk_rate_table rk3568_cpuclk_rates[] __initdata = { -+ RK3568_CPUCLK_RATE(2208000000, 0, 1, 11, 11, 11, 11), -+ RK3568_CPUCLK_RATE(2184000000, 0, 1, 11, 11, 11, 11), -+ RK3568_CPUCLK_RATE(2088000000, 0, 1, 9, 9, 9, 9), -+ RK3568_CPUCLK_RATE(2016000000, 0, 1, 9, 9, 9, 9), -+ RK3568_CPUCLK_RATE(1992000000, 0, 1, 9, 9, 9, 9), -+ RK3568_CPUCLK_RATE(1896000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1800000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1704000000, 0, 1, 7, 7, 7, 7), - RK3568_CPUCLK_RATE(1608000000, 0, 1, 5, 5, 5, 5),