kernel: bump 5.4 to 5.4.75 (#5780)

[mac80211]
 5b29614 mac80211: another fix for the sta connection monitor
 1ed6eb1 mac80211: backport sched_set_fifo_low
 cba4120 mac80211: add support for specifying a per-device scan list
 e0d482f rt2x00: mt7620: differentiate based on SoC's CHIP_VER

[package]
 amd64-microcode/intel-microcode/linux-firmware: update version
This commit is contained in:
AmadeusGhost 2020-11-14 00:52:35 +08:00 committed by GitHub
parent 67198ef5be
commit 5d98c4178e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
260 changed files with 4338 additions and 1695 deletions

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@ -8,11 +8,11 @@ endif
LINUX_VERSION-4.14 = .195
LINUX_VERSION-4.19 = .138
LINUX_VERSION-5.4 = .72
LINUX_VERSION-5.4 = .75
LINUX_KERNEL_HASH-4.14.195 = 394f28798670240baacd9e2cce521fbd79f8da5e1fc191695b0e11381445a021
LINUX_KERNEL_HASH-4.19.138 = d15c27d05f6c527269b75b30cc72972748e55720e7e00ad8abbaa4fe3b1d5e02
LINUX_KERNEL_HASH-5.4.72 = 0e24645bd56fe5b55a7a662895f5562c103d71b54d097281f0c9c71ff22c1172
LINUX_KERNEL_HASH-5.4.75 = d2466fd6eb5433e7bf287b617b11b2640c65a7ea93a57eb7a80d7f537cbc1470
remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))
sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))

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@ -45,7 +45,7 @@ define Package/arm-trusted-firmware-mvebu-espressobin-v3-v5-1gb-1cs
TITLE:=ARM Trusted Firmware for Marvell ESPRESSObin V3-V5 (1GB 1CS)
DEPENDS:=+u-boot-espressobin
UBOOT:=espressobin
DDR_TOPOLOGY:=2
DDR_TOPOLOGY:=4
CLOCKSPRESET:=CPU_800_DDR_800
PLAT:=a3700
endef

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@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=tfa-layerscape
PKG_VERSION:=LSDK-20.04
PKG_RELEASE:=2
PKG_VERSION:=LSDK-20.04-update-290520
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/atf
PKG_SOURCE_VERSION:=4a82c939a0211196e2b80a495f966383803753bb
PKG_MIRROR_HASH:=31c264551ce800b646d7dcc5baa62cfbb4c8fa3299a93931c7ef71dc3e88380d
PKG_SOURCE_VERSION:=7d748e6f0ec652ba7c43733dc67a3d0b0217390a
PKG_MIRROR_HASH:=d209c9ad18aac9f18375450b98b8dab00f0382ccb485df14623bf9b72ea1dd9b
PKG_BUILD_DEPENDS:=tfa-layerscape/host
include $(INCLUDE_DIR)/host-build.mk

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@ -14,6 +14,10 @@ board=$(board_name)
case "$board" in
alfa-network,ap121f|\
alfa-network,ap121fe|\
alfa-network,n2q|\
alfa-network,n5q|\
alfa-network,r36a|\
allnet,all-wap02860ac|\
arduino,yun|\
buffalo,bhr-4grv2|\
@ -37,6 +41,7 @@ netgear,wnr612-v2|\
ocedo,koala|\
ocedo,raccoon|\
openmesh,om5p-ac-v2|\
samsung,wam250|\
ubnt,nanostation-m|\
yuncore,a770|\
yuncore,a782|\
@ -75,6 +80,9 @@ netgear,wndr4300sw)
qihoo,c301)
ubootenv_add_uci_config "/dev/mtd9" "0x0" "0x10000" "0x10000"
;;
wallys,dr531)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0xf800" "0x10000"
;;
esac
config_load ubootenv

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@ -32,15 +32,21 @@ ubootenv_mtdinfo () {
case "$board" in
alfa-network,ap120c-ac |\
edgecore,ecw5211 |\
glinet,gl-b1300 |\
luma,wrtq-329acn |\
openmesh,a42 |\
openmesh,a62)
ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x10000" "0x10000"
;;
buffalo,wtr-m2133hp)
ubootenv_add_uci_config "/dev/mtd8" "0x0" "0x40000" "0x20000"
;;
linksys,ea6350v3)
ubootenv_add_uci_config "/dev/mtd7" "0x0" "0x20000" "0x20000"
;;
linksys,ea8300)
linksys,ea8300 |\
linksys,mr8300)
ubootenv_add_uci_config "/dev/mtd7" "0x0" "0x40000" "0x20000"
;;
zyxel,nbg6617)

View File

@ -31,6 +31,9 @@ ubootenv_mtdinfo () {
}
case "$board" in
edgecore,ecw5410)
ubootenv_add_uci_config "/dev/mtd11" "0x0" "0x10000" "0x10000"
;;
linksys,ea7500-v1 |\
linksys,ea8500)
ubootenv_add_uci_config "/dev/mtd10" "0x0" "0x20000" "0x20000"

View File

@ -27,7 +27,14 @@ glinet,gl-mv1000)
globalscale,espressobin|\
globalscale,espressobin-emmc|\
globalscale,espressobin-v7|\
globalscale,espressobin-v7-emmc|\
globalscale,espressobin-v7-emmc)
idx="$(find_mtd_index u-boot-env)"
if [ -n "$idx" ]; then
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000" "1"
else
ubootenv_add_uci_config "/dev/mtd0" "0x3f0000" "0x10000" "0x10000" "1"
fi
;;
marvell,armada8040-mcbin-doubleshot|\
marvell,armada8040-mcbin-singleshot)
ubootenv_add_uci_config "/dev/mtd0" "0x3f0000" "0x10000" "0x10000" "1"

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@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=uboot-layerscape
PKG_VERSION:=LSDK-20.04
PKG_RELEASE:=2
PKG_VERSION:=LSDK-20.04-update-290520
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot
PKG_SOURCE_VERSION:=b0833bd0e26c059277f0673c9887b967f1ea5837
PKG_MIRROR_HASH:=3cc01d4853ba56d9bcfe5366eddb5f664ae110741146d04f03434d38b4b5b0a0
PKG_SOURCE_VERSION:=1e55b2f9e7f56b76569089b9e950f49c1579580e
PKG_MIRROR_HASH:=46aace27e1367f40b424a64215d524a99c3bd62f49057550039e72d5a1ab7edb
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk

View File

@ -1,6 +1,6 @@
fdtaddr=0x8f000000
loadaddr=0x81000000
fdt_high=0xffffffffffffffff
fdt_high=0x8fffffff
initrd_high=0xffffffffffffffff
qspi_boot=sf probe 0:0;sf read $loadaddr 1000000 2800000;bootm $loadaddr
bootargs=rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),-(firmware)

View File

@ -1,8 +1,8 @@
fdtaddr=0x8f000000
loadaddr=0x81000000
fdt_high=0xffffffffffffffff
fdt_high=0x8fffffff
initrd_high=0xffffffffffffffff
sd_boot=mmc read $fdtaddr 7800 800;mmc read $loadaddr 8000 8000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr
bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
bootcmd=echo starting openwrt ...;pfe stop;run sd_boot
bootdelay=3

View File

@ -3,6 +3,6 @@ loadaddr=0x81000000
fdt_high=0xffffffffffffffff
initrd_high=0xffffffffffffffff
qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),16m(kernel),32m(rootfs),48m@0x1000000(firmware)
bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)
bootcmd=echo starting openwrt ...;pfe stop;run qspi_boot
bootdelay=3

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@ -1,8 +1,8 @@
fdtaddr=0x8f000000
loadaddr=0x81000000
fdt_high=0xffffffff
fdt_high=0x8fffffff
initrd_high=0xffffffff
sd_boot=mmc read ${fdtaddr} 7800 800;mmc read ${loadaddr} 8000 8000;bootm ${loadaddr} - ${fdtaddr}
bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr
bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
bootcmd=echo starting openwrt ...;run sd_boot
bootdelay=3

View File

@ -1,8 +1,8 @@
fdtaddr=0x8f000000
loadaddr=0x81000000
fdt_high=0xffffffff
fdt_high=0x8fffffff
initrd_high=0xffffffff
sd_boot=mmc read $fdtaddr 7800 800;mmc read $loadaddr 8000 8000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 cma=64M@0x0-0xb0000000
sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr
bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
bootcmd=echo starting openwrt ...;run sd_boot
bootdelay=3

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@ -3,6 +3,6 @@ loadaddr=0x81000000
fdt_high=0xffffffff
initrd_high=0xffffffff
nor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mtdblock6 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(rcw),2m(u-boot),1m(u-boot-env),11m(reserved-1),1m(dtb),16m(kernel),32m(rootfs),48m@0x1000000(firmware) cma=64M@0x0-0xb0000000
bootargs=root=/dev/mtdblock6 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(rcw),2m(u-boot),1m(u-boot-env),11m(reserved-1),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) cma=64M@0x0-0xb0000000
bootcmd=echo starting openwrt ...;run nor_boot
bootdelay=3

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@ -1,9 +1,9 @@
fdtaddr=0x8f000000
loadaddr=0x81000000
fdt_high=0xffffffffffffffff
fdt_high=0x8fffffff
initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
sd_boot=mmc read $fdtaddr 7800 800;mmc read $loadaddr 8000 8000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr
bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
bootcmd=echo starting openwrt ...;run sd_boot
bootdelay=3

View File

@ -4,6 +4,6 @@ fdt_high=0xffffffffffffffff
initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
nor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),48m@0x1000000(firmware)
bootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)
bootcmd=echo starting openwrt ...;run nor_boot
bootdelay=3

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@ -1,9 +1,9 @@
fdtaddr=0x8f000000
loadaddr=0x81000000
fdt_high=0xffffffffffffffff
fdt_high=0x8fffffff
initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
sd_boot=mmc read $fdtaddr 7800 800;mmc read $loadaddr 8000 8000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr
bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
bootcmd=echo starting openwrt ...;run sd_boot
bootdelay=3

View File

@ -4,6 +4,6 @@ fdt_high=0xffffffffffffffff
initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),48m@0x1000000(firmware)
bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)
bootcmd=echo starting openwrt ...;run qspi_boot
bootdelay=3

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@ -4,7 +4,7 @@ fdt_high=0xa0000000
initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
mc_init=mmc read 80000000 5000 1800;mmc read 80300000 7000 800;fsl_mc start mc 80000000 80300000;mmc read 80400000 6800 800;fsl_mc apply dpl 80400000
sd_boot=mmc read $fdtaddr 7800 800;mmc read $loadaddr 8000 8000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
sd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr
bootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200
bootcmd=echo starting openwrt ...;run mc_init;run sd_boot
bootdelay=3

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@ -5,6 +5,6 @@ initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
mc_init=sf probe 0:0;sf read 80000000 a00000 300000;sf read 80300000 e00000 100000;fsl_mc start mc 80000000 80300000;sf read 80400000 d00000 100000;fsl_mc apply dpl 80400000
qspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mtdblock10 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=20c0000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),48m@0x1000000(firmware)
bootargs=root=/dev/mtdblock10 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=20c0000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)
bootcmd=echo starting openwrt ...;run mc_init;run qspi_boot
bootdelay=3

View File

@ -5,6 +5,6 @@ initrd_high=0xffffffffffffffff
hwconfig=fsl_ddr:bank_intlv=auto
mc_init=fsl_mc start mc 580a00000 580e00000;fsl_mc apply dpl 580d00000
nor_boot=cp.b 580f00000 $fdtaddr 100000;cp.b 581000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr
bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS1,115200 mtdparts=580000000.nor:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),48m@0x1000000(firmware)
bootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS1,115200 mtdparts=580000000.nor:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)
bootcmd=echo starting openwrt ...;run mc_init;run nor_boot
bootdelay=3

View File

@ -1,8 +1,8 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.07
PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a
PKG_VERSION:=2020.10
PKG_HASH:=0d481bbdc05c0ee74908ec2f56a6daa53166cc6a78a0e4fac2ac5d025770a622
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk

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@ -19,6 +19,7 @@ index 1ce6ebdfeb..816126267b 100644
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_PING=y
CONFIG_CMD_SMC=y

View File

@ -1,237 +0,0 @@
From e05fdd93645dab2217bb5bfabcc04845415cf7ed Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw2@infradead.org>
Date: Fri, 19 Jun 2020 12:40:20 +0100
Subject: [PATCH] pinctrl: mediatek: add PUPD/R0/R1 support for MT7623
The pins for the MMC controller weren't being set up correctly because the
pinctrl driver only sets the GPIO pullup/pulldown config and doesn't
handle the special cases with PUPD/R0/R1 control.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
---
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 129 ++++++++++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 19 ++-
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 3 +
3 files changed, 146 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
index d58d840e08..0f5dcb2c63 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -262,6 +262,132 @@ static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
};
+static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {
+ /* MSDC0 */
+ PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1),
+ PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1),
+ PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1),
+ PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1),
+ PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1),
+ PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1),
+ PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1),
+ PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1),
+ PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1),
+ PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1),
+ PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1),
+ /* MSDC1 */
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1),
+ PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1),
+ PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1),
+ PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1),
+ PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1),
+ /* MSDC1 */
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1),
+ PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1),
+ PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1),
+ PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1),
+ PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1),
+ /* MSDC0E */
+ PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1),
+ PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1),
+ PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1),
+ PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1),
+ PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1),
+ PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1),
+ PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1),
+ PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1),
+ PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1),
+ PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1),
+ PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1),
+ PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {
+ /* MSDC0 */
+ PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1),
+ PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1),
+ PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1),
+ PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1),
+ PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1),
+ PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1),
+ PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1),
+ PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1),
+ PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1),
+ PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1),
+ PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1),
+ /* MSDC1 */
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1),
+ PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1),
+ PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1),
+ PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1),
+ PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1),
+ /* MSDC2 */
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1),
+ PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1),
+ PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1),
+ PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1),
+ PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1),
+ /* MSDC0E */
+ PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1),
+ PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1),
+ PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1),
+ PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1),
+ PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1),
+ PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1),
+ PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1),
+ PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1),
+ PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1),
+ PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1),
+ PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1),
+ PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
+ /* MSDC0 */
+ PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1),
+ PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1),
+ PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1),
+ PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1),
+ PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1),
+ PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1),
+ PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1),
+ PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1),
+ PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1),
+ PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1),
+ PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1),
+ /* MSDC1 */
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1),
+ PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1),
+ PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1),
+ PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1),
+ PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1),
+ /* MSDC2 */
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1),
+ PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1),
+ PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1),
+ PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1),
+ PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1),
+ /* MSDC0E */
+ PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1),
+ PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1),
+ PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1),
+ PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1),
+ PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1),
+ PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1),
+ PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1),
+ PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1),
+ PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1),
+ PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1),
+ PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1),
+ PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
+};
+
static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
@@ -272,6 +398,9 @@ static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range),
};
static const struct mtk_pin_desc mt7623_pins[] = {
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index e8187a3780..6553dde45c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -296,7 +296,7 @@ static const struct pinconf_param mtk_conf_params[] = {
};
-int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg)
+int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg, u32 val)
{
int err, disable, pullup;
@@ -323,12 +323,14 @@ int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg)
return 0;
}
-int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg)
+int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg, u32 val)
{
- int err, disable, pullup;
+ int err, disable, pullup, r0, r1;
disable = (arg == PIN_CONFIG_BIAS_DISABLE);
pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+ r0 = !!(val & 1);
+ r1 = !!(val & 2);
if (disable) {
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
@@ -344,6 +346,13 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg)
return err;
}
+ /* Also set PUPD/R0/R1 if the pin has them */
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
+ if (err != -EINVAL) {
+ mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
+ mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
+ }
+
return 0;
}
@@ -419,9 +428,9 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (rev == MTK_PINCTRL_V0)
- err = mtk_pinconf_bias_set_v0(dev, pin, param);
+ err = mtk_pinconf_bias_set_v0(dev, pin, param, arg);
else
- err = mtk_pinconf_bias_set_v1(dev, pin, param);
+ err = mtk_pinconf_bias_set_v1(dev, pin, param, arg);
if (err)
goto err;
break;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index e815761450..5e51a9a90c 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -51,6 +51,9 @@ enum {
PINCTRL_PIN_REG_PULLEN,
PINCTRL_PIN_REG_PULLSEL,
PINCTRL_PIN_REG_DRV,
+ PINCTRL_PIN_REG_PUPD,
+ PINCTRL_PIN_REG_R0,
+ PINCTRL_PIN_REG_R1,
PINCTRL_PIN_REG_MAX,
};
--
2.26.2

View File

@ -1,95 +0,0 @@
From 6731bef6966ea2b26cdcfe0109ff5a950003fd03 Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw2@infradead.org>
Date: Fri, 19 Jun 2020 23:07:17 +0100
Subject: [PATCH] env/fat.c: allow loading from a FAT partition on the MMC boot
device
I don't want to have to specify the device; only the partition.
This allows me to use the same image on internal eMMC or SD card for
Banana Pi R2, and it finds its own environment either way.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
[trini: Add #if/#else/#endif logic around CONFIG_SYS_MMC_ENV_DEV usage,
whitespace changes]
Signed-off-by: Tom Rini <trini@konsulko.com>
---
env/Kconfig | 4 ++++
env/fat.c | 32 ++++++++++++++++++++++++++++++--
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig
index 38e7fadbb9..5784136674 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -434,6 +434,10 @@ config ENV_FAT_DEVICE_AND_PART
If none, first valid partition in device D. If no
partition table then means device D.
+ If ENV_FAT_INTERFACE is set to "mmc" then device 'D' can be omitted,
+ leaving the string starting with a colon, and the boot device will
+ be used.
+
config ENV_FAT_FILE
string "Name of the FAT file to use for the environment"
depends on ENV_IS_IN_FAT
diff --git a/env/fat.c b/env/fat.c
index 35a1955e63..63aced9317 100644
--- a/env/fat.c
+++ b/env/fat.c
@@ -29,6 +29,34 @@
# define LOADENV
#endif
+__weak int mmc_get_env_dev(void)
+{
+#ifdef CONFIG_SYS_MMC_ENV_DEV
+ return CONFIG_SYS_MMC_ENV_DEV;
+#else
+ return 0;
+#endif
+}
+
+static char *env_fat_device_and_part(void)
+{
+#ifdef CONFIG_MMC
+ static char *part_str;
+
+ if (!part_str) {
+ part_str = CONFIG_ENV_FAT_DEVICE_AND_PART;
+ if (!strcmp(CONFIG_ENV_FAT_INTERFACE, "mmc") && part_str[0] == ':') {
+ part_str = "0" CONFIG_ENV_FAT_DEVICE_AND_PART;
+ part_str[0] += mmc_get_env_dev();
+ }
+ }
+
+ return part_str;
+#else
+ return CONFIG_ENV_FAT_DEVICE_AND_PART;
+#endif
+}
+
static int env_fat_save(void)
{
env_t __aligned(ARCH_DMA_MINALIGN) env_new;
@@ -43,7 +71,7 @@ static int env_fat_save(void)
return err;
part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
- CONFIG_ENV_FAT_DEVICE_AND_PART,
+ env_fat_device_and_part(),
&dev_desc, &info, 1);
if (part < 0)
return 1;
@@ -89,7 +117,7 @@ static int env_fat_load(void)
#endif
part = blk_get_device_part_str(CONFIG_ENV_FAT_INTERFACE,
- CONFIG_ENV_FAT_DEVICE_AND_PART,
+ env_fat_device_and_part(),
&dev_desc, &info, 1);
if (part < 0)
goto err_env_relocate;
--
2.26.2

View File

@ -1,51 +0,0 @@
From e3cc511eef5d99491e0c51324be499b688dde8de Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw2@infradead.org>
Date: Sun, 12 Jul 2020 23:33:01 +0100
Subject: [PATCH 1/3] board: mediatek: fix mmc_get_boot_dev() for platforms
without external SD
On the UniElec U7623 board there is no external SD slot and the preloader
doesn't fill in the magic field at 0x81dffff0 to indicate that it was
booted from eMMC.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
---
board/mediatek/mt7623/mt7623_rfb.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c
index 4ec2764976..984e75ccaf 100644
--- a/board/mediatek/mt7623/mt7623_rfb.c
+++ b/board/mediatek/mt7623/mt7623_rfb.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -15,10 +16,15 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_MMC
int mmc_get_boot_dev(void)
{
int g_mmc_devid = -1;
char *uflag = (char *)0x81DFFFF0;
+
+ if (!find_mmc_device(1))
+ return 0;
+
if (strncmp(uflag,"eMMC",4)==0) {
g_mmc_devid = 0;
printf("Boot From Emmc(id:%d)\n\n", g_mmc_devid);
@@ -33,3 +39,4 @@ int mmc_get_env_dev(void)
{
return mmc_get_boot_dev();
}
+#endif
--
2.26.2

View File

@ -1,326 +0,0 @@
From 3fad1ca28d4c87346d18b89438bf2084fb2c3896 Mon Sep 17 00:00:00 2001
From: David Woodhouse <dwmw2@infradead.org>
Date: Sun, 12 Jul 2020 23:33:03 +0100
Subject: [PATCH 3/3] board: mediatek: Add support for UniElec U7623 board
This is an MT7623A-based board, very similar to the Banana Pi R2.
http://www.unielecinc.com/q/news/cn/p/product/detail.html?qd_guid=OjXwKCaRlN
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
---
arch/arm/dts/Makefile | 1 +
.../arm/dts/mt7623a-unielec-u7623-02-emmc.dts | 211 ++++++++++++++++++
board/mediatek/mt7623/MAINTAINERS | 7 +
configs/mt7623a_unielec_u7623_02_defconfig | 54 +++++
4 files changed, 273 insertions(+)
create mode 100644 arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
create mode 100644 configs/mt7623a_unielec_u7623_02_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a3a1e3fbe4..caa7756c5d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -949,6 +949,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
+ mt7623a-unielec-u7623-02-emmc.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt8512-bm1-emmc.dtb \
diff --git a/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
new file mode 100644
index 0000000000..fdeec75b05
--- /dev/null
+++ b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7623.dtsi"
+#include "mt7623-u-boot.dtsi"
+
+/ {
+ model = "UniElec U7623-02 eMMC";
+ compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ tick-timer = &timer0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led3 {
+ label = "u7623-01:green:led3";
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led4 {
+ label = "u7623-01:green:led4";
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&eth {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "rgmii";
+ mediatek,switch = "mt7530";
+ mediatek,mcm;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ status = "okay";
+ bus-width = <8>;
+ max-frequency = <50000000>;
+ cap-mmc-highspeed;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ non-removable;
+};
+
+&pinctrl {
+ ephy_default: ephy_default {
+ mux {
+ function = "eth";
+ groups = "mdc_mdio", "ephy";
+ };
+
+ conf {
+ pins = "G2_TXEN", "G2_TXD0", "G2_TXD1", "G2_TXD2",
+ "G2_TXD3", "G2_TXC", "G2_RXC", "G2_RXD0",
+ "G2_RXD1", "G2_RXD2", "G2_RXD3", "G2_RXDV",
+ "MDC", "MDIO";
+ drive-strength = <12>;
+ mediatek,tdsel = <5>;
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ pcie_default: pcie-default {
+ mux {
+ function = "pcie";
+ groups = "pcie0_0_perst", "pcie1_0_perst";
+ };
+ };
+
+ uart0_pins_a: uart0-default {
+ mux {
+ function = "uart";
+ groups = "uart0_0_txd_rxd";
+ };
+ };
+
+ uart1_pins_a: uart1-default {
+ mux {
+ function = "uart";
+ groups = "uart1_0_txd_rxd";
+ };
+ };
+
+ uart2_pins_a: uart2-default {
+ mux {
+ function = "uart";
+ groups = "uart2_0_txd_rxd";
+ };
+ };
+
+ uart2_pins_b: uart2-alt {
+ mux {
+ function = "uart";
+ groups = "uart2_1_txd_rxd";
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_default>;
+ status = "okay";
+
+ pcie@0,0 {
+ status = "okay";
+ };
+
+ pcie@1,0 {
+ status = "okay";
+ };
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_b>;
+ status = "okay";
+};
diff --git a/board/mediatek/mt7623/MAINTAINERS b/board/mediatek/mt7623/MAINTAINERS
index eeb0375d70..1a8d796bd3 100644
--- a/board/mediatek/mt7623/MAINTAINERS
+++ b/board/mediatek/mt7623/MAINTAINERS
@@ -5,3 +5,10 @@ S: Maintained
F: board/mediatek/mt7623
F: include/configs/mt7623.h
F: configs/mt7623n_bpir2_defconfig
+
+UNIELEC U7623
+M: Ryder Lee <ryder.lee@mediatek.com>
+M: David Woodhouse <dwmw2@infradead.org>
+S: Maintained
+F: arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts
+F: configs/mt7623a_unielec_u7623_02_defconfig
diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig
new file mode 100644
index 0000000000..72b5f31092
--- /dev/null
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_TEXT_BASE=0x81e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x100000
+CONFIG_TARGET_MT7623=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_DEFAULT_FDT_FILE="mt7623a-unielec-u7623-02-emmc.dtb"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_MEDIATEK_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7623=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_WDT_MTK=y
+CONFIG_LZMA=y
--
2.26.2

View File

@ -1,11 +1,9 @@
--- a/Makefile
+++ b/Makefile
@@ -1667,8 +1667,10 @@ u-boot-elf.lds: arch/u-boot-elf.lds prepare FORCE
--- a/Makefile 2020-10-13 13:39:06.471438591 +0800
+++ b/Makefile 2020-10-13 13:39:39.190798462 +0800
@@ -1725,6 +1725,10 @@
ifeq ($(CONFIG_SPL),y)
spl/u-boot-spl-mtk.bin: spl/u-boot-spl
-u-boot-mtk.bin: u-boot.dtb u-boot.img spl/u-boot-spl-mtk.bin FORCE
- $(call if_changed,binman)
+OBJCOPYFLAGS_u-boot-mtk.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-mtk.bin: u-boot.img spl/u-boot-spl-mtk.bin FORCE

View File

@ -8,10 +8,10 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.10-rc4
PKG_VERSION:=2020.10
PKG_RELEASE:=1
PKG_HASH:=0a7bdd2c7df2c14daf2730fcf3277fd917aadfaae935529e29c7412314bbf260
PKG_HASH:=0d481bbdc05c0ee74908ec2f56a6daa53166cc6a78a0e4fac2ac5d025770a622
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
@ -38,14 +38,12 @@ endef
define U-Boot/espressobin
NAME:=Marvell ESPRESSObin
BUILD_DEVICES:=globalscale_espressobin globalscale_espressobin-v7
BUILD_SUBTARGET:=cortexa53
UBOOT_CONFIG:=mvebu_espressobin-88f3720
endef
define U-Boot/espressobin-emmc
NAME:=Marvell ESPRESSObin
BUILD_DEVICES:=globalscale_espressobin-emmc globalscale_espressobin-v7-emmc
BUILD_SUBTARGET:=cortexa53
UBOOT_CONFIG:=mvebu_espressobin-88f3720
UBOOT_MAKE_FLAGS+=DEVICE_TREE=armada-3720-espressobin-emmc
@ -53,7 +51,6 @@ endef
define U-Boot/uDPU
NAME:=Methode uDPU
BUILD_DEVICES:=methode_udpu
BUILD_SUBTARGET:=cortexa53
endef
@ -68,12 +65,15 @@ Build/Exports:=$(Host/Exports)
define Build/Configure
# enable additional options beyond <device>_defconfig
echo CONFIG_NET_RANDOM_ETHADDR=y >> $(PKG_BUILD_DIR)/configs/$(UBOOT_CONFIG)_defconfig
echo CONFIG_CMD_SETEXPR=y >> $(PKG_BUILD_DIR)/configs/$(UBOOT_CONFIG)_defconfig
$(call Build/Configure/U-Boot)
endef
define Package/u-boot/install
$(if $(findstring cortexa53,$(BUILD_SUBTARGET)),,$(Package/u-boot/install/default))
endef
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)

View File

@ -1,10 +0,0 @@
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -151,6 +151,7 @@ const struct flash_info spi_nor_ids[] =
{ INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
+ { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },

View File

@ -1,13 +0,0 @@
Increase max gunzip size in mvebu_armada-37xx.h.
This is required in order to boot itb images.
--- a/include/configs/mvebu_armada-37xx.h
+++ b/include/configs/mvebu_armada-37xx.h
@@ -12,6 +12,7 @@
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
/* auto boot */

View File

@ -1,43 +0,0 @@
From 264c45575ec6a3d507dc4e43954b8a78283aca6c Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Thu, 10 Sep 2020 17:58:43 +0200
Subject: [PATCH] mmc: xenon_sdhci: Add missing common host capabilities
Use mmc_of_parse() to set the common host properties. That includes
"bus-width", so parsing it can be removed from the driver.
But more importantly, "non-removable" is now respected, which fixes
the usage of eMMC.
Signed-off-by: Andre Heider <a.heider@gmail.com>
---
drivers/mmc/xenon_sdhci.c | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
--- a/drivers/mmc/xenon_sdhci.c
+++ b/drivers/mmc/xenon_sdhci.c
@@ -485,20 +485,10 @@ static int xenon_sdhci_probe(struct udev
armada_3700_soc_pad_voltage_set(host);
host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
- switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
- 1)) {
- case 8:
- host->host_caps |= MMC_MODE_8BIT;
- break;
- case 4:
- host->host_caps |= MMC_MODE_4BIT;
- break;
- case 1:
- break;
- default:
- printf("Invalid \"bus-width\" value\n");
- return -EINVAL;
- }
+
+ ret = mmc_of_parse(dev, &plat->cfg);
+ if (ret)
+ return ret;
host->ops = &xenon_sdhci_ops;

View File

@ -1,14 +1,16 @@
From 753947e2c374820dcbc9c86626812aeb7d460653 Mon Sep 17 00:00:00 2001
From cdcfd9211c805624a702b6ff81b9bd9515344749 Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Fri, 4 Sep 2020 16:34:22 +0200
Subject: [PATCH] arm64: dts: armada-3720-espressobin: use Linux
model/compatible strings
Fix the actual board vendor and ease synching dts files from Linux.
Signed-off-by: Andre Heider <a.heider@gmail.com>
---
arch/arm/dts/armada-3720-espressobin.dts | 4 ++--
board/Marvell/mvebu_armada-37xx/board.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
board/Marvell/mvebu_armada-37xx/board.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@ -25,7 +27,24 @@ Fix the actual board vendor and ease synching dts files from Linux.
stdout-path = "serial0:115200n8";
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -201,7 +201,7 @@ static int mii_multi_chip_mode_write(str
@@ -88,14 +88,14 @@ int board_late_init(void)
if (env_get("fdtfile"))
return 0;
- if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+ if (!of_machine_is_compatible("globalscale,espressobin"))
return 0;
/* If the memory controller has been configured for DDR4, we're running on v7 */
ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
& A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
- emmc = of_machine_is_compatible("marvell,armada-3720-espressobin-emmc");
+ emmc = of_machine_is_compatible("globalscale,espressobin-emmc");
if (ddr4 && emmc)
env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
@@ -248,7 +248,7 @@ static int mii_multi_chip_mode_write(str
/* Bring-up board-specific network stuff */
int board_network_enable(struct mii_dev *bus)
{
@ -34,7 +53,7 @@ Fix the actual board vendor and ease synching dts files from Linux.
return 0;
/*
@@ -253,7 +253,7 @@ int ft_board_setup(void *blob, struct bd
@@ -300,7 +300,7 @@ int ft_board_setup(void *blob, struct bd
int part_off;
/* Fill SPI MTD partitions for Linux kernel on Espressobin */

View File

@ -1,21 +1,20 @@
From ee59573dd531df96de0d9dc8e79b34ed3716c864 Mon Sep 17 00:00:00 2001
From a9ac1dd46a4fd11880be80227e1eb102e3c61dd8 Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Fri, 4 Sep 2020 15:38:58 +0200
Subject: [PATCH] arm64: dts: armada-3720-espressobin: split common parts to
.dtsi
Subject: [PATCH] arm64: dts: armada-3720-espressobin: split common parts
to .dtsi
Move most of the dts to the new common
arch/arm/dts/armada-3720-espressobin.dtsi file, just like Linux has.
Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.
The dts itself is imported from Linux.
Signed-off-by: Andre Heider <a.heider@gmail.com>
---
arch/arm/dts/armada-3720-espressobin.dts | 190 ++----------------
...sobin.dts => armada-3720-espressobin.dtsi} | 3 -
2 files changed, 20 insertions(+), 173 deletions(-)
rewrite arch/arm/dts/armada-3720-espressobin.dts (95%)
copy arch/arm/dts/{armada-3720-espressobin.dts => armada-3720-espressobin.dtsi} (96%)
arch/arm/dts/armada-3720-espressobin.dts | 164 +--------------------
arch/arm/dts/armada-3720-espressobin.dtsi | 167 ++++++++++++++++++++++
2 files changed, 174 insertions(+), 157 deletions(-)
create mode 100644 arch/arm/dts/armada-3720-espressobin.dtsi
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts

View File

@ -1,10 +1,12 @@
From 83908b6e2e5a7d7b0f4d040ffb4bf3ce6807b8fe Mon Sep 17 00:00:00 2001
From 408bba2fb84ad0b02c3f9529065126b40899e256 Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Fri, 4 Sep 2020 15:44:41 +0200
Subject: [PATCH] arm64: dts: a3720: add support for boards with populated emmc
Subject: [PATCH] arm64: dts: a3720: add support for espressobin with
populated emmc
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since sdhc0 is used for the sd card.
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.
Signed-off-by: Andre Heider <a.heider@gmail.com>
---

View File

@ -1,100 +0,0 @@
From d59406482c1847959305a986376b35e57da28e69 Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Sat, 5 Sep 2020 12:45:59 +0200
Subject: [PATCH] arm: mvebu: Espressobin: Set environment variable fdtfile
Required for the generic distro mechanism.
Linux ships with 4 variants:
marvell/armada-3720-espressobin-v7-emmc.dtb
marvell/armada-3720-espressobin-v7.dtb
marvell/armada-3720-espressobin-emmc.dtb
marvell/armada-3720-espressobin.dtb
Use available information to determine the appropriate filename.
Tested on a v5 board without eMMC.
Signed-off-by: Andre Heider <a.heider@gmail.com>
---
board/Marvell/mvebu_armada-37xx/board.c | 47 +++++++++++++++++++++
configs/mvebu_espressobin-88f3720_defconfig | 1 +
2 files changed, 48 insertions(+)
--- a/board/Marvell/mvebu_armada-37xx/board.c
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -5,6 +5,7 @@
#include <common.h>
#include <dm.h>
+#include <env.h>
#include <i2c.h>
#include <init.h>
#include <phy.h>
@@ -50,6 +51,22 @@ DECLARE_GLOBAL_DATA_PTR;
#define MVEBU_G2_SMI_PHY_CMD_REG (24)
#define MVEBU_G2_SMI_PHY_DATA_REG (25)
+/*
+ * Memory Controller Registers
+ *
+ * Assembled based on public information:
+ * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
+ *
+ * And checked against the written register values for the various topologies:
+ * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
+ */
+#define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
+#define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
+#define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
+#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
+#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
+
int board_early_init_f(void)
{
return 0;
@@ -63,6 +80,36 @@ int board_init(void)
return 0;
}
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ bool ddr4, emmc;
+
+ if (env_get("fdtfile"))
+ return 0;
+
+ if (!of_machine_is_compatible("globalscale,espressobin"))
+ return 0;
+
+ /* If the memory controller has been configured for DDR4, we're running on v7 */
+ ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
+ & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
+
+ emmc = of_machine_is_compatible("globalscale,espressobin-emmc");
+
+ if (ddr4 && emmc)
+ env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
+ else if (ddr4)
+ env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
+ else if (emmc)
+ env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
+ else
+ env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
+
+ return 0;
+}
+#endif
+
/* Board specific AHCI / SATA enable code */
int board_ahci_enable(void)
{
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -84,3 +84,4 @@ CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SHA1=y
CONFIG_SHA256=y
+CONFIG_BOARD_LATE_INIT=y

View File

@ -8,10 +8,10 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2019.10
PKG_VERSION:=2020.04
PKG_RELEASE:=1
PKG_HASH:=8d6d6070739522dd236cba7055b8736bfe92b4fac0ea18ad809829ca79667014
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk

View File

@ -154,6 +154,12 @@ define U-Boot/nanopi_m1_plus
BUILD_DEVICES:=friendlyarm_nanopi-m1-plus
endef
define U-Boot/zeropi
BUILD_SUBTARGET:=cortexa7
NAME:=ZeroPi (H3)
BUILD_DEVICES:=friendlyarm_zeropi
endef
define U-Boot/nanopi_neo_air
BUILD_SUBTARGET:=cortexa7
NAME:=U-Boot for NanoPi NEO Air (H3)
@ -166,6 +172,12 @@ define U-Boot/nanopi_neo
BUILD_DEVICES:=friendlyarm_nanopi-neo
endef
define U-Boot/nanopi_r1
BUILD_SUBTARGET:=cortexa7
NAME:=U-Boot for NanoPi R1 (H3)
BUILD_DEVICES:=friendlyarm_nanopi-r1
endef
define U-Boot/orangepi_r1
BUILD_SUBTARGET:=cortexa7
NAME:=Orange Pi R1 (H2+)
@ -272,7 +284,7 @@ endef
define U-Boot/Bananapi_M2_Ultra
BUILD_SUBTARGET:=cortexa7
NAME:=Bananapi M2 Ultra
BUILD_DEVICES:=lemaker_bananapi-m2-ultra
BUILD_DEVICES:=sinovoip_bananapi-m2-ultra
endef
UBOOT_TARGETS := \
@ -299,10 +311,12 @@ UBOOT_TARGETS := \
Linksprite_pcDuino3 \
Lamobo_R1 \
nanopi_m1_plus \
zeropi \
nanopi_neo \
nanopi_neo_air \
nanopi_neo_plus2 \
nanopi_neo2 \
nanopi_r1 \
orangepi_zero \
orangepi_r1 \
orangepi_one \

View File

@ -0,0 +1,81 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
- sun8i-h3-rervision-dvk.dtb
+ sun8i-h3-rervision-dvk.dtb \
+ sun8i-h3-zeropi.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-zeropi.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyElec ZeroPi";
+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_nanopi>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ gmac_power_pin_nanopi: gmac_power_pin@0 {
+ pins = "PD6";
+ function = "gpio_out";
+ };
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "peripheral";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+};

View File

@ -0,0 +1,24 @@
--- /dev/null
+++ b/configs/zeropi_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MACPWR="PD6"
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SPL=y
+CONFIG_SYS_CLK_FREQ=480000000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y

View File

@ -0,0 +1,198 @@
From 0e8043aff1aae95d1f7b7422b91b57d9569860d3 Mon Sep 17 00:00:00 2001
From: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
Date: Mon, 12 Oct 2020 18:39:53 +0000
Subject: [PATCH] sunxi: add support for FriendlyARM NanoPi R1
Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++++++++++++
configs/nanopi_r1_defconfig | 22 +++++
3 files changed, 169 insertions(+)
create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
create mode 100644 configs/nanopi_r1_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -531,6 +531,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
+ sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
+ */
+
+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R1";
+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>;
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0
+ 1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ /delete-node/ pwr;
+ status {
+ label = "nanopi:red:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ wan {
+ label = "nanopi:green:wan";
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ lan {
+ label = "nanopi:green:lan";
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_npi>;
+
+ /delete-node/ k1;
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ sdio_wifi: sdio_wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&r_pio {
+ sw_r_npi: key_pins {
+ pins = "PL3";
+ function = "gpio_in";
+ };
+};
--- /dev/null
+++ b/configs/nanopi_r1_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MACPWR="PD6"
+# CONFIG_VIDEO_DE2 is not set
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SYS_CLK_FREQ=480000000
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-r1"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2

View File

@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=amd64-microcode
PKG_VERSION:=20180524
PKG_VERSION:=20191218
PKG_RELEASE:=1
PKG_SOURCE:=amd64-microcode_3.$(PKG_VERSION).$(PKG_RELEASE).tar.xz
PKG_SOURCE_URL:=http://ftp.debian.org/debian/pool/non-free/a/amd64-microcode/
PKG_HASH:=7c389c357c242e7161f6872bf4e12011a71e4c0683f06fb1bcfad650a78bf0a9
PKG_HASH:=f469b79348097c5f04641b67a39d0ee5a2a1916c9556281626c04f2275d4132d
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-3.$(PKG_VERSION).$(PKG_RELEASE)
PKG_LICENSE_FILE:=LICENSE.amd-ucode

View File

@ -173,9 +173,9 @@ define Package/ath10k-firmware-qca9984/install
$(1)/lib/firmware/ath10k/QCA9984/hw1.0/firmware-5.bin
endef
$(eval $(call BuildPackage,ath10k-firmware-qca9887))
#$(eval $(call BuildPackage,ath10k-firmware-qca9887))
#$(eval $(call BuildPackage,ath10k-firmware-qca9888))
$(eval $(call BuildPackage,ath10k-firmware-qca988x))
#$(eval $(call BuildPackage,ath10k-firmware-qca988x))
#$(eval $(call BuildPackage,ath10k-firmware-qca99x0))
#$(eval $(call BuildPackage,ath10k-firmware-qca6174))
#$(eval $(call BuildPackage,ath10k-firmware-qca9984))

View File

@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=intel-microcode
PKG_VERSION:=20190918
PKG_VERSION:=20200616
PKG_RELEASE:=1
PKG_SOURCE:=intel-microcode_3.$(PKG_VERSION).$(PKG_RELEASE).tar.xz
PKG_SOURCE_URL:=http://ftp.debian.org/debian/pool/non-free/i/intel-microcode/
PKG_HASH:=b7ecb5dd30d71e9b3c2ab184693a876171392e0d80d138c3560c662e5f2a2247
PKG_HASH:=bcc3b81c452fe4649a948c022475d76c1cdfbb730f36749a082f412f1406a3b9
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-3.$(PKG_VERSION).$(PKG_RELEASE)
PKG_BUILD_DEPENDS:=iucode-tool/host

View File

@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=ls-rcw
PKG_VERSION:=LSDK-20.04
PKG_RELEASE:=2
PKG_VERSION:=LSDK-20.04-update-290520
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/rcw
PKG_SOURCE_VERSION:=5689bf9c9f087f50aaa0d91b43d8a791fedbedd3
PKG_MIRROR_HASH:=45709aa92f84fea8100b472a29762bfe69a333e6aca7a4fc4edc8cc3e10bf44e
PKG_SOURCE_VERSION:=e0fab6d9b61003caef577f7474c2fac61e6ba2ff
PKG_MIRROR_HASH:=b6bc66e27b7c6db31101fdc2e6be7255181861bd38d8f25eb5eb80c468983eb2
include $(INCLUDE_DIR)/package.mk

View File

@ -8,12 +8,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=linux-firmware
PKG_VERSION:=20200619
PKG_VERSION:=20201022
PKG_RELEASE:=1
PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_HASH:=962d3ae197d226c8259f9cc7746f7ef12a9d23787cd56bd27302021ba6339722
PKG_HASH:=bf586e0beb4c65f22bf0a79811f259aa0a5a7cc9f70eebecb260525b6914cef7
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>

View File

@ -20,12 +20,14 @@ define Package/mwifiex-pcie-firmware/install
endef
$(eval $(call BuildPackage,mwifiex-pcie-firmware))
Package/mwifiex-sdio-firmware = $(call Package/firmware-default,Marvell 8887 firmware)
Package/mwifiex-sdio-firmware = $(call Package/firmware-default,Marvell 8887/8997 firmware)
define Package/mwifiex-sdio-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/mrvl
$(INSTALL_DATA) \
$(PKG_BUILD_DIR)/mrvl/sd8887_uapsta.bin \
$(PKG_BUILD_DIR)/mrvl/sdsd8997_combo_v4.bin \
$(1)/lib/firmware/mrvl/
ln -s ../mrvl/sdsd8997_combo_v4.bin $(1)/lib/firmware/mrvl/sd8997_uapsta.bin
endef
$(eval $(call BuildPackage,mwifiex-sdio-firmware))

View File

@ -31,7 +31,7 @@ define Package/ath10k-firmware-qca9887/install
$(PKG_BUILD_DIR)/ath10k/QCA9887/hw1.0/board.bin \
$(1)/lib/firmware/ath10k/QCA9887/hw1.0/board.bin
endef
# $(eval $(call BuildPackage,ath10k-firmware-qca9887))
$(eval $(call BuildPackage,ath10k-firmware-qca9887))
Package/ath10k-firmware-qca9888 = $(call Package/firmware-default,ath10k qca9888 firmware)
define Package/ath10k-firmware-qca9888/install
@ -55,7 +55,7 @@ define Package/ath10k-firmware-qca988x/install
$(PKG_BUILD_DIR)/ath10k/QCA988X/hw2.0/firmware-5.bin \
$(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-5.bin
endef
# $(eval $(call BuildPackage,ath10k-firmware-qca988x))
$(eval $(call BuildPackage,ath10k-firmware-qca988x))
Package/ath10k-firmware-qca6174 = $(call Package/firmware-default,ath10k qca6174 firmware)
define Package/ath10k-firmware-qca6174/install

View File

@ -191,10 +191,10 @@ define KernelPackage/sound-soc-core
KCONFIG:= \
CONFIG_SND_SOC \
CONFIG_SND_SOC_ADI=n \
CONFIG_SND_SOC_DMAENGINE_PCM=y \
CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y \
CONFIG_SND_SOC_ALL_CODECS=n
FILES:=$(LINUX_DIR)/sound/soc/snd-soc-core.ko
AUTOLOAD:=$(call AutoLoad,55, snd-soc-core)
AUTOLOAD:=$(call AutoLoad,55,snd-soc-core)
$(call AddDepends/sound)
endef
@ -254,6 +254,20 @@ endef
$(eval $(call KernelPackage,sound-soc-imx-sgtl5000))
define KernelPackage/sound-soc-spdif
TITLE:=SoC S/PDIF codec support
KCONFIG:=CONFIG_SND_SOC_SPDIF
FILES:= \
$(LINUX_DIR)/sound/soc/codecs/snd-soc-spdif-tx.ko \
$(LINUX_DIR)/sound/soc/codecs/snd-soc-spdif-rx.ko
DEPENDS:=+kmod-sound-soc-core
AUTOLOAD:=$(call AutoProbe,snd-soc-spdif-tx snd-soc-spdif-rx)
$(call AddDepends/sound)
endef
$(eval $(call KernelPackage,sound-soc-spdif))
define KernelPackage/pcspkr
DEPENDS:=@TARGET_x86 +kmod-input-core
TITLE:=PC speaker support

View File

@ -34,6 +34,7 @@ drv_mac80211_init_device_config() {
config_add_boolean noscan ht_coex acs_exclude_dfs
config_add_array ht_capab
config_add_array channels
config_add_array scan_list
config_add_boolean \
rxldpc \
short_gi_80 \
@ -897,6 +898,7 @@ drv_mac80211_setup() {
rxantenna txantenna \
frag rts beacon_int:100 htmode
json_get_values basic_rate_list basic_rate
json_get_values scan_list scan_list
json_select ..
find_phy || {

View File

@ -0,0 +1,139 @@
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
@@ -78,6 +78,9 @@ struct rt2800_ops {
int (*drv_init_registers)(struct rt2x00_dev *rt2x00dev);
__le32 *(*drv_get_txwi)(struct queue_entry *entry);
unsigned int (*drv_get_dma_done)(struct data_queue *queue);
+ int (*hw_get_chippkg)(void);
+ int (*hw_get_chipver)(void);
+ int (*hw_get_chipeco)(void);
};
static inline u32 rt2800_register_read(struct rt2x00_dev *rt2x00dev,
@@ -195,6 +198,27 @@ static inline unsigned int rt2800_drv_ge
return rt2800ops->drv_get_dma_done(queue);
}
+static inline int rt2800_hw_get_chippkg(struct rt2x00_dev *rt2x00dev)
+{
+ const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;
+
+ return rt2800ops->hw_get_chippkg();
+}
+
+static inline int rt2800_hw_get_chipver(struct rt2x00_dev *rt2x00dev)
+{
+ const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;
+
+ return rt2800ops->hw_get_chipver();
+}
+
+static inline int rt2800_hw_get_chipeco(struct rt2x00_dev *rt2x00dev)
+{
+ const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;
+
+ return rt2800ops->hw_get_chipeco();
+}
+
void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
const u8 command, const u8 token,
const u8 arg0, const u8 arg1);
--- a/drivers/net/wireless/ralink/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800pci.c
@@ -286,6 +286,10 @@ static int rt2800pci_read_eeprom(struct
return retval;
}
+static int rt2800pci_get_chippkg(void) { return 0; }
+static int rt2800pci_get_chipver(void) { return 0; }
+static int rt2800pci_get_chipeco(void) { return 0; }
+
static const struct ieee80211_ops rt2800pci_mac80211_ops = {
.tx = rt2x00mac_tx,
.start = rt2x00mac_start,
@@ -328,6 +332,9 @@ static const struct rt2800_ops rt2800pci
.drv_init_registers = rt2800mmio_init_registers,
.drv_get_txwi = rt2800mmio_get_txwi,
.drv_get_dma_done = rt2800mmio_get_dma_done,
+ .hw_get_chippkg = rt2800pci_get_chippkg,
+ .hw_get_chipver = rt2800pci_get_chipver,
+ .hw_get_chipeco = rt2800pci_get_chipeco,
};
static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
--- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c
@@ -27,6 +27,12 @@
#include "rt2800lib.h"
#include "rt2800mmio.h"
+/* Needed to probe CHIP_VER register on MT7620 */
+#ifdef CONFIG_SOC_MT7620
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/mt7620.h>
+#endif
+
/* Allow hardware encryption to be disabled. */
static bool modparam_nohwcrypt;
module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
@@ -118,6 +124,27 @@ static int rt2800soc_write_firmware(stru
return 0;
}
+#ifdef CONFIG_SOC_MT7620
+static int rt2800soc_get_chippkg(void)
+{
+ return mt7620_get_pkg();
+}
+
+static int rt2800soc_get_chipver(void)
+{
+ return mt7620_get_chipver();
+}
+
+static int rt2800soc_get_chipeco(void)
+{
+ return mt7620_get_eco();
+}
+#else
+static int rt2800soc_get_chippkg(void) { return 0; }
+static int rt2800soc_get_chipver(void) { return 0; }
+static int rt2800soc_get_chipeco(void) { return 0; }
+#endif
+
static const struct ieee80211_ops rt2800soc_mac80211_ops = {
.tx = rt2x00mac_tx,
.start = rt2x00mac_start,
@@ -159,6 +186,9 @@ static const struct rt2800_ops rt2800soc
.drv_init_registers = rt2800mmio_init_registers,
.drv_get_txwi = rt2800mmio_get_txwi,
.drv_get_dma_done = rt2800mmio_get_dma_done,
+ .hw_get_chippkg = rt2800soc_get_chippkg,
+ .hw_get_chipver = rt2800soc_get_chipver,
+ .hw_get_chipeco = rt2800soc_get_chipeco,
};
static const struct rt2x00lib_ops rt2800soc_rt2x00_ops = {
--- a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c
@@ -628,6 +628,10 @@ static int rt2800usb_probe_hw(struct rt2
return 0;
}
+static int rt2800usb_get_chippkg(void) { return 0; }
+static int rt2800usb_get_chipver(void) { return 0; }
+static int rt2800usb_get_chipeco(void) { return 0; }
+
static const struct ieee80211_ops rt2800usb_mac80211_ops = {
.tx = rt2x00mac_tx,
.start = rt2x00mac_start,
@@ -671,6 +675,9 @@ static const struct rt2800_ops rt2800usb
.drv_init_registers = rt2800usb_init_registers,
.drv_get_txwi = rt2800usb_get_txwi,
.drv_get_dma_done = rt2800usb_get_dma_done,
+ .hw_get_chippkg = rt2800usb_get_chippkg,
+ .hw_get_chipver = rt2800usb_get_chipver,
+ .hw_get_chipeco = rt2800usb_get_chipeco,
};
static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {

View File

@ -0,0 +1,408 @@
--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
@@ -1042,6 +1042,11 @@
#define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
#define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
+#define BB_PA_MODE_CFG0 0x1214
+#define BB_PA_MODE_CFG1 0x1218
+#define RF_PA_MODE_CFG0 0x121C
+#define RF_PA_MODE_CFG1 0x1220
+
/*
* EDCA_AC0_CFG:
*/
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
@@ -3685,14 +3685,16 @@ static void rt2800_config_channel_rf7620
rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
- /* Default: XO=20MHz , SDM mode */
- rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
- rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
- rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
-
- rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
- rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
- rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ /* Default: XO=20MHz , SDM mode */
+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
+ rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
+ rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
+
+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
+ rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
+ rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
+ }
rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
@@ -3726,18 +3728,23 @@ static void rt2800_config_channel_rf7620
rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
}
- if (conf_is_ht40(conf)) {
- rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
- rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
- } else {
- rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
- rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ if (conf_is_ht40(conf)) {
+ rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
+ } else {
+ rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
+ }
}
- rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
- rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
- conf_is_ht40(conf) && (rf->channel == 11));
- rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
+ rt2800_hw_get_chipeco(rt2x00dev) == 2) {
+ rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
+ rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
+ conf_is_ht40(conf) && (rf->channel == 11));
+ rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
+ }
if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
if (conf_is_ht40(conf)) {
@@ -3837,25 +3844,29 @@ static void rt2800_config_alc(struct rt2
if (i == 10000)
rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
- if (chan->center_freq > 2457) {
- bbp = rt2800_bbp_read(rt2x00dev, 30);
- bbp = 0x40;
- rt2800_bbp_write(rt2x00dev, 30, bbp);
- rt2800_rfcsr_write(rt2x00dev, 39, 0);
- if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
- rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
- else
- rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
- } else {
- bbp = rt2800_bbp_read(rt2x00dev, 30);
- bbp = 0x1f;
- rt2800_bbp_write(rt2x00dev, 30, bbp);
- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
- if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
- rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
- else
- rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
+ if (chan->center_freq > 2457) {
+ bbp = rt2800_bbp_read(rt2x00dev, 30);
+ bbp = 0x40;
+ rt2800_bbp_write(rt2x00dev, 30, bbp);
+ rt2800_rfcsr_write(rt2x00dev, 39, 0);
+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
+ rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
+ else
+ rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
+ } else {
+ bbp = rt2800_bbp_read(rt2x00dev, 30);
+ bbp = 0x1f;
+ rt2800_bbp_write(rt2x00dev, 30, bbp);
+ rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
+ if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
+ rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
+ else
+ rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
+ }
}
+
rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
rt2800_vco_calibration(rt2x00dev);
@@ -5887,18 +5898,33 @@ static int rt2800_init_registers(struct
} else if (rt2x00_rt(rt2x00dev, RT5350)) {
rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
} else if (rt2x00_rt(rt2x00dev, RT6352)) {
- rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
- rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
- rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
- rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
- rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
- rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
- 0x3630363A);
- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
- 0x3630363A);
+ if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
+ 0x00000000);
+ rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
+ 0x000055FF);
+ rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
+ 0x00550055);
+ rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
+ 0x000055FF);
+ rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
+ 0x00550055);
+ } else {
+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
+ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
+ rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
+ rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
+ rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
+ rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
+ 0x6C6C666C);
+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
+ 0x6C6C666C);
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
+ 0x3630363A);
+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
+ 0x3630363A);
+ }
reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
@@ -7042,14 +7068,16 @@ static void rt2800_init_bbp_6352(struct
rt2800_bbp_write(rt2x00dev, 188, 0x00);
rt2800_bbp_write(rt2x00dev, 189, 0x00);
- rt2800_bbp_write(rt2x00dev, 91, 0x06);
- rt2800_bbp_write(rt2x00dev, 92, 0x04);
- rt2800_bbp_write(rt2x00dev, 93, 0x54);
- rt2800_bbp_write(rt2x00dev, 99, 0x50);
- rt2800_bbp_write(rt2x00dev, 148, 0x84);
- rt2800_bbp_write(rt2x00dev, 167, 0x80);
- rt2800_bbp_write(rt2x00dev, 178, 0xFF);
- rt2800_bbp_write(rt2x00dev, 106, 0x13);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ rt2800_bbp_write(rt2x00dev, 91, 0x06);
+ rt2800_bbp_write(rt2x00dev, 92, 0x04);
+ rt2800_bbp_write(rt2x00dev, 93, 0x54);
+ rt2800_bbp_write(rt2x00dev, 99, 0x50);
+ rt2800_bbp_write(rt2x00dev, 148, 0x84);
+ rt2800_bbp_write(rt2x00dev, 167, 0x80);
+ rt2800_bbp_write(rt2x00dev, 178, 0xFF);
+ rt2800_bbp_write(rt2x00dev, 106, 0x13);
+ }
/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
@@ -10388,31 +10416,36 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
- if (rt2800_clk_is_20mhz(rt2x00dev))
- rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
- else
- rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
- rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
- rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
- rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
- rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
- rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
- rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
- rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
- rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
- rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
- rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
- rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
-
- rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
- rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
- rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
+ if (rt2800_clk_is_20mhz(rt2x00dev))
+ rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
+ else
+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
+ rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
+ rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
+ rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
+ rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
+ rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
+ rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
+ rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
+ rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
+ rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
+ rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
+ rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
+ rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
+ rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
+ rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
+ rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
+ rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
+ }
+
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
+ rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
+ rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
+ rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
+ }
/* Initialize RF channel register to default value */
rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
@@ -10478,63 +10511,71 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
- rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
- rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
- rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
- rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
-
- rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
-
- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
-
- /* Initialize RF channel register for DRQFN */
- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
+ }
+
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
+
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
+ }
+
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
+ rt2800_hw_get_chipver(rt2x00dev) == 1) {
+ /* Initialize RF channel register for DRQFN */
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
+ }
/* Initialize RF DC calibration register to default value */
rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
@@ -10597,12 +10638,17 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
- rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
- rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
- rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
+ }
- rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
- rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
+ if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
+ rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
+ rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
+ }
rt2800_r_calibration(rt2x00dev);
rt2800_rf_self_txdc_cal(rt2x00dev);

View File

@ -0,0 +1,32 @@
From: Felix Fietkau <nbd@nbd.name>
Date: Mon, 28 Sep 2020 08:35:28 +0200
Subject: [PATCH] backports: add sched_set_fifo_low
It is needed for mt76
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
create mode 100644 backport/backport-include/linux/sched.h
--- /dev/null
+++ b/backport-include/linux/sched.h
@@ -0,0 +1,19 @@
+#ifndef __BACKPORT_LINUX_SCHED_H
+#define __BACKPORT_LINUX_SCHED_H
+
+#include_next <linux/sched.h>
+#include <linux/version.h>
+
+#if LINUX_VERSION_IS_LESS(5,9,0)
+#include <uapi/linux/sched/types.h>
+
+static inline void sched_set_fifo_low(struct task_struct *p)
+{
+ struct sched_param sparam = {.sched_priority = 1};
+
+ sched_setscheduler(p, SCHED_FIFO, &sparam);
+}
+
+#endif
+
+#endif

View File

@ -13,7 +13,18 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/net/mac80211/status.c
+++ b/net/mac80211/status.c
@@ -1129,6 +1129,8 @@ void ieee80211_tx_status_ext(struct ieee
@@ -991,10 +991,6 @@ static void __ieee80211_tx_status(struct
if (!(info->flags & IEEE80211_TX_CTL_INJECTED) && acked)
ieee80211_frame_acked(sta, skb);
- if ((sta->sdata->vif.type == NL80211_IFTYPE_STATION) &&
- ieee80211_hw_check(&local->hw, REPORTS_TX_ACK_STATUS))
- ieee80211_sta_tx_notify(sta->sdata, (void *) skb->data,
- acked, info->status.tx_time);
}
/* SNMP counters
@@ -1129,11 +1125,18 @@ void ieee80211_tx_status_ext(struct ieee
noack_success = !!(info->flags & IEEE80211_TX_STAT_NOACK_TRANSMITTED);
if (pubsta) {
@ -22,17 +33,38 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
if (!acked && !noack_success)
sta->status_stats.retry_failed++;
sta->status_stats.retry_count += retry_count;
@@ -1143,6 +1145,13 @@ void ieee80211_tx_status_ext(struct ieee
if (ieee80211_hw_check(&local->hw, REPORTS_TX_ACK_STATUS)) {
+ if (sdata->vif.type == NL80211_IFTYPE_STATION &&
+ skb && !(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP))
+ ieee80211_sta_tx_notify(sdata, (void *) skb->data,
+ acked, info->status.tx_time);
+
if (acked) {
sta->status_stats.last_ack = jiffies;
@@ -1143,6 +1146,11 @@ void ieee80211_tx_status_ext(struct ieee
/* Track when last packet was ACKed */
sta->status_stats.last_pkt_time = jiffies;
+ /* Reset connection monitor */
+ if (sdata->vif.type == NL80211_IFTYPE_STATION &&
+ unlikely(sdata->u.mgd.probe_send_count > 0)) {
+ unlikely(sdata->u.mgd.probe_send_count > 0))
+ sdata->u.mgd.probe_send_count = 0;
+ ieee80211_queue_work(&local->hw, &sdata->work);
+ }
+
if (info->status.is_valid_ack_signal) {
sta->status_stats.last_ack_signal =
(s8)info->status.ack_signal;
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
@@ -2508,7 +2508,9 @@ void ieee80211_sta_tx_notify(struct ieee
!sdata->u.mgd.probe_send_count)
return;
- if (!ack)
+ if (ack)
+ sdata->u.mgd.probe_send_count = 0;
+ else
sdata->u.mgd.nullfunc_failed = true;
ieee80211_queue_work(&sdata->local->hw, &sdata->work);
}

View File

@ -8,9 +8,9 @@ PKG_LICENSE_FILES:=
PKG_SOURCE_URL:=https://github.com/openwrt/mt76
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2020-08-25
PKG_SOURCE_VERSION:=b36d7ae096a3d8c7d6a8a246f2e8a471a467041e
PKG_MIRROR_HASH:=da35e999f1bd50ce7061125ccb976129c8485e3593521206831380846953d3cf
PKG_SOURCE_DATE:=2020-09-23
PKG_SOURCE_VERSION:=b22977c2727db7fea8d487573edb3aa668d8309d
PKG_MIRROR_HASH:=4182823ec5a97d842e7404b3c8139de8af4f35948008890d50e4dad95add996b
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_BUILD_PARALLEL:=1

View File

@ -5,9 +5,9 @@ PKG_NAME:=nat46
PKG_MIRROR_HASH:=d0bc80038cadeb7e857118e8d6bae242670ab27377af49f74bad494e0e5da598
PKG_SOURCE_URL:=https://github.com/ayourtch/nat46.git
PKG_SOURCE_DATE:=2020-08-06
PKG_SOURCE_DATE:=2020-08-17
PKG_SOURCE_PROTO:=git
PKG_SOURCE_VERSION:=71e9f0941a666c7010bb6d31d45bb795439038fa
PKG_SOURCE_VERSION:=362640b41ae52b732d9e9729e61ac555492442a3
PKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>
PKG_LICENSE:=GPL-2.0

View File

@ -898,6 +898,7 @@ wpa_supplicant_prepare_interface() {
fi
wpa_supplicant_teardown_interface "$ifname"
cat > "$_config" <<EOF
${scan_list:+freq_list=$scan_list}
$ap_scan
$country_str
EOF

View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=restool
PKG_VERSION:=LSDK-20.04
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/restool
@ -22,7 +22,7 @@ define Package/restool
SECTION:=net
CATEGORY:=Network
TITLE:=Layerscape DPAA2 dynamical management tool
DEPENDS:=@TARGET_layerscape
DEPENDS:=@TARGET_layerscape_armv8_64b
endef
MAKE_FLAGS += \

View File

@ -250,7 +250,7 @@ foreach my $mirror (@ARGV) {
push @mirrors, "ftp://ftp.riken.jp/Linux/kernel.org/$dir";
push @mirrors, "ftp://www.mirrorservice.org/sites/ftp.kernel.org/pub/$dir";
}
} elsif ($mirror =~ /^\@GNOME\/(.+)$/) {
} elsif ($mirror =~ /^\@GNOME\/(.+)$/) {
push @mirrors, "https://mirrors.ustc.edu.cn/gnome/sources/$1";
push @mirrors, "https://mirror.csclub.uwaterloo.ca/gnome/sources/$1";
push @mirrors, "http://ftp.acc.umu.se/pub/GNOME/sources/$1";
@ -260,13 +260,11 @@ foreach my $mirror (@ARGV) {
push @mirrors, "http://ftp.belnet.be/ftp.gnome.org/sources/$1";
push @mirrors, "ftp://ftp.cse.buffalo.edu/pub/Gnome/sources/$1";
push @mirrors, "ftp://ftp.nara.wide.ad.jp/pub/X11/GNOME/sources/$1";
}
else {
} else {
push @mirrors, $mirror;
}
}
push @mirrors, 'https://sources.cdn.openwrt.org';
#push @mirrors, 'https://mirror1.openwrt.org';
push @mirrors, 'https://sources.openwrt.org';
push @mirrors, 'https://mirror2.openwrt.org/sources';

View File

@ -48,7 +48,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
#include "xhci.h"
#include "xhci-trace.h"
@@ -60,6 +62,44 @@
@@ -62,6 +64,44 @@
#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
@ -93,7 +93,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
static const char hcd_name[] = "xhci_hcd";
static struct hc_driver __read_mostly xhci_pci_hc_driver;
@@ -291,6 +331,873 @@ static void xhci_pme_acpi_rtd3_enable(st
@@ -296,6 +336,873 @@ static void xhci_pme_acpi_rtd3_enable(st
static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
#endif /* CONFIG_ACPI */
@ -967,7 +967,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
/* called during probe() after chip reset completes */
static int xhci_pci_setup(struct usb_hcd *hcd)
{
@@ -332,6 +1239,27 @@ static int xhci_pci_probe(struct pci_dev
@@ -337,6 +1244,27 @@ static int xhci_pci_probe(struct pci_dev
struct hc_driver *driver;
struct usb_hcd *hcd;
@ -995,7 +995,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
driver = (struct hc_driver *)id->driver_data;
/* Prevent runtime suspending between USB-2 and USB-3 initialization */
@@ -393,6 +1321,16 @@ static void xhci_pci_remove(struct pci_d
@@ -398,6 +1326,16 @@ static void xhci_pci_remove(struct pci_d
{
struct xhci_hcd *xhci;
@ -1012,7 +1012,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
xhci = hcd_to_xhci(pci_get_drvdata(dev));
xhci->xhc_state |= XHCI_STATE_REMOVING;
@@ -520,6 +1458,11 @@ static int xhci_pci_resume(struct usb_hc
@@ -537,6 +1475,11 @@ static int xhci_pci_resume(struct usb_hc
if (pdev->vendor == PCI_VENDOR_ID_INTEL)
usb_enable_intel_xhci_ports(pdev);

View File

@ -13,7 +13,7 @@ produce a noisy warning.
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -278,6 +278,7 @@ static void xhci_pci_quirks(struct devic
@@ -283,6 +283,7 @@ static void xhci_pci_quirks(struct devic
pdev->device == 0x0015) {
xhci->quirks |= XHCI_RESET_ON_RESUME;
xhci->quirks |= XHCI_ZERO_64B_REGS;
@ -43,7 +43,7 @@ produce a noisy warning.
hcd->msi_enabled = 1;
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1880,6 +1880,7 @@ struct xhci_hcd {
@@ -1881,6 +1881,7 @@ struct xhci_hcd {
struct xhci_hub usb2_rhub;
struct xhci_hub usb3_rhub;
/* support xHCI 1.0 spec USB2 hardware LPM */

View File

@ -34,7 +34,7 @@ v2: use bool to indicate ongoing half-duplex send, use it afterwards
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1279,6 +1279,7 @@ config SERIAL_AR933X
@@ -1280,6 +1280,7 @@ config SERIAL_AR933X
tristate "AR933X serial port support"
depends on HAVE_CLK && ATH79
select SERIAL_CORE

View File

@ -13,7 +13,7 @@ Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -2265,8 +2265,15 @@ static int bcm2835_clk_probe(struct plat
@@ -2267,8 +2267,15 @@ static int bcm2835_clk_probe(struct plat
if (ret)
return ret;
@ -30,7 +30,7 @@ Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
}
static const struct cprman_plat_data cprman_bcm2835_plat_data = {
@@ -2292,7 +2299,11 @@ static struct platform_driver bcm2835_cl
@@ -2294,7 +2301,11 @@ static struct platform_driver bcm2835_cl
.probe = bcm2835_clk_probe,
};

View File

@ -14,7 +14,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1379,6 +1379,11 @@ bcm2835_register_pll_divider(struct bcm2
@@ -1381,6 +1381,11 @@ bcm2835_register_pll_divider(struct bcm2
divider->div.hw.init = &init;
divider->div.table = NULL;

View File

@ -36,7 +36,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return NULL;
@@ -1380,8 +1385,10 @@ bcm2835_register_pll_divider(struct bcm2
@@ -1382,8 +1387,10 @@ bcm2835_register_pll_divider(struct bcm2
divider->div.table = NULL;
if (!(cprman_read(cprman, data->cm_reg) & data->hold_mask)) {
@ -49,7 +49,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
}
divider->cprman = cprman;
@@ -2189,6 +2196,8 @@ static const struct bcm2835_clk_desc clk
@@ -2191,6 +2198,8 @@ static const struct bcm2835_clk_desc clk
.ctl_reg = CM_PERIICTL),
};
@ -58,7 +58,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
/*
* Permanently take a reference on the parent of the SDRAM clock.
*
@@ -2208,6 +2217,19 @@ static int bcm2835_mark_sdc_parent_criti
@@ -2210,6 +2219,19 @@ static int bcm2835_mark_sdc_parent_criti
return clk_prepare_enable(parent);
}
@ -78,7 +78,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static int bcm2835_clk_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -2218,6 +2240,7 @@ static int bcm2835_clk_probe(struct plat
@@ -2220,6 +2242,7 @@ static int bcm2835_clk_probe(struct plat
const size_t asize = ARRAY_SIZE(clk_desc_array);
const struct cprman_plat_data *pdata;
size_t i;
@ -86,7 +86,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
int ret;
pdata = of_device_get_match_data(&pdev->dev);
@@ -2237,6 +2260,13 @@ static int bcm2835_clk_probe(struct plat
@@ -2239,6 +2262,13 @@ static int bcm2835_clk_probe(struct plat
if (IS_ERR(cprman->regs))
return PTR_ERR(cprman->regs);

View File

@ -90,7 +90,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
.set_rate = bcm2835_clock_set_rate,
.determine_rate = bcm2835_clock_determine_rate,
.set_parent = bcm2835_clock_set_parent,
@@ -2239,6 +2267,7 @@ static int bcm2835_clk_probe(struct plat
@@ -2241,6 +2269,7 @@ static int bcm2835_clk_probe(struct plat
const struct bcm2835_clk_desc *desc;
const size_t asize = ARRAY_SIZE(clk_desc_array);
const struct cprman_plat_data *pdata;
@ -98,7 +98,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
size_t i;
u32 clk_id;
int ret;
@@ -2260,6 +2289,14 @@ static int bcm2835_clk_probe(struct plat
@@ -2262,6 +2291,14 @@ static int bcm2835_clk_probe(struct plat
if (IS_ERR(cprman->regs))
return PTR_ERR(cprman->regs);

View File

@ -20,7 +20,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1471,6 +1471,15 @@ static struct clk_hw *bcm2835_register_c
@@ -1473,6 +1473,15 @@ static struct clk_hw *bcm2835_register_c
init.flags = data->flags | CLK_IGNORE_UNUSED;
/*

View File

@ -14,7 +14,7 @@ use the same logic.
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2575,7 +2575,12 @@ static int pl011_setup_port(struct devic
@@ -2578,7 +2578,12 @@ static int pl011_setup_port(struct devic
if (IS_ERR(base))
return PTR_ERR(base);

View File

@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1650,6 +1650,23 @@ static void pl011_put_poll_char(struct u
@@ -1653,6 +1653,23 @@ static void pl011_put_poll_char(struct u
#endif /* CONFIG_CONSOLE_POLL */
@ -50,7 +50,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static int pl011_hwinit(struct uart_port *port)
{
struct uart_amba_port *uap =
@@ -1666,7 +1683,7 @@ static int pl011_hwinit(struct uart_port
@@ -1669,7 +1686,7 @@ static int pl011_hwinit(struct uart_port
if (retval)
return retval;
@ -59,7 +59,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
/* Clear pending error and receive interrupts */
pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
@@ -2321,7 +2338,7 @@ static int pl011_console_setup(struct co
@@ -2324,7 +2341,7 @@ static int pl011_console_setup(struct co
plat->init();
}
@ -68,7 +68,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
if (uap->vendor->fixed_options) {
baud = uap->fixed_baud;
@@ -2506,6 +2523,7 @@ static struct uart_driver amba_reg = {
@@ -2509,6 +2526,7 @@ static struct uart_driver amba_reg = {
.cons = AMBA_CONSOLE,
};
@ -76,7 +76,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static int pl011_probe_dt_alias(int index, struct device *dev)
{
struct device_node *np;
@@ -2537,6 +2555,7 @@ static int pl011_probe_dt_alias(int inde
@@ -2540,6 +2558,7 @@ static int pl011_probe_dt_alias(int inde
return ret;
}

View File

@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1383,6 +1383,7 @@ static bool pl011_tx_char(struct uart_am
@@ -1386,6 +1386,7 @@ static bool pl011_tx_char(struct uart_am
return false; /* unable to transmit character */
pl011_write(c, uap, REG_DR);

View File

@ -36,7 +36,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
- reg
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -2662,6 +2662,11 @@ static int pl011_probe(struct amba_devic
@@ -2665,6 +2665,11 @@ static int pl011_probe(struct amba_devic
if (IS_ERR(uap->clk))
return PTR_ERR(uap->clk);

View File

@ -234,7 +234,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
static int bcm2708_fb_register(struct bcm2708_fb *fb)
--- a/drivers/video/fbdev/core/fbmem.c
+++ b/drivers/video/fbdev/core/fbmem.c
@@ -1072,6 +1072,30 @@ fb_blank(struct fb_info *info, int blank
@@ -1076,6 +1076,30 @@ fb_blank(struct fb_info *info, int blank
}
EXPORT_SYMBOL(fb_blank);
@ -265,7 +265,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
@@ -1080,6 +1104,7 @@ static long do_fb_ioctl(struct fb_info *
@@ -1084,6 +1108,7 @@ static long do_fb_ioctl(struct fb_info *
struct fb_fix_screeninfo fix;
struct fb_cmap cmap_from;
struct fb_cmap_user cmap;
@ -273,7 +273,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
void __user *argp = (void __user *)arg;
long ret = 0;
@@ -1155,6 +1180,15 @@ static long do_fb_ioctl(struct fb_info *
@@ -1159,6 +1184,15 @@ static long do_fb_ioctl(struct fb_info *
unlock_fb_info(info);
console_unlock();
break;
@ -289,7 +289,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
default:
lock_fb_info(info);
fb = info->fbops;
@@ -1300,6 +1334,7 @@ static long fb_compat_ioctl(struct file
@@ -1304,6 +1338,7 @@ static long fb_compat_ioctl(struct file
case FBIOPAN_DISPLAY:
case FBIOGET_CON2FBMAP:
case FBIOPUT_CON2FBMAP:

View File

@ -20,7 +20,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
--- a/drivers/media/i2c/tc358743.c
+++ b/drivers/media/i2c/tc358743.c
@@ -1947,7 +1947,7 @@ static int tc358743_probe_of(struct tc35
@@ -1949,7 +1949,7 @@ static int tc358743_probe_of(struct tc35
state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
state->pdata.enable_hdcp = false;
/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */

View File

@ -24,7 +24,7 @@ Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
--- a/drivers/media/i2c/tc358743.c
+++ b/drivers/media/i2c/tc358743.c
@@ -1606,11 +1606,20 @@ static int tc358743_g_mbus_config(struct
@@ -1608,11 +1608,20 @@ static int tc358743_g_mbus_config(struct
struct v4l2_mbus_config *cfg)
{
struct tc358743_state *state = to_state(sd);
@ -47,7 +47,7 @@ Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
switch (state->csi_lanes_in_use) {
case 1:
@@ -2052,6 +2061,7 @@ static int tc358743_probe(struct i2c_cli
@@ -2054,6 +2063,7 @@ static int tc358743_probe(struct i2c_cli
if (pdata) {
state->pdata = *pdata;
state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;

View File

@ -13,7 +13,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
--- a/drivers/media/i2c/tc358743.c
+++ b/drivers/media/i2c/tc358743.c
@@ -1976,6 +1976,7 @@ static int tc358743_probe_of(struct tc35
@@ -1978,6 +1978,7 @@ static int tc358743_probe_of(struct tc35
/*
* The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
* The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
@ -21,7 +21,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
*/
bps_pr_lane = 2 * endpoint.link_frequencies[0];
if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
@@ -1988,23 +1989,41 @@ static int tc358743_probe_of(struct tc35
@@ -1990,23 +1991,41 @@ static int tc358743_probe_of(struct tc35
state->pdata.refclk_hz * state->pdata.pll_prd;
/*

View File

@ -78,7 +78,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
{
i2c_wrreg(sd, reg, val, 2);
@@ -2062,6 +2079,7 @@ static int tc358743_probe(struct i2c_cli
@@ -2064,6 +2081,7 @@ static int tc358743_probe(struct i2c_cli
struct tc358743_platform_data *pdata = client->dev.platform_data;
struct v4l2_subdev *sd;
u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
@ -86,7 +86,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
int err;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
@@ -2094,7 +2112,8 @@ static int tc358743_probe(struct i2c_cli
@@ -2096,7 +2114,8 @@ static int tc358743_probe(struct i2c_cli
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
/* i2c access */

View File

@ -26,7 +26,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
--- a/drivers/media/i2c/tc358743.c
+++ b/drivers/media/i2c/tc358743.c
@@ -1688,12 +1688,23 @@ static int tc358743_enum_mbus_code(struc
@@ -1690,12 +1690,23 @@ static int tc358743_enum_mbus_code(struc
return 0;
}
@ -51,7 +51,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
if (format->pad != 0)
return -EINVAL;
@@ -1703,23 +1714,7 @@ static int tc358743_get_fmt(struct v4l2_
@@ -1705,23 +1716,7 @@ static int tc358743_get_fmt(struct v4l2_
format->format.height = state->timings.bt.height;
format->format.field = V4L2_FIELD_NONE;
@ -76,7 +76,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
return 0;
}
@@ -1734,18 +1729,11 @@ static int tc358743_set_fmt(struct v4l2_
@@ -1736,18 +1731,11 @@ static int tc358743_set_fmt(struct v4l2_
int ret = tc358743_get_fmt(sd, cfg, format);
format->format.code = code;

View File

@ -13,7 +13,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -2352,7 +2352,7 @@ static int bcm2835_clk_probe(struct plat
@@ -2354,7 +2354,7 @@ static int bcm2835_clk_probe(struct plat
return ret;
/* note that we have registered all the clocks */

View File

@ -10,7 +10,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -247,6 +247,10 @@ static void xhci_pci_quirks(struct devic
@@ -252,6 +252,10 @@ static void xhci_pci_quirks(struct devic
pdev->device == 0x3432)
xhci->quirks |= XHCI_BROKEN_STREAMS;

View File

@ -42,7 +42,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
cprman_write(cprman, data->ctl_reg, ctl);
@@ -1492,7 +1496,7 @@ static struct clk_hw *bcm2835_register_c
@@ -1494,7 +1498,7 @@ static struct clk_hw *bcm2835_register_c
init.ops = &bcm2835_vpu_clock_clk_ops;
} else {
init.ops = &bcm2835_clock_clk_ops;

View File

@ -61,7 +61,7 @@ Signed-off-by: Eric Anholt <eric@anholt.net>
.determine_rate = bcm2835_clock_determine_rate,
.set_parent = bcm2835_clock_set_parent,
.get_parent = bcm2835_clock_get_parent,
@@ -1496,7 +1510,6 @@ static struct clk_hw *bcm2835_register_c
@@ -1498,7 +1512,6 @@ static struct clk_hw *bcm2835_register_c
init.ops = &bcm2835_vpu_clock_clk_ops;
} else {
init.ops = &bcm2835_clock_clk_ops;

View File

@ -15,7 +15,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1453,6 +1453,103 @@ command_cleanup:
@@ -1456,6 +1456,103 @@ command_cleanup:
}
/*
@ -119,7 +119,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
* non-error returns are a promise to giveback() the urb later
* we drop ownership so next owner (or urb unlink) can get it
*/
@@ -5335,6 +5432,7 @@ static const struct hc_driver xhci_hc_dr
@@ -5337,6 +5434,7 @@ static const struct hc_driver xhci_hc_dr
.endpoint_reset = xhci_endpoint_reset,
.check_bandwidth = xhci_check_bandwidth,
.reset_bandwidth = xhci_reset_bandwidth,

View File

@ -42,7 +42,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
#ifdef CONFIG_DMA_ENGINE
/* DMA stuff */
bool using_tx_dma;
@@ -813,6 +814,7 @@ __acquires(&uap->port.lock)
@@ -816,6 +817,7 @@ __acquires(&uap->port.lock)
if (!uap->using_tx_dma)
return;
@ -50,7 +50,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
dmaengine_terminate_async(uap->dmatx.chan);
if (uap->dmatx.queued) {
@@ -939,6 +941,7 @@ static void pl011_dma_rx_chars(struct ua
@@ -942,6 +944,7 @@ static void pl011_dma_rx_chars(struct ua
fifotaken = pl011_fifo_to_tty(uap);
}
@ -58,7 +58,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
spin_unlock(&uap->port.lock);
dev_vdbg(uap->port.dev,
"Took %d chars from DMA buffer and %d chars from the FIFO\n",
@@ -1347,6 +1350,7 @@ __acquires(&uap->port.lock)
@@ -1350,6 +1353,7 @@ __acquires(&uap->port.lock)
{
pl011_fifo_to_tty(uap);
@ -66,7 +66,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
spin_unlock(&uap->port.lock);
tty_flip_buffer_push(&uap->port.state->port);
/*
@@ -1482,6 +1486,7 @@ static irqreturn_t pl011_int(int irq, vo
@@ -1485,6 +1489,7 @@ static irqreturn_t pl011_int(int irq, vo
int handled = 0;
spin_lock_irqsave(&uap->port.lock, flags);
@ -74,7 +74,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
status = pl011_read(uap, REG_RIS) & uap->im;
if (status) {
do {
@@ -1501,7 +1506,7 @@ static irqreturn_t pl011_int(int irq, vo
@@ -1504,7 +1509,7 @@ static irqreturn_t pl011_int(int irq, vo
UART011_CTSMIS|UART011_RIMIS))
pl011_modem_status(uap);
if (status & UART011_TXIS)

View File

@ -23,7 +23,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -248,8 +248,10 @@ static void xhci_pci_quirks(struct devic
@@ -253,8 +253,10 @@ static void xhci_pci_quirks(struct devic
xhci->quirks |= XHCI_BROKEN_STREAMS;
if (pdev->vendor == PCI_VENDOR_ID_VIA &&
@ -85,6 +85,6 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
+#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(36)
#define XHCI_DISABLE_SPARSE BIT_ULL(38)
unsigned int num_active_eps;
unsigned int limit_active_eps;

View File

@ -12,7 +12,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -2278,9 +2278,11 @@ static bool bcm2835_clk_is_claimed(const
@@ -2280,9 +2280,11 @@ static bool bcm2835_clk_is_claimed(const
int i;
for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) {

View File

@ -33,7 +33,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
#define USB_VENDOR_ID_BELKIN 0x050d
#define USB_DEVICE_ID_FLIP_KVM 0x3201
@@ -1244,6 +1247,9 @@
@@ -1245,6 +1248,9 @@
#define USB_VENDOR_ID_XAT 0x2505
#define USB_DEVICE_ID_XAT_CSR 0x0220

View File

@ -12,7 +12,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1732,16 +1732,12 @@ static const struct bcm2835_clk_desc clk
@@ -1734,16 +1734,12 @@ static const struct bcm2835_clk_desc clk
.hold_mask = CM_PLLA_HOLDCORE,
.fixed_divider = 1,
.flags = CLK_SET_RATE_PARENT),
@ -35,7 +35,7 @@ Signed-off-by: popcornmix <popcornmix@gmail.com>
[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
SOC_ALL,
.name = "plla_dsi0",
@@ -2019,14 +2015,12 @@ static const struct bcm2835_clk_desc clk
@@ -2021,14 +2017,12 @@ static const struct bcm2835_clk_desc clk
.int_bits = 6,
.frac_bits = 0,
.tcnt_mux = 3),

View File

@ -25,7 +25,7 @@ Co-authored-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -2399,7 +2399,7 @@ static int __init __bcm2835_clk_driver_i
@@ -2401,7 +2401,7 @@ static int __init __bcm2835_clk_driver_i
{
return platform_driver_register(&bcm2835_clk_driver);
}

View File

@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1323,6 +1323,32 @@ static void pl011_start_tx(struct uart_p
@@ -1326,6 +1326,32 @@ static void pl011_start_tx(struct uart_p
pl011_start_tx_pio(uap);
}
@ -50,7 +50,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
static void pl011_stop_rx(struct uart_port *port)
{
struct uart_amba_port *uap =
@@ -2164,6 +2190,8 @@ static const struct uart_ops amba_pl011_
@@ -2167,6 +2193,8 @@ static const struct uart_ops amba_pl011_
.stop_tx = pl011_stop_tx,
.start_tx = pl011_start_tx,
.stop_rx = pl011_stop_rx,

View File

@ -29,7 +29,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.org>
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1444,6 +1444,10 @@ static bool pl011_tx_chars(struct uart_a
@@ -1447,6 +1447,10 @@ static bool pl011_tx_chars(struct uart_a
if (likely(from_irq) && count-- == 0)
break;

View File

@ -82,7 +82,7 @@ Cc: linux-rockchip@lists.infradead.org
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -1019,7 +1019,8 @@ static int advk_pcie_probe(struct platfo
@@ -1018,7 +1018,8 @@ static int advk_pcie_probe(struct platfo
return ret;
}
@ -402,7 +402,7 @@ Cc: linux-rockchip@lists.infradead.org
}
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -2277,6 +2277,7 @@ struct irq_domain;
@@ -2278,6 +2278,7 @@ struct irq_domain;
struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
int pci_parse_request_of_pci_ranges(struct device *dev,
struct list_head *resources,
@ -410,7 +410,7 @@ Cc: linux-rockchip@lists.infradead.org
struct resource **bus_range);
/* Arch may override this (weak) */
@@ -2285,9 +2286,11 @@ struct device_node *pcibios_get_phb_of_n
@@ -2286,9 +2287,11 @@ struct device_node *pcibios_get_phb_of_n
#else /* CONFIG_OF */
static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }

View File

@ -135,7 +135,7 @@ Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
/* Internal helper functions that deal with control events. */
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -427,6 +427,11 @@ struct v4l2_fract {
@@ -426,6 +426,11 @@ struct v4l2_fract {
__u32 denominator;
};
@ -147,7 +147,7 @@ Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
/**
* struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP
*
@@ -1725,6 +1730,7 @@ enum v4l2_ctrl_type {
@@ -1724,6 +1729,7 @@ enum v4l2_ctrl_type {
V4L2_CTRL_TYPE_U8 = 0x0100,
V4L2_CTRL_TYPE_U16 = 0x0101,
V4L2_CTRL_TYPE_U32 = 0x0102,

View File

@ -155,7 +155,7 @@ Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
*/
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -925,11 +925,12 @@ struct v4l2_requestbuffers {
@@ -924,11 +924,12 @@ struct v4l2_requestbuffers {
};
/* capabilities for struct v4l2_requestbuffers and v4l2_create_buffers */
@ -173,7 +173,7 @@ Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
/**
* struct v4l2_plane - plane info for multi-planar buffers
@@ -1051,6 +1052,8 @@ static inline __u64 v4l2_timeval_to_ns(c
@@ -1050,6 +1051,8 @@ static inline __u64 v4l2_timeval_to_ns(c
#define V4L2_BUF_FLAG_IN_REQUEST 0x00000080
/* timecode field is valid */
#define V4L2_BUF_FLAG_TIMECODE 0x00000100

View File

@ -47,7 +47,7 @@ Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
replace define V4L2_DEC_CMD_PAUSE_TO_BLACK decoder-cmds
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -1989,6 +1989,7 @@ struct v4l2_encoder_cmd {
@@ -1988,6 +1988,7 @@ struct v4l2_encoder_cmd {
#define V4L2_DEC_CMD_STOP (1)
#define V4L2_DEC_CMD_PAUSE (2)
#define V4L2_DEC_CMD_RESUME (3)

View File

@ -289,7 +289,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
case V4L2_PIX_FMT_YUV422M: descr = "Planar YUV 4:2:2 (N-C)"; break;
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -737,6 +737,10 @@ struct v4l2_pix_format {
@@ -736,6 +736,10 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */
#define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2') /* Sunxi Tiled NV12 Format */
#define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */

View File

@ -22,7 +22,7 @@ Signed-off-by: Maxime Ripard <maxime@cerno.tech>
#define MAX_TUNING_LOOP 40
@@ -2754,7 +2754,7 @@ static void sdhci_timeout_timer(struct t
@@ -2756,7 +2756,7 @@ static void sdhci_timeout_timer(struct t
spin_lock_irqsave(&host->lock, flags);
if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
@ -31,7 +31,7 @@ Signed-off-by: Maxime Ripard <maxime@cerno.tech>
mmc_hostname(host->mmc));
sdhci_dumpregs(host);
@@ -2776,7 +2776,7 @@ static void sdhci_timeout_data_timer(str
@@ -2778,7 +2778,7 @@ static void sdhci_timeout_data_timer(str
if (host->data || host->data_cmd ||
(host->cmd && sdhci_data_line_cmd(host->cmd))) {

View File

@ -75,7 +75,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
/* Compressed formats */
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -769,6 +769,7 @@ struct v4l2_pix_format {
@@ -768,6 +768,7 @@ struct v4l2_pix_format {
#define V4L2_META_FMT_VSP1_HGT v4l2_fourcc('V', 'S', 'P', 'T') /* R-Car VSP1 2-D Histogram */
#define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */
#define V4L2_META_FMT_D4XX v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */

View File

@ -84,7 +84,7 @@ Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
/* Compressed formats */
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -770,6 +770,7 @@ struct v4l2_pix_format {
@@ -769,6 +769,7 @@ struct v4l2_pix_format {
#define V4L2_META_FMT_UVC v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */
#define V4L2_META_FMT_D4XX v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */
#define V4L2_META_FMT_SENSOR_DATA v4l2_fourcc('S', 'E', 'N', 'S') /* Sensor Ancillary metadata */

View File

@ -10,7 +10,7 @@ Signed-off-by: Jacko Dirks <jdirks.linuxdev@gmail.com>
--- a/drivers/media/i2c/tc358743.c
+++ b/drivers/media/i2c/tc358743.c
@@ -2002,6 +2002,7 @@ static int tc358743_probe_of(struct tc35
@@ -2004,6 +2004,7 @@ static int tc358743_probe_of(struct tc35
switch (bps_pr_lane) {
default:
dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);

View File

@ -132,6 +132,6 @@ it on BCM4708 family.
#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
+#define XHCI_FAKE_DOORBELL BIT_ULL(36)
#define XHCI_DISABLE_SPARSE BIT_ULL(38)
unsigned int num_active_eps;
unsigned int limit_active_eps;

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