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qualcommax: ipq60xx: add reserved NSS memory nodes

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coolsnowwolf 2024-06-07 12:48:08 +08:00
parent a87cb8cd96
commit 5c11df48ac
2 changed files with 200 additions and 1 deletions
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194
target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-nss.dtsi Normal file
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@ -0,0 +1,194 @@
// SPDX-License-Identifier: GPL-2.0-only
/ {
nss_dummy_reg: nss-regulator {
compatible = "regulator-fixed";
regulator-name = "nss-reg";
regulator-min-microvolt = <848000>;
regulator-max-microvolt = <848000>;
regulator-always-on;
regulator-boot-on;
};
};
&soc {
nss-common {
compatible = "qcom,nss-common";
reg = <0x0 0x01868010 0x0 0x1000>, <0x0 0x40000000 0x0 0x1000>;
reg-names = "nss-misc-reset", "nss-misc-reset-flag";
memory-region = <&nss_region>;
};
nss0: nss@40000000 {
compatible = "qcom,nss";
interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>,
<0 399 0x1>, <0 398 0x1>, <0 397 0x1>,
<0 396 0x1>, <0 395 0x1>, <0 394 0x1>,
<0 393 0x1>;
reg = <0x0 0x39000000 0x0 0x1000>, <0x0 0x0b111000 0x0 0x1000>;
reg-names = "nphys", "qgic-phys";
clocks = <&gcc GCC_NSS_NOC_CLK>,
<&gcc GCC_NSS_PTP_REF_CLK>,
<&gcc GCC_NSS_CSR_CLK>, <&gcc GCC_NSS_CFG_CLK>,
<&gcc GCC_NSSNOC_QOSGEN_REF_CLK>,
<&gcc GCC_NSSNOC_SNOC_CLK>,
<&gcc GCC_NSSNOC_TIMEOUT_REF_CLK>,
<&gcc GCC_MEM_NOC_UBI32_CLK>,
<&gcc GCC_NSS_CE_AXI_CLK>,
<&gcc GCC_NSS_CE_APB_CLK>,
<&gcc GCC_NSSNOC_CE_AXI_CLK>,
<&gcc GCC_NSSNOC_CE_APB_CLK>,
<&gcc GCC_NSSNOC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_CORE_CLK>,
<&gcc GCC_UBI0_AHB_CLK>,
<&gcc GCC_UBI0_AXI_CLK>,
<&gcc GCC_UBI0_NC_AXI_CLK>,
<&gcc GCC_UBI0_UTCM_CLK>,
<&gcc GCC_SNOC_NSSNOC_CLK>;
clock-names = "nss-noc-clk", "nss-ptp-ref-clk",
"nss-csr-clk", "nss-cfg-clk",
"nss-nssnoc-qosgen-ref-clk",
"nss-nssnoc-snoc-clk",
"nss-nssnoc-timeout-ref-clk",
"nss-mem-noc-ubi32-clk",
"nss-ce-axi-clk", "nss-ce-apb-clk",
"nss-nssnoc-ce-axi-clk",
"nss-nssnoc-ce-apb-clk",
"nss-nssnoc-ahb-clk",
"nss-core-clk", "nss-ahb-clk",
"nss-axi-clk", "nss-nc-axi-clk",
"nss-utcm-clk", "nss-snoc-nssnoc-clk";
qcom,id = <0>;
qcom,num-queue = <4>;
qcom,num-irq = <10>;
qcom,num-pri = <4>;
qcom,load-addr = <0x40000000>;
qcom,low-frequency = <187200000>;
qcom,mid-frequency = <748800000>;
qcom,max-frequency = <1497600000>;
qcom,bridge-enabled;
qcom,ipv4-enabled;
qcom,ipv4-reasm-enabled;
qcom,ipv6-enabled;
qcom,ipv6-reasm-enabled;
qcom,wlanredirect-enabled;
qcom,tun6rd-enabled;
qcom,l2tpv2-enabled;
qcom,gre-enabled;
qcom,gre-redir-enabled;
qcom,gre-redir-mark-enabled;
qcom,map-t-enabled;
qcom,portid-enabled;
qcom,ppe-enabled;
qcom,pppoe-enabled;
qcom,pptp-enabled;
qcom,tunipip6-enabled;
qcom,shaping-enabled;
qcom,wlan-dataplane-offload-enabled;
qcom,vlan-enabled;
qcom,capwap-enabled;
qcom,dtls-enabled;
qcom,tls-enabled;
qcom,crypto-enabled;
qcom,ipsec-enabled;
qcom,qvpn-enabled;
qcom,pvxlan-enabled;
qcom,clmap-enabled;
qcom,vxlan-enabled;
qcom,match-enabled;
qcom,mirror-enabled;
mx-supply = <&nss_dummy_reg>;
npu-supply = <&nss_dummy_reg>;
};
nss_crypto: qcom,nss_crypto {
compatible = "qcom,nss-crypto";
#address-cells = <1>;
#size-cells = <1>;
qcom,max-contexts = <64>;
qcom,max-context-size = <32>;
ranges;
eip197_node {
compatible = "qcom,eip197";
reg-names = "crypto_pbase";
reg = <0x39800000 0x7ffff>;
clocks = <&gcc GCC_NSS_CRYPTO_CLK>,
<&gcc GCC_NSSNOC_CRYPTO_CLK>,
<&gcc GCC_CRYPTO_PPE_CLK>;
clock-names = "crypto_clk", "crypto_nocclk",
"crypto_ppeclk";
clock-frequency = /bits/ 64 <300000000 300000000 300000000>;
qcom,dma-mask = <0xff>;
qcom,transform-enabled;
qcom,aes128-cbc;
qcom,aes192-cbc;
qcom,aes256-cbc;
qcom,aes128-ctr;
qcom,aes192-ctr;
qcom,aes256-ctr;
qcom,aes128-ecb;
qcom,aes192-ecb;
qcom,aes256-ecb;
qcom,3des-cbc;
qcom,md5-hash;
qcom,sha160-hash;
qcom,sha224-hash;
qcom,sha256-hash;
qcom,sha384-hash;
qcom,sha512-hash;
qcom,md5-hmac;
qcom,sha160-hmac;
qcom,sha224-hmac;
qcom,sha256-hmac;
qcom,sha384-hmac;
qcom,sha512-hmac;
qcom,aes128-gcm-gmac;
qcom,aes192-gcm-gmac;
qcom,aes256-gcm-gmac;
qcom,aes128-cbc-md5-hmac;
qcom,aes128-cbc-sha160-hmac;
qcom,aes192-cbc-md5-hmac;
qcom,aes192-cbc-sha160-hmac;
qcom,aes256-cbc-md5-hmac;
qcom,aes256-cbc-sha160-hmac;
qcom,aes128-ctr-sha160-hmac;
qcom,aes192-ctr-sha160-hmac;
qcom,aes256-ctr-sha160-hmac;
qcom,aes128-ctr-md5-hmac;
qcom,aes192-ctr-md5-hmac;
qcom,aes256-ctr-md5-hmac;
qcom,3des-cbc-md5-hmac;
qcom,3des-cbc-sha160-hmac;
qcom,aes128-cbc-sha256-hmac;
qcom,aes192-cbc-sha256-hmac;
qcom,aes256-cbc-sha256-hmac;
qcom,aes128-ctr-sha256-hmac;
qcom,aes192-ctr-sha256-hmac;
qcom,aes256-ctr-sha256-hmac;
qcom,3des-cbc-sha256-hmac;
qcom,aes128-cbc-sha384-hmac;
qcom,aes192-cbc-sha384-hmac;
qcom,aes256-cbc-sha384-hmac;
qcom,aes128-ctr-sha384-hmac;
qcom,aes192-ctr-sha384-hmac;
qcom,aes256-ctr-sha384-hmac;
qcom,aes128-cbc-sha512-hmac;
qcom,aes192-cbc-sha512-hmac;
qcom,aes256-cbc-sha512-hmac;
qcom,aes128-ctr-sha512-hmac;
qcom,aes192-ctr-sha512-hmac;
qcom,aes256-ctr-sha512-hmac;
engine0 {
reg_offset = <0x80000>;
qcom,ifpp-enabled;
qcom,ipue-enabled;
qcom,ofpp-enabled;
qcom,opue-enabled;
};
};
};
};

7
target/linux/qualcommax/patches-6.1/0133-arm64-dts-ipq6018-add-reserved-memory-nodes.patch
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@ -1,10 +1,15 @@
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -212,6 +212,16 @@
@@ -212,6 +212,21 @@
reg = <0x0 0x4ab00000 0x0 0x5500000>;
no-map;
};
+
+ nss_region: nss@40000000 {
+ no-map;
+ reg = <0x0 0x40000000 0x0 0x01000000>;
+ };
+
+ q6_etr_region: q6_etr_dump@50000000 {
+ reg = <0x0 0x50000000 0x0 0x100000>;
+ no-map;