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kernel: 5.18: refresh patches

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This commit is contained in:
lean 2022-07-10 17:49:04 +08:00
parent 31dacf9899
commit 53951abdef
8 changed files with 25 additions and 26 deletions
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2
target/linux/rockchip/patches-5.18/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
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@ -31,7 +31,7 @@ Signed-off-by: wevsty <ty@wevs.org>
reg = <0x0 0xff100000 0x0 0x1000>; reg = <0x0 0xff100000 0x0 0x1000>;
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1937,6 +1937,16 @@ @@ -2017,6 +2017,16 @@
}; };
}; };

2
target/linux/rockchip/patches-5.18/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch
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@ -40,5 +40,5 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o +obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o

2
target/linux/rockchip/patches-5.18/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch
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@ -11,7 +11,7 @@ Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -1010,6 +1010,13 @@ @@ -1005,6 +1005,13 @@
status = "disabled"; status = "disabled";
}; };

8
target/linux/rockchip/patches-5.18/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
View File

@ -24,7 +24,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
#include "rk3328.dtsi" #include "rk3328.dtsi"
/ { / {
@@ -119,6 +120,72 @@ @@ -121,6 +122,72 @@
regulator-boot-on; regulator-boot-on;
vin-supply = <&vdd_5v>; vin-supply = <&vdd_5v>;
}; };
@ -97,7 +97,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
}; };
&cpu0 { &cpu0 {
@@ -137,6 +204,10 @@ @@ -139,6 +206,10 @@
cpu-supply = <&vdd_arm>; cpu-supply = <&vdd_arm>;
}; };
@ -108,7 +108,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
&display_subsystem { &display_subsystem {
status = "disabled"; status = "disabled";
}; };
@@ -206,6 +277,7 @@ @@ -202,6 +273,7 @@
regulator-name = "vdd_log"; regulator-name = "vdd_log";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
@ -116,7 +116,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
regulator-min-microvolt = <712500>; regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>; regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>; regulator-ramp-delay = <12500>;
@@ -220,6 +292,7 @@ @@ -216,6 +288,7 @@
regulator-name = "vdd_arm"; regulator-name = "vdd_arm";
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;

6
target/linux/rockchip/patches-5.18/900-arm-boot-add-dts-files.patch
View File

@ -1,6 +1,6 @@
--- a/arch/arm64/boot/dts/rockchip/Makefile --- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -9,8 +9,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb @@ -9,8 +9,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
@ -13,7 +13,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
@@ -22,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb @@ -22,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-or
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
@ -21,7 +21,7 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb
@@ -40,6 +45,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb @@ -40,6 +45,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-na
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb

1
target/linux/rockchip/patches-5.18/901-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch
View File

@ -19,4 +19,3 @@
/ { / {
aliases { aliases {

2
target/linux/rockchip/patches-5.18/902-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
View File

@ -20,7 +20,7 @@ Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -140,6 +140,21 @@ opp-1296000000 { @@ -140,6 +140,21 @@
opp-microvolt = <1300000>; opp-microvolt = <1300000>;
clock-latency-ns = <40000>; clock-latency-ns = <40000>;
}; };

28
target/linux/x86/patches-5.18/993-bnx2x_warpcore_8727_2_5g_sgmii_txfault.patch
View File

@ -43,7 +43,7 @@
val16 |= 0x0040; val16 |= 0x0040;
break; break;
default: default:
@@ -8172,6 +8184,7 @@ static int bnx2x_get_edc_mode(struct bnx @@ -8174,6 +8186,7 @@ static int bnx2x_get_edc_mode(struct bnx
break; break;
} }
case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
@ -51,7 +51,7 @@
case SFP_EEPROM_CON_TYPE_VAL_LC: case SFP_EEPROM_CON_TYPE_VAL_LC:
case SFP_EEPROM_CON_TYPE_VAL_RJ45: case SFP_EEPROM_CON_TYPE_VAL_RJ45:
check_limiting_mode = 1; check_limiting_mode = 1;
@@ -8182,7 +8195,8 @@ static int bnx2x_get_edc_mode(struct bnx @@ -8184,7 +8197,8 @@ static int bnx2x_get_edc_mode(struct bnx
(val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
DP(NETIF_MSG_LINK, "1G SFP module detected\n"); DP(NETIF_MSG_LINK, "1G SFP module detected\n");
phy->media_type = ETH_PHY_SFP_1G_FIBER; phy->media_type = ETH_PHY_SFP_1G_FIBER;
@ -61,7 +61,7 @@
u8 gport = params->port; u8 gport = params->port;
phy->req_line_speed = SPEED_1000; phy->req_line_speed = SPEED_1000;
if (!CHIP_IS_E1x(bp)) { if (!CHIP_IS_E1x(bp)) {
@@ -8342,7 +8356,7 @@ static int bnx2x_wait_for_sfp_module_ini @@ -8344,7 +8358,7 @@ static int bnx2x_wait_for_sfp_module_ini
* some phys type ( e.g. JDSU ) * some phys type ( e.g. JDSU )
*/ */
@ -70,7 +70,7 @@
if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
rc = bnx2x_warpcore_read_sfp_module_eeprom( rc = bnx2x_warpcore_read_sfp_module_eeprom(
phy, params, I2C_DEV_ADDR_A0, 1, 1, &val, phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
@@ -9236,6 +9250,7 @@ static void bnx2x_8727_config_speed(stru @@ -9238,6 +9252,7 @@ static void bnx2x_8727_config_speed(stru
u16 tmp1, val; u16 tmp1, val;
/* Set option 1G speed */ /* Set option 1G speed */
if ((phy->req_line_speed == SPEED_1000) || if ((phy->req_line_speed == SPEED_1000) ||
@ -78,7 +78,7 @@
(phy->media_type == ETH_PHY_SFP_1G_FIBER)) { (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
DP(NETIF_MSG_LINK, "Setting 1G force\n"); DP(NETIF_MSG_LINK, "Setting 1G force\n");
bnx2x_cl45_write(bp, phy, bnx2x_cl45_write(bp, phy,
@@ -9245,6 +9260,22 @@ static void bnx2x_8727_config_speed(stru @@ -9247,6 +9262,22 @@ static void bnx2x_8727_config_speed(stru
bnx2x_cl45_read(bp, phy, bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
@ -101,7 +101,7 @@
/* Power down the XAUI until link is up in case of dual-media /* Power down the XAUI until link is up in case of dual-media
* and 1G * and 1G
*/ */
@@ -9266,7 +9297,7 @@ static void bnx2x_8727_config_speed(stru @@ -9268,7 +9299,7 @@ static void bnx2x_8727_config_speed(stru
DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
bnx2x_cl45_write(bp, phy, bnx2x_cl45_write(bp, phy,
@ -110,7 +110,7 @@
bnx2x_cl45_write(bp, phy, bnx2x_cl45_write(bp, phy,
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
} else { } else {
@@ -9274,9 +9305,12 @@ static void bnx2x_8727_config_speed(stru @@ -9276,9 +9307,12 @@ static void bnx2x_8727_config_speed(stru
* registers although it is default * registers although it is default
*/ */
bnx2x_cl45_write(bp, phy, bnx2x_cl45_write(bp, phy,
@ -124,7 +124,7 @@
MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
bnx2x_cl45_write(bp, phy, bnx2x_cl45_write(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
@@ -9565,6 +9599,11 @@ static u8 bnx2x_8727_read_status(struct @@ -9567,6 +9601,11 @@ static u8 bnx2x_8727_read_status(struct
vars->line_speed = SPEED_10000; vars->line_speed = SPEED_10000;
DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n", DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
params->port); params->port);
@ -136,7 +136,7 @@
} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
link_up = 1; link_up = 1;
vars->line_speed = SPEED_1000; vars->line_speed = SPEED_1000;
@@ -9596,7 +9635,8 @@ static u8 bnx2x_8727_read_status(struct @@ -9598,7 +9637,8 @@ static u8 bnx2x_8727_read_status(struct
} }
if ((DUAL_MEDIA(params)) && if ((DUAL_MEDIA(params)) &&
@ -146,7 +146,7 @@
bnx2x_cl45_read(bp, phy, bnx2x_cl45_read(bp, phy,
MDIO_PMA_DEVAD, MDIO_PMA_DEVAD,
MDIO_PMA_REG_8727_PCS_GP, &val1); MDIO_PMA_REG_8727_PCS_GP, &val1);
@@ -11720,6 +11760,7 @@ static const struct bnx2x_phy phy_warpco @@ -11722,6 +11762,7 @@ static const struct bnx2x_phy phy_warpco
SUPPORTED_100baseT_Full | SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Full |
SUPPORTED_1000baseKX_Full | SUPPORTED_1000baseKX_Full |
@ -154,7 +154,7 @@
SUPPORTED_10000baseT_Full | SUPPORTED_10000baseT_Full |
SUPPORTED_10000baseKR_Full | SUPPORTED_10000baseKR_Full |
SUPPORTED_20000baseKR2_Full | SUPPORTED_20000baseKR2_Full |
@@ -11906,6 +11947,7 @@ static const struct bnx2x_phy phy_8727 = @@ -11908,6 +11949,7 @@ static const struct bnx2x_phy phy_8727 =
.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
.mdio_ctrl = 0, .mdio_ctrl = 0,
.supported = (SUPPORTED_10000baseT_Full | .supported = (SUPPORTED_10000baseT_Full |
@ -162,7 +162,7 @@
SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Full |
SUPPORTED_FIBRE | SUPPORTED_FIBRE |
SUPPORTED_Pause | SUPPORTED_Pause |
@@ -12253,6 +12295,7 @@ static int bnx2x_populate_int_phy(struct @@ -12255,6 +12297,7 @@ static int bnx2x_populate_int_phy(struct
break; break;
case PORT_HW_CFG_NET_SERDES_IF_SFI: case PORT_HW_CFG_NET_SERDES_IF_SFI:
phy->supported &= (SUPPORTED_1000baseT_Full | phy->supported &= (SUPPORTED_1000baseT_Full |
@ -170,7 +170,7 @@
SUPPORTED_10000baseT_Full | SUPPORTED_10000baseT_Full |
SUPPORTED_FIBRE | SUPPORTED_FIBRE |
SUPPORTED_Pause | SUPPORTED_Pause |
@@ -13937,7 +13980,8 @@ void bnx2x_period_func(struct link_param @@ -13939,7 +13982,8 @@ void bnx2x_period_func(struct link_param
& PORT_HW_CFG_NET_SERDES_IF_MASK) == & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
PORT_HW_CFG_NET_SERDES_IF_SFI) { PORT_HW_CFG_NET_SERDES_IF_SFI) {
if (bnx2x_is_sfp_module_plugged(phy, params)) { if (bnx2x_is_sfp_module_plugged(phy, params)) {
@ -193,7 +193,7 @@
static int int_mode; static int int_mode;
module_param(int_mode, int, 0444); module_param(int_mode, int, 0444);
MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X " MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
@@ -12336,6 +12340,8 @@ static int bnx2x_init_bp(struct bnx2x *b @@ -12342,6 +12346,8 @@ static int bnx2x_init_bp(struct bnx2x *b
if (BP_NOMCP(bp) && (func == 0)) if (BP_NOMCP(bp) && (func == 0))
dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");