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filogic: add support for ASUS TUF AX6000
Hardware ======== SOC: MediaTek MT7986 RAM: 512MB DDR3 FLASH: 256MB SPI-NAND WIFI: Mediatek MT7986 DBDC 802.11ax 2.4/5 GHz 4T4R ETH: MediaTek MT7530 Switch (LAN) MaxLinear GPY211C 2.5 N-Base-T PHY (WAN) MaxLinear GPY211C 2.5 N-Base-T PHY (LAN) UART: 3V3 115200 8N1 (Do not connect VCC) USB 3.1 Signed-off-by: Patryk Kowalczyk <patryk@kowalczyk.ws>
This commit is contained in:
Patryk Kowalczyk
parent
8a28dd39d4
commit
4a7dd142ff
394
target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
Normal file
394
target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts
Normal file
@ -0,0 +1,394 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7986a.dtsi"
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/ {
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model = "ASUS TUF-AX6000";
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compatible = "asus,tuf-ax6000", "mediatek,mt7986a";
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aliases {
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serial0 = &uart0;
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led-boot = &led_system;
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led-failsafe = &led_system;
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led-running = &led_system;
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led-upgrade = &led_system;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs-override = "ubi.mtd=UBI_DEV";
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};
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memory {
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reg = <0 0x40000000 0 0x20000000>;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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mesh {
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label = "wps";
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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wlan {
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label = "white:wlan";
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gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy1tpt";
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};
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led_system: system {
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label = "white:system";
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gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
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};
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wan-red {
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label = "red:wan";
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gpios = <&pio 12 GPIO_ACTIVE_LOW>;
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};
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cover-blue {
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label = "blue:cover";
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gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
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};
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cover-red {
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label = "red:cover";
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gpios = <&pio 21 GPIO_ACTIVE_HIGH>;
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};
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cover-green {
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label = "green:cover";
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gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
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};
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "2500base-x";
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phy-handle = <&phy6>;
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&mdio {
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reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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reset-delay-us = <50000>;
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reset-post-delay-us = <20000>;
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phy5: phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <5>;
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mxl,led-drive-vdd;
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mxl,led-config = <0x03f0 0x0 0x0 0x0>;
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};
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phy6: phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <6>;
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/* LED0: CONN (WAN white) */
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mxl,led-config = <0x03f0 0x0 0x0 0x0>;
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};
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switch: switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
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reset-assert-us = <10000>;
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reset-deassert-us = <10000>;
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};
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};
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&pio {
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spi_flash_pins: spi-flash-pins-33-to-38 {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <8>;
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mediatek,pull-down-adv = <0>; /* bias-disable */
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};
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};
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wf_2g_5g_pins: wf_2g_5g-pins {
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mux {
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function = "wifi";
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groups = "wf_2g", "wf_5g";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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wf_dbdc_pins: wf-dbdc-pins {
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mux {
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function = "wifi";
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groups = "wf_dbdc";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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};
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&pcie_phy {
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status = "okay";
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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status = "okay";
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flash@0 {
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compatible = "spi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <20000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x400000>;
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label = "bootloader";
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read-only;
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};
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partition@400000 {
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reg = <0x400000 0xfc00000>;
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label = "UBI_DEV";
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};
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};
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan4";
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phy-handle = <&swphy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-handle = <&swphy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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phy-handle = <&swphy3>;
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};
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port@4 {
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reg = <4>;
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label = "lan1";
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phy-handle = <&swphy4>;
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};
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port@5 {
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reg = <5>;
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label = "lan5";
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phy-handle = <&phy5>;
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phy-mode = "2500base-x";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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swphy1: phy@1 {
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reg = <1>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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swphy2: phy@2 {
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reg = <2>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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swphy3: phy@3 {
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reg = <3>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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swphy4: phy@4 {
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reg = <4>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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};
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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pinctrl-names = "default", "dbdc";
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pinctrl-0 = <&wf_2g_5g_pins>;
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pinctrl-1 = <&wf_dbdc_pins>;
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status = "okay";
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};
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&trng {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&ssusb {
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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status = "okay";
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};
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&usb_phy {
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status = "okay";
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};
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@ -21,6 +21,13 @@ mediatek_setup_interfaces()
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ruijie,rg-x60-pro)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
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;;
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asus,tuf-ax6000|\
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glinet,gl-mt6000|\
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tplink,tl-xdr4288|\
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tplink,tl-xdr6088|\
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tplink,tl-xtr8488)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
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;;
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bananapi,bpi-r3)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan"
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;;
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@ -54,12 +61,6 @@ mediatek_setup_interfaces()
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mediatek,mt7988a-rfb)
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ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3 eth1" eth2
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;;
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glinet,gl-mt6000|\
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tplink,tl-xdr4288|\
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tplink,tl-xdr6088|\
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tplink,tl-xtr8488)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
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;;
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tplink,tl-xdr6086)
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ucidef_set_interfaces_lan_wan "lan1 lan2" eth1
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;;
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@ -82,7 +83,8 @@ mediatek_setup_macs()
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local label_mac=""
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case $board in
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asus,tuf-ax4200)
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asus,tuf-ax4200|\
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asus,tuf-ax6000)
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CI_UBIPART="UBI_DEV"
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addr=$(mtd_get_mac_binary_ubi "Factory" 0x4)
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wan_mac="${addr}"
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@ -27,6 +27,10 @@ case "$FIRMWARE" in
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;;
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"mediatek/mt7986_eeprom_mt7976_dual.bin")
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case "$board" in
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asus,tuf-ax6000)
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CI_UBIPART="UBI_DEV"
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caldata_extract_ubi "Factory" 0x0 0x1000
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;;
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glinet,gl-mt6000|\
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jdcloud,re-cs-05)
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caldata_extract_mmc "factory" 0x0 0x1000
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@ -15,7 +15,8 @@ case "$board" in
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[ "$PHYNBR" = "1" ] && \
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macaddr_setbit_la "$(macaddr_add $addr 0x600000)" > /sys${DEVPATH}/macaddress
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;;
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asus,tuf-ax4200)
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asus,tuf-ax4200|\
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asus,tuf-ax6000)
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CI_UBIPART="UBI_DEV"
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addr=$(mtd_get_mac_binary_ubi "Factory" 0x4)
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# Originally, phy0 is phy1 mac with LA bit set. However, this would conflict
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@ -2,7 +2,8 @@
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preinit_set_mac_address() {
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case $(board_name) in
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asus,tuf-ax4200)
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asus,tuf-ax4200|\
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asus,tuf-ax6000)
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CI_UBIPART="UBI_DEV"
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addr=$(mtd_get_mac_binary_ubi "Factory" 0x4)
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ip link set dev eth0 address "$addr"
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@ -16,7 +16,8 @@ platform_do_upgrade() {
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local board=$(board_name)
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case "$board" in
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asus,tuf-ax4200)
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asus,tuf-ax4200|\
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asus,tuf-ax6000)
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CI_UBIPART="UBI_DEV"
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CI_KERNPART="linux"
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nand_do_upgrade "$1"
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@ -97,6 +97,22 @@ define Device/asus_tuf-ax4200
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endef
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TARGET_DEVICES += asus_tuf-ax4200
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define Device/asus_tuf-ax6000
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DEVICE_VENDOR := ASUS
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DEVICE_MODEL := TUF-AX6000
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DEVICE_DTS := mt7986a-asus-tuf-ax6000
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DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_DTS_LOADADDR := 0x47000000
|
||||
DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
|
||||
IMAGES := sysupgrade.bin
|
||||
KERNEL := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += asus_tuf-ax6000
|
||||
|
||||
define Device/bananapi_bpi-r3
|
||||
DEVICE_VENDOR := Bananapi
|
||||
DEVICE_MODEL := BPi-R3
|
||||
|
||||
Loading…
Reference in New Issue
Block a user