mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
ipq806x: sync upstream source code (#5320)
This commit is contained in:
AmadeusGhost
GitHub
parent
7ba6311016
commit
46524d9336
@ -70,24 +70,6 @@ endef
|
||||
$(eval $(call KernelPackage,usb-phy-nop))
|
||||
|
||||
|
||||
define KernelPackage/usb-phy-qcom-dwc3
|
||||
TITLE:=DWC3 USB QCOM PHY driver
|
||||
DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x)
|
||||
KCONFIG:= CONFIG_PHY_QCOM_DWC3
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-dwc3.ko
|
||||
AUTOLOAD:=$(call AutoLoad,45,phy-qcom-dwc3,1)
|
||||
$(call AddDepends/usb)
|
||||
endef
|
||||
|
||||
define KernelPackage/usb-phy-qcom-dwc3/description
|
||||
This driver provides support for the integrated DesignWare
|
||||
USB3 IP Core within the QCOM SoCs.
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,usb-phy-qcom-dwc3))
|
||||
|
||||
|
||||
define KernelPackage/phy-ath79-usb
|
||||
TITLE:=Support for ATH79 USB PHY
|
||||
KCONFIG:=CONFIG_PHY_AR7100_USB \
|
||||
|
||||
@ -19,7 +19,7 @@ DEFAULT_PACKAGES += \
|
||||
kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
|
||||
kmod-ata-ahci kmod-ata-ahci-platform \
|
||||
kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \
|
||||
kmod-usb-phy-qcom-dwc3 kmod-usb3 kmod-usb-dwc3-qcom \
|
||||
kmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \
|
||||
kmod-ath10k-ct wpad-openssl \
|
||||
uboot-envtools
|
||||
|
||||
|
||||
@ -27,10 +27,17 @@ qcom,ipq8064-ap161)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan" "1:lan" "2:lan" "3u@eth1" "6:wan" "4u@eth0"
|
||||
;;
|
||||
linksys,ea7500-v1)
|
||||
hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
|
||||
ucidef_add_switch "switch0" \
|
||||
"2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0"
|
||||
ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
|
||||
ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
|
||||
;;
|
||||
linksys,ea8500)
|
||||
hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan"
|
||||
"1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0"
|
||||
ucidef_set_interface_macaddr "lan" "$hw_mac_addr"
|
||||
ucidef_set_interface_macaddr "wan" "$hw_mac_addr"
|
||||
;;
|
||||
|
||||
@ -29,6 +29,7 @@ case "$FIRMWARE" in
|
||||
caldata_extract "ART" 0x1000 0x2f20
|
||||
ath10k_patch_mac $(mtd_get_mac_binary ART 0x1e)
|
||||
;;
|
||||
linksys,ea7500-v1 |\
|
||||
linksys,ea8500)
|
||||
caldata_extract "art" 0x1000 0x2f20
|
||||
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) +1)
|
||||
@ -63,6 +64,7 @@ case "$FIRMWARE" in
|
||||
caldata_extract "ART" 0x5000 0x2f20
|
||||
ath10k_patch_mac $(mtd_get_mac_binary ART 0x18)
|
||||
;;
|
||||
linksys,ea7500-v1 |\
|
||||
linksys,ea8500)
|
||||
caldata_extract "art" 0x5000 0x2f20
|
||||
ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) +2)
|
||||
|
||||
@ -4,6 +4,7 @@ START=99
|
||||
|
||||
boot() {
|
||||
case $(board_name) in
|
||||
linksys,ea7500-v1 |\
|
||||
linksys,ea8500)
|
||||
mtd resetbc s_env || true
|
||||
;;
|
||||
|
||||
@ -27,6 +27,7 @@ platform_do_upgrade() {
|
||||
zyxel,nbg6817)
|
||||
zyxel_do_upgrade "$1"
|
||||
;;
|
||||
linksys,ea7500-v1 |\
|
||||
linksys,ea8500)
|
||||
platform_do_upgrade_linksys "$1"
|
||||
;;
|
||||
|
||||
@ -180,7 +180,6 @@ CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
@ -493,7 +492,6 @@ CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_EHCI_HCD is not set
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VDSO=y
|
||||
|
||||
@ -49,7 +49,6 @@ CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
|
||||
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
@ -59,7 +58,6 @@ CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_HAS_SG_CHAIN=y
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=6
|
||||
CONFIG_ARM_L1_CACHE_SHIFT_6=y
|
||||
# CONFIG_ARM_LPAE is not set
|
||||
CONFIG_ARM_MODULE_PLTS=y
|
||||
CONFIG_ARM_PATCH_IDIV=y
|
||||
CONFIG_ARM_PATCH_PHYS_VIRT=y
|
||||
@ -67,9 +65,7 @@ CONFIG_ARM_PATCH_PHYS_VIRT=y
|
||||
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
|
||||
CONFIG_ARM_QCOM_CPUIDLE=y
|
||||
# CONFIG_ARM_SMMU is not set
|
||||
# CONFIG_ARM_SP805_WATCHDOG is not set
|
||||
CONFIG_ARM_THUMB=y
|
||||
# CONFIG_ARM_THUMBEE is not set
|
||||
CONFIG_ARM_UNWIND=y
|
||||
CONFIG_ARM_VIRT_EXT=y
|
||||
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
|
||||
@ -89,8 +85,6 @@ CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_32v6K=y
|
||||
CONFIG_CPU_32v7=y
|
||||
CONFIG_CPU_ABRT_EV7=y
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_CPU_CACHE_V7=y
|
||||
CONFIG_CPU_CACHE_VIPT=y
|
||||
CONFIG_CPU_COPY_V6=y
|
||||
@ -105,11 +99,10 @@ CONFIG_CPU_FREQ_GOV_COMMON=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_HAS_ASID=y
|
||||
# CONFIG_CPU_ICACHE_DISABLE is not set
|
||||
# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_LADDER=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
@ -151,7 +144,6 @@ CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_GPIO=y
|
||||
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
|
||||
# CONFIG_DEBUG_USER is not set
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
@ -159,13 +151,13 @@ CONFIG_DMA_REMAP=y
|
||||
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
# CONFIG_DWMAC_DWC_QOS_ETH is not set
|
||||
# CONFIG_DWMAC_GENERIC is not set
|
||||
CONFIG_DWMAC_IPQ806X=y
|
||||
# CONFIG_DWMAC_QCOM_ETHQOS is not set
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
CONFIG_EDAC_ATOMIC_SCRUB=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_ETHERNET_PACKET_MANGLE=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
@ -194,7 +186,7 @@ CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
@ -249,6 +241,8 @@ CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HWSPINLOCK_QCOM=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HZ=100
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_HZ_FIXED=0
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
@ -365,7 +359,6 @@ CONFIG_PAGE_POOL=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIE_BW is not set
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_QCOM=y
|
||||
@ -460,6 +453,7 @@ CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_MC146818_LIB=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
# CONFIG_SDM_CAMCC_845 is not set
|
||||
# CONFIG_SDM_DISPCC_845 is not set
|
||||
@ -469,7 +463,6 @@ CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
# CONFIG_SDM_LPASSCC_845 is not set
|
||||
# CONFIG_SDM_VIDEOCC_845 is not set
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
# CONFIG_SERIAL_AMBA_PL011 is not set
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
@ -500,7 +493,6 @@ CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
@ -511,13 +503,12 @@ CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UBIFS_FS_ZSTD=y
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_UNWINDER_ARM=y
|
||||
# CONFIG_UNWINDER_FRAME_POINTER is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
# CONFIG_USB_EHCI_HCD is not set
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VDSO=y
|
||||
|
||||
@ -4,6 +4,10 @@
|
||||
model = "Qualcomm IPQ8064/DB149";
|
||||
compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi2_serial;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -14,11 +18,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
alias {
|
||||
serial0 = &uart2;
|
||||
mdio-gpio0 = &mdio0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
@ -61,7 +60,8 @@
|
||||
gsbi2: gsbi@12480000 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "okay";
|
||||
uart2: serial@12490000 {
|
||||
|
||||
gsbi2_serial: serial@12490000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@ -292,6 +292,7 @@
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x00010 0x2613a0 /* PWS_REG */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
|
||||
@ -818,7 +818,7 @@
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
uart2: serial@12490000 {
|
||||
gsbi2_serial: serial@12490000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x12490000 0x1000>,
|
||||
<0x12480000 0x1000>;
|
||||
@ -893,7 +893,7 @@
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
uart5: serial@1a240000 {
|
||||
gsbi5_serial: serial@1a240000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x1a240000 0x1000>,
|
||||
<0x1a200000 0x1000>;
|
||||
|
||||
@ -20,112 +20,24 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&qcom_pinmux {
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "okay";
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
|
||||
serial@16340000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
&gsbi5 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "okay";
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem";
|
||||
};
|
||||
};
|
||||
&flash {
|
||||
partitions {
|
||||
compatible = "qcom,smem";
|
||||
};
|
||||
};
|
||||
|
||||
@ -214,11 +126,3 @@
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -20,127 +20,33 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&qcom_pinmux {
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio2", "gpio27", "gpio28",
|
||||
"gpio29", "gpio30", "gpio31",
|
||||
"gpio32", "gpio51", "gpio52",
|
||||
"gpio59", "gpio60", "gpio61",
|
||||
"gpio62" , "gpio66";
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
pins = "gpio27", "gpio28", "gpio29",
|
||||
"gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59",
|
||||
"gpio60", "gpio61", "gpio62",
|
||||
"gpio2", "gpio66";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "okay";
|
||||
serial@16340000 {
|
||||
status = "okay";
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
|
||||
&flash {
|
||||
partitions {
|
||||
compatible = "qcom,smem";
|
||||
};
|
||||
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
&gsbi5 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "okay";
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "qcom,smem";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
@ -32,10 +31,6 @@
|
||||
label-mac-device = &gmac2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
@ -124,15 +119,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33",
|
||||
@ -168,25 +154,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pin: usb0_pwr_en_pin {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
@ -33,7 +32,6 @@
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs noinitrd";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
@ -123,15 +121,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
@ -142,51 +131,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pins: usb0_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
|
||||
@ -4,6 +4,10 @@
|
||||
model = "Qualcomm IPQ8064/DB149";
|
||||
compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi2_serial;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -13,42 +17,9 @@
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
alias {
|
||||
serial0 = &uart2;
|
||||
mdio-gpio0 = &mdio0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&qcom_pinmux {
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii0_pins: rgmii0_pins {
|
||||
mux {
|
||||
pins = "gpio2", "gpio66";
|
||||
@ -61,66 +32,47 @@
|
||||
&gsbi2 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "okay";
|
||||
uart2: serial@12490000 {
|
||||
|
||||
gsbi2_serial: serial@12490000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi5 {
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
status = "okay";
|
||||
&gsbi4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@1a280000 {
|
||||
status = "okay";
|
||||
spi-max-frequency = <50000000>;
|
||||
&gsbi4_serial {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
&flash {
|
||||
m25p,fast-read;
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 0>;
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "s25fl256s1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
m25p,fast-read;
|
||||
|
||||
partition@0 {
|
||||
label = "lowlevel_init";
|
||||
reg = <0x0 0x1b0000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "u-boot";
|
||||
reg = <0x1b0000 0x80000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x230000 0x40000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "caldata";
|
||||
reg = <0x270000 0x40000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "firmware";
|
||||
reg = <0x2b0000 0x1d50000>;
|
||||
};
|
||||
};
|
||||
partition@0 {
|
||||
label = "lowlevel_init";
|
||||
reg = <0x0 0x1b0000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
partition@1 {
|
||||
label = "u-boot";
|
||||
reg = <0x1b0000 0x80000>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
partition@2 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x230000 0x40000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "caldata";
|
||||
reg = <0x270000 0x40000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "firmware";
|
||||
reg = <0x2b0000 0x1d50000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
@ -208,4 +160,4 @@
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <3>;
|
||||
phy-handle = <&phy7>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,302 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
#include "qcom-ipq8064-v2.0.dtsi"
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Linksys EA7500 V1 WiFi Router";
|
||||
compatible = "linksys,ea7500-v1", "qcom,ipq8064";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x42000000 0xe000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
rsvd@41200000 {
|
||||
reg = <0x41200000 0x300000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
|
||||
led-boot = &led_power;
|
||||
led-failsafe = &led_power;
|
||||
led-running = &led_power;
|
||||
led-upgrade = &led_power;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyMSM0,115200n8";
|
||||
stdout-path = "serial0:115200n8";
|
||||
append-rootblock = "ubi.mtd="; /* append to bootargs adding the root deviceblock nbr from bootloader */
|
||||
find-rootblock = "ubi.mtd="; /* look for root deviceblock nbr in this bootarg */
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
led_power: power {
|
||||
label = "ea7500-v1:white:power";
|
||||
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qcom_pinmux {
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio65", "gpio68";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio6";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "okay";
|
||||
serial@16340000 {
|
||||
status = "okay";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
force_gen1 = <1>;
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand_controller {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
compatible = "qcom,nandcs";
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "SBL1";
|
||||
reg = <0x0000000 0x0040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "MIBIB";
|
||||
reg = <0x0040000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "SBL2";
|
||||
reg = <0x0180000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@2c0000 {
|
||||
label = "SBL3";
|
||||
reg = <0x02c0000 0x0280000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@540000 {
|
||||
label = "DDRCONFIG";
|
||||
reg = <0x0540000 0x0120000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@660000 {
|
||||
label = "SSD";
|
||||
reg = <0x0660000 0x0120000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "TZ";
|
||||
reg = <0x0780000 0x0280000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@a00000 {
|
||||
label = "RPM";
|
||||
reg = <0x0a00000 0x0280000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
art: partition@c80000 {
|
||||
label = "art";
|
||||
reg = <0x0c80000 0x0140000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@dc0000 {
|
||||
label = "APPSBL";
|
||||
reg = <0x0dc0000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@ec0000 {
|
||||
label = "u_env";
|
||||
reg = <0x0ec0000 0x0040000>;
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
label = "s_env";
|
||||
reg = <0x0f00000 0x0040000>;
|
||||
};
|
||||
|
||||
partition@f40000 {
|
||||
label = "devinfo";
|
||||
reg = <0x0f40000 0x0040000>;
|
||||
};
|
||||
|
||||
partition@f80000 {
|
||||
label = "kernel1";
|
||||
reg = <0x0f80000 0x2800000>; /* 3 MB spill to rootfs*/
|
||||
};
|
||||
|
||||
partition@1280000 {
|
||||
label = "rootfs1";
|
||||
reg = <0x1280000 0x2500000>;
|
||||
};
|
||||
|
||||
partition@3780000 {
|
||||
label = "kernel2";
|
||||
reg = <0x3780000 0x2800000>;
|
||||
};
|
||||
|
||||
partition@3a80000 {
|
||||
label = "rootfs2";
|
||||
reg = <0x3a80000 0x2500000>;
|
||||
};
|
||||
|
||||
partition@5f80000 {
|
||||
label = "sysdiag";
|
||||
reg = <0x5f80000 0x100000>;
|
||||
};
|
||||
|
||||
partition@6080000 {
|
||||
label = "syscfg";
|
||||
reg = <0x6080000 0x1f80000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
qca,ar8327-initvals = <
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x00010 0x2613a0 /* PWS_REG */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
0x00094 0x4e /* PORT6_STATUS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii";
|
||||
qcom,id = <1>;
|
||||
|
||||
pinctrl-0 = <&rgmii2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac2 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
qcom,id = <2>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&adm_dma {
|
||||
status = "okay";
|
||||
};
|
||||
@ -22,7 +22,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
@ -33,7 +32,6 @@
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyMSM0,115200n8";
|
||||
stdout-path = "serial0:115200n8";
|
||||
append-rootblock = "ubi.mtd="; /* append to bootargs adding the root deviceblock nbr from bootloader */
|
||||
};
|
||||
|
||||
@ -94,15 +92,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio53", "gpio54";
|
||||
@ -111,51 +100,6 @@
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
@ -335,6 +279,7 @@
|
||||
0x00004 0x7600000 /* PAD0_MODE */
|
||||
0x00008 0x1000000 /* PAD5_MODE */
|
||||
0x0000c 0x80 /* PAD6_MODE */
|
||||
0x00010 0x2613a0 /* PWS_REG */
|
||||
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
||||
0x000e0 0xc74164de /* SGMII_CTRL */
|
||||
0x0007c 0x4e /* PORT0_STATUS */
|
||||
|
||||
@ -23,7 +23,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
@ -34,7 +33,6 @@
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs noinitrd";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
@ -124,15 +122,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
@ -142,73 +131,21 @@
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
status = "okay";
|
||||
serial@16340000 {
|
||||
status = "okay";
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
|
||||
&gsbi5 {
|
||||
status = "disabled";
|
||||
|
||||
spi@1a280000 {
|
||||
status = "disabled";
|
||||
};
|
||||
/*
|
||||
* The i2c device on gsbi4 should not be enabled.
|
||||
* On ipq806x designs gsbi4 i2c is meant for exclusive
|
||||
* RPM usage. Turning this on in kernel manifests as
|
||||
* i2c failure for the RPM.
|
||||
*/
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
@ -38,7 +37,6 @@
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs noinitrd";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
@ -132,15 +130,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
@ -151,51 +140,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb0_pwr_en_pins: usb0_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
|
||||
@ -24,14 +24,12 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
sdcc1 = &sdcc1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/mmcblk0p3 rootfstype=squashfs,ext4 rootwait noinitrd";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
@ -65,15 +63,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio53";
|
||||
@ -84,13 +73,6 @@
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio1";
|
||||
input-disable;
|
||||
@ -98,14 +80,6 @@
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
|
||||
input-disable;
|
||||
@ -140,13 +114,6 @@
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
drive-strength = <12>;
|
||||
@ -289,15 +256,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
ports-implemented = <0x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -1 +0,0 @@
|
||||
#include "qcom-ipq8064.dtsi"
|
||||
@ -1,30 +1,43 @@
|
||||
#include "qcom-ipq8064-v1.0.dtsi"
|
||||
#include "qcom-ipq8064.dtsi"
|
||||
|
||||
/ {
|
||||
soc: soc {
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
};
|
||||
|
||||
pcie0: pci@1b500000 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
pcie1: pci@1b700000 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
pcie2: pci@1b900000 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&CPU_SPC {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
&ss_phy_0 {
|
||||
rx_eq = <2>;
|
||||
tx_deamp_3_5db = <32>;
|
||||
mpll = <0xa0>;
|
||||
qcom,rx-eq = <2>;
|
||||
qcom,tx-deamp_3_5db = <32>;
|
||||
qcom,mpll = <5>;
|
||||
};
|
||||
|
||||
&ss_phy_1 {
|
||||
rx_eq = <2>;
|
||||
tx_deamp_3_5db = <32>;
|
||||
mpll = <0xa0>;
|
||||
qcom,rx-eq = <2>;
|
||||
qcom,tx-deamp_3_5db = <32>;
|
||||
qcom,mpll = <5>;
|
||||
};
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power;
|
||||
@ -31,10 +30,6 @@
|
||||
led-upgrade = &general;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
@ -135,15 +130,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
button_pins: button_pins {
|
||||
mux {
|
||||
pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
|
||||
@ -176,25 +162,6 @@
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_green;
|
||||
@ -31,10 +30,6 @@
|
||||
led-upgrade = &power_green;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
@ -347,15 +342,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14",
|
||||
@ -391,25 +377,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb_pwr_en_pins: usb_pwr_en_pins {
|
||||
mux {
|
||||
pins = "gpio22";
|
||||
|
||||
@ -42,7 +42,6 @@
|
||||
|
||||
aliases {
|
||||
mdio-gpio0 = &mdio0;
|
||||
serial0 = &gsbi4_serial;
|
||||
ethernet0 = &gmac1;
|
||||
ethernet1 = &gmac0;
|
||||
|
||||
@ -52,10 +51,6 @@
|
||||
led-upgrade = &led_pass;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@ -341,39 +336,21 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
status = "okay";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
};
|
||||
|
||||
&gsbi4_serial {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gsbi5 {
|
||||
status = "okay";
|
||||
&flash {
|
||||
compatible = "jedec,spi-nor";
|
||||
};
|
||||
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
&sata_phy {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@1a280000 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-0 = <&spi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
s25fl256s1@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
&sata {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&ss_phy_0 { /* USB3 port 0 SS phy */
|
||||
@ -494,51 +471,6 @@
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36", "gpio37",
|
||||
"gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42", "gpio43",
|
||||
"gpio44", "gpio45", "gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30",
|
||||
"gpio31", "gpio32", "gpio51", "gpio52",
|
||||
"gpio59", "gpio60", "gpio61", "gpio62";
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
|
||||
@ -23,8 +23,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
|
||||
led-boot = &power;
|
||||
led-failsafe = &diag;
|
||||
led-running = &power;
|
||||
@ -34,7 +32,6 @@
|
||||
chosen {
|
||||
/* use "ubi_rootfs" volume in "ubi" partition as rootfs */
|
||||
bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
@ -458,51 +455,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usb_pwr_en_pins: usb_pwr_en_pins {
|
||||
mux{
|
||||
pins = "gpio68";
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -22,7 +22,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
sdcc1 = &sdcc1;
|
||||
|
||||
@ -34,7 +33,6 @@
|
||||
|
||||
chosen {
|
||||
bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd";
|
||||
stdout-path = "serial0:115200n8";
|
||||
append-rootblock = "root=/dev/mmcblk0p";
|
||||
};
|
||||
|
||||
@ -105,15 +103,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio9", "gpio26", "gpio33", "gpio64";
|
||||
@ -124,13 +113,6 @@
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio1";
|
||||
input-disable;
|
||||
@ -138,14 +120,6 @@
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
|
||||
input-disable;
|
||||
@ -153,13 +127,6 @@
|
||||
};
|
||||
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
function = "gsbi5";
|
||||
drive-strength = <10>;
|
||||
bias-none;
|
||||
};
|
||||
|
||||
cs {
|
||||
pins = "gpio20";
|
||||
drive-strength = <12>;
|
||||
|
||||
@ -27,7 +27,6 @@
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
mdio-gpio0 = &mdio0;
|
||||
|
||||
led-boot = &power_white;
|
||||
@ -37,10 +36,6 @@
|
||||
label-mac-device = &gmac2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&button_pins>;
|
||||
@ -134,15 +129,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
i2c4_pins: i2c4_pinmux {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13";
|
||||
function = "gsbi4";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
led_pins: led_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
|
||||
@ -153,38 +139,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
disable {
|
||||
pins = "gpio34", "gpio35", "gpio36",
|
||||
"gpio37", "gpio38";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-disable;
|
||||
};
|
||||
pullups {
|
||||
pins = "gpio39";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
hold {
|
||||
pins = "gpio40", "gpio41", "gpio42",
|
||||
"gpio43", "gpio44", "gpio45",
|
||||
"gpio46", "gpio47";
|
||||
function = "nand";
|
||||
drive-strength = <10>;
|
||||
bias-bus-hold;
|
||||
};
|
||||
};
|
||||
|
||||
mdio0_pins: mdio0_pins {
|
||||
mux {
|
||||
pins = "gpio0", "gpio1";
|
||||
function = "mdio";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
clk {
|
||||
pins = "gpio1";
|
||||
input-disable;
|
||||
@ -192,14 +147,6 @@
|
||||
};
|
||||
|
||||
rgmii2_pins: rgmii2_pins {
|
||||
mux {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
|
||||
"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
|
||||
function = "rgmii2";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
tx {
|
||||
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
|
||||
input-disable;
|
||||
|
||||
@ -1,45 +1,63 @@
|
||||
#include "qcom-ipq8064-v2.0.dtsi"
|
||||
#include "qcom-ipq8064.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm IPQ8065";
|
||||
compatible = "qcom,ipq8065", "qcom,ipq8064";
|
||||
|
||||
soc: soc {
|
||||
|
||||
rpm@108000 {
|
||||
|
||||
regulators {
|
||||
|
||||
smb208_s2a: s2a {
|
||||
regulator-min-microvolt = <775000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
};
|
||||
|
||||
smb208_s2b: s2b {
|
||||
regulator-min-microvolt = <775000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
aliases {
|
||||
serial0 = &gsbi4_serial;
|
||||
};
|
||||
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
qcom,l2 {
|
||||
qcom,l2-cpufreq = <384000000 600000000 1400000000>;
|
||||
};
|
||||
|
||||
idle-states {
|
||||
CPU_SPC: spc {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&opp_table0 {
|
||||
compatible = "operating-points-v2-qcom-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
&pcie0 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
phy-tx0-term-offset = <0>;
|
||||
};
|
||||
|
||||
&sata {
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
&smb208_s2a {
|
||||
regulator-min-microvolt = <775000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
};
|
||||
|
||||
&smb208_s2b {
|
||||
regulator-min-microvolt = <775000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
};
|
||||
|
||||
&ss_phy_0 {
|
||||
qcom,rx-eq = <2>;
|
||||
qcom,tx-deamp_3_5db = <32>;
|
||||
qcom,mpll = <5>;
|
||||
};
|
||||
|
||||
&ss_phy_1 {
|
||||
qcom,rx-eq = <2>;
|
||||
qcom,tx-deamp_3_5db = <32>;
|
||||
qcom,mpll = <5>;
|
||||
};
|
||||
|
||||
&opp_table0 {
|
||||
/*
|
||||
* On ipq8065 1.2 ghz freq is not present
|
||||
* Remove it to make cpufreq work and not
|
||||
@ -49,7 +67,6 @@
|
||||
/delete-node/opp-1200000000;
|
||||
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-microvolt-speed0-pvs0-v0 = <975000>;
|
||||
opp-microvolt-speed0-pvs1-v0 = <950000>;
|
||||
opp-microvolt-speed0-pvs2-v0 = <925000>;
|
||||
@ -57,12 +74,9 @@
|
||||
opp-microvolt-speed0-pvs4-v0 = <875000>;
|
||||
opp-microvolt-speed0-pvs5-v0 = <825000>;
|
||||
opp-microvolt-speed0-pvs6-v0 = <775000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <100000>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt-speed0-pvs0-v0 = <1000000>;
|
||||
opp-microvolt-speed0-pvs1-v0 = <975000>;
|
||||
opp-microvolt-speed0-pvs2-v0 = <950000>;
|
||||
@ -70,12 +84,9 @@
|
||||
opp-microvolt-speed0-pvs4-v0 = <900000>;
|
||||
opp-microvolt-speed0-pvs5-v0 = <850000>;
|
||||
opp-microvolt-speed0-pvs6-v0 = <800000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <100000>;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt-speed0-pvs0-v0 = <1050000>;
|
||||
opp-microvolt-speed0-pvs1-v0 = <1025000>;
|
||||
opp-microvolt-speed0-pvs2-v0 = <1000000>;
|
||||
@ -83,12 +94,9 @@
|
||||
opp-microvolt-speed0-pvs4-v0 = <950000>;
|
||||
opp-microvolt-speed0-pvs5-v0 = <900000>;
|
||||
opp-microvolt-speed0-pvs6-v0 = <850000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <100000>;
|
||||
};
|
||||
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt-speed0-pvs0-v0 = <1100000>;
|
||||
opp-microvolt-speed0-pvs1-v0 = <1075000>;
|
||||
opp-microvolt-speed0-pvs2-v0 = <1050000>;
|
||||
@ -96,12 +104,9 @@
|
||||
opp-microvolt-speed0-pvs4-v0 = <1000000>;
|
||||
opp-microvolt-speed0-pvs5-v0 = <950000>;
|
||||
opp-microvolt-speed0-pvs6-v0 = <900000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <100000>;
|
||||
};
|
||||
|
||||
opp-1400000000 {
|
||||
opp-hz = /bits/ 64 <1400000000>;
|
||||
opp-microvolt-speed0-pvs0-v0 = <1175000>;
|
||||
opp-microvolt-speed0-pvs1-v0 = <1150000>;
|
||||
opp-microvolt-speed0-pvs2-v0 = <1125000>;
|
||||
@ -109,8 +114,6 @@
|
||||
opp-microvolt-speed0-pvs4-v0 = <1075000>;
|
||||
opp-microvolt-speed0-pvs5-v0 = <1025000>;
|
||||
opp-microvolt-speed0-pvs6-v0 = <975000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <100000>;
|
||||
};
|
||||
|
||||
opp-1725000000 {
|
||||
|
||||
@ -109,6 +109,23 @@ define Device/compex_wpq864
|
||||
endef
|
||||
TARGET_DEVICES += compex_wpq864
|
||||
|
||||
define Device/linksys_ea7500-v1
|
||||
$(call Device/LegacyImage)
|
||||
DEVICE_VENDOR := Linksys
|
||||
DEVICE_MODEL := EA7500
|
||||
DEVICE_VARIANT := v1
|
||||
SOC := qcom-ipq8064
|
||||
PAGESIZE := 2048
|
||||
BLOCKSIZE := 128k
|
||||
KERNEL_SIZE := 3072k
|
||||
KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem
|
||||
UBINIZE_OPTS := -E 5
|
||||
IMAGES := factory.bin sysupgrade.bin
|
||||
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | pad-to $$$$(PAGESIZE)
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct
|
||||
endef
|
||||
TARGET_DEVICES += linksys_ea7500-v1
|
||||
|
||||
define Device/linksys_ea8500
|
||||
$(call Device/LegacyImage)
|
||||
DEVICE_VENDOR := Linksys
|
||||
|
||||
16
target/linux/ipq806x/modules.mk
Normal file
16
target/linux/ipq806x/modules.mk
Normal file
@ -0,0 +1,16 @@
|
||||
define KernelPackage/phy-qcom-ipq806x-usb
|
||||
TITLE:=Qualcomm IPQ806x DWC3 USB PHY driver
|
||||
DEPENDS:=@TARGET_ipq806x
|
||||
KCONFIG:= CONFIG_PHY_QCOM_IPQ806X_USB
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.ko
|
||||
AUTOLOAD:=$(call AutoLoad,45,phy-qcom-ipq806x-usb,1)
|
||||
$(call AddDepends/usb)
|
||||
endef
|
||||
|
||||
define KernelPackage/phy-qcom-ipq806x-usb/description
|
||||
This driver provides support for the integrated DesignWare
|
||||
USB3 IP Core within the QCOM SoCs.
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,phy-qcom-ipq806x-usb))
|
||||
@ -1,614 +0,0 @@
|
||||
From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Gross <agross@codeaurora.org>
|
||||
Date: Thu, 9 Mar 2017 08:19:18 +0100
|
||||
Subject: [PATCH 32/69] phy: add qcom dwc3 phy
|
||||
|
||||
Signed-off-by: Andy Gross <agross@codeaurora.org>
|
||||
---
|
||||
|
||||
--- a/drivers/phy/qualcomm/Kconfig
|
||||
+++ b/drivers/phy/qualcomm/Kconfig
|
||||
@@ -91,3 +91,15 @@ config PHY_QCOM_USB_HSIC
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
|
||||
+
|
||||
+config PHY_QCOM_DWC3
|
||||
+ tristate "QCOM DWC3 USB PHY support"
|
||||
+ depends on ARCH_QCOM
|
||||
+ depends on HAS_IOMEM
|
||||
+ depends on OF
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ This option enables support for the Synopsis PHYs present inside the
|
||||
+ Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
|
||||
+ PHY controllers.
|
||||
+
|
||||
--- a/drivers/phy/qualcomm/Makefile
|
||||
+++ b/drivers/phy/qualcomm/Makefile
|
||||
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-
|
||||
obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
|
||||
+obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c
|
||||
@@ -0,0 +1,578 @@
|
||||
+/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 and
|
||||
+ * only version 2 as published by the Free Software Foundation.
|
||||
+ *
|
||||
+* This program is distributed in the hope that it will be useful,
|
||||
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+* GNU General Public License for more details.
|
||||
+*/
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+
|
||||
+/**
|
||||
+ * USB QSCRATCH Hardware registers
|
||||
+ */
|
||||
+#define QSCRATCH_GENERAL_CFG (0x08)
|
||||
+#define HSUSB_PHY_CTRL_REG (0x10)
|
||||
+
|
||||
+/* PHY_CTRL_REG */
|
||||
+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
|
||||
+#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
|
||||
+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
|
||||
+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
|
||||
+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
|
||||
+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
|
||||
+#define HSUSB_CTRL_COMMONONN BIT(11)
|
||||
+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
|
||||
+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
|
||||
+#define HSUSB_CTRL_CLAMP_EN BIT(7)
|
||||
+#define HSUSB_CTRL_RETENABLEN BIT(1)
|
||||
+#define HSUSB_CTRL_POR BIT(0)
|
||||
+
|
||||
+/* QSCRATCH_GENERAL_CFG */
|
||||
+#define HSUSB_GCFG_XHCI_REV BIT(2)
|
||||
+
|
||||
+/**
|
||||
+ * USB QSCRATCH Hardware registers
|
||||
+ */
|
||||
+#define SSUSB_PHY_CTRL_REG (0x30)
|
||||
+#define SSUSB_PHY_PARAM_CTRL_1 (0x34)
|
||||
+#define SSUSB_PHY_PARAM_CTRL_2 (0x38)
|
||||
+#define CR_PROTOCOL_DATA_IN_REG (0x3c)
|
||||
+#define CR_PROTOCOL_DATA_OUT_REG (0x40)
|
||||
+#define CR_PROTOCOL_CAP_ADDR_REG (0x44)
|
||||
+#define CR_PROTOCOL_CAP_DATA_REG (0x48)
|
||||
+#define CR_PROTOCOL_READ_REG (0x4c)
|
||||
+#define CR_PROTOCOL_WRITE_REG (0x50)
|
||||
+
|
||||
+/* PHY_CTRL_REG */
|
||||
+#define SSUSB_CTRL_REF_USE_PAD BIT(28)
|
||||
+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
|
||||
+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
|
||||
+#define SSUSB_CTRL_SS_PHY_EN BIT(8)
|
||||
+#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
|
||||
+
|
||||
+/* SSPHY control registers - Does this need 0x30? */
|
||||
+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
|
||||
+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane)
|
||||
+
|
||||
+/* SSPHY SoC version specific values */
|
||||
+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
|
||||
+#define SSPHY_TX_DEEMPH_3_5DB 23 /* Override value for transmit
|
||||
+ preemphasis */
|
||||
+#define SSPHY_MPLL_VALUE 0 /* Override value for mpll */
|
||||
+
|
||||
+/* QSCRATCH PHY_PARAM_CTRL1 fields */
|
||||
+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK 0x07f00000u
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK 0x000fc000u
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK 0x00003f00u
|
||||
+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK 0x000000f8u
|
||||
+
|
||||
+#define PHY_PARAM_CTRL1_MASK \
|
||||
+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS_MASK)
|
||||
+
|
||||
+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
|
||||
+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
|
||||
+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
|
||||
+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
|
||||
+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
|
||||
+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
|
||||
+
|
||||
+/* RX OVRD IN HI bits */
|
||||
+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
|
||||
+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
|
||||
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
|
||||
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018
|
||||
+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
|
||||
+#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003
|
||||
+
|
||||
+/* TX OVRD DRV LO register bits */
|
||||
+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
|
||||
+#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
|
||||
+#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
|
||||
+#define TX_OVRD_DRV_LO_EN BIT(14)
|
||||
+
|
||||
+/* SS CAP register bits */
|
||||
+#define SS_CR_CAP_ADDR_REG BIT(0)
|
||||
+#define SS_CR_CAP_DATA_REG BIT(0)
|
||||
+#define SS_CR_READ_REG BIT(0)
|
||||
+#define SS_CR_WRITE_REG BIT(0)
|
||||
+
|
||||
+struct qcom_dwc3_usb_phy {
|
||||
+ struct regmap *base;
|
||||
+ struct device *dev;
|
||||
+ struct clk *xo_clk;
|
||||
+ struct clk *ref_clk;
|
||||
+ u32 rx_eq;
|
||||
+ u32 tx_deamp_3_5db;
|
||||
+ u32 mpll;
|
||||
+};
|
||||
+
|
||||
+struct qcom_dwc3_phy_drvdata {
|
||||
+ struct phy_ops ops;
|
||||
+ u32 clk_rate;
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
+ * Write register and read back masked value to confirm it is written
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @offset - register offset.
|
||||
+ * @mask - register bitmask specifying what should be updated
|
||||
+ * @val - value to write.
|
||||
+ */
|
||||
+static inline void qcom_dwc3_phy_write_readback(
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
|
||||
+ const u32 mask, u32 val)
|
||||
+{
|
||||
+ u32 write_val, tmp;
|
||||
+
|
||||
+ tmp = regmap_read(phy_dwc3->base, offset, &tmp);
|
||||
+ tmp &= ~mask; /* retain other bits */
|
||||
+ write_val = tmp | val;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, offset, write_val);
|
||||
+
|
||||
+ /* Read back to see if val was written */
|
||||
+ regmap_read(phy_dwc3->base, offset, &tmp);
|
||||
+ tmp &= mask; /* clear other bits */
|
||||
+
|
||||
+ if (tmp != val)
|
||||
+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
|
||||
+ val, offset);
|
||||
+}
|
||||
+
|
||||
+static int wait_for_latch(struct regmap *base, u32 addr)
|
||||
+{
|
||||
+ u32 retry = 10, data;
|
||||
+
|
||||
+ while (true) {
|
||||
+ regmap_read(base, addr, &data);
|
||||
+ if (!data)
|
||||
+ break;
|
||||
+
|
||||
+ if (--retry == 0)
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ usleep_range(10, 20);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * Write SSPHY register
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @addr - SSPHY address to write.
|
||||
+ * @val - value to write.
|
||||
+ */
|
||||
+static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
|
||||
+ u32 addr, u32 val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, addr);
|
||||
+ regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, CR_PROTOCOL_DATA_IN_REG, val);
|
||||
+ regmap_write(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG, SS_CR_CAP_DATA_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_CAP_DATA_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, CR_PROTOCOL_WRITE_REG, SS_CR_WRITE_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base, CR_PROTOCOL_WRITE_REG);
|
||||
+
|
||||
+err_wait:
|
||||
+ if (ret)
|
||||
+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * Read SSPHY register.
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @addr - SSPHY address to read.
|
||||
+ */
|
||||
+static int qcom_dwc3_ss_read_phycreg(struct regmap *base, u32 addr, u32 *val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ regmap_write(base, CR_PROTOCOL_DATA_IN_REG, addr);
|
||||
+ regmap_write(base, CR_PROTOCOL_CAP_ADDR_REG, SS_CR_CAP_ADDR_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(base, CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ /*
|
||||
+ * Due to hardware bug, first read of SSPHY register might be
|
||||
+ * incorrect. Hence as workaround, SW should perform SSPHY register
|
||||
+ * read twice, but use only second read and ignore first read.
|
||||
+ */
|
||||
+ regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(base, CR_PROTOCOL_READ_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ /* throwaway read */
|
||||
+ regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, &ret);
|
||||
+
|
||||
+ regmap_write(base, CR_PROTOCOL_READ_REG, SS_CR_READ_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(base, CR_PROTOCOL_READ_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ regmap_read(base, CR_PROTOCOL_DATA_OUT_REG, val);
|
||||
+
|
||||
+err_wait:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_hs_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 val;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
|
||||
+ * enable clamping, and disable RETENTION (power-on default is ENABLED)
|
||||
+ */
|
||||
+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
|
||||
+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
|
||||
+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
|
||||
+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
|
||||
+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
|
||||
+
|
||||
+ /* use core clock if external reference is not present */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ val |= HSUSB_CTRL_USE_CLKCORE;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, HSUSB_PHY_CTRL_REG, val);
|
||||
+ usleep_range(2000, 2200);
|
||||
+
|
||||
+ /* Disable (bypass) VBUS and ID filters */
|
||||
+ regmap_write(phy_dwc3->base, QSCRATCH_GENERAL_CFG, HSUSB_GCFG_XHCI_REV);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_hs_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_ss_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 data = 0;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* reset phy */
|
||||
+ regmap_read(phy_dwc3->base, SSUSB_PHY_CTRL_REG, &data);
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG,
|
||||
+ data | SSUSB_CTRL_SS_PHY_RESET);
|
||||
+ usleep_range(2000, 2200);
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
|
||||
+
|
||||
+ /* clear REF_PAD if we don't have XO clk */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ data &= ~SSUSB_CTRL_REF_USE_PAD;
|
||||
+ else
|
||||
+ data |= SSUSB_CTRL_REF_USE_PAD;
|
||||
+
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
|
||||
+
|
||||
+ /* wait for ref clk to become stable, this can take up to 30ms */
|
||||
+ msleep(30);
|
||||
+
|
||||
+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
|
||||
+ regmap_write(phy_dwc3->base, SSUSB_PHY_CTRL_REG, data);
|
||||
+
|
||||
+ /*
|
||||
+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
|
||||
+ * in HS mode instead of SS mode. Workaround it by asserting
|
||||
+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
|
||||
+ */
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x102D, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data |= (1 << 7);
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x102D, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base, 0x1010, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~0xff0;
|
||||
+ data |= 0x20;
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x1010, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Fix RX Equalization setting as follows
|
||||
+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
|
||||
+ */
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
|
||||
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
|
||||
+ data |= phy_dwc3->rx_eq << RX_OVRD_IN_HI_RX_EQ_SHIFT;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Set EQ and TX launch amplitudes as follows
|
||||
+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
|
||||
+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
|
||||
+ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
|
||||
+ */
|
||||
+ ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
|
||||
+ data |= phy_dwc3->tx_deamp_3_5db << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
|
||||
+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
|
||||
+ data |= 0x6E;
|
||||
+ data |= TX_OVRD_DRV_LO_EN;
|
||||
+ ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ qcom_dwc3_ss_write_phycreg(phy_dwc3, 0x30, phy_dwc3->mpll);
|
||||
+
|
||||
+ /*
|
||||
+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
|
||||
+ * TX_FULL_SWING [26:20] amplitude to 110
|
||||
+ * TX_DEEMPH_6DB [19:14] to 32
|
||||
+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version
|
||||
+ * LOS_BIAS [7:3] to 9
|
||||
+ */
|
||||
+ regmap_read(phy_dwc3->base, SSUSB_PHY_PARAM_CTRL_1, &data);
|
||||
+
|
||||
+ data &= ~PHY_PARAM_CTRL1_MASK;
|
||||
+
|
||||
+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS(0x9);
|
||||
+
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
|
||||
+ PHY_PARAM_CTRL1_MASK, data);
|
||||
+
|
||||
+err_phy_trans:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_dwc3_ss_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Sequence to put SSPHY in low power state:
|
||||
+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG
|
||||
+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG
|
||||
+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
|
||||
+ */
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_SS_PHY_EN, 0x0);
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_REF_USE_PAD, 0x0);
|
||||
+ qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_dwc3_hs_phy_init,
|
||||
+ .exit = qcom_dwc3_hs_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 60000000,
|
||||
+};
|
||||
+
|
||||
+static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_dwc3_ss_phy_init,
|
||||
+ .exit = qcom_dwc3_ss_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 125000000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id qcom_dwc3_phy_table[] = {
|
||||
+ { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
|
||||
+ { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
|
||||
+
|
||||
+static int qcom_dwc3_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct qcom_dwc3_usb_phy *phy_dwc3;
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct phy *generic_phy;
|
||||
+ struct resource *res;
|
||||
+ const struct of_device_id *match;
|
||||
+ const struct qcom_dwc3_phy_drvdata *data;
|
||||
+ struct device_node *np;
|
||||
+
|
||||
+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
|
||||
+ if (!phy_dwc3)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
|
||||
+ data = match->data;
|
||||
+
|
||||
+ phy_dwc3->dev = &pdev->dev;
|
||||
+
|
||||
+ phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
|
||||
+ if (IS_ERR_OR_NULL(phy_dwc3->base))
|
||||
+ return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL;
|
||||
+
|
||||
+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
|
||||
+ if (IS_ERR(phy_dwc3->ref_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
|
||||
+ return PTR_ERR(phy_dwc3->ref_clk);
|
||||
+ }
|
||||
+
|
||||
+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
|
||||
+
|
||||
+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
|
||||
+ if (IS_ERR(phy_dwc3->xo_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
|
||||
+ phy_dwc3->xo_clk = NULL;
|
||||
+ }
|
||||
+
|
||||
+ /* Parse device node to probe HSIO settings */
|
||||
+ np = of_node_get(pdev->dev.of_node);
|
||||
+ if (!of_compat_cmp(match->compatible, "qcom,dwc3-ss-usb-phy",
|
||||
+ strlen(match->compatible))) {
|
||||
+
|
||||
+ if (of_property_read_u32(np, "rx_eq", &phy_dwc3->rx_eq) ||
|
||||
+ of_property_read_u32(np, "tx_deamp_3_5db",
|
||||
+ &phy_dwc3->tx_deamp_3_5db) ||
|
||||
+ of_property_read_u32(np, "mpll", &phy_dwc3->mpll)) {
|
||||
+
|
||||
+ dev_err(phy_dwc3->dev, "cannot get HSIO settings from device node, using default values\n");
|
||||
+
|
||||
+ /* Default HSIO settings */
|
||||
+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
|
||||
+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
|
||||
+ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
|
||||
+ &data->ops);
|
||||
+
|
||||
+ if (IS_ERR(generic_phy))
|
||||
+ return PTR_ERR(generic_phy);
|
||||
+
|
||||
+ phy_set_drvdata(generic_phy, phy_dwc3);
|
||||
+ platform_set_drvdata(pdev, phy_dwc3);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
|
||||
+ of_phy_simple_xlate);
|
||||
+
|
||||
+ if (IS_ERR(phy_provider))
|
||||
+ return PTR_ERR(phy_provider);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver qcom_dwc3_phy_driver = {
|
||||
+ .probe = qcom_dwc3_phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "qcom-dwc3-usb-phy",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = qcom_dwc3_phy_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(qcom_dwc3_phy_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:phy-qcom-dwc3");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
||||
+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|
||||
+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
|
||||
@ -51,41 +51,62 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
||||
#else
|
||||
#define do_extend_cmdline 0
|
||||
#endif
|
||||
@@ -67,6 +69,59 @@ static uint32_t get_cell_size(const void
|
||||
@@ -67,6 +69,80 @@ static uint32_t get_cell_size(const void
|
||||
return cell_size;
|
||||
}
|
||||
|
||||
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
|
||||
+/**
|
||||
+ * taken from arch/x86/boot/string.c
|
||||
+ * local_strstr - Find the first substring in a %NUL terminated string
|
||||
+ * @s1: The string to be searched
|
||||
+ * @s2: The string to search for
|
||||
+ */
|
||||
+static char *local_strstr(const char *s1, const char *s2)
|
||||
+{
|
||||
+ size_t l1, l2;
|
||||
+
|
||||
+ l2 = strlen(s2);
|
||||
+ if (!l2)
|
||||
+ return (char *)s1;
|
||||
+ l1 = strlen(s1);
|
||||
+ while (l1 >= l2) {
|
||||
+ l1--;
|
||||
+ if (!memcmp(s1, s2, l2))
|
||||
+ return (char *)s1;
|
||||
+ s1++;
|
||||
+ }
|
||||
+ return NULL;
|
||||
+}
|
||||
+
|
||||
+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
|
||||
+{
|
||||
+ char *ptr, *end;
|
||||
+ char *ptr, *end, *tmp;
|
||||
+ char *root="root=";
|
||||
+ char *find_rootblock;
|
||||
+ int i, l;
|
||||
+ const char *rootblock;
|
||||
+
|
||||
+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
|
||||
+ ptr = str - 1;
|
||||
+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
|
||||
+ if(!find_rootblock)
|
||||
+ find_rootblock = root;
|
||||
+
|
||||
+ do {
|
||||
+ //first find an 'r' at the begining or after a space
|
||||
+ do {
|
||||
+ ptr++;
|
||||
+ ptr = strchr(ptr, 'r');
|
||||
+ if(!ptr) return dest;
|
||||
+ //ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86
|
||||
+ ptr = local_strstr(str, find_rootblock);
|
||||
+
|
||||
+ } while (ptr != str && *(ptr-1) != ' ');
|
||||
+
|
||||
+ //then check for the rest
|
||||
+ for(i = 1; i <= 4; i++)
|
||||
+ if(*(ptr+i) != *(root+i)) break;
|
||||
+
|
||||
+ } while (i != 5);
|
||||
+ if(!ptr)
|
||||
+ return dest;
|
||||
+
|
||||
+ end = strchr(ptr, ' ');
|
||||
+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
|
||||
+
|
||||
+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
|
||||
+ // Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too.
|
||||
+ tmp = strchr(ptr, ',');
|
||||
+
|
||||
+ if(tmp)
|
||||
+ end = end < tmp ? end : tmp - 1;
|
||||
+
|
||||
+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
|
||||
+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
|
||||
+ ptr = end + 1;
|
||||
+
|
||||
@ -111,7 +132,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
||||
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
|
||||
{
|
||||
char cmdline[COMMAND_LINE_SIZE];
|
||||
@@ -86,12 +141,21 @@ static void merge_fdt_bootargs(void *fdt
|
||||
@@ -86,12 +162,21 @@ static void merge_fdt_bootargs(void *fdt
|
||||
|
||||
/* and append the ATAG_CMDLINE */
|
||||
if (fdt_cmdline) {
|
||||
@ -133,7 +154,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
||||
}
|
||||
*ptr = '\0';
|
||||
|
||||
@@ -166,7 +230,9 @@ int atags_to_fdt(void *atag_list, void *
|
||||
@@ -166,7 +251,9 @@ int atags_to_fdt(void *atag_list, void *
|
||||
else
|
||||
setprop_string(fdt, "/chosen", "bootargs",
|
||||
atag->u.cmdline.cmdline);
|
||||
@ -144,7 +165,7 @@ Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
||||
if (memcount >= sizeof(mem_reg_property)/4)
|
||||
continue;
|
||||
if (!atag->u.mem.size)
|
||||
@@ -210,6 +276,10 @@ int atags_to_fdt(void *atag_list, void *
|
||||
@@ -210,6 +297,10 @@ int atags_to_fdt(void *atag_list, void *
|
||||
setprop(fdt, "/memory", "reg", mem_reg_property,
|
||||
4 * memcount * memsize);
|
||||
}
|
||||
|
||||
@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -843,6 +843,19 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
@@ -843,6 +843,20 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-ipq4019-ap.dk07.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c2.dtb \
|
||||
qcom-ipq8064-ap148.dtb \
|
||||
@ -18,6 +18,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
+ qcom-ipq8064-d7800.dtb \
|
||||
+ qcom-ipq8064-db149.dtb \
|
||||
+ qcom-ipq8064-ap161.dtb \
|
||||
+ qcom-ipq8064-ea7500-v1.dtb \
|
||||
+ qcom-ipq8064-ea8500.dtb \
|
||||
+ qcom-ipq8064-r7500.dtb \
|
||||
+ qcom-ipq8064-r7500v2.dtb \
|
||||
|
||||
@ -1,79 +0,0 @@
|
||||
From 2034addc7e193dc81d7ca60d8884832751b76758 Mon Sep 17 00:00:00 2001
|
||||
From: Ajay Kishore <akisho@codeaurora.org>
|
||||
Date: Tue, 24 Jan 2017 14:14:16 +0530
|
||||
Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
|
||||
|
||||
For IPQ806x targets, TZ protects the registers that are used to
|
||||
configure the routing of interrupts to a target processor.
|
||||
To resolve this, this patch uses scm call to route GPIO interrupts
|
||||
to application processor. Also the scm call interface is changed.
|
||||
|
||||
Change-Id: Ib6c06829d04bc8c20483c36e63da92e26cdef9ce
|
||||
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
|
||||
---
|
||||
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
@@ -22,7 +22,8 @@
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/log2.h>
|
||||
-
|
||||
+#include <linux/qcom_scm.h>
|
||||
+#include <linux/io.h>
|
||||
#include "../core.h"
|
||||
#include "../pinconf.h"
|
||||
#include "pinctrl-msm.h"
|
||||
@@ -706,6 +707,9 @@ static void msm_gpio_irq_mask(struct irq
|
||||
const struct msm_pingroup *g;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
+ u32 addr;
|
||||
+ int ret;
|
||||
+ const __be32 *reg;
|
||||
|
||||
g = &pctrl->soc->groups[d->hwirq];
|
||||
|
||||
@@ -819,6 +823,7 @@ static int msm_gpio_irq_set_type(struct
|
||||
const struct msm_pingroup *g;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
+ int ret;
|
||||
|
||||
g = &pctrl->soc->groups[d->hwirq];
|
||||
|
||||
@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
|
||||
else
|
||||
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
|
||||
|
||||
+ ret = of_device_is_compatible(pctrl->dev->of_node,
|
||||
+ "qcom,ipq8064-pinctrl");
|
||||
/* Route interrupts to application cpu */
|
||||
- val = msm_readl_intr_target(pctrl, g);
|
||||
- val &= ~(7 << g->intr_target_bit);
|
||||
- val |= g->intr_target_kpss_val << g->intr_target_bit;
|
||||
- msm_writel_intr_target(val, pctrl, g);
|
||||
+ if (!ret) {
|
||||
+ val = msm_readl_intr_target(pctrl, g);
|
||||
+ val &= ~(7 << g->intr_target_bit);
|
||||
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
|
||||
+ msm_writel_intr_target(val, pctrl, g);
|
||||
+ } else {
|
||||
+ const __be32 *reg = of_get_property(pctrl->dev->of_node, "reg", NULL);
|
||||
+ if (reg) {
|
||||
+ u32 addr = be32_to_cpup(reg) + g->intr_target_reg;
|
||||
+ qcom_scm_io_readl(addr, &val);
|
||||
+ __iormb();
|
||||
+
|
||||
+ val &= ~(7 << g->intr_target_bit);
|
||||
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
|
||||
+
|
||||
+ __iowmb();
|
||||
+ ret = qcom_scm_io_writel(addr, val);
|
||||
+ if (ret)
|
||||
+ pr_err("\n Routing interrupts to Apps proc failed");
|
||||
+ }
|
||||
+ }
|
||||
|
||||
/* Update configuration for gpio.
|
||||
* RAW_STATUS_EN is left on for all gpio irqs. Due to the
|
||||
@ -1,29 +0,0 @@
|
||||
--- a/drivers/phy/qualcomm/phy-qcom-dwc3.c
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-dwc3.c
|
||||
@@ -491,7 +491,6 @@ static int qcom_dwc3_phy_probe(struct pl
|
||||
struct qcom_dwc3_usb_phy *phy_dwc3;
|
||||
struct phy_provider *phy_provider;
|
||||
struct phy *generic_phy;
|
||||
- struct resource *res;
|
||||
const struct of_device_id *match;
|
||||
const struct qcom_dwc3_phy_drvdata *data;
|
||||
struct device_node *np;
|
||||
@@ -505,7 +504,17 @@ static int qcom_dwc3_phy_probe(struct pl
|
||||
|
||||
phy_dwc3->dev = &pdev->dev;
|
||||
|
||||
- phy_dwc3->base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
|
||||
+ np = of_parse_phandle(pdev->dev.of_node, "regmap", 0);
|
||||
+ if (!np)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ if (!of_device_is_compatible(np, "syscon"))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ phy_dwc3->base = device_node_to_regmap(np);
|
||||
+
|
||||
+ of_node_put(np);
|
||||
+
|
||||
if (IS_ERR_OR_NULL(phy_dwc3->base))
|
||||
return PTR_ERR_OR_ZERO(phy_dwc3->base) ? : -EINVAL;
|
||||
|
||||
@ -60,7 +60,7 @@ will be executed twice with the same parameters for the same pinctrl.
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -671,6 +671,7 @@
|
||||
@@ -119,6 +119,7 @@
|
||||
reg = <0x800000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
@ -0,0 +1,29 @@
|
||||
From 51befb888f62b1a62434fb4b82328d698a30f9de Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Thu, 19 Mar 2020 23:44:24 +0100
|
||||
Subject: ARM: dts: qcom: add scm definition to ipq806x
|
||||
|
||||
Add missing scm definition for ipq806x soc
|
||||
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20200319224424.18473-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
---
|
||||
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -93,6 +93,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ firmware {
|
||||
+ scm {
|
||||
+ compatible = "qcom,scm-ipq806x", "qcom,scm";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
130
target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch
Normal file
130
target/linux/ipq806x/patches-5.4/082-ipq8064-dtsi-tweaks.patch
Normal file
@ -0,0 +1,130 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -20,7 +20,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
- cpu@0 {
|
||||
+ cpu0: cpu@0 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
device_type = "cpu";
|
||||
@@ -30,7 +30,7 @@
|
||||
qcom,saw = <&saw0>;
|
||||
};
|
||||
|
||||
- cpu@1 {
|
||||
+ cpu1: cpu@1 {
|
||||
compatible = "qcom,krait";
|
||||
enable-method = "qcom,kpss-acc-v1";
|
||||
device_type = "cpu";
|
||||
@@ -67,7 +67,7 @@
|
||||
no-map;
|
||||
};
|
||||
|
||||
- smem@41000000 {
|
||||
+ smem: smem@41000000 {
|
||||
reg = <0x41000000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
@@ -155,6 +155,7 @@
|
||||
function = "pcie3_rst";
|
||||
drive-strength = <12>;
|
||||
bias-disable;
|
||||
+ output-low;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -219,21 +220,23 @@
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
+ clock-output-names = "acpu0_aux";
|
||||
};
|
||||
|
||||
acc1: clock-controller@2098000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
+ clock-output-names = "acpu1_aux";
|
||||
};
|
||||
|
||||
saw0: regulator@2089000 {
|
||||
- compatible = "qcom,saw2";
|
||||
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
saw1: regulator@2099000 {
|
||||
- compatible = "qcom,saw2";
|
||||
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
@@ -251,7 +254,7 @@
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
- serial@12490000 {
|
||||
+ gsbi2_serial: serial@12490000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x12490000 0x1000>,
|
||||
<0x12480000 0x1000>;
|
||||
@@ -326,7 +329,7 @@
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
- serial@1a240000 {
|
||||
+ gsbi5_serial: serial@1a240000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x1a240000 0x1000>,
|
||||
<0x1a200000 0x1000>;
|
||||
@@ -397,7 +400,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- sata@29000000 {
|
||||
+ sata: sata@29000000 {
|
||||
compatible = "qcom,ipq806x-ahci", "generic-ahci";
|
||||
reg = <0x29000000 0x180>;
|
||||
|
||||
@@ -430,6 +433,7 @@
|
||||
reg = <0x00900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
+ #power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
tcsr: syscon@1a400000 {
|
||||
@@ -625,13 +629,13 @@
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
- amba {
|
||||
- compatible = "simple-bus";
|
||||
+ amba: amba {
|
||||
+ compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
- sdcc@12400000 {
|
||||
+ sdcc1: sdcc@12400000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
@@ -645,13 +649,12 @@
|
||||
non-removable;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
- mmc-ddr-1_8v;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
- sdcc@12180000 {
|
||||
+ sdcc3: sdcc@12180000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
status = "disabled";
|
||||
@ -0,0 +1,992 @@
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
||||
@@ -8,6 +8,8 @@
|
||||
#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+#include <dt-bindings/mfd/qcom-rpm.h>
|
||||
+#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
@@ -28,6 +30,16 @@
|
||||
next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc0>;
|
||||
qcom,saw = <&saw0>;
|
||||
+ clocks = <&kraitcc 0>, <&kraitcc 4>;
|
||||
+ clock-names = "cpu", "l2";
|
||||
+ clock-latency = <100000>;
|
||||
+ cpu-supply = <&smb208_s2a>;
|
||||
+ operating-points-v2 = <&opp_table0>;
|
||||
+ voltage-tolerance = <5>;
|
||||
+ cooling-min-state = <0>;
|
||||
+ cooling-max-state = <10>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SPC>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@@ -38,11 +50,458 @@
|
||||
next-level-cache = <&L2>;
|
||||
qcom,acc = <&acc1>;
|
||||
qcom,saw = <&saw1>;
|
||||
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
|
||||
+ clock-names = "cpu", "l2";
|
||||
+ clock-latency = <100000>;
|
||||
+ cpu-supply = <&smb208_s2b>;
|
||||
+ operating-points-v2 = <&opp_table0>;
|
||||
+ voltage-tolerance = <5>;
|
||||
+ cooling-min-state = <0>;
|
||||
+ cooling-max-state = <10>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ cpu-idle-states = <&CPU_SPC>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
+ qcom,saw = <&saw_l2>;
|
||||
+ };
|
||||
+
|
||||
+ qcom,l2 {
|
||||
+ qcom,l2-rates = <384000000 1000000000 1200000000>;
|
||||
+ qcom,l2-cpufreq = <384000000 600000000 1200000000>;
|
||||
+ qcom,l2-volt = <1100000 1100000 1150000>;
|
||||
+ qcom,l2-supply = <&smb208_s1a>;
|
||||
+ };
|
||||
+
|
||||
+ idle-states {
|
||||
+ CPU_SPC: spc {
|
||||
+ compatible = "qcom,idle-state-spc", "arm,idle-state";
|
||||
+ status = "disabled";
|
||||
+ entry-latency-us = <400>;
|
||||
+ exit-latency-us = <900>;
|
||||
+ min-residency-us = <3000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ opp_table0: opp_table0 {
|
||||
+ compatible = "operating-points-v2-kryo-cpu";
|
||||
+ nvmem-cells = <&speedbin_efuse>;
|
||||
+
|
||||
+ opp-384000000 {
|
||||
+ opp-hz = /bits/ 64 <384000000>;
|
||||
+ opp-microvolt-speed0-pvs0-v0 = <1000000>;
|
||||
+ opp-microvolt-speed0-pvs1-v0 = <925000>;
|
||||
+ opp-microvolt-speed0-pvs2-v0 = <875000>;
|
||||
+ opp-microvolt-speed0-pvs3-v0 = <800000>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <100000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt-speed0-pvs0-v0 = <1050000>;
|
||||
+ opp-microvolt-speed0-pvs1-v0 = <975000>;
|
||||
+ opp-microvolt-speed0-pvs2-v0 = <925000>;
|
||||
+ opp-microvolt-speed0-pvs3-v0 = <850000>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <100000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-800000000 {
|
||||
+ opp-hz = /bits/ 64 <800000000>;
|
||||
+ opp-microvolt-speed0-pvs0-v0 = <1100000>;
|
||||
+ opp-microvolt-speed0-pvs1-v0 = <1025000>;
|
||||
+ opp-microvolt-speed0-pvs2-v0 = <995000>;
|
||||
+ opp-microvolt-speed0-pvs3-v0 = <900000>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <100000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1000000000 {
|
||||
+ opp-hz = /bits/ 64 <1000000000>;
|
||||
+ opp-microvolt-speed0-pvs0-v0 = <1150000>;
|
||||
+ opp-microvolt-speed0-pvs1-v0 = <1075000>;
|
||||
+ opp-microvolt-speed0-pvs2-v0 = <1025000>;
|
||||
+ opp-microvolt-speed0-pvs3-v0 = <950000>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <100000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt-speed0-pvs0-v0 = <1200000>;
|
||||
+ opp-microvolt-speed0-pvs1-v0 = <1125000>;
|
||||
+ opp-microvolt-speed0-pvs2-v0 = <1075000>;
|
||||
+ opp-microvolt-speed0-pvs3-v0 = <1000000>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <100000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1400000000 {
|
||||
+ opp-hz = /bits/ 64 <1400000000>;
|
||||
+ opp-microvolt-speed0-pvs0-v0 = <1250000>;
|
||||
+ opp-microvolt-speed0-pvs1-v0 = <1175000>;
|
||||
+ opp-microvolt-speed0-pvs2-v0 = <1125000>;
|
||||
+ opp-microvolt-speed0-pvs3-v0 = <1050000>;
|
||||
+ opp-supported-hw = <0x1>;
|
||||
+ clock-latency-ns = <100000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ thermal-zones {
|
||||
+ tsens_tz_sensor0 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor1 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 1>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor2 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 2>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor3 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 3>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor4 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 4>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor5 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 5>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor6 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 6>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor7 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 7>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor8 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 8>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor9 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 9>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsens_tz_sensor10 {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <0>;
|
||||
+ thermal-sensors = <&tsens 10>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-critical-hi {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_high";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-hi {
|
||||
+ temperature = <105000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_hi";
|
||||
+ };
|
||||
+
|
||||
+ cpu-config-lo {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "configurable_lo";
|
||||
+ };
|
||||
+
|
||||
+ cpu-critical-low {
|
||||
+ temperature = <0>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical_low";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -93,6 +552,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ fab-scaling {
|
||||
+ compatible = "qcom,fab-scaling";
|
||||
+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
|
||||
+ clock-names = "apps-fab-clk", "ddr-fab-clk";
|
||||
+ fab_freq_high = <533000000>;
|
||||
+ fab_freq_nominal = <400000000>;
|
||||
+ cpu_freq_threshold = <1000000000>;
|
||||
+ };
|
||||
+
|
||||
firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm-ipq806x", "qcom,scm";
|
||||
@@ -120,6 +588,84 @@
|
||||
reg-names = "lpass-lpaif";
|
||||
};
|
||||
|
||||
+ qfprom: qfprom@700000 {
|
||||
+ compatible = "qcom,qfprom", "syscon";
|
||||
+ reg = <0x700000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ status = "okay";
|
||||
+ tsens_calib: calib@400 {
|
||||
+ reg = <0x400 0xb>;
|
||||
+ };
|
||||
+ tsens_backup: backup@410 {
|
||||
+ reg = <0x410 0xb>;
|
||||
+ };
|
||||
+ speedbin_efuse: speedbin@0c0 {
|
||||
+ reg = <0x0c0 0x4>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rpm: rpm@108000 {
|
||||
+ compatible = "qcom,rpm-ipq8064";
|
||||
+ reg = <0x108000 0x1000>;
|
||||
+ qcom,ipc = <&l2cc 0x8 2>;
|
||||
+
|
||||
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "ack", "err", "wakeup";
|
||||
+
|
||||
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
|
||||
+ clock-names = "ram";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rpmcc: clock-controller {
|
||||
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ regulators {
|
||||
+ compatible = "qcom,rpm-smb208-regulators";
|
||||
+
|
||||
+ smb208_s1a: s1a {
|
||||
+ regulator-min-microvolt = <1050000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+
|
||||
+ smb208_s1b: s1b {
|
||||
+ regulator-min-microvolt = <1050000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+
|
||||
+ smb208_s2a: s2a {
|
||||
+ regulator-min-microvolt = < 800000>;
|
||||
+ regulator-max-microvolt = <1250000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+
|
||||
+ smb208_s2b: s2b {
|
||||
+ regulator-min-microvolt = < 800000>;
|
||||
+ regulator-max-microvolt = <1250000>;
|
||||
+
|
||||
+ qcom,switch-mode-frequency = <1200000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rng@1a500000 {
|
||||
+ compatible = "qcom,prng";
|
||||
+ reg = <0x1a500000 0x200>;
|
||||
+ clocks = <&gcc PRNG_CLK>;
|
||||
+ clock-names = "core";
|
||||
+ };
|
||||
+
|
||||
qcom_pinmux: pinmux@800000 {
|
||||
compatible = "qcom,ipq8064-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
@@ -159,6 +705,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ i2c4_pins: i2c4_pinmux {
|
||||
+ mux {
|
||||
+ pins = "gpio12", "gpio13";
|
||||
+ function = "gsbi4";
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
spi_pins: spi_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19", "gpio21";
|
||||
@@ -168,6 +723,53 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ nand_pins: nand_pins {
|
||||
+ disable {
|
||||
+ pins = "gpio34", "gpio35", "gpio36",
|
||||
+ "gpio37", "gpio38";
|
||||
+ function = "nand";
|
||||
+ drive-strength = <10>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ pullups {
|
||||
+ pins = "gpio39";
|
||||
+ function = "nand";
|
||||
+ drive-strength = <10>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ hold {
|
||||
+ pins = "gpio40", "gpio41", "gpio42",
|
||||
+ "gpio43", "gpio44", "gpio45",
|
||||
+ "gpio46", "gpio47";
|
||||
+ function = "nand";
|
||||
+ drive-strength = <10>;
|
||||
+ bias-bus-hold;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ mdio0_pins: mdio0_pins {
|
||||
+ mux {
|
||||
+ pins = "gpio0", "gpio1";
|
||||
+ function = "mdio";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rgmii2_pins: rgmii2_pins {
|
||||
+ mux {
|
||||
+ pins = "gpio27", "gpio28", "gpio29",
|
||||
+ "gpio30", "gpio31", "gpio32",
|
||||
+ "gpio51", "gpio52", "gpio59",
|
||||
+ "gpio60", "gpio61", "gpio62";
|
||||
+ function = "rgmii2";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
leds_pins: leds_pins {
|
||||
mux {
|
||||
pins = "gpio7", "gpio8", "gpio9",
|
||||
@@ -229,6 +831,17 @@
|
||||
clock-output-names = "acpu1_aux";
|
||||
};
|
||||
|
||||
+ l2cc: clock-controller@2011000 {
|
||||
+ compatible = "qcom,kpss-gcc", "syscon";
|
||||
+ reg = <0x2011000 0x1000>;
|
||||
+ clock-output-names = "acpu_l2_aux";
|
||||
+ };
|
||||
+
|
||||
+ kraitcc: clock-controller {
|
||||
+ compatible = "qcom,krait-cc-v1";
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
saw0: regulator@2089000 {
|
||||
compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
@@ -241,6 +854,17 @@
|
||||
regulator;
|
||||
};
|
||||
|
||||
+ saw_l2: regulator@02012000 {
|
||||
+ compatible = "qcom,saw2", "syscon";
|
||||
+ reg = <0x02012000 0x1000>;
|
||||
+ regulator;
|
||||
+ };
|
||||
+
|
||||
+ sic_non_secure: sic-non-secure@12100000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x12100000 0x10000>;
|
||||
+ };
|
||||
+
|
||||
gsbi2: gsbi@12480000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <2>;
|
||||
@@ -436,6 +1060,15 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
+ tsens: thermal-sensor@900000 {
|
||||
+ compatible = "qcom,ipq8064-tsens";
|
||||
+ reg = <0x900000 0x3680>;
|
||||
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
|
||||
+ nvmem-cell-names = "calib", "calib_backup";
|
||||
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ #thermal-sensor-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
tcsr: syscon@1a400000 {
|
||||
compatible = "qcom,tcsr-ipq8064", "syscon";
|
||||
reg = <0x1a400000 0x100>;
|
||||
@@ -448,6 +1081,95 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
+ sfpb_mutex_block: syscon@1200600 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x01200600 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ hs_phy_0: hs_phy_0 {
|
||||
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
||||
+ reg = <0x110f8800 0x30>;
|
||||
+ clocks = <&gcc USB30_0_UTMI_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ss_phy_0: ss_phy_0 {
|
||||
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
||||
+ reg = <0x110f8830 0x30>;
|
||||
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ usb3_0: usb3@110f8800 {
|
||||
+ compatible = "qcom,dwc3", "syscon";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ reg = <0x110f8800 0x8000>;
|
||||
+ clocks = <&gcc USB30_0_MASTER_CLK>;
|
||||
+ clock-names = "core";
|
||||
+
|
||||
+ ranges;
|
||||
+
|
||||
+ resets = <&gcc USB30_0_MASTER_RESET>;
|
||||
+ reset-names = "master";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3_0: dwc3@11000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x11000000 0xcd00>;
|
||||
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&hs_phy_0>, <&ss_phy_0>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ snps,dis_u3_susphy_quirk;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hs_phy_1: hs_phy_1 {
|
||||
+ compatible = "qcom,ipq806x-usb-phy-hs";
|
||||
+ reg = <0x100f8800 0x30>;
|
||||
+ clocks = <&gcc USB30_1_UTMI_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ss_phy_1: ss_phy_1 {
|
||||
+ compatible = "qcom,ipq806x-usb-phy-ss";
|
||||
+ reg = <0x100f8830 0x30>;
|
||||
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
||||
+ clock-names = "ref";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ usb3_1: usb3@100f8800 {
|
||||
+ compatible = "qcom,dwc3", "syscon";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ reg = <0x100f8800 0x8000>;
|
||||
+ clocks = <&gcc USB30_1_MASTER_CLK>;
|
||||
+ clock-names = "core";
|
||||
+
|
||||
+ ranges;
|
||||
+
|
||||
+ resets = <&gcc USB30_1_MASTER_RESET>;
|
||||
+ reset-names = "master";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ dwc3_1: dwc3@10000000 {
|
||||
+ compatible = "snps,dwc3";
|
||||
+ reg = <0x10000000 0xcd00>;
|
||||
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&hs_phy_1>, <&ss_phy_1>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ dr_mode = "host";
|
||||
+ snps,dis_u3_susphy_quirk;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pcie0: pci@1b500000 {
|
||||
compatible = "qcom,pcie-ipq8064";
|
||||
reg = <0x1b500000 0x1000
|
||||
@@ -601,6 +1323,167 @@
|
||||
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
+ adm_dma: dma@18300000 {
|
||||
+ compatible = "qcom,adm";
|
||||
+ reg = <0x18300000 0x100000>;
|
||||
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ #dma-cells = <1>;
|
||||
+
|
||||
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
|
||||
+ clock-names = "core", "iface";
|
||||
+
|
||||
+ resets = <&gcc ADM0_RESET>,
|
||||
+ <&gcc ADM0_PBUS_RESET>,
|
||||
+ <&gcc ADM0_C0_RESET>,
|
||||
+ <&gcc ADM0_C1_RESET>,
|
||||
+ <&gcc ADM0_C2_RESET>;
|
||||
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
|
||||
+ qcom,ee = <0>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ nand_controller: nand-controller@1ac00000 {
|
||||
+ compatible = "qcom,ipq806x-nand";
|
||||
+ reg = <0x1ac00000 0x800>;
|
||||
+
|
||||
+ clocks = <&gcc EBI2_CLK>,
|
||||
+ <&gcc EBI2_AON_CLK>;
|
||||
+ clock-names = "core", "aon";
|
||||
+
|
||||
+ dmas = <&adm_dma 3>;
|
||||
+ dma-names = "rxtx";
|
||||
+ qcom,cmd-crci = <15>;
|
||||
+ qcom,data-crci = <3>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ nss_common: syscon@03000000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x03000000 0x0000FFFF>;
|
||||
+ };
|
||||
+
|
||||
+ qsgmii_csr: syscon@1bb00000 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x1bb00000 0x000001FF>;
|
||||
+ };
|
||||
+
|
||||
+ stmmac_axi_setup: stmmac-axi-config {
|
||||
+ snps,wr_osr_lmt = <7>;
|
||||
+ snps,rd_osr_lmt = <7>;
|
||||
+ snps,blen = <16 0 0 0 0 0 0>;
|
||||
+ };
|
||||
+
|
||||
+ mdio0: mdio@37000000 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ compatible = "qcom,ipq8064-mdio", "syscon";
|
||||
+ reg = <0x37000000 0x200000>;
|
||||
+ resets = <&gcc GMAC_CORE1_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac0: ethernet@37000000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac";
|
||||
+ reg = <0x37000000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ snps,axi-config = <&stmmac_axi_setup>;
|
||||
+ snps,pbl = <32>;
|
||||
+ snps,aal = <1>;
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE1_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE1_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac1: ethernet@37200000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac";
|
||||
+ reg = <0x37200000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ snps,axi-config = <&stmmac_axi_setup>;
|
||||
+ snps,pbl = <32>;
|
||||
+ snps,aal = <1>;
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE2_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE2_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac2: ethernet@37400000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
||||
+ reg = <0x37400000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ snps,axi-config = <&stmmac_axi_setup>;
|
||||
+ snps,pbl = <32>;
|
||||
+ snps,aal = <1>;
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE3_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE3_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ gmac3: ethernet@37600000 {
|
||||
+ device_type = "network";
|
||||
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
|
||||
+ reg = <0x37600000 0x200000>;
|
||||
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq";
|
||||
+
|
||||
+ snps,axi-config = <&stmmac_axi_setup>;
|
||||
+ snps,pbl = <32>;
|
||||
+ snps,aal = <1>;
|
||||
+
|
||||
+ qcom,nss-common = <&nss_common>;
|
||||
+ qcom,qsgmii-csr = <&qsgmii_csr>;
|
||||
+
|
||||
+ clocks = <&gcc GMAC_CORE4_CLK>;
|
||||
+ clock-names = "stmmaceth";
|
||||
+
|
||||
+ resets = <&gcc GMAC_CORE4_RESET>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
vsdcc_fixed: vsdcc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SDCC Power";
|
||||
@@ -676,4 +1559,17 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ sfpb_mutex: sfpb-mutex {
|
||||
+ compatible = "qcom,sfpb-mutex";
|
||||
+ syscon = <&sfpb_mutex_block 4 4>;
|
||||
+
|
||||
+ #hwlock-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ smem {
|
||||
+ compatible = "qcom,smem";
|
||||
+ memory-region = <&smem>;
|
||||
+ hwlocks = <&sfpb_mutex 3>;
|
||||
+ };
|
||||
};
|
||||
@ -0,0 +1,89 @@
|
||||
This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
|
||||
instead of keeping a local version.
|
||||
We drop partitions, LEDs and keys from the file as we will implement
|
||||
them differently anyway.
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
|
||||
@@ -42,16 +42,6 @@
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
-
|
||||
- partition@0 {
|
||||
- label = "rootfs";
|
||||
- reg = <0x0 0x1000000>;
|
||||
- };
|
||||
-
|
||||
- partition@1 {
|
||||
- label = "scratch";
|
||||
- reg = <0x1000000 0x1000000>;
|
||||
- };
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -64,64 +54,5 @@
|
||||
ports-implemented = <0x1>;
|
||||
status = "ok";
|
||||
};
|
||||
-
|
||||
- gpio_keys {
|
||||
- compatible = "gpio-keys";
|
||||
- pinctrl-0 = <&buttons_pins>;
|
||||
- pinctrl-names = "default";
|
||||
-
|
||||
- button@1 {
|
||||
- label = "reset";
|
||||
- linux,code = <KEY_RESTART>;
|
||||
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
|
||||
- linux,input-type = <1>;
|
||||
- debounce-interval = <60>;
|
||||
- };
|
||||
- button@2 {
|
||||
- label = "wps";
|
||||
- linux,code = <KEY_WPS_BUTTON>;
|
||||
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
|
||||
- linux,input-type = <1>;
|
||||
- debounce-interval = <60>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- leds {
|
||||
- compatible = "gpio-leds";
|
||||
- pinctrl-0 = <&leds_pins>;
|
||||
- pinctrl-names = "default";
|
||||
-
|
||||
- led@7 {
|
||||
- label = "led_usb1";
|
||||
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
|
||||
- linux,default-trigger = "usbdev";
|
||||
- default-state = "off";
|
||||
- };
|
||||
-
|
||||
- led@8 {
|
||||
- label = "led_usb3";
|
||||
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
|
||||
- linux,default-trigger = "usbdev";
|
||||
- default-state = "off";
|
||||
- };
|
||||
-
|
||||
- led@9 {
|
||||
- label = "status_led_fail";
|
||||
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
|
||||
- default-state = "off";
|
||||
- };
|
||||
-
|
||||
- led@26 {
|
||||
- label = "sata_led";
|
||||
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
|
||||
- default-state = "off";
|
||||
- };
|
||||
-
|
||||
- led@53 {
|
||||
- label = "status_led_pass";
|
||||
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
|
||||
- default-state = "off";
|
||||
- };
|
||||
- };
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,26 @@
|
||||
This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches
|
||||
instead of keeping a local version. This patch adds our local adjustments
|
||||
for the (local) additional contents of qcom-ipq8064.dtsi
|
||||
|
||||
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
|
||||
@@ -56,3 +56,19 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&CPU_SPC {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie0 {
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+};
|
||||
+
|
||||
+&pcie1 {
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+};
|
||||
+
|
||||
+&pcie2 {
|
||||
+ phy-tx0-term-offset = <7>;
|
||||
+};
|
||||
@ -0,0 +1,104 @@
|
||||
From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
|
||||
From: Ajay Kishore <akisho@codeaurora.org>
|
||||
Date: Fri, 27 Mar 2020 23:32:08 +0100
|
||||
Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
|
||||
|
||||
For IPQ806x targets, TZ protects the registers that are used to
|
||||
configure the routing of interrupts to a target processor.
|
||||
To resolve this, this patch uses scm call to route GPIO interrupts
|
||||
to application processor. Also the scm call interface is changed.
|
||||
|
||||
Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
|
||||
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
|
||||
1 file changed, 37 insertions(+), 6 deletions(-)
|
||||
|
||||
(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
|
||||
|
||||
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
|
||||
@@ -22,6 +22,8 @@
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/log2.h>
|
||||
+#include <linux/qcom_scm.h>
|
||||
+#include <linux/io.h>
|
||||
|
||||
#include "../core.h"
|
||||
#include "../pinconf.h"
|
||||
@@ -57,6 +59,8 @@ struct msm_pinctrl {
|
||||
struct irq_chip irq_chip;
|
||||
int irq;
|
||||
|
||||
+ bool intr_target_use_scm;
|
||||
+
|
||||
raw_spinlock_t lock;
|
||||
|
||||
DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
|
||||
@@ -64,6 +68,7 @@ struct msm_pinctrl {
|
||||
|
||||
const struct msm_pinctrl_soc_data *soc;
|
||||
void __iomem *regs[MAX_NR_TILES];
|
||||
+ u32 phys_base[MAX_NR_TILES];
|
||||
};
|
||||
|
||||
#define MSM_ACCESSOR(name) \
|
||||
@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
|
||||
else
|
||||
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
|
||||
|
||||
- /* Route interrupts to application cpu */
|
||||
- val = msm_readl_intr_target(pctrl, g);
|
||||
- val &= ~(7 << g->intr_target_bit);
|
||||
- val |= g->intr_target_kpss_val << g->intr_target_bit;
|
||||
- msm_writel_intr_target(val, pctrl, g);
|
||||
+ /* Route interrupts to application cpu.
|
||||
+ * With intr_target_use_scm interrupts are routed to
|
||||
+ * application cpu using scm calls.
|
||||
+ */
|
||||
+ if (pctrl->intr_target_use_scm) {
|
||||
+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
|
||||
+ int ret;
|
||||
+
|
||||
+ qcom_scm_io_readl(addr, &val);
|
||||
+
|
||||
+ val &= ~(7 << g->intr_target_bit);
|
||||
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
|
||||
+
|
||||
+ ret = qcom_scm_io_writel(addr, val);
|
||||
+ if (ret)
|
||||
+ dev_err(pctrl->dev,
|
||||
+ "Failed routing %lu interrupt to Apps proc",
|
||||
+ d->hwirq);
|
||||
+ } else {
|
||||
+ val = msm_readl_intr_target(pctrl, g);
|
||||
+ val &= ~(7 << g->intr_target_bit);
|
||||
+ val |= g->intr_target_kpss_val << g->intr_target_bit;
|
||||
+ msm_writel_intr_target(val, pctrl, g);
|
||||
+ }
|
||||
|
||||
/* Update configuration for gpio.
|
||||
* RAW_STATUS_EN is left on for all gpio irqs. Due to the
|
||||
@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
|
||||
pctrl->dev = &pdev->dev;
|
||||
pctrl->soc = soc_data;
|
||||
pctrl->chip = msm_gpio_template;
|
||||
+ pctrl->intr_target_use_scm = of_device_is_compatible(
|
||||
+ pctrl->dev->of_node,
|
||||
+ "qcom,ipq8064-pinctrl");
|
||||
|
||||
raw_spin_lock_init(&pctrl->lock);
|
||||
|
||||
@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
|
||||
pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pctrl->regs[0]))
|
||||
return PTR_ERR(pctrl->regs[0]);
|
||||
+
|
||||
+ pctrl->phys_base[0] = res->start;
|
||||
}
|
||||
|
||||
msm_pinctrl_setup_pm_reset(pctrl);
|
||||
@ -1,9 +1,15 @@
|
||||
From a3488aa9bed37c56e405967d44e821c484b5d6b9 Mon Sep 17 00:00:00 2001
|
||||
From: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Date: Fri, 28 Sep 2018 15:19:50 +0530
|
||||
Subject: [PATCH] ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
|
||||
From 8d8cec9bf6e9260397872785f249dfb59a417d08 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Wed, 19 Feb 2020 18:59:39 +0100
|
||||
Subject: ipq8064: pinctrl: Fixed missing RGMII pincontrol definitions
|
||||
|
||||
Add missing gpio definition for mdio and rgmii2.
|
||||
|
||||
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20200219175940.744-1-ansuelsmth@gmail.com
|
||||
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
---
|
||||
drivers/pinctrl/qcom/pinctrl-ipq8064.c | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
@ -1,7 +1,7 @@
|
||||
From 53ae145a7afa7686e03332d61eed90b7fa7c2529 Mon Sep 17 00:00:00 2001
|
||||
From 000de5417107623925a4cf0310579f744ff43c28 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Tue, 4 Feb 2020 19:38:06 +0100
|
||||
Subject: [PATCH v2] watchdog: qcom-wdt: disable pretimeout on timer platform
|
||||
Date: Tue, 4 Feb 2020 20:56:48 +0100
|
||||
Subject: watchdog: qcom-wdt: disable pretimeout on timer platform
|
||||
|
||||
Some platform like ipq806x doesn't support pretimeout and define
|
||||
some interrupts used by qcom,msm-timer. Change the driver to check
|
||||
@ -9,6 +9,11 @@ and use pretimeout only on qcom,kpss-wdt as it's the only platform
|
||||
that actually supports it.
|
||||
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
|
||||
Link: https://lore.kernel.org/r/20200204195648.23350-1-ansuelsmth@gmail.com
|
||||
[groeck: Conflict resolution]
|
||||
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
|
||||
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
|
||||
---
|
||||
drivers/watchdog/qcom-wdt.c | 31 +++++++++++++++++++++++--------
|
||||
1 file changed, 23 insertions(+), 8 deletions(-)
|
||||
@ -1,13 +1,16 @@
|
||||
From a16fcf911a020e46439a3bb3e702463fc3159831 Mon Sep 17 00:00:00 2001
|
||||
From 1aec193ea41d672d11592714cdda8167eb3b38fc Mon Sep 17 00:00:00 2001
|
||||
From: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Date: Wed, 18 Nov 2015 12:38:56 +0530
|
||||
Subject: [PATCH 62/69] ipq806x: gcc: Added the enable regs and mask for PRNG
|
||||
Date: Wed, 18 Mar 2020 14:16:56 +0100
|
||||
Subject: ipq806x: gcc: Added the enable regs and mask for PRNG
|
||||
|
||||
kernel got hanged while reading from /dev/hwrng at the
|
||||
Kernel got hanged while reading from /dev/hwrng at the
|
||||
time of PRNG clock enable
|
||||
|
||||
Change-Id: I89856c7e19e6639508e6a2774304583a3ec91172
|
||||
Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Link: https://lkml.kernel.org/r/20200318131657.345-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/qcom/gcc-ipq806x.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
@ -1,9 +1,16 @@
|
||||
From d30840e2b1cf79d90392e6051b0c0b6006d29d8b Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Thu, 9 Mar 2017 09:32:40 +0100
|
||||
Subject: [PATCH 64/69] clk: clk-rpm fixes
|
||||
From eec152734be10c72d2d413a27ca9d282c28cdb61 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Tue, 10 Mar 2020 15:37:56 +0100
|
||||
Subject: clk: qcom: clk-rpm: add missing rpm clk for ipq806x
|
||||
|
||||
Add missing definition of rpm clk for ipq806x soc
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Acked-by: John Crispin <john@phrozen.org>
|
||||
Reviewed-by: Rob Herring <robh@kernel.org>
|
||||
Link: https://lkml.kernel.org/r/20200310143756.244-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
|
||||
drivers/clk/qcom/clk-rpm.c | 35 ++++++++++++++++++++++
|
||||
@ -12,32 +19,19 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
|
||||
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
|
||||
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
|
||||
@@ -16,6 +16,7 @@ Required properties :
|
||||
@@ -15,6 +15,7 @@ Required properties :
|
||||
"qcom,rpmcc-msm8916", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8974", "qcom,rpmcc"
|
||||
"qcom,rpmcc-apq8064", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
+ "qcom,rpmcc-ipq806x", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8996", "qcom,rpmcc"
|
||||
"qcom,rpmcc-msm8998", "qcom,rpmcc"
|
||||
"qcom,rpmcc-qcs404", "qcom,rpmcc"
|
||||
|
||||
--- a/include/dt-bindings/clock/qcom,rpmcc.h
|
||||
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
|
||||
@@ -37,6 +37,10 @@
|
||||
#define RPM_XO_A0 27
|
||||
#define RPM_XO_A1 28
|
||||
#define RPM_XO_A2 29
|
||||
+#define RPM_NSS_FABRIC_0_CLK 30
|
||||
+#define RPM_NSS_FABRIC_0_A_CLK 31
|
||||
+#define RPM_NSS_FABRIC_1_CLK 32
|
||||
+#define RPM_NSS_FABRIC_1_A_CLK 33
|
||||
|
||||
/* SMD RPM clocks */
|
||||
#define RPM_SMD_XO_CLK_SRC 0
|
||||
--- a/drivers/clk/qcom/clk-rpm.c
|
||||
+++ b/drivers/clk/qcom/clk-rpm.c
|
||||
@@ -512,6 +512,16 @@ DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_
|
||||
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
|
||||
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
|
||||
@@ -543,10 +543,45 @@ static const struct rpm_clk_desc rpm_clk
|
||||
.num_clks = ARRAY_SIZE(apq8064_clks),
|
||||
};
|
||||
|
||||
+/* ipq806x */
|
||||
+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
|
||||
@ -49,13 +43,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
|
||||
+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
|
||||
+
|
||||
static struct clk_rpm *apq8064_clks[] = {
|
||||
[RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
|
||||
[RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
|
||||
@@ -538,15 +548,40 @@ static struct clk_rpm *apq8064_clks[] =
|
||||
[RPM_XO_A2] = &apq8064_xo_a2_clk,
|
||||
};
|
||||
|
||||
+static struct clk_rpm *ipq806x_clks[] = {
|
||||
+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
|
||||
+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
|
||||
@ -75,11 +62,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
|
||||
+};
|
||||
+
|
||||
static const struct rpm_clk_desc rpm_clk_apq8064 = {
|
||||
.clks = apq8064_clks,
|
||||
.num_clks = ARRAY_SIZE(apq8064_clks),
|
||||
};
|
||||
|
||||
+static const struct rpm_clk_desc rpm_clk_ipq806x = {
|
||||
+ .clks = ipq806x_clks,
|
||||
+ .num_clks = ARRAY_SIZE(ipq806x_clks),
|
||||
@ -93,3 +75,16 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
|
||||
--- a/include/dt-bindings/clock/qcom,rpmcc.h
|
||||
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
|
||||
@@ -37,6 +37,10 @@
|
||||
#define RPM_XO_A0 27
|
||||
#define RPM_XO_A1 28
|
||||
#define RPM_XO_A2 29
|
||||
+#define RPM_NSS_FABRIC_0_CLK 30
|
||||
+#define RPM_NSS_FABRIC_0_A_CLK 31
|
||||
+#define RPM_NSS_FABRIC_1_CLK 32
|
||||
+#define RPM_NSS_FABRIC_1_A_CLK 33
|
||||
|
||||
/* SMD RPM clocks */
|
||||
#define RPM_SMD_XO_CLK_SRC 0
|
||||
@ -1,9 +1,17 @@
|
||||
From ef10381ca4d01848ebedb4afb2c78feb8052f103 Mon Sep 17 00:00:00 2001
|
||||
From: Adrian Panella <ianchi74@outlook.com>
|
||||
Date: Thu, 9 Mar 2017 08:26:54 +0100
|
||||
Subject: [PATCH 53/69] regulator: add smb208 support
|
||||
From b5f25304aece9f2e7eaab275bbb5461c666bf38c Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Wed, 19 Feb 2020 17:37:11 +0100
|
||||
Subject: regulator: add smb208 support
|
||||
|
||||
Smb208 regulators are used on some ipq806x soc.
|
||||
Add support for it to make it avaiable on some routers
|
||||
that use it.
|
||||
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
||||
Acked-by: Lee Jones <lee.jones@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20200219163711.479-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 4 ++++
|
||||
drivers/regulator/qcom_rpm-regulator.c | 9 +++++++++
|
||||
@ -1,13 +1,7 @@
|
||||
Subject: [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs
|
||||
Date: Tue, 14 Aug 2018 17:42:33 +0530
|
||||
Message-Id: <1534248753-2440-15-git-send-email-sricharan@codeaurora.org>
|
||||
X-Mailer: git-send-email 1.9.1
|
||||
In-Reply-To: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org>
|
||||
References: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org>
|
||||
Sender: linux-kernel-owner@vger.kernel.org
|
||||
Precedence: bulk
|
||||
List-ID: <linux-kernel.vger.kernel.org>
|
||||
X-Mailing-List: linux-kernel@vger.kernel.org
|
||||
From a8811ec764f95a04ba82f6f457e28c5e9e36e36b Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Fri, 13 Mar 2020 18:52:13 +0100
|
||||
Subject: cpufreq: qcom: Add support for krait based socs
|
||||
|
||||
In Certain QCOM SoCs like ipq8064, apq8064, msm8960, msm8974
|
||||
that has KRAIT processors the voltage/current value of each OPP
|
||||
@ -18,27 +12,27 @@ the efuse value. This is similar to the existing code for
|
||||
kryo cores. So adding support for krait cores here.
|
||||
|
||||
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
|
||||
---
|
||||
.../devicetree/bindings/opp/qcom-nvmem-cpufreq.txt | 3 +-
|
||||
drivers/cpufreq/Kconfig.arm | 2 +-
|
||||
drivers/cpufreq/cpufreq-dt-platdev.c | 5 +
|
||||
drivers/cpufreq/qcom-cpufreq-nvmem.c | 151 +++++++++++++++++++--
|
||||
4 files changed, 149 insertions(+), 12 deletions(-)
|
||||
drivers/cpufreq/qcom-cpufreq-nvmem.c | 191 +++++++++++++++++++--
|
||||
4 files changed, 183 insertions(+), 18 deletions(-)
|
||||
|
||||
# diff --git a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
# index 6dcdfcd..7bc0f1a 100644
|
||||
# --- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
# +++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
# @@ -19,7 +19,8 @@ In 'cpus' nodes:
|
||||
--- a/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
+++ b/Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
@@ -19,7 +19,8 @@ In 'cpu' nodes:
|
||||
|
||||
# In 'operating-points-v2' table:
|
||||
# - compatible: Should be
|
||||
# - - 'operating-points-v2-qcom-cpu' for apq8096 and msm8996.
|
||||
# + - 'operating-points-v2-qcom-cpu' for apq8096, msm8996, msm8974,
|
||||
# + apq8064, msm8960 and ipq8074.
|
||||
# - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
|
||||
# efuse registers that has information about the
|
||||
# speedbin that is used to select the right frequency/voltage
|
||||
In 'operating-points-v2' table:
|
||||
- compatible: Should be
|
||||
- - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
|
||||
+ - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
|
||||
+ apq8064, ipq8064, msm8960 and ipq8074.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
--- a/drivers/cpufreq/Kconfig.arm
|
||||
+++ b/drivers/cpufreq/Kconfig.arm
|
||||
@@ -134,7 +134,7 @@ config ARM_OMAP2PLUS_CPUFREQ
|
||||
@ -77,16 +71,17 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
|
||||
struct qcom_cpufreq_drv {
|
||||
- struct opp_table **opp_tables;
|
||||
+ struct opp_table **opp_tables1;
|
||||
+ struct opp_table **opp_tables2;
|
||||
+ struct opp_table **names_opp_tables;
|
||||
+ struct opp_table **hw_opp_tables;
|
||||
struct opp_table **genpd_opp_tables;
|
||||
u32 versions;
|
||||
const struct qcom_cpufreq_match_data *data;
|
||||
@@ -62,6 +64,79 @@ struct qcom_cpufreq_drv {
|
||||
@@ -62,6 +64,84 @@ struct qcom_cpufreq_drv {
|
||||
|
||||
static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
|
||||
|
||||
+static void get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver,
|
||||
+static void get_krait_bin_format_a(struct device *cpu_dev,
|
||||
+ int *speed, int *pvs, int *pvs_ver,
|
||||
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
|
||||
+{
|
||||
+ u32 pte_efuse;
|
||||
@ -99,9 +94,9 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
+
|
||||
+ if (*speed == 0xf) {
|
||||
+ *speed = 0;
|
||||
+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
|
||||
+ dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
|
||||
+ } else {
|
||||
+ pr_info("Speed bin: %d\n", *speed);
|
||||
+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
|
||||
+ }
|
||||
+
|
||||
+ *pvs = (pte_efuse >> 10) & 0x7;
|
||||
@ -110,39 +105,43 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
+
|
||||
+ if (*pvs == 0x7) {
|
||||
+ *pvs = 0;
|
||||
+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
|
||||
+ dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
|
||||
+ } else {
|
||||
+ pr_info("PVS bin: %d\n", *pvs);
|
||||
+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver,
|
||||
+static void get_krait_bin_format_b(struct device *cpu_dev,
|
||||
+ int *speed, int *pvs, int *pvs_ver,
|
||||
+ struct nvmem_cell *pvs_nvmem, u8 *buf)
|
||||
+{
|
||||
+ u32 pte_efuse, redundant_sel;
|
||||
+
|
||||
+ pte_efuse = *((u32 *)buf);
|
||||
+ redundant_sel = (pte_efuse >> 24) & 0x7;
|
||||
+ *speed = pte_efuse & 0x7;
|
||||
+
|
||||
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
|
||||
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
|
||||
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
|
||||
+
|
||||
+ switch (redundant_sel) {
|
||||
+ case 1:
|
||||
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
|
||||
+ *speed = (pte_efuse >> 27) & 0xf;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ *pvs = (pte_efuse >> 27) & 0xf;
|
||||
+ *speed = pte_efuse & 0x7;
|
||||
+ break;
|
||||
+ default:
|
||||
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
|
||||
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
|
||||
+ *speed = pte_efuse & 0x7;
|
||||
+ }
|
||||
+
|
||||
+ /* Check SPEED_BIN_BLOW_STATUS */
|
||||
+ if (pte_efuse & BIT(3)) {
|
||||
+ pr_info("Speed bin: %d\n", *speed);
|
||||
+ dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
|
||||
+ } else {
|
||||
+ pr_warn("Speed bin not set. Defaulting to 0!\n");
|
||||
+ dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
|
||||
+ *speed = 0;
|
||||
+ }
|
||||
+
|
||||
@ -150,19 +149,19 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
+ pte_efuse = *(((u32 *)buf) + 4);
|
||||
+ pte_efuse &= BIT(21);
|
||||
+ if (pte_efuse) {
|
||||
+ pr_info("PVS bin: %d\n", *pvs);
|
||||
+ dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
|
||||
+ } else {
|
||||
+ pr_warn("PVS bin not set. Defaulting to 0!\n");
|
||||
+ dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
|
||||
+ *pvs = 0;
|
||||
+ }
|
||||
+
|
||||
+ pr_info("PVS version: %d\n", *pvs_ver);
|
||||
+ dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
|
||||
+}
|
||||
+
|
||||
static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
|
||||
{
|
||||
size_t len;
|
||||
@@ -93,11 +168,13 @@ static enum _msm8996_version qcom_cpufre
|
||||
@@ -93,11 +173,13 @@ static enum _msm8996_version qcom_cpufre
|
||||
|
||||
static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
|
||||
struct nvmem_cell *speedbin_nvmem,
|
||||
@ -176,7 +175,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
|
||||
msm8996_version = qcom_cpufreq_get_msm_id();
|
||||
if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
|
||||
@@ -125,10 +202,44 @@ static int qcom_cpufreq_kryo_name_versio
|
||||
@@ -125,10 +207,51 @@ static int qcom_cpufreq_kryo_name_versio
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -190,13 +189,20 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
+ size_t len;
|
||||
+
|
||||
+ speedbin = nvmem_cell_read(speedbin_nvmem, &len);
|
||||
+ if (len == 4) {
|
||||
+ get_krait_bin_format_a(&speed, &pvs, &pvs_ver,
|
||||
+
|
||||
+ if (IS_ERR(speedbin))
|
||||
+ return PTR_ERR(speedbin);
|
||||
+
|
||||
+ switch (len) {
|
||||
+ case 4:
|
||||
+ get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
|
||||
+ speedbin_nvmem, speedbin);
|
||||
+ } else if (len == 8) {
|
||||
+ get_krait_bin_format_b(&speed, &pvs, &pvs_ver,
|
||||
+ break;
|
||||
+ case 8:
|
||||
+ get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
|
||||
+ speedbin_nvmem, speedbin);
|
||||
+ } else {
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
@ -221,7 +227,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
static const char *qcs404_genpd_names[] = { "cpr", NULL };
|
||||
|
||||
static const struct qcom_cpufreq_match_data match_data_qcs404 = {
|
||||
@@ -141,6 +252,7 @@ static int qcom_cpufreq_probe(struct pla
|
||||
@@ -141,6 +264,7 @@ static int qcom_cpufreq_probe(struct pla
|
||||
struct nvmem_cell *speedbin_nvmem;
|
||||
struct device_node *np;
|
||||
struct device *cpu_dev;
|
||||
@ -229,7 +235,7 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
unsigned cpu;
|
||||
const struct of_device_id *match;
|
||||
int ret;
|
||||
@@ -153,7 +265,7 @@ static int qcom_cpufreq_probe(struct pla
|
||||
@@ -153,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
|
||||
if (!np)
|
||||
return -ENOENT;
|
||||
|
||||
@ -238,106 +244,111 @@ Signed-off-by: Sricharan R <sricharan@codeaurora.org>
|
||||
if (!ret) {
|
||||
of_node_put(np);
|
||||
return -ENOENT;
|
||||
@@ -181,7 +293,7 @@ static int qcom_cpufreq_probe(struct pla
|
||||
@@ -181,7 +305,8 @@ static int qcom_cpufreq_probe(struct pla
|
||||
goto free_drv;
|
||||
}
|
||||
|
||||
- ret = drv->data->get_version(cpu_dev, speedbin_nvmem, drv);
|
||||
+ ret = drv->data->get_version(cpu_dev, speedbin_nvmem, &pvs_name, drv);
|
||||
+ ret = drv->data->get_version(cpu_dev,
|
||||
+ speedbin_nvmem, &pvs_name, drv);
|
||||
if (ret) {
|
||||
nvmem_cell_put(speedbin_nvmem);
|
||||
goto free_drv;
|
||||
@@ -190,12 +302,18 @@ static int qcom_cpufreq_probe(struct pla
|
||||
@@ -190,12 +315,20 @@ static int qcom_cpufreq_probe(struct pla
|
||||
}
|
||||
of_node_put(np);
|
||||
|
||||
- drv->opp_tables = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables),
|
||||
+ drv->opp_tables1 = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables1),
|
||||
+ drv->names_opp_tables = kcalloc(num_possible_cpus(),
|
||||
+ sizeof(*drv->names_opp_tables),
|
||||
GFP_KERNEL);
|
||||
- if (!drv->opp_tables) {
|
||||
+ if (!drv->opp_tables1) {
|
||||
+ if (!drv->names_opp_tables) {
|
||||
ret = -ENOMEM;
|
||||
goto free_drv;
|
||||
}
|
||||
+ drv->opp_tables2 = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tables2),
|
||||
+ drv->hw_opp_tables = kcalloc(num_possible_cpus(),
|
||||
+ sizeof(*drv->hw_opp_tables),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!drv->opp_tables2) {
|
||||
+ if (!drv->hw_opp_tables) {
|
||||
+ ret = -ENOMEM;
|
||||
+ goto free_opp1;
|
||||
+ goto free_opp_names;
|
||||
+ }
|
||||
|
||||
drv->genpd_opp_tables = kcalloc(num_possible_cpus(),
|
||||
sizeof(*drv->genpd_opp_tables),
|
||||
@@ -213,11 +331,22 @@ static int qcom_cpufreq_probe(struct pla
|
||||
@@ -213,11 +346,23 @@ static int qcom_cpufreq_probe(struct pla
|
||||
}
|
||||
|
||||
if (drv->data->get_version) {
|
||||
- drv->opp_tables[cpu] =
|
||||
- dev_pm_opp_set_supported_hw(cpu_dev,
|
||||
- &drv->versions, 1);
|
||||
- if (IS_ERR(drv->opp_tables[cpu])) {
|
||||
- ret = PTR_ERR(drv->opp_tables[cpu]);
|
||||
+
|
||||
+ if (pvs_name) {
|
||||
+ drv->opp_tables1[cpu] = dev_pm_opp_set_prop_name(cpu_dev,
|
||||
+ drv->names_opp_tables[cpu] = dev_pm_opp_set_prop_name(
|
||||
+ cpu_dev,
|
||||
+ pvs_name);
|
||||
+ if (IS_ERR(drv->opp_tables1[cpu])) {
|
||||
+ ret = PTR_ERR(drv->opp_tables1[cpu]);
|
||||
+ if (IS_ERR(drv->names_opp_tables[cpu])) {
|
||||
+ ret = PTR_ERR(drv->names_opp_tables[cpu]);
|
||||
+ dev_err(cpu_dev, "Failed to add OPP name %s\n",
|
||||
+ pvs_name);
|
||||
+ goto free_opp;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ drv->opp_tables2[cpu] = dev_pm_opp_set_supported_hw(cpu_dev,
|
||||
&drv->versions, 1);
|
||||
- if (IS_ERR(drv->opp_tables[cpu])) {
|
||||
- ret = PTR_ERR(drv->opp_tables[cpu]);
|
||||
+ if (IS_ERR(drv->opp_tables2[cpu])) {
|
||||
+ ret = PTR_ERR(drv->opp_tables2[cpu]);
|
||||
+ drv->hw_opp_tables[cpu] = dev_pm_opp_set_supported_hw(
|
||||
+ cpu_dev, &drv->versions, 1);
|
||||
+ if (IS_ERR(drv->hw_opp_tables[cpu])) {
|
||||
+ ret = PTR_ERR(drv->hw_opp_tables[cpu]);
|
||||
dev_err(cpu_dev,
|
||||
"Failed to set supported hardware\n");
|
||||
goto free_genpd_opp;
|
||||
@@ -259,11 +388,18 @@ free_genpd_opp:
|
||||
@@ -259,11 +404,18 @@ free_genpd_opp:
|
||||
kfree(drv->genpd_opp_tables);
|
||||
free_opp:
|
||||
for_each_possible_cpu(cpu) {
|
||||
- if (IS_ERR_OR_NULL(drv->opp_tables[cpu]))
|
||||
+ if (IS_ERR_OR_NULL(drv->opp_tables1[cpu]))
|
||||
+ if (IS_ERR_OR_NULL(drv->names_opp_tables[cpu]))
|
||||
+ break;
|
||||
+ dev_pm_opp_put_prop_name(drv->opp_tables1[cpu]);
|
||||
+ dev_pm_opp_put_prop_name(drv->names_opp_tables[cpu]);
|
||||
+ }
|
||||
+ for_each_possible_cpu(cpu) {
|
||||
+ if (IS_ERR_OR_NULL(drv->opp_tables2[cpu]))
|
||||
+ if (IS_ERR_OR_NULL(drv->hw_opp_tables[cpu]))
|
||||
break;
|
||||
- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
|
||||
+ dev_pm_opp_put_supported_hw(drv->opp_tables2[cpu]);
|
||||
+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
|
||||
}
|
||||
- kfree(drv->opp_tables);
|
||||
+ kfree(drv->opp_tables2);
|
||||
+free_opp1:
|
||||
+ kfree(drv->opp_tables1);
|
||||
+ kfree(drv->hw_opp_tables);
|
||||
+free_opp_names:
|
||||
+ kfree(drv->names_opp_tables);
|
||||
free_drv:
|
||||
kfree(drv);
|
||||
|
||||
@@ -278,13 +414,16 @@ static int qcom_cpufreq_remove(struct pl
|
||||
@@ -278,13 +430,16 @@ static int qcom_cpufreq_remove(struct pl
|
||||
platform_device_unregister(cpufreq_dt_pdev);
|
||||
|
||||
for_each_possible_cpu(cpu) {
|
||||
- if (drv->opp_tables[cpu])
|
||||
- dev_pm_opp_put_supported_hw(drv->opp_tables[cpu]);
|
||||
+ if (drv->opp_tables1[cpu])
|
||||
+ dev_pm_opp_put_supported_hw(drv->opp_tables1[cpu]);
|
||||
+ if (drv->opp_tables2[cpu])
|
||||
+ dev_pm_opp_put_supported_hw(drv->opp_tables2[cpu]);
|
||||
+ if (drv->names_opp_tables[cpu])
|
||||
+ dev_pm_opp_put_supported_hw(drv->names_opp_tables[cpu]);
|
||||
+ if (drv->hw_opp_tables[cpu])
|
||||
+ dev_pm_opp_put_supported_hw(drv->hw_opp_tables[cpu]);
|
||||
if (drv->genpd_opp_tables[cpu])
|
||||
dev_pm_opp_detach_genpd(drv->genpd_opp_tables[cpu]);
|
||||
}
|
||||
|
||||
- kfree(drv->opp_tables);
|
||||
+ kfree(drv->opp_tables1);
|
||||
+ kfree(drv->opp_tables2);
|
||||
+ kfree(drv->names_opp_tables);
|
||||
+ kfree(drv->hw_opp_tables);
|
||||
kfree(drv->genpd_opp_tables);
|
||||
kfree(drv);
|
||||
|
||||
@@ -303,6 +442,10 @@ static const struct of_device_id qcom_cp
|
||||
@@ -303,6 +458,10 @@ static const struct of_device_id qcom_cp
|
||||
{ .compatible = "qcom,apq8096", .data = &match_data_kryo },
|
||||
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
|
||||
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
|
||||
@ -0,0 +1,26 @@
|
||||
From 2dea651680cea1f3a29925de51002f33d1f55711 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Fri, 1 May 2020 00:22:25 +0200
|
||||
Subject: cpufreq: qcom: fix wrong compatible binding
|
||||
|
||||
Binding in Documentation is still "operating-points-v2-kryo-cpu".
|
||||
Restore the old binding to fix the compatibility problem.
|
||||
|
||||
Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
|
||||
---
|
||||
drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
|
||||
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
|
||||
@@ -277,7 +277,7 @@ static int qcom_cpufreq_probe(struct pla
|
||||
if (!np)
|
||||
return -ENOENT;
|
||||
|
||||
- ret = of_device_is_compatible(np, "operating-points-v2-qcom-cpu");
|
||||
+ ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
|
||||
if (!ret) {
|
||||
of_node_put(np);
|
||||
return -ENOENT;
|
||||
@ -1,14 +1,21 @@
|
||||
From 5de1da6c862de6a92ac9aed521f21fd5a180f22b Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Sat, 2 Feb 2019 02:48:35 +0100
|
||||
Subject: [PATCH] net: mdio: add ipq8064 mdio driver
|
||||
From caaa71fac36ec8c19145dbf8262a9b77ab09f1a1 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Wed, 4 Mar 2020 22:38:32 +0100
|
||||
Subject: net: mdio: add ipq8064 mdio driver
|
||||
|
||||
Currently ipq806x soc use generic bitbang driver to
|
||||
comunicate with the gmac ethernet interface.
|
||||
Add a dedicated driver created by chunkeey to fix this.
|
||||
|
||||
Co-developed-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/phy/Kconfig | 8 ++
|
||||
drivers/net/phy/Makefile | 1 +
|
||||
drivers/net/phy/mdio-ipq8064.c | 163 +++++++++++++++++++++++++++++++++
|
||||
3 files changed, 172 insertions(+)
|
||||
drivers/net/phy/mdio-ipq8064.c | 166 +++++++++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 175 insertions(+)
|
||||
create mode 100644 drivers/net/phy/mdio-ipq8064.c
|
||||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
@ -40,12 +47,13 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/phy/mdio-ipq8064.c
|
||||
@@ -0,0 +1,163 @@
|
||||
@@ -0,0 +1,166 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+//
|
||||
+// Qualcomm IPQ8064 MDIO interface driver
|
||||
+//
|
||||
+// Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
|
||||
+/* Qualcomm IPQ8064 MDIO interface driver
|
||||
+ *
|
||||
+ * Copyright (C) 2019 Christian Lamparter <chunkeey@gmail.com>
|
||||
+ * Copyright (C) 2020 Ansuel Smith <ansuelsmth@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/kernel.h>
|
||||
@ -74,8 +82,8 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
+
|
||||
+#define MII_DATA_REG_ADDR 0x14
|
||||
+
|
||||
+#define MII_MDIO_DELAY (1000)
|
||||
+#define MII_MDIO_RETRY (10)
|
||||
+#define MII_MDIO_DELAY_USEC (1000)
|
||||
+#define MII_MDIO_RETRY_MSEC (10)
|
||||
+
|
||||
+struct ipq8064_mdio {
|
||||
+ struct regmap *base; /* NSS_GMAC0_BASE */
|
||||
@ -84,34 +92,30 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
+static int
|
||||
+ipq8064_mdio_wait_busy(struct ipq8064_mdio *priv)
|
||||
+{
|
||||
+ int i;
|
||||
+ u32 busy;
|
||||
+
|
||||
+ for (i = 0; i < MII_MDIO_RETRY; i++) {
|
||||
+ unsigned int busy;
|
||||
+
|
||||
+ regmap_read(priv->base, MII_ADDR_REG_ADDR, &busy);
|
||||
+ if (!(busy & MII_BUSY))
|
||||
+ return 0;
|
||||
+
|
||||
+ udelay(MII_MDIO_DELAY);
|
||||
+ }
|
||||
+
|
||||
+ return -ETIMEDOUT;
|
||||
+ return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy,
|
||||
+ !(busy & MII_BUSY), MII_MDIO_DELAY_USEC,
|
||||
+ MII_MDIO_RETRY_MSEC * USEC_PER_MSEC);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset)
|
||||
+{
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+ u32 miiaddr = MII_BUSY | MII_CLKRANGE_250_300M;
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+ u32 ret_val;
|
||||
+ int err;
|
||||
+
|
||||
+ /* Reject clause 45 */
|
||||
+ if (reg_offset & MII_ADDR_C45)
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
+ miiaddr |= ((phy_addr << MII_ADDR_SHIFT) & MII_ADDR_MASK) |
|
||||
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
|
||||
+
|
||||
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
|
||||
+ udelay(10);
|
||||
+ usleep_range(8, 10);
|
||||
+
|
||||
+ err = ipq8064_mdio_wait_busy(priv);
|
||||
+ if (err)
|
||||
@ -124,8 +128,12 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
+static int
|
||||
+ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data)
|
||||
+{
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+ u32 miiaddr = MII_WRITE | MII_BUSY | MII_CLKRANGE_250_300M;
|
||||
+ struct ipq8064_mdio *priv = bus->priv;
|
||||
+
|
||||
+ /* Reject clause 45 */
|
||||
+ if (reg_offset & MII_ADDR_C45)
|
||||
+ return -EOPNOTSUPP;
|
||||
+
|
||||
+ regmap_write(priv->base, MII_DATA_REG_ADDR, data);
|
||||
+
|
||||
@ -133,7 +141,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
+ ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK);
|
||||
+
|
||||
+ regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr);
|
||||
+ udelay(10);
|
||||
+ usleep_range(8, 10);
|
||||
+
|
||||
+ return ipq8064_mdio_wait_busy(priv);
|
||||
+}
|
||||
@ -157,13 +165,14 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
+ bus->parent = &pdev->dev;
|
||||
+
|
||||
+ priv = bus->priv;
|
||||
+ priv->base = syscon_node_to_regmap(np);
|
||||
+ if (IS_ERR_OR_NULL(priv->base)) {
|
||||
+ priv->base = syscon_regmap_lookup_by_phandle(np, "master");
|
||||
+ if (IS_ERR_OR_NULL(priv->base)) {
|
||||
+ pr_err("master phandle not found\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ priv->base = device_node_to_regmap(np);
|
||||
+ if (IS_ERR(priv->base)) {
|
||||
+ if (priv->base == ERR_PTR(-EPROBE_DEFER))
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
+ dev_err(&pdev->dev, "error getting device regmap, error=%pe\n",
|
||||
+ priv->base);
|
||||
+ return PTR_ERR(priv->base);
|
||||
+ }
|
||||
+
|
||||
+ ret = of_mdiobus_register(bus, np);
|
||||
@ -203,4 +212,5 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
+
|
||||
+MODULE_DESCRIPTION("Qualcomm IPQ8064 MDIO interface driver");
|
||||
+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
|
||||
+MODULE_AUTHOR("Ansuel Smith <ansuelsmth@gmail.com>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -0,0 +1,621 @@
|
||||
From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001
|
||||
From: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Date: Fri, 17 Jul 2020 15:16:31 +0200
|
||||
Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver
|
||||
|
||||
This has lost in the original push for the dwc3 qcom driver.
|
||||
This is needed for ipq806x SoC as without this the usb ports
|
||||
doesn't work at all.
|
||||
|
||||
Signed-off-by: Andy Gross <agross@codeaurora.org>
|
||||
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
||||
Tested-by: Jonathan McDowell <noodles@earth.li>
|
||||
Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
|
||||
Light modification to Kconfig as some config are missing in kernel 5.4
|
||||
|
||||
drivers/phy/qualcomm/Kconfig | 10 +
|
||||
drivers/phy/qualcomm/Makefile | 1 +
|
||||
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++
|
||||
3 files changed, 582 insertions(+)
|
||||
create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
|
||||
--- a/drivers/phy/qualcomm/Kconfig
|
||||
+++ b/drivers/phy/qualcomm/Kconfig
|
||||
@@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
|
||||
+
|
||||
+config PHY_QCOM_IPQ806X_USB
|
||||
+ tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
|
||||
+ depends on HAS_IOMEM
|
||||
+ depends on OF && (ARCH_QCOM || COMPILE_TEST)
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ This option enables support for the Synopsis PHYs present inside the
|
||||
+ Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
|
||||
+ both HS and SS PHY controllers.
|
||||
--- a/drivers/phy/qualcomm/Makefile
|
||||
+++ b/drivers/phy/qualcomm/Makefile
|
||||
@@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-
|
||||
obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o
|
||||
obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o
|
||||
+obj-$(CONFIG_PHY_QCOM_IPQ806X_USB) += phy-qcom-ipq806x-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
@@ -0,0 +1,571 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+
|
||||
+/* USB QSCRATCH Hardware registers */
|
||||
+#define QSCRATCH_GENERAL_CFG (0x08)
|
||||
+#define HSUSB_PHY_CTRL_REG (0x10)
|
||||
+
|
||||
+/* PHY_CTRL_REG */
|
||||
+#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
|
||||
+#define HSUSB_CTRL_USB2_SUSPEND BIT(23)
|
||||
+#define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
|
||||
+#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
|
||||
+#define HSUSB_CTRL_USE_CLKCORE BIT(18)
|
||||
+#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
|
||||
+#define HSUSB_CTRL_COMMONONN BIT(11)
|
||||
+#define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
|
||||
+#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
|
||||
+#define HSUSB_CTRL_CLAMP_EN BIT(7)
|
||||
+#define HSUSB_CTRL_RETENABLEN BIT(1)
|
||||
+#define HSUSB_CTRL_POR BIT(0)
|
||||
+
|
||||
+/* QSCRATCH_GENERAL_CFG */
|
||||
+#define HSUSB_GCFG_XHCI_REV BIT(2)
|
||||
+
|
||||
+/* USB QSCRATCH Hardware registers */
|
||||
+#define SSUSB_PHY_CTRL_REG (0x00)
|
||||
+#define SSUSB_PHY_PARAM_CTRL_1 (0x04)
|
||||
+#define SSUSB_PHY_PARAM_CTRL_2 (0x08)
|
||||
+#define CR_PROTOCOL_DATA_IN_REG (0x0c)
|
||||
+#define CR_PROTOCOL_DATA_OUT_REG (0x10)
|
||||
+#define CR_PROTOCOL_CAP_ADDR_REG (0x14)
|
||||
+#define CR_PROTOCOL_CAP_DATA_REG (0x18)
|
||||
+#define CR_PROTOCOL_READ_REG (0x1c)
|
||||
+#define CR_PROTOCOL_WRITE_REG (0x20)
|
||||
+
|
||||
+/* PHY_CTRL_REG */
|
||||
+#define SSUSB_CTRL_REF_USE_PAD BIT(28)
|
||||
+#define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
|
||||
+#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
|
||||
+#define SSUSB_CTRL_SS_PHY_EN BIT(8)
|
||||
+#define SSUSB_CTRL_SS_PHY_RESET BIT(7)
|
||||
+
|
||||
+/* SSPHY control registers - Does this need 0x30? */
|
||||
+#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
|
||||
+#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
|
||||
+
|
||||
+/* SSPHY SoC version specific values */
|
||||
+#define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
|
||||
+/* Override value for transmit preemphasis */
|
||||
+#define SSPHY_TX_DEEMPH_3_5DB 23
|
||||
+/* Override value for mpll */
|
||||
+#define SSPHY_MPLL_VALUE 0
|
||||
+
|
||||
+/* QSCRATCH PHY_PARAM_CTRL1 fields */
|
||||
+#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)
|
||||
+#define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)
|
||||
+
|
||||
+#define PHY_PARAM_CTRL1_MASK \
|
||||
+ (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS_MASK)
|
||||
+
|
||||
+#define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
|
||||
+ (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
|
||||
+ (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
|
||||
+#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
|
||||
+ (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
|
||||
+#define PHY_PARAM_CTRL1_LOS_BIAS(x) \
|
||||
+ (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
|
||||
+
|
||||
+/* RX OVRD IN HI bits */
|
||||
+#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
|
||||
+#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
|
||||
+#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
|
||||
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
|
||||
+#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)
|
||||
+#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
|
||||
+#define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)
|
||||
+
|
||||
+/* TX OVRD DRV LO register bits */
|
||||
+#define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)
|
||||
+#define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)
|
||||
+#define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7)
|
||||
+#define TX_OVRD_DRV_LO_EN BIT(14)
|
||||
+
|
||||
+/* MPLL bits */
|
||||
+#define SSPHY_MPLL_MASK GENMASK(8, 5)
|
||||
+#define SSPHY_MPLL(x) ((x) << 5)
|
||||
+
|
||||
+/* SS CAP register bits */
|
||||
+#define SS_CR_CAP_ADDR_REG BIT(0)
|
||||
+#define SS_CR_CAP_DATA_REG BIT(0)
|
||||
+#define SS_CR_READ_REG BIT(0)
|
||||
+#define SS_CR_WRITE_REG BIT(0)
|
||||
+
|
||||
+struct usb_phy {
|
||||
+ void __iomem *base;
|
||||
+ struct device *dev;
|
||||
+ struct clk *xo_clk;
|
||||
+ struct clk *ref_clk;
|
||||
+ u32 rx_eq;
|
||||
+ u32 tx_deamp_3_5db;
|
||||
+ u32 mpll;
|
||||
+};
|
||||
+
|
||||
+struct phy_drvdata {
|
||||
+ struct phy_ops ops;
|
||||
+ u32 clk_rate;
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
+ * Write register and read back masked value to confirm it is written
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @offset - register offset.
|
||||
+ * @mask - register bitmask specifying what should be updated
|
||||
+ * @val - value to write.
|
||||
+ */
|
||||
+static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
|
||||
+ u32 offset,
|
||||
+ const u32 mask, u32 val)
|
||||
+{
|
||||
+ u32 write_val, tmp = readl(phy_dwc3->base + offset);
|
||||
+
|
||||
+ tmp &= ~mask; /* retain other bits */
|
||||
+ write_val = tmp | val;
|
||||
+
|
||||
+ writel(write_val, phy_dwc3->base + offset);
|
||||
+
|
||||
+ /* Read back to see if val was written */
|
||||
+ tmp = readl(phy_dwc3->base + offset);
|
||||
+ tmp &= mask; /* clear other bits */
|
||||
+
|
||||
+ if (tmp != val)
|
||||
+ dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
|
||||
+}
|
||||
+
|
||||
+static int wait_for_latch(void __iomem *addr)
|
||||
+{
|
||||
+ u32 retry = 10;
|
||||
+
|
||||
+ while (true) {
|
||||
+ if (!readl(addr))
|
||||
+ break;
|
||||
+
|
||||
+ if (--retry == 0)
|
||||
+ return -ETIMEDOUT;
|
||||
+
|
||||
+ usleep_range(10, 20);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * Write SSPHY register
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @addr - SSPHY address to write.
|
||||
+ * @val - value to write.
|
||||
+ */
|
||||
+static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
|
||||
+ u32 addr, u32 val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
|
||||
+ writel(SS_CR_CAP_ADDR_REG,
|
||||
+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
|
||||
+ writel(SS_CR_CAP_DATA_REG,
|
||||
+ phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
|
||||
+
|
||||
+err_wait:
|
||||
+ if (ret)
|
||||
+ dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
+ * Read SSPHY register.
|
||||
+ *
|
||||
+ * @base - QCOM DWC3 PHY base virtual address.
|
||||
+ * @addr - SSPHY address to read.
|
||||
+ */
|
||||
+static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
|
||||
+ u32 addr, u32 *val)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
|
||||
+ writel(SS_CR_CAP_ADDR_REG,
|
||||
+ phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ /*
|
||||
+ * Due to hardware bug, first read of SSPHY register might be
|
||||
+ * incorrect. Hence as workaround, SW should perform SSPHY register
|
||||
+ * read twice, but use only second read and ignore first read.
|
||||
+ */
|
||||
+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ /* throwaway read */
|
||||
+ readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
|
||||
+
|
||||
+ writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+
|
||||
+ ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
|
||||
+ if (ret)
|
||||
+ goto err_wait;
|
||||
+
|
||||
+ *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
|
||||
+
|
||||
+err_wait:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 val;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
|
||||
+ * enable clamping, and disable RETENTION (power-on default is ENABLED)
|
||||
+ */
|
||||
+ val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
|
||||
+ HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
|
||||
+ HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
|
||||
+ HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
|
||||
+ HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
|
||||
+
|
||||
+ /* use core clock if external reference is not present */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ val |= HSUSB_CTRL_USE_CLKCORE;
|
||||
+
|
||||
+ writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
|
||||
+ usleep_range(2000, 2200);
|
||||
+
|
||||
+ /* Disable (bypass) VBUS and ID filters */
|
||||
+ writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+ u32 data;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->xo_clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(phy_dwc3->ref_clk);
|
||||
+ if (ret) {
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* reset phy */
|
||||
+ data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+ writel(data | SSUSB_CTRL_SS_PHY_RESET,
|
||||
+ phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+ usleep_range(2000, 2200);
|
||||
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+
|
||||
+ /* clear REF_PAD if we don't have XO clk */
|
||||
+ if (!phy_dwc3->xo_clk)
|
||||
+ data &= ~SSUSB_CTRL_REF_USE_PAD;
|
||||
+ else
|
||||
+ data |= SSUSB_CTRL_REF_USE_PAD;
|
||||
+
|
||||
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+
|
||||
+ /* wait for ref clk to become stable, this can take up to 30ms */
|
||||
+ msleep(30);
|
||||
+
|
||||
+ data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
|
||||
+ writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
|
||||
+
|
||||
+ /*
|
||||
+ * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
|
||||
+ * in HS mode instead of SS mode. Workaround it by asserting
|
||||
+ * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
|
||||
+ */
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data |= (1 << 7);
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~0xff0;
|
||||
+ data |= 0x20;
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Fix RX Equalization setting as follows
|
||||
+ * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
|
||||
+ * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
|
||||
+ */
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
|
||||
+ data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
|
||||
+ data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ /*
|
||||
+ * Set EQ and TX launch amplitudes as follows
|
||||
+ * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
|
||||
+ * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
|
||||
+ * LANE0.TX_OVRD_DRV_LO.EN set to 1.
|
||||
+ */
|
||||
+ ret = usb_ss_read_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
|
||||
+ data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
|
||||
+ data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
|
||||
+ data |= 0x6E;
|
||||
+ data |= TX_OVRD_DRV_LO_EN;
|
||||
+ ret = usb_ss_write_phycreg(phy_dwc3,
|
||||
+ SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
|
||||
+ if (ret)
|
||||
+ goto err_phy_trans;
|
||||
+
|
||||
+ data = 0;
|
||||
+ data &= ~SSPHY_MPLL_MASK;
|
||||
+ data |= SSPHY_MPLL(phy_dwc3->mpll);
|
||||
+ usb_ss_write_phycreg(phy_dwc3, 0x30, data);
|
||||
+
|
||||
+ /*
|
||||
+ * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
|
||||
+ * TX_FULL_SWING [26:20] amplitude to 110
|
||||
+ * TX_DEEMPH_6DB [19:14] to 32
|
||||
+ * TX_DEEMPH_3_5DB [13:8] set based on SoC version
|
||||
+ * LOS_BIAS [7:3] to 9
|
||||
+ */
|
||||
+ data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
|
||||
+
|
||||
+ data &= ~PHY_PARAM_CTRL1_MASK;
|
||||
+
|
||||
+ data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
|
||||
+ PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
|
||||
+ PHY_PARAM_CTRL1_LOS_BIAS(0x9);
|
||||
+
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
|
||||
+ PHY_PARAM_CTRL1_MASK, data);
|
||||
+
|
||||
+err_phy_trans:
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Sequence to put SSPHY in low power state:
|
||||
+ * 1. Clear REF_PHY_EN in PHY_CTRL_REG
|
||||
+ * 2. Clear REF_USE_PAD in PHY_CTRL_REG
|
||||
+ * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
|
||||
+ */
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_SS_PHY_EN, 0x0);
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_REF_USE_PAD, 0x0);
|
||||
+ usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
|
||||
+ SSUSB_CTRL_TEST_POWERDOWN, 0x0);
|
||||
+
|
||||
+ clk_disable_unprepare(phy_dwc3->ref_clk);
|
||||
+ clk_disable_unprepare(phy_dwc3->xo_clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_ipq806x_usb_hs_phy_init,
|
||||
+ .exit = qcom_ipq806x_usb_hs_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 60000000,
|
||||
+};
|
||||
+
|
||||
+static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
|
||||
+ .ops = {
|
||||
+ .init = qcom_ipq806x_usb_ss_phy_init,
|
||||
+ .exit = qcom_ipq806x_usb_ss_phy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+ },
|
||||
+ .clk_rate = 125000000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
|
||||
+ { .compatible = "qcom,ipq806x-usb-phy-hs",
|
||||
+ .data = &qcom_ipq806x_usb_hs_drvdata },
|
||||
+ { .compatible = "qcom,ipq806x-usb-phy-ss",
|
||||
+ .data = &qcom_ipq806x_usb_ss_drvdata },
|
||||
+ { /* Sentinel */ }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
|
||||
+
|
||||
+static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ resource_size_t size;
|
||||
+ struct phy *generic_phy;
|
||||
+ struct usb_phy *phy_dwc3;
|
||||
+ const struct phy_drvdata *data;
|
||||
+ struct phy_provider *phy_provider;
|
||||
+
|
||||
+ phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
|
||||
+ if (!phy_dwc3)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ data = of_device_get_match_data(&pdev->dev);
|
||||
+
|
||||
+ phy_dwc3->dev = &pdev->dev;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!res)
|
||||
+ return -EINVAL;
|
||||
+ size = resource_size(res);
|
||||
+ phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
|
||||
+
|
||||
+ if (IS_ERR(phy_dwc3->base)) {
|
||||
+ dev_err(phy_dwc3->dev, "failed to map reg\n");
|
||||
+ return PTR_ERR(phy_dwc3->base);
|
||||
+ }
|
||||
+
|
||||
+ phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
|
||||
+ if (IS_ERR(phy_dwc3->ref_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
|
||||
+ return PTR_ERR(phy_dwc3->ref_clk);
|
||||
+ }
|
||||
+
|
||||
+ clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
|
||||
+
|
||||
+ phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
|
||||
+ if (IS_ERR(phy_dwc3->xo_clk)) {
|
||||
+ dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
|
||||
+ phy_dwc3->xo_clk = NULL;
|
||||
+ }
|
||||
+
|
||||
+ /* Parse device node to probe HSIO settings */
|
||||
+ if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
|
||||
+ &phy_dwc3->rx_eq))
|
||||
+ phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
|
||||
+
|
||||
+ if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
|
||||
+ &phy_dwc3->tx_deamp_3_5db))
|
||||
+ phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
|
||||
+
|
||||
+ if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
|
||||
+ phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
||||
+
|
||||
+ generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
|
||||
+
|
||||
+ if (IS_ERR(generic_phy))
|
||||
+ return PTR_ERR(generic_phy);
|
||||
+
|
||||
+ phy_set_drvdata(generic_phy, phy_dwc3);
|
||||
+ platform_set_drvdata(pdev, phy_dwc3);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
|
||||
+ of_phy_simple_xlate);
|
||||
+
|
||||
+ if (IS_ERR(phy_provider))
|
||||
+ return PTR_ERR(phy_provider);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver qcom_ipq806x_usb_phy_driver = {
|
||||
+ .probe = qcom_ipq806x_usb_phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "qcom-ipq806x-usb-phy",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = qcom_ipq806x_usb_phy_table,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+module_platform_driver(qcom_ipq806x_usb_phy_driver);
|
||||
+
|
||||
+MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
|
||||
+MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
|
||||
+MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
|
||||
@ -0,0 +1,31 @@
|
||||
From 3d7b0ca5300bd01b176f2b4c10e173db802560d8 Mon Sep 17 00:00:00 2001
|
||||
From: Colin Ian King <colin.king@canonical.com>
|
||||
Date: Tue, 21 Jul 2020 16:06:13 +0100
|
||||
Subject: phy: qualcomm: fix setting of tx_deamp_3_5db when device property
|
||||
read fails
|
||||
|
||||
Currently when reading of the device property for "qcom,tx-deamp_3_5db"
|
||||
fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This
|
||||
looks like a copy-n-paste error and in fact should be assigning the
|
||||
default instead to phy_dwc3->tx_deamp_3_5db
|
||||
|
||||
Addresses-Coverity: ("Copy-paste error")
|
||||
Fixes: ef19b117b834 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver")
|
||||
Signed-off-by: Colin Ian King <colin.king@canonical.com>
|
||||
Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
|
||||
@@ -531,7 +531,7 @@ static int qcom_ipq806x_usb_phy_probe(st
|
||||
|
||||
if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
|
||||
&phy_dwc3->tx_deamp_3_5db))
|
||||
- phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
|
||||
+ phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
|
||||
|
||||
if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
|
||||
phy_dwc3->mpll = SSPHY_MPLL_VALUE;
|
||||
Loading…
Reference in New Issue
Block a user