From 4186aca221a75c28c13f4f2fe9fc3291307072c7 Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Fri, 8 Jun 2018 15:40:11 +0800 Subject: [PATCH] update kernel version to 4.9.106 and 4.14.48 --- include/kernel-version.mk | 8 +- ...mware-loader-for-uPD720201-and-uPD72.patch | 6 +- .../802-usb-xhci-force-msi-renesas-xhci.patch | 2 +- ...-ath79-add-lots-of-missing-registers.patch | 10 +- .../910-unaligned_access_hacks.patch | 4 +- ...support-for-performing-fake-doorbell.patch | 2 +- .../011-kbuild-export-SUBARCH.patch | 2 +- ...prevent-redefinition-of-struct-ethhd.patch | 2 +- ...tfilter-exit_net-cleanup-check-added.patch | 2 +- .../hack-4.14/202-reduce_module_size.patch | 2 +- .../hack-4.14/207-disable-modorder.patch | 4 +- .../generic/hack-4.14/220-gc_sections.patch | 2 +- .../hack-4.14/773-bgmac-add-srab-switch.patch | 6 +- .../generic/hack-4.14/902-debloat_proc.patch | 2 +- ...-gic-timer-fix-clocksource-counter-w.patch | 23 - ...orruption-related-to-cache-coherence.patch | 90 - ...ame2-and-add-RENAME_WHITEOUT-support.patch | 6 +- ...41-jffs2-add-RENAME_EXCHANGE-support.patch | 8 +- ..._wwan-add-BroadMobi-BM806U-2020-2033.patch | 28 - .../pending-4.14/201-extra_optimization.patch | 2 +- ...Add-support-for-MAP-E-FMRs-mesh-mode.patch | 10 +- .../811-pci_disable_usb_common_quirks.patch | 21 +- .../pending-4.14/834-ledtrig-libata.patch | 8 +- .../pending-4.9/890-uart_optional_sysrq.patch | 2 +- ...am-Process-multiple-pending-descript.patch | 22 +- target/linux/lantiq/Makefile | 2 +- target/linux/lantiq/ase/config-4.9 | 24 - .../lantiq/base-files/etc/board.d/01_leds | 4 + .../lantiq/base-files/etc/board.d/02_network | 9 +- .../etc/hotplug.d/firmware/12-ath9k-eeprom | 24 +- .../lantiq/base-files/lib/upgrade/platform.sh | 8 +- target/linux/lantiq/config-4.14 | 7 - target/linux/lantiq/config-4.9 | 199 - target/linux/lantiq/falcon/config-4.9 | 10 - .../files-4.14/arch/mips/boot/dts/ACMP252.dts | 2 +- .../arch/mips/boot/dts/ARV4518PWR01.dtsi | 2 +- .../arch/mips/boot/dts/ARV4519PW.dts | 2 +- .../arch/mips/boot/dts/ARV4520PW.dts | 2 +- .../arch/mips/boot/dts/ARV452CQW.dts | 2 +- .../arch/mips/boot/dts/ARV7510PW22.dts | 2 +- .../arch/mips/boot/dts/ARV7518PW.dts | 2 +- .../arch/mips/boot/dts/ARV7519RW22.dts | 4 +- .../arch/mips/boot/dts/ARV752DPW.dts | 2 +- .../arch/mips/boot/dts/ARV752DPW22.dts | 2 +- .../arch/mips/boot/dts/ARV8539PW22.dts | 2 +- .../arch/mips/boot/dts/BTHOMEHUBV3A.dts | 2 +- .../arch/mips/boot/dts/BTHOMEHUBV5A.dts | 2 +- .../arch/mips/boot/dts/EASY80920.dtsi | 2 +- .../mips/boot/dts/FRITZ3370-REV2-HYNIX.dts | 55 + .../mips/boot/dts/FRITZ3370-REV2-MICRON.dts | 53 + .../{FRITZ3370.dts => FRITZ3370-REV2.dtsi} | 129 +- .../arch/mips/boot/dts/GIGASX76X.dts | 2 +- .../files-4.14/arch/mips/boot/dts/H201L.dts | 2 +- .../arch/mips/boot/dts/P2601HNFX.dts | 2 +- .../arch/mips/boot/dts/P2812HNUFX.dtsi | 4 +- .../arch/mips/boot/dts/TDW89X0.dtsi | 4 +- .../arch/mips/boot/dts/VGV7510KW22.dtsi | 2 +- .../arch/mips/boot/dts/VGV7519.dtsi | 4 +- .../files-4.14/arch/mips/boot/dts/VR200v.dts | 4 +- .../files-4.14/arch/mips/boot/dts/WBMR.dts | 2 +- .../files-4.14/arch/mips/boot/dts/WBMR300.dts | 4 +- .../files-4.9/arch/mips/boot/dts/ACMP252.dts | 102 - .../arch/mips/boot/dts/ALL0333CJ.dts | 120 - .../arch/mips/boot/dts/ARV4510PW.dts | 232 - .../arch/mips/boot/dts/ARV4518PWR01.dts | 8 - .../arch/mips/boot/dts/ARV4518PWR01.dtsi | 198 - .../arch/mips/boot/dts/ARV4518PWR01A.dts | 14 - .../arch/mips/boot/dts/ARV4519PW.dts | 195 - .../arch/mips/boot/dts/ARV4520PW.dts | 221 - .../arch/mips/boot/dts/ARV4525PW.dts | 169 - .../arch/mips/boot/dts/ARV452CQW.dts | 237 - .../arch/mips/boot/dts/ARV7506PW11.dts | 165 - .../arch/mips/boot/dts/ARV7510PW22.dts | 196 - .../arch/mips/boot/dts/ARV7518PW.dts | 232 - .../arch/mips/boot/dts/ARV7519PW.dts | 229 - .../arch/mips/boot/dts/ARV7519RW22.dts | 231 - .../arch/mips/boot/dts/ARV7525PW.dts | 155 - .../arch/mips/boot/dts/ARV752DPW.dts | 238 - .../arch/mips/boot/dts/ARV752DPW22.dts | 259 - .../arch/mips/boot/dts/ARV8539PW22.dts | 180 - .../files-4.9/arch/mips/boot/dts/ASL56026.dts | 171 - .../arch/mips/boot/dts/BTHOMEHUBV2B.dts | 262 - .../arch/mips/boot/dts/BTHOMEHUBV3A.dts | 208 - .../arch/mips/boot/dts/BTHOMEHUBV5A.dts | 282 - .../files-4.9/arch/mips/boot/dts/DGN1000B.dts | 171 - .../files-4.9/arch/mips/boot/dts/DGN3500.dts | 8 - .../files-4.9/arch/mips/boot/dts/DGN3500.dtsi | 213 - .../files-4.9/arch/mips/boot/dts/DGN3500B.dts | 8 - .../files-4.9/arch/mips/boot/dts/DM200.dts | 215 - .../arch/mips/boot/dts/EASY50712.dts | 83 - .../arch/mips/boot/dts/EASY50810.dts | 93 - .../arch/mips/boot/dts/EASY80920.dtsi | 298 - .../arch/mips/boot/dts/EASY80920NAND.dts | 68 - .../arch/mips/boot/dts/EASY80920NOR.dts | 43 - .../arch/mips/boot/dts/EASY88388.dts | 106 - .../arch/mips/boot/dts/EASY88444.dts | 80 - .../arch/mips/boot/dts/EASY98000-base.dtsi | 110 - .../arch/mips/boot/dts/EASY98000NAND.dts | 40 - .../arch/mips/boot/dts/EASY98000NOR.dts | 38 - .../arch/mips/boot/dts/EASY98000SFLASH.dts | 16 - .../arch/mips/boot/dts/EASY98020.dts | 95 - .../arch/mips/boot/dts/EASY98020V18.dts | 68 - .../arch/mips/boot/dts/EASY98021.dts | 81 - .../arch/mips/boot/dts/EASY98035SYNCE.dts | 76 - .../arch/mips/boot/dts/EASY98035SYNCE1588.dts | 76 - .../arch/mips/boot/dts/FALCON-MDU.dts | 53 - .../arch/mips/boot/dts/FALCON-SFP.dts | 76 - .../arch/mips/boot/dts/FRITZ3370.dts | 288 - .../arch/mips/boot/dts/FRITZ7320.dts | 161 - .../arch/mips/boot/dts/FRITZ7360SL.dts | 228 - .../arch/mips/boot/dts/GIGASX76X.dts | 122 - .../files-4.9/arch/mips/boot/dts/H201L.dts | 159 - .../arch/mips/boot/dts/P2601HNFX.dts | 190 - .../arch/mips/boot/dts/P2812HNUF1.dts | 72 - .../arch/mips/boot/dts/P2812HNUF3.dts | 66 - .../arch/mips/boot/dts/P2812HNUFX.dtsi | 280 - .../files-4.9/arch/mips/boot/dts/TDW8970.dts | 8 - .../files-4.9/arch/mips/boot/dts/TDW8980.dts | 35 - .../files-4.9/arch/mips/boot/dts/TDW89X0.dtsi | 274 - .../files-4.9/arch/mips/boot/dts/VG3503J.dts | 163 - .../arch/mips/boot/dts/VGV7510KW22.dtsi | 253 - .../arch/mips/boot/dts/VGV7510KW22BRN.dts | 67 - .../arch/mips/boot/dts/VGV7510KW22NOR.dts | 33 - .../files-4.9/arch/mips/boot/dts/VGV7519.dtsi | 298 - .../arch/mips/boot/dts/VGV7519BRN.dts | 73 - .../arch/mips/boot/dts/VGV7519NOR.dts | 32 - .../files-4.9/arch/mips/boot/dts/VR200v.dts | 283 - .../files-4.9/arch/mips/boot/dts/WBMR.dts | 185 - .../files-4.9/arch/mips/boot/dts/WBMR300.dts | 306 - .../arch/mips/boot/dts/amazonse.dtsi | 174 - .../files-4.9/arch/mips/boot/dts/ar9.dtsi | 216 - .../files-4.9/arch/mips/boot/dts/danube.dtsi | 212 - .../arch/mips/boot/dts/falcon-sflash-16M.dtsi | 37 - .../files-4.9/arch/mips/boot/dts/falcon.dtsi | 392 -- .../files-4.9/arch/mips/boot/dts/vr9.dtsi | 260 - target/linux/lantiq/image/Makefile | 26 +- ...antiq-autoselect-soc-rev-matching-fw.patch | 4 +- .../0001-MIPS-lantiq-add-pcie-driver.patch | 5520 ----------------- .../0004-MIPS-lantiq-add-atm-hack.patch | 500 -- ...-MIPS-lantiq-backport-old-timer-code.patch | 1034 --- .../0018-MTD-nand-lots-of-xrx200-fixes.patch | 122 - ...antiq-handle-NO_XIP-on-cfi0001-flash.patch | 25 - ...25p80-allow-loading-mtd-name-from-OF.patch | 44 - ...ET-PHY-adds-driver-for-lantiq-PHY11G.patch | 294 - ...ET-lantiq-adds-PHY11G-firmware-blobs.patch | 364 -- ...0025-NET-MIPS-lantiq-adds-xrx200-net.patch | 3394 ---------- .../0026-NET-multi-phy-support.patch | 53 - ...hy-intel-xway-add-VR9-version-number.patch | 62 - ...-phy-intel-xway-add-VR9-v1.1-phy-ids.patch | 71 - .../0028-NET-lantiq-various-etop-fixes.patch | 880 --- .../0030-GPIO-add-named-gpio-exports.patch | 170 - ...PS-lantiq-add-FALC-ON-i2c-bus-master.patch | 1034 --- ...iq-wifi-and-ethernet-eeprom-handling.patch | 219 - .../0040-USB-DWC2-enable-usb-power-gpio.patch | 35 - ...42-arch-mips-increase-io_space_limit.patch | 23 - ...-fix-copy-paste-error-in-xrx200_grps.patch | 11 - .../lantiq/patches-4.9/0047-poweroff.patch | 23 - ...0-MIPS-Lantiq-Fix-cascaded-IRQ-setup.patch | 87 - ...e-lantiq-settings-match-vendor-drive.patch | 130 - ...PS-lantiq-improve-USB-initialization.patch | 202 - ...dd-support-for-Lantiq-SSC-SPI-contro.patch | 1078 ---- ...ix-platform_no_drv_owner.cocci-warni.patch | 28 - ...antiq-ssc-add-LTQ_-prefix-to-defines.patch | 723 --- .../patches-4.9/0101-find_active_root.patch | 93 - .../0151-lantiq-ifxmips_pcie-use-of.patch | 166 - .../lantiq/patches-4.9/0152-lantiq-VPE.patch | 180 - .../0154-lantiq-pci-bar11mask-fix.patch | 22 - .../patches-4.9/0155-lantiq-VPE-nosmp.patch | 14 - .../0160-owrt-lantiq-multiple-flash.patch | 221 - ...q-lock-DMA-register-accesses-for-SMP.patch | 152 - ...-cmdset-0001-disable-buffered-writes.patch | 11 - ...add-gphy-clk-src-device-tree-binding.patch | 30 - .../0302-xrx200-add-sensors-driver.patch | 184 - target/linux/lantiq/xrx200/config-4.9 | 90 - target/linux/lantiq/xway/config-4.9 | 48 - target/linux/lantiq/xway_legacy/config-4.9 | 37 - target/linux/mediatek/32/target.mk | 13 - target/linux/mediatek/Makefile | 4 +- target/linux/mediatek/base-files/etc/inittab | 2 +- .../base-files/lib/upgrade/platform.sh | 64 +- target/linux/mediatek/image/32.mk | 32 - target/linux/mediatek/image/Makefile | 50 +- target/linux/mediatek/image/mt7622.mk | 9 + target/linux/mediatek/image/mt7623.mk | 6 + target/linux/mediatek/modules.mk | 51 + target/linux/mediatek/mt7622/config-4.14 | 461 ++ .../{32 => mt7622}/profiles/default.mk | 0 target/linux/mediatek/mt7622/target.mk | 11 + .../linux/mediatek/{ => mt7623}/config-4.14 | 21 +- .../linux/mediatek/mt7623/profiles/default.mk | 15 + target/linux/mediatek/mt7623/target.mk | 16 + ...a-mediatek-turn-into-platform-driver.patch | 4 +- ...dd-reset-controller-dt-bindings-requ.patch | 114 + ...rap-fixup-warnings-from-coding-style.patch | 71 + ...support-option-to-disable-usb3-ports.patch | 108 + ...-remove-dummy-wakeup-debounce-clocks.patch | 119 + ...-add-optional-mcu-and-dma-bus-clocks.patch | 227 + ...-usb-mtu3-support-36-bit-DMA-address.patch | 362 ++ ...CE-RG_IDDIG-to-implement-manual-DRD-.patch | 274 + ...9-usb-mtu3-add-support-for-usb3.1-IP.patch | 152 + ...get-optional-vbus-for-host-only-mode.patch | 40 + ...et-invalid-dr_mode-as-dual-role-mode.patch | 29 + ..._sel-for-u2port-only-if-works-as-dua.patch | 44 + ...mtu3-add-a-optional-property-to-disa.patch | 25 + ...mtu3-remove-dummy-clocks-and-add-opt.patch | 41 + ...gs-usb-mtu3-remove-optional-pinctrls.patch | 30 + ...mediatek-add-MT7622-string-to-the-PM.patch | 38 + ...ap-add-pwrap_read32-for-reading-in-3.patch | 134 + ...ap-add-pwrap_write32-for-writing-in-.patch | 132 + ...ap-refactor-pwrap_init-for-the-vario.patch | 227 + ...ap-add-MediaTek-MT6380-as-one-slave-.patch | 98 + ...ap-add-common-way-for-setup-CS-timin.patch | 121 + ...tek-pwrap-add-support-for-MT7622-SoC.patch | 237 + ...ce-Kconfig-for-all-SoC-drivers-under.patch | 57 + ...leanup-message-for-platform-selectio.patch | 34 + ...y-phy-mtk-tphy-add-set_mode-callback.patch | 86 + ...-dma_set_mask_and_coherent-in-probe-.patch | 35 + ...-ports-count-from-xhci-in-xhci_mtk_s.patch | 53 + ...-mtk-check-clock-stability-of-U3_MAC.patch | 36 + ...support-option-to-disable-usb3-ports.patch | 85 + ...-remove-dummy-wakeup-debounce-clocks.patch | 86 + ...-add-optional-mcu-and-dma-bus-clocks.patch | 139 + ...dify-description-for-MTK-xHCI-config.patch | 32 + ...mtk-xhci-add-a-optional-property-to-.patch | 25 + ...mtk-xhci-remove-dummy-clocks-and-add.patch | 58 + ...add-new-compatible-strings-and-impro.patch | 42 + ...d-mtk-nor-add-suspend-resume-support.patch | 128 + ...mediatek-add-bindings-for-MediaTek-S.patch | 41 + ...tek-add-driver-for-RTC-on-MT7622-SoC.patch | 471 ++ ...ance-the-description-for-MediaTek-PM.patch | 39 + ...nge-the-compile-sequence-of-mtk_nand.patch | 31 + ...Add-reg-source_cg-latch-ck-for-Media.patch | 60 + ...ediatek-add-support-of-mt2701-mt2712.patch | 187 + ...Mediatek-Document-bindings-for-MT271.patch | 196 + ...ek-Add-dt-bindings-for-MT2712-clocks.patch | 446 ++ ...lk-mediatek-Add-MT2712-clock-support.patch | 2296 +++++++ ...k-mediatek-document-clk-bindings-for.patch | 190 + ...-clocks-dt-bindings-required-header-.patch | 310 + ...tek-add-clock-support-for-MT7622-SoC.patch | 1388 +++++ ...-remove-mediatek-mt8135-mmc-from-mmc.patch | 61 + ...e-hs400_tune_response-only-for-mt817.patch | 70 + ...3-mmc-mediatek-add-pad_tune0-support.patch | 256 + ...add-async-fifo-and-data-tune-support.patch | 170 + ...-mmc-mediatek-add-busy_check-support.patch | 67 + ...-stop_clk-fix-and-enhance_rx-support.patch | 168 + ...iatek-add-support-of-source_cg-clock.patch | 85 + ...58-mmc-mediatek-add-latch-ck-support.patch | 45 + ...rove-eMMC-hs400-mode-read-performanc.patch | 68 + ...fer-to-use-rise-edge-latching-for-cm.patch | 28 + ...m-mediatek-Add-MT2712-MT7622-support.patch | 145 + ...-nand_reset-to-reset-NAND-devices-in.patch | 41 + ...atek-add-mt2712-into-compatible-list.patch | 24 + ...0165-mtd-nand-mtk-update-DT-bindings.patch | 41 + ...port-different-MTK-NAND-flash-contro.patch | 380 ++ ...Support-MT7622-NAND-flash-controller.patch | 109 + ...ndings-add-mmc-support-to-MT7623-SoC.patch | 26 + ...trl-add-bindings-for-MediaTek-MT7622.patch | 371 ++ ...-cleanup-for-placing-all-drivers-und.patch | 32 + ...ek-add-pinctrl-driver-for-MT7622-SoC.patch | 1675 +++++ ...-group-drivers-under-indpendent-menu.patch | 223 + ...up-test-building-of-MediaTek-clock-d.patch | 27 + ...mediatek-add-condition-to-property-m.patch | 27 + ...ove-superfluous-pin-setup-for-MT7622.patch | 102 + ...-all-warnings-for-missing-struct-clk.patch | 68 + ...-use-auto-instead-of-force-to-bypass.patch | 75 + ...-make-shared-banks-optional-for-V1-T.patch | 30 + ...tk-tphy-use-of_device_get_match_data.patch | 51 + ...x-error-handling-in-mt2701_afe_pcm_d.patch | 81 + ...ek-rework-clock-functions-for-MT2701.patch | 919 +++ ...atek-cleanup-audio-driver-for-MT2701.patch | 428 ++ ...date-clock-related-properties-of-MT2.patch | 258 + ...-add-some-core-clocks-for-MT2701-AFE.patch | 93 + ...dify-MT2701-AFE-driver-to-adapt-mfd-.patch | 128 + ...date-MT2701-AFE-documentation-to-ada.patch | 214 + ...error-code-for-getting-extcon-device.patch | 26 + ...s-remote-wakeup-for-mt2712-with-two-.patch | 233 + ...sb-mtu3-update-USB-wakeup-properties.patch | 47 + ...ports-remote-wakeup-for-mt2712-with-.patch | 265 + ...low-imod-interval-to-be-configurable.patch | 138 + ...mtk-xhci-update-USB-wakeup-propertie.patch | 49 + ...ust-dependency-of-reset.c-to-avoid-u.patch | 71 + ...-mt7622-fix-potential-uninitialized-.patch | 49 + ...-mt7622-align-error-handling-of-mtk_.patch | 50 + ...modify-functions-name-more-generally.patch | 554 ++ ...g-mediatek-Setup-default-RNG-quality.patch | 25 + ...s-thermal-add-binding-for-MT7622-SoC.patch | 26 + ...9-thermal-mtk-Cleanup-unused-defines.patch | 51 + ...-mediatek-add-support-for-MT7622-SoC.patch | 81 + ...k-mediatek-add-missing-required-rese.patch | 64 + ...-bindings-add-support-for-MT7622-SoC.patch | 22 + ...-mediatek-add-support-for-MT7622-SoC.patch | 42 + ...ngine-Add-MediaTek-High-Speed-DMA-co.patch | 51 + ...ek-Add-MediaTek-High-Speed-DMA-contr.patch | 1128 ++++ ...k-mediatek-update-audsys-documentati.patch | 45 + ...k-mediatek-add-audsys-support-for-MT.patch | 23 + ...ate-missing-clock-data-for-MT7622-au.patch | 38 + ...-devm_of_platform_populate-for-MT762.patch | 42 + ...22-add-clock-controller-device-nodes.patch | 130 + ...-add-power-domain-controller-device-.patch | 45 + ...622-add-pinctrl-related-device-nodes.patch | 252 + ...mt7622-add-PMIC-MT6380-related-nodes.patch | 155 + ...622-add-cpufreq-related-device-nodes.patch | 112 + ...mt7622-turn-uart0-clock-to-real-ones.patch | 45 + ...-add-SoC-and-peripheral-related-devi.patch | 420 ++ ...t7622-add-flash-related-device-nodes.patch | 96 + ...dts-mt7622-add-ethernet-device-nodes.patch | 84 + ...m64-dts-mt7622-add-PCIe-device-nodes.patch | 116 + ...m64-dts-mt7622-add-SATA-device-nodes.patch | 87 + ...rm64-dts-mt7622-add-usb-device-nodes.patch | 119 + ...7622-add-High-Speed-DMA-device-nodes.patch | 31 + ...-mt7622-add-mmc-related-device-nodes.patch | 200 + ...config-for-testing-these-new-drivers.patch | 288 + .../mvebu/base-files/etc/board.d/02_network | 9 + target/linux/mvebu/base-files/lib/mvebu.sh | 9 + target/linux/mvebu/config-4.14 | 8 +- .../arm/boot/dts/armada-385-linksys-venom.dts | 6 + .../mvebu/image/armada-3720-db.bootscript | 10 + target/linux/mvebu/image/cortex-a53.mk | 13 + target/linux/mvebu/image/cortex-a72.mk | 26 + ...Mangle-bootloader-s-kernel-arguments.patch | 201 + .../300-mvneta-tx-queue-workaround.patch | 4 +- .../403-net-mvneta-convert-to-phylink.patch | 52 +- ...04-net-mvneta-hack-fix-phy_interface.patch | 2 +- ...le-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch | 8 +- ...ta-add-module-EEPROM-reading-support.patch | 4 +- ...eeprom-ethtool-access-into-netdev-co.patch | 4 +- target/linux/oxnas/Makefile | 20 +- .../linux/oxnas/{config-4.4 => config-4.14} | 341 +- ...20-akitio.dts => ox820-akitio-mycloud.dts} | 126 +- .../dts/ox820-cloudengines-pogoplug-pro.dts | 98 + ...-stg212.dts => ox820-mitrastar-stg212.dts} | 70 +- .../arch/arm/boot/dts/ox820-pogoplug-pro.dts | 94 - .../arch/arm/boot/dts/ox820-pogoplug-v3.dts | 91 - ...{ox820-kd20.dts => ox820-shuttle-kd20.dts} | 102 +- .../oxnas/files/arch/arm/boot/dts/ox820.dtsi | 342 - .../files/arch/arm/configs/ox820_defconfig | 104 - .../debug/uncompress-ox820.h} | 0 .../oxnas/files/arch/arm/mach-oxnas/Kconfig | 25 - .../oxnas/files/arch/arm/mach-oxnas/Makefile | 8 - .../files/arch/arm/mach-oxnas/Makefile.boot | 2 - .../oxnas/files/arch/arm/mach-oxnas/fiq.S | 87 - .../oxnas/files/arch/arm/mach-oxnas/headsmp.S | 27 - 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target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch create mode 100644 target/linux/mediatek/patches-4.14/0219-arm64-dts-mt7622-add-PCIe-device-nodes.patch create mode 100644 target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch create mode 100644 target/linux/mediatek/patches-4.14/0221-arm64-dts-mt7622-add-usb-device-nodes.patch create mode 100644 target/linux/mediatek/patches-4.14/0222-arm64-dts-mt7622-add-High-Speed-DMA-device-nodes.patch create mode 100644 target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch create mode 100644 target/linux/mediatek/patches-4.14/0224-add-mt7622-defconfig-for-testing-these-new-drivers.patch create mode 100644 target/linux/mvebu/image/armada-3720-db.bootscript create mode 100644 target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch rename target/linux/oxnas/{config-4.4 => config-4.14} (51%) rename target/linux/oxnas/files/arch/arm/boot/dts/{ox820-akitio.dts => ox820-akitio-mycloud.dts} (50%) create mode 100644 target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts rename target/linux/oxnas/files/arch/arm/boot/dts/{ox820-stg212.dts => ox820-mitrastar-stg212.dts} (58%) delete mode 100644 target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts delete mode 100644 target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts rename target/linux/oxnas/files/arch/arm/boot/dts/{ox820-kd20.dts => ox820-shuttle-kd20.dts} (65%) delete mode 100644 target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi delete mode 100644 target/linux/oxnas/files/arch/arm/configs/ox820_defconfig rename target/linux/oxnas/files/arch/arm/{mach-oxnas/include/mach/uncompress.h => include/debug/uncompress-ox820.h} (100%) delete mode 100644 target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig delete mode 100644 target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile delete mode 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target/linux/oxnas/files/drivers/clk/clk-oxnas.c delete mode 100644 target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c delete mode 100644 target/linux/oxnas/files/drivers/irqchip/irq-rps.c delete mode 100644 target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c delete mode 100644 target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c delete mode 100644 target/linux/oxnas/files/drivers/pinctrl/pinctrl-oxnas.c delete mode 100644 target/linux/oxnas/files/drivers/reset/reset-ox820.c create mode 100644 target/linux/oxnas/image/ox810se.mk create mode 100644 target/linux/oxnas/image/ox820.mk create mode 100644 target/linux/oxnas/ox810se/config-default create mode 100644 target/linux/oxnas/ox810se/profiles/00-default.mk create mode 100644 target/linux/oxnas/ox810se/target.mk create mode 100644 target/linux/oxnas/ox820/config-default rename target/linux/oxnas/{ => ox820}/profiles/00-default.mk (100%) create mode 100644 target/linux/oxnas/ox820/target.mk create mode 100644 target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch create mode 100644 target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch create mode 100644 target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch create mode 100644 target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch create mode 100644 target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch create mode 100644 target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch create mode 100644 target/linux/oxnas/patches-4.14/500-oxnas-sata.patch create mode 100644 target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch create mode 100644 target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch rename target/linux/oxnas/{patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch => patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch} (84%) rename target/linux/oxnas/{patches-4.4 => patches-4.14}/999-libata-hacks.patch (82%) delete mode 100644 target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch delete mode 100644 target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch delete mode 100644 target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch delete mode 100644 target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch delete mode 100644 target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch delete mode 100644 target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch delete mode 100644 target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch delete mode 100644 target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch delete mode 100644 target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch delete mode 100644 target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch delete mode 100644 target/linux/oxnas/patches-4.4/350-oxnas-reset.patch delete mode 100644 target/linux/oxnas/patches-4.4/400-oxnas-nand.patch delete mode 100644 target/linux/oxnas/patches-4.4/500-oxnas-sata.patch delete mode 100644 target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch delete mode 100644 target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch delete mode 100644 target/linux/oxnas/patches-4.4/900-more-boards.patch diff --git a/include/kernel-version.mk b/include/kernel-version.mk index 877fa880f..6c220f3f2 100644 --- a/include/kernel-version.mk +++ b/include/kernel-version.mk @@ -4,13 +4,13 @@ LINUX_RELEASE?=1 LINUX_VERSION-3.18 = .71 LINUX_VERSION-4.4 = .121 -LINUX_VERSION-4.9 = .105 -LINUX_VERSION-4.14 = .44 +LINUX_VERSION-4.9 = .106 +LINUX_VERSION-4.14 = .48 LINUX_KERNEL_HASH-3.18.71 = 5abc9778ad44ce02ed6c8ab52ece8a21c6d20d21f6ed8a19287b4a38a50c1240 LINUX_KERNEL_HASH-4.4.121 = 44a88268b5088dc326b30c9b9133ac35a9a200b636b7268d08f32abeae6ca729 -LINUX_KERNEL_HASH-4.9.105 = d085d228e3ac1fdbdf5a31bb8154e4e8a0943a9085f0384842601db8e9d96dc4 -LINUX_KERNEL_HASH-4.14.44 = 2eb356e6af25f6ca65affe7704be8c4e0cdf224505e7441ac9d5b6e8d96ec8e4 +LINUX_KERNEL_HASH-4.9.106 = 2d409bb29588ea9a61bae006255ee97a675ded364c87a9ff43f687c5271bbe3c +LINUX_KERNEL_HASH-4.14.48 = 80a0608f611fe7a5c54556402cdc2880a21301e1c4e1b19d4c1db82ad2bf22b9 remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1)))) sanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1))))))) diff --git a/target/linux/apm821xx/patches-4.14/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch b/target/linux/apm821xx/patches-4.14/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch index efaf61a5f..e8154253a 100644 --- a/target/linux/apm821xx/patches-4.14/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch +++ b/target/linux/apm821xx/patches-4.14/801-usb-xhci-add-firmware-loader-for-uPD720201-and-uPD72.patch @@ -44,7 +44,7 @@ Signed-off-by: Christian Lamparter #include "xhci.h" #include "xhci-trace.h" -@@ -244,6 +246,458 @@ static void xhci_pme_acpi_rtd3_enable(st +@@ -255,6 +257,458 @@ static void xhci_pme_acpi_rtd3_enable(st static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { } #endif /* CONFIG_ACPI */ @@ -503,7 +503,7 @@ Signed-off-by: Christian Lamparter /* called during probe() after chip reset completes */ static int xhci_pci_setup(struct usb_hcd *hcd) { -@@ -279,6 +733,22 @@ static int xhci_pci_probe(struct pci_dev +@@ -290,6 +744,22 @@ static int xhci_pci_probe(struct pci_dev struct hc_driver *driver; struct usb_hcd *hcd; @@ -526,7 +526,7 @@ Signed-off-by: Christian Lamparter driver = (struct hc_driver *)id->driver_data; /* For some HW implementation, a XHCI reset is just not enough... */ -@@ -343,6 +813,16 @@ static void xhci_pci_remove(struct pci_d +@@ -354,6 +824,16 @@ static void xhci_pci_remove(struct pci_d { struct xhci_hcd *xhci; diff --git a/target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch b/target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch index b78a7881c..3545b99aa 100644 --- a/target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch +++ b/target/linux/apm821xx/patches-4.14/802-usb-xhci-force-msi-renesas-xhci.patch @@ -13,7 +13,7 @@ produce a noisy warning. --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c -@@ -202,7 +202,7 @@ static void xhci_pci_quirks(struct devic +@@ -213,7 +213,7 @@ static void xhci_pci_quirks(struct devic xhci->quirks |= XHCI_TRUST_TX_LENGTH; if (pdev->vendor == PCI_VENDOR_ID_RENESAS && pdev->device == 0x0015) diff --git a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch b/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch index 5963ee899..d1755394f 100644 --- a/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch +++ b/target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch @@ -156,7 +156,7 @@ Signed-off-by: John Crispin /* * PLL block */ -@@ -166,8 +260,14 @@ +@@ -166,9 +260,15 @@ #define AR71XX_AHB_DIV_SHIFT 20 #define AR71XX_AHB_DIV_MASK 0x7 @@ -164,14 +164,14 @@ Signed-off-by: John Crispin +#define AR71XX_ETH1_PLL_SHIFT 19 + #define AR724X_PLL_REG_CPU_CONFIG 0x00 --#define AR724X_PLL_REG_PCIE_CONFIG 0x18 -+#define AR724X_PLL_REG_PCIE_CONFIG 0x10 -+ + #define AR724X_PLL_REG_PCIE_CONFIG 0x10 + +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16) +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25) - ++ #define AR724X_PLL_FB_SHIFT 0 #define AR724X_PLL_FB_MASK 0x3ff + #define AR724X_PLL_REF_DIV_SHIFT 10 @@ -178,6 +278,8 @@ #define AR724X_DDR_DIV_SHIFT 22 #define AR724X_DDR_DIV_MASK 0x3 diff --git a/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch index e2ca932af..9897679a6 100644 --- a/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-4.14/910-unaligned_access_hacks.patch @@ -724,7 +724,7 @@ | TCPOLEN_TIMESTAMP)) --- a/net/xfrm/xfrm_input.c +++ b/net/xfrm/xfrm_input.c -@@ -187,8 +187,8 @@ int xfrm_parse_spi(struct sk_buff *skb, +@@ -193,8 +193,8 @@ int xfrm_parse_spi(struct sk_buff *skb, if (!pskb_may_pull(skb, hlen)) return -EINVAL; @@ -737,7 +737,7 @@ EXPORT_SYMBOL(xfrm_parse_spi); --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -3842,14 +3842,16 @@ static bool tcp_parse_aligned_timestamp( +@@ -3844,14 +3844,16 @@ static bool tcp_parse_aligned_timestamp( { const __be32 *ptr = (const __be32 *)(th + 1); diff --git a/target/linux/bcm53xx/patches-4.14/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-4.14/180-usb-xhci-add-support-for-performing-fake-doorbell.patch index 9f58370a1..3bee392f4 100644 --- a/target/linux/bcm53xx/patches-4.14/180-usb-xhci-add-support-for-performing-fake-doorbell.patch +++ b/target/linux/bcm53xx/patches-4.14/180-usb-xhci-add-support-for-performing-fake-doorbell.patch @@ -129,7 +129,7 @@ it on BCM4708 family. +++ b/drivers/usb/host/xhci.h @@ -1831,6 +1831,7 @@ struct xhci_hcd { #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) - /* Reserved. It was XHCI_U2_DISABLE_WAKE */ + #define XHCI_U2_DISABLE_WAKE (1 << 27) #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) +#define XHCI_FAKE_DOORBELL (1 << 29) #define XHCI_SUSPEND_DELAY (1 << 30) diff --git a/target/linux/generic/backport-4.14/011-kbuild-export-SUBARCH.patch b/target/linux/generic/backport-4.14/011-kbuild-export-SUBARCH.patch index 0ce742959..3df01c34b 100644 --- a/target/linux/generic/backport-4.14/011-kbuild-export-SUBARCH.patch +++ b/target/linux/generic/backport-4.14/011-kbuild-export-SUBARCH.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/Makefile +++ b/Makefile -@@ -433,8 +433,8 @@ KBUILD_CFLAGS_MODULE := -DMODULE +@@ -428,8 +428,8 @@ KBUILD_CFLAGS_MODULE := -DMODULE KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds GCC_PLUGINS_CFLAGS := diff --git a/target/linux/generic/backport-4.14/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch b/target/linux/generic/backport-4.14/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch index 784c548c8..45039ce13 100644 --- a/target/linux/generic/backport-4.14/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch +++ b/target/linux/generic/backport-4.14/272-uapi-if_ether.h-prevent-redefinition-of-struct-ethhd.patch @@ -26,7 +26,7 @@ Signed-off-by: Hauke Mehrtens /* * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble -@@ -149,11 +150,13 @@ +@@ -150,11 +151,13 @@ * This is an Ethernet frame header. */ diff --git a/target/linux/generic/backport-4.14/336-v4.15-netfilter-exit_net-cleanup-check-added.patch b/target/linux/generic/backport-4.14/336-v4.15-netfilter-exit_net-cleanup-check-added.patch index d4b99a5dc..431098fa0 100644 --- a/target/linux/generic/backport-4.14/336-v4.15-netfilter-exit_net-cleanup-check-added.patch +++ b/target/linux/generic/backport-4.14/336-v4.15-netfilter-exit_net-cleanup-check-added.patch @@ -11,7 +11,7 @@ Signed-off-by: Pablo Neira Ayuso --- a/net/ipv4/netfilter/ipt_CLUSTERIP.c +++ b/net/ipv4/netfilter/ipt_CLUSTERIP.c -@@ -829,6 +829,7 @@ static void clusterip_net_exit(struct ne +@@ -834,6 +834,7 @@ static void clusterip_net_exit(struct ne cn->procdir = NULL; #endif nf_unregister_net_hook(net, &cip_arp_ops); diff --git a/target/linux/generic/hack-4.14/202-reduce_module_size.patch b/target/linux/generic/hack-4.14/202-reduce_module_size.patch index 7d67e847c..2cbb6add9 100644 --- a/target/linux/generic/hack-4.14/202-reduce_module_size.patch +++ b/target/linux/generic/hack-4.14/202-reduce_module_size.patch @@ -13,7 +13,7 @@ Signed-off-by: Felix Fietkau --- a/Makefile +++ b/Makefile -@@ -430,7 +430,7 @@ KBUILD_AFLAGS_KERNEL := +@@ -425,7 +425,7 @@ KBUILD_AFLAGS_KERNEL := KBUILD_CFLAGS_KERNEL := KBUILD_AFLAGS_MODULE := -DMODULE KBUILD_CFLAGS_MODULE := -DMODULE diff --git a/target/linux/generic/hack-4.14/207-disable-modorder.patch b/target/linux/generic/hack-4.14/207-disable-modorder.patch index 8f99cde61..5fb956c98 100644 --- a/target/linux/generic/hack-4.14/207-disable-modorder.patch +++ b/target/linux/generic/hack-4.14/207-disable-modorder.patch @@ -15,7 +15,7 @@ Signed-off-by: Felix Fietkau --- a/Makefile +++ b/Makefile -@@ -1233,7 +1233,6 @@ all: modules +@@ -1227,7 +1227,6 @@ all: modules PHONY += modules modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin @@ -23,7 +23,7 @@ Signed-off-by: Felix Fietkau @$(kecho) ' Building modules, stage 2.'; $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost -@@ -1262,7 +1261,6 @@ _modinst_: +@@ -1256,7 +1255,6 @@ _modinst_: rm -f $(MODLIB)/build ; \ ln -s $(CURDIR) $(MODLIB)/build ; \ fi diff --git a/target/linux/generic/hack-4.14/220-gc_sections.patch b/target/linux/generic/hack-4.14/220-gc_sections.patch index ef7cd6f89..7fd493d2f 100644 --- a/target/linux/generic/hack-4.14/220-gc_sections.patch +++ b/target/linux/generic/hack-4.14/220-gc_sections.patch @@ -33,7 +33,7 @@ Signed-off-by: Gabor Juhos # Read KERNELRELEASE from include/config/kernel.release (if it exists) KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null) KERNELVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) -@@ -787,11 +792,6 @@ ifdef CONFIG_DEBUG_SECTION_MISMATCH +@@ -781,11 +786,6 @@ ifdef CONFIG_DEBUG_SECTION_MISMATCH KBUILD_CFLAGS += $(call cc-option, -fno-inline-functions-called-once) endif diff --git a/target/linux/generic/hack-4.14/773-bgmac-add-srab-switch.patch b/target/linux/generic/hack-4.14/773-bgmac-add-srab-switch.patch index a6ba81fb0..33a18a835 100644 --- a/target/linux/generic/hack-4.14/773-bgmac-add-srab-switch.patch +++ b/target/linux/generic/hack-4.14/773-bgmac-add-srab-switch.patch @@ -32,7 +32,7 @@ Signed-off-by: Hauke Mehrtens #include #include #include -@@ -1409,6 +1410,17 @@ static const struct ethtool_ops bgmac_et +@@ -1410,6 +1411,17 @@ static const struct ethtool_ops bgmac_et .set_link_ksettings = phy_ethtool_set_link_ksettings, }; @@ -50,7 +50,7 @@ Signed-off-by: Hauke Mehrtens /************************************************** * MII **************************************************/ -@@ -1538,6 +1550,14 @@ int bgmac_enet_probe(struct bgmac *bgmac +@@ -1539,6 +1551,14 @@ int bgmac_enet_probe(struct bgmac *bgmac net_dev->hw_features = net_dev->features; net_dev->vlan_features = net_dev->features; @@ -65,7 +65,7 @@ Signed-off-by: Hauke Mehrtens err = register_netdev(bgmac->net_dev); if (err) { dev_err(bgmac->dev, "Cannot register net device\n"); -@@ -1560,6 +1580,10 @@ EXPORT_SYMBOL_GPL(bgmac_enet_probe); +@@ -1561,6 +1581,10 @@ EXPORT_SYMBOL_GPL(bgmac_enet_probe); void bgmac_enet_remove(struct bgmac *bgmac) { diff --git a/target/linux/generic/hack-4.14/902-debloat_proc.patch b/target/linux/generic/hack-4.14/902-debloat_proc.patch index 4f5fb7022..3f47d2235 100644 --- a/target/linux/generic/hack-4.14/902-debloat_proc.patch +++ b/target/linux/generic/hack-4.14/902-debloat_proc.patch @@ -243,7 +243,7 @@ Signed-off-by: Felix Fietkau } --- a/mm/vmstat.c +++ b/mm/vmstat.c -@@ -1944,10 +1944,12 @@ void __init init_mm_internals(void) +@@ -1946,10 +1946,12 @@ void __init init_mm_internals(void) start_shepherd_timer(); #endif #ifdef CONFIG_PROC_FS diff --git a/target/linux/generic/pending-4.14/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch b/target/linux/generic/pending-4.14/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch deleted file mode 100644 index a554aa112..000000000 --- a/target/linux/generic/pending-4.14/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: Felix Fietkau -Date: Wed, 21 Feb 2018 13:40:12 +0100 -Subject: [PATCH] clocksource: mips-gic-timer: fix clocksource counter width - -This code needs to use ffs instead of fls on the mask to determine the -shift for reading the GIC_CONFIG_COUNTBITS field. - -Fixes: e07127a077c7 ("clocksource: mips-gic-timer: Use new GIC accessor functions") -Cc: Paul Burton -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/clocksource/mips-gic-timer.c -+++ b/drivers/clocksource/mips-gic-timer.c -@@ -164,7 +164,7 @@ static int __init __gic_clocksource_init - - /* Set clocksource mask. */ - count_width = read_gic_config() & GIC_CONFIG_COUNTBITS; -- count_width >>= __fls(GIC_CONFIG_COUNTBITS); -+ count_width >>= __ffs(GIC_CONFIG_COUNTBITS); - count_width *= 4; - count_width += 32; - gic_clocksource.mask = CLOCKSOURCE_MASK(count_width); diff --git a/target/linux/generic/pending-4.14/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch b/target/linux/generic/pending-4.14/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch deleted file mode 100644 index 69d926bd5..000000000 --- a/target/linux/generic/pending-4.14/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch +++ /dev/null @@ -1,90 +0,0 @@ -From patchwork Thu Apr 26 23:28:34 2018 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: [v2] MIPS: c-r4k: fix data corruption related to cache coherence. -X-Patchwork-Submitter: NeilBrown -X-Patchwork-Id: 19259 -Message-Id: <87vacdlf8d.fsf@notabene.neil.brown.name> -To: James Hogan -Cc: Ralf Baechle , - Paul Burton , linux-mips@linux-mips.org, - linux-kernel@vger.kernel.org -Date: Fri, 27 Apr 2018 09:28:34 +1000 -From: NeilBrown -List-Id: linux-mips - -When DMA will be performed to a MIPS32 1004K CPS, the -L1-cache for the range needs to be flushed and invalidated -first. -The code currently takes one of two approaches. -1/ If the range is less than the size of the dcache, then - HIT type requests flush/invalidate cache lines for the - particular addresses. HIT-type requests a globalised - by the CPS so this is safe on SMP. - -2/ If the range is larger than the size of dcache, then - INDEX type requests flush/invalidate the whole cache. - INDEX type requests affect the local cache only. CPS - does not propagate them in any way. So this invalidation - is not safe on SMP CPS systems. - -Data corruption due to '2' can quite easily be demonstrated by -repeatedly "echo 3 > /proc/sys/vm/drop_caches" and then sha1sum -a file that is several times the size of available memory. -Dropping caches means that large contiguous extents (large than -dcache) are more likely. - -This was not a problem before Linux-4.8 because option 2 was -never used if CONFIG_MIPS_CPS was defined. The commit -which removed that apparently didn't appreciate the full -consequence of the change. - -We could, in theory, globalize the INDEX based flush by sending an IPI -to other cores. These cache invalidation routines can be called with -interrupts disabled and synchronous IPI require interrupts to be -enabled. Asynchronous IPI may not trigger writeback soon enough. -So we cannot use IPI in practice. - -We can already test is IPI would be needed for an INDEX operation -with r4k_op_needs_ipi(R4K_INDEX). If this is True then we mustn't try -the INDEX approach as we cannot use IPI. If this is False (e.g. when -there is only one core and hence one L1 cache) then it is safe to -use the INDEX approach without IPI. - -This patch avoids options 2 if r4k_op_needs_ipi(R4K_INDEX), and so -eliminates the corruption. - -Fixes: c00ab4896ed5 ("MIPS: Remove cpu_has_safe_index_cacheops") -Cc: stable@vger.kernel.org # v4.8+ -Signed-off-by: NeilBrown ---- - arch/mips/mm/c-r4k.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/arch/mips/mm/c-r4k.c -+++ b/arch/mips/mm/c-r4k.c -@@ -851,9 +851,12 @@ static void r4k_dma_cache_wback_inv(unsi - /* - * Either no secondary cache or the available caches don't have the - * subset property so we have to flush the primary caches -- * explicitly -+ * explicitly. -+ * If we would need IPI to perform an INDEX-type operation, then -+ * we have to use the HIT-type alternative as IPI cannot be used -+ * here due to interrupts possibly being disabled. - */ -- if (size >= dcache_size) { -+ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { - r4k_blast_dcache(); - } else { - R4600_HIT_CACHEOP_WAR_IMPL; -@@ -890,7 +893,7 @@ static void r4k_dma_cache_inv(unsigned l - return; - } - -- if (size >= dcache_size) { -+ if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) { - r4k_blast_dcache(); - } else { - R4600_HIT_CACHEOP_WAR_IMPL; diff --git a/target/linux/generic/pending-4.14/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch b/target/linux/generic/pending-4.14/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch index b9bb3f71f..c97e93250 100644 --- a/target/linux/generic/pending-4.14/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch +++ b/target/linux/generic/pending-4.14/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch @@ -8,7 +8,7 @@ Signed-off-by: Felix Fietkau --- a/fs/jffs2/dir.c +++ b/fs/jffs2/dir.c -@@ -756,6 +756,24 @@ static int jffs2_mknod (struct inode *di +@@ -752,6 +752,24 @@ static int jffs2_mknod (struct inode *di return ret; } @@ -33,7 +33,7 @@ Signed-off-by: Felix Fietkau static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry, struct inode *new_dir_i, struct dentry *new_dentry, unsigned int flags) -@@ -766,7 +784,7 @@ static int jffs2_rename (struct inode *o +@@ -762,7 +780,7 @@ static int jffs2_rename (struct inode *o uint8_t type; uint32_t now; @@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau return -EINVAL; /* The VFS will check for us and prevent trying to rename a -@@ -832,9 +850,14 @@ static int jffs2_rename (struct inode *o +@@ -828,9 +846,14 @@ static int jffs2_rename (struct inode *o if (d_is_dir(old_dentry) && !victim_f) inc_nlink(new_dir_i); diff --git a/target/linux/generic/pending-4.14/141-jffs2-add-RENAME_EXCHANGE-support.patch b/target/linux/generic/pending-4.14/141-jffs2-add-RENAME_EXCHANGE-support.patch index 4b30bc7cd..093a73ab6 100644 --- a/target/linux/generic/pending-4.14/141-jffs2-add-RENAME_EXCHANGE-support.patch +++ b/target/linux/generic/pending-4.14/141-jffs2-add-RENAME_EXCHANGE-support.patch @@ -6,7 +6,7 @@ Signed-off-by: Felix Fietkau --- a/fs/jffs2/dir.c +++ b/fs/jffs2/dir.c -@@ -781,18 +781,31 @@ static int jffs2_rename (struct inode *o +@@ -777,18 +777,31 @@ static int jffs2_rename (struct inode *o int ret; struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb); struct jffs2_inode_info *victim_f = NULL; @@ -40,7 +40,7 @@ Signed-off-by: Felix Fietkau victim_f = JFFS2_INODE_INFO(d_inode(new_dentry)); if (d_is_dir(new_dentry)) { struct jffs2_full_dirent *fd; -@@ -827,7 +840,7 @@ static int jffs2_rename (struct inode *o +@@ -823,7 +836,7 @@ static int jffs2_rename (struct inode *o if (ret) return ret; @@ -49,7 +49,7 @@ Signed-off-by: Felix Fietkau /* There was a victim. Kill it off nicely */ if (d_is_dir(new_dentry)) clear_nlink(d_inode(new_dentry)); -@@ -853,6 +866,12 @@ static int jffs2_rename (struct inode *o +@@ -849,6 +862,12 @@ static int jffs2_rename (struct inode *o if (flags & RENAME_WHITEOUT) /* Replace with whiteout */ ret = jffs2_whiteout(old_dir_i, old_dentry); @@ -62,7 +62,7 @@ Signed-off-by: Felix Fietkau else /* Unlink the original */ ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), -@@ -884,7 +903,7 @@ static int jffs2_rename (struct inode *o +@@ -880,7 +899,7 @@ static int jffs2_rename (struct inode *o return ret; } diff --git a/target/linux/generic/pending-4.14/182-net-qmi_wwan-add-BroadMobi-BM806U-2020-2033.patch b/target/linux/generic/pending-4.14/182-net-qmi_wwan-add-BroadMobi-BM806U-2020-2033.patch deleted file mode 100644 index 8ed0bde02..000000000 --- a/target/linux/generic/pending-4.14/182-net-qmi_wwan-add-BroadMobi-BM806U-2020-2033.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 743989254ea9f132517806d8893ca9b6cf9dc86b Mon Sep 17 00:00:00 2001 -From: Pawel Dembicki -Date: Sat, 24 Mar 2018 22:08:14 +0100 -Subject: [PATCH] net: qmi_wwan: add BroadMobi BM806U 2020:2033 - -BroadMobi BM806U is an Qualcomm MDM9225 based 3G/4G modem. -Tested hardware BM806U is mounted on D-Link DWR-921-C3 router. -The USB id is added to qmi_wwan.c to allow QMI communication with -the BM806U. - -Tested on 4.14 kernel and OpenWRT. - -Signed-off-by: Pawel Dembicki -Signed-off-by: David S. Miller ---- - drivers/net/usb/qmi_wwan.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/usb/qmi_wwan.c -+++ b/drivers/net/usb/qmi_wwan.c -@@ -1184,6 +1184,7 @@ static const struct usb_device_id produc - {QMI_FIXED_INTF(0x19d2, 0x2002, 4)}, /* ZTE (Vodafone) K3765-Z */ - {QMI_FIXED_INTF(0x2001, 0x7e19, 4)}, /* D-Link DWM-221 B1 */ - {QMI_FIXED_INTF(0x2001, 0x7e35, 4)}, /* D-Link DWM-222 */ -+ {QMI_FIXED_INTF(0x2020, 0x2033, 4)}, /* BroadMobi BM806U */ - {QMI_FIXED_INTF(0x0f3d, 0x68a2, 8)}, /* Sierra Wireless MC7700 */ - {QMI_FIXED_INTF(0x114f, 0x68a2, 8)}, /* Sierra Wireless MC7750 */ - {QMI_FIXED_INTF(0x1199, 0x68a2, 8)}, /* Sierra Wireless MC7710 in QMI mode */ diff --git a/target/linux/generic/pending-4.14/201-extra_optimization.patch b/target/linux/generic/pending-4.14/201-extra_optimization.patch index 3c3353c7d..445c0bd87 100644 --- a/target/linux/generic/pending-4.14/201-extra_optimization.patch +++ b/target/linux/generic/pending-4.14/201-extra_optimization.patch @@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau --- a/Makefile +++ b/Makefile -@@ -650,12 +650,12 @@ KBUILD_CFLAGS += $(call cc-disable-warni +@@ -645,12 +645,12 @@ KBUILD_CFLAGS += $(call cc-disable-warni ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE KBUILD_CFLAGS += $(call cc-option,-Oz,-Os) diff --git a/target/linux/generic/pending-4.14/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-4.14/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch index 11f12bb6d..09dfd1b90 100644 --- a/target/linux/generic/pending-4.14/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch +++ b/target/linux/generic/pending-4.14/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch @@ -413,7 +413,7 @@ Signed-off-by: Steven Barth } static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[], -@@ -2060,6 +2271,12 @@ static void ip6_tnl_dellink(struct net_d +@@ -2064,6 +2275,12 @@ static void ip6_tnl_dellink(struct net_d static size_t ip6_tnl_get_size(const struct net_device *dev) { @@ -426,7 +426,7 @@ Signed-off-by: Steven Barth return /* IFLA_IPTUN_LINK */ nla_total_size(4) + -@@ -2089,6 +2306,24 @@ static size_t ip6_tnl_get_size(const str +@@ -2093,6 +2310,24 @@ static size_t ip6_tnl_get_size(const str nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + @@ -451,7 +451,7 @@ Signed-off-by: Steven Barth 0; } -@@ -2096,6 +2331,9 @@ static int ip6_tnl_fill_info(struct sk_b +@@ -2100,6 +2335,9 @@ static int ip6_tnl_fill_info(struct sk_b { struct ip6_tnl *tunnel = netdev_priv(dev); struct __ip6_tnl_parm *parm = &tunnel->parms; @@ -461,7 +461,7 @@ Signed-off-by: Steven Barth if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || -@@ -2105,9 +2343,27 @@ static int ip6_tnl_fill_info(struct sk_b +@@ -2109,9 +2347,27 @@ static int ip6_tnl_fill_info(struct sk_b nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || @@ -490,7 +490,7 @@ Signed-off-by: Steven Barth if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || -@@ -2147,6 +2403,7 @@ static const struct nla_policy ip6_tnl_p +@@ -2151,6 +2407,7 @@ static const struct nla_policy ip6_tnl_p [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, diff --git a/target/linux/generic/pending-4.14/811-pci_disable_usb_common_quirks.patch b/target/linux/generic/pending-4.14/811-pci_disable_usb_common_quirks.patch index 410a26759..f40214c29 100644 --- a/target/linux/generic/pending-4.14/811-pci_disable_usb_common_quirks.patch +++ b/target/linux/generic/pending-4.14/811-pci_disable_usb_common_quirks.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/usb/host/pci-quirks.c +++ b/drivers/usb/host/pci-quirks.c -@@ -107,6 +107,8 @@ struct amd_chipset_type { +@@ -124,6 +124,8 @@ struct amd_chipset_type { u8 rev; }; @@ -19,9 +19,9 @@ Signed-off-by: Felix Fietkau static struct amd_chipset_info { struct pci_dev *nb_dev; struct pci_dev *smbus_dev; -@@ -511,6 +513,10 @@ void usb_amd_dev_put(void) +@@ -620,6 +622,10 @@ bool usb_amd_pt_check_port(struct device } - EXPORT_SYMBOL_GPL(usb_amd_dev_put); + EXPORT_SYMBOL_GPL(usb_amd_pt_check_port); +#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */ + @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau /* * Make sure the controller is completely inactive, unable to * generate interrupts or do DMA. -@@ -590,8 +596,17 @@ reset_needed: +@@ -699,8 +705,17 @@ reset_needed: uhci_reset_hc(pdev, base); return 1; } @@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) { u16 cmd; -@@ -1178,3 +1193,4 @@ bool usb_xhci_needs_pci_reset(struct pci +@@ -1287,3 +1302,4 @@ bool usb_xhci_needs_pci_reset(struct pci return false; } EXPORT_SYMBOL_GPL(usb_xhci_needs_pci_reset); @@ -65,8 +65,8 @@ Signed-off-by: Felix Fietkau int usb_amd_find_chipset_info(void); int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev); bool usb_amd_hang_symptom_quirk(void); -@@ -19,12 +22,29 @@ void sb800_prefetch(struct device *dev, - bool usb_xhci_needs_pci_reset(struct pci_dev *pdev); +@@ -20,6 +23,18 @@ bool usb_xhci_needs_pci_reset(struct pci + bool usb_amd_pt_check_port(struct device *device, int port); #else struct pci_dev; +static inline int usb_amd_find_chipset_info(void) @@ -84,9 +84,10 @@ Signed-off-by: Felix Fietkau static inline void usb_amd_quirk_pll_disable(void) {} static inline void usb_amd_quirk_pll_enable(void) {} static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {} - static inline void usb_amd_dev_put(void) {} - static inline void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) {} - static inline void sb800_prefetch(struct device *dev, int on) {} +@@ -30,6 +45,11 @@ static inline bool usb_amd_pt_check_port + { + return false; + } +static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {} +static inline bool usb_xhci_needs_pci_reset(struct pci_dev *pdev) +{ diff --git a/target/linux/generic/pending-4.14/834-ledtrig-libata.patch b/target/linux/generic/pending-4.14/834-ledtrig-libata.patch index 608bad00c..9ecefc913 100644 --- a/target/linux/generic/pending-4.14/834-ledtrig-libata.patch +++ b/target/linux/generic/pending-4.14/834-ledtrig-libata.patch @@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle /** * ata_build_rw_tf - Build ATA taskfile for given read/write request * @tf: Target ATA taskfile -@@ -5114,6 +5127,9 @@ struct ata_queued_cmd *ata_qc_new_init(s +@@ -5120,6 +5133,9 @@ struct ata_queued_cmd *ata_qc_new_init(s if (tag < 0) return NULL; } @@ -75,7 +75,7 @@ Signed-off-by: Daniel Golle qc = __ata_qc_from_tag(ap, tag); qc->tag = tag; -@@ -6015,6 +6031,9 @@ struct ata_port *ata_port_alloc(struct a +@@ -6021,6 +6037,9 @@ struct ata_port *ata_port_alloc(struct a ap->stats.unhandled_irq = 1; ap->stats.idle_irq = 1; #endif @@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle ata_sff_port_init(ap); return ap; -@@ -6036,6 +6055,12 @@ static void ata_host_release(struct devi +@@ -6042,6 +6061,12 @@ static void ata_host_release(struct devi kfree(ap->pmp_link); kfree(ap->slave_link); @@ -98,7 +98,7 @@ Signed-off-by: Daniel Golle kfree(ap); host->ports[i] = NULL; } -@@ -6482,7 +6507,23 @@ int ata_host_register(struct ata_host *h +@@ -6488,7 +6513,23 @@ int ata_host_register(struct ata_host *h host->ports[i]->print_id = atomic_inc_return(&ata_print_id); host->ports[i]->local_port_no = i + 1; } diff --git a/target/linux/generic/pending-4.9/890-uart_optional_sysrq.patch b/target/linux/generic/pending-4.9/890-uart_optional_sysrq.patch index b317070e5..6cb745ee3 100644 --- a/target/linux/generic/pending-4.9/890-uart_optional_sysrq.patch +++ b/target/linux/generic/pending-4.9/890-uart_optional_sysrq.patch @@ -26,7 +26,7 @@ Signed-off-by: Felix Fietkau { --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug -@@ -410,6 +410,11 @@ config MAGIC_SYSRQ_DEFAULT_ENABLE +@@ -396,6 +396,11 @@ config MAGIC_SYSRQ_DEFAULT_ENABLE This may be set to 1 or 0 to enable or disable them all, or to a bitmask as described in Documentation/sysrq.txt. diff --git a/target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch b/target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch index dca516e87..881d08c7e 100644 --- a/target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch +++ b/target/linux/ipq40xx/patches-4.14/040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch @@ -114,7 +114,7 @@ Signed-off-by: Vinod Koul struct list_head node; }; -@@ -539,7 +544,7 @@ static void bam_free_chan(struct dma_cha +@@ -540,7 +545,7 @@ static void bam_free_chan(struct dma_cha vchan_free_chan_resources(to_virt_chan(chan)); @@ -123,7 +123,7 @@ Signed-off-by: Vinod Koul dev_err(bchan->bdev->dev, "Cannot free busy channel\n"); goto err; } -@@ -632,8 +637,6 @@ static struct dma_async_tx_descriptor *b +@@ -633,8 +638,6 @@ static struct dma_async_tx_descriptor *b if (flags & DMA_PREP_INTERRUPT) async_desc->flags |= DESC_FLAG_EOT; @@ -132,7 +132,7 @@ Signed-off-by: Vinod Koul async_desc->num_desc = num_alloc; async_desc->curr_desc = async_desc->desc; -@@ -684,14 +687,16 @@ err_out: +@@ -685,14 +688,16 @@ err_out: static int bam_dma_terminate_all(struct dma_chan *chan) { struct bam_chan *bchan = to_bam_chan(chan); @@ -152,7 +152,7 @@ Signed-off-by: Vinod Koul } vchan_get_all_descriptors(&bchan->vc, &head); -@@ -763,9 +768,9 @@ static int bam_resume(struct dma_chan *c +@@ -764,9 +769,9 @@ static int bam_resume(struct dma_chan *c */ static u32 process_channel_irqs(struct bam_device *bdev) { @@ -164,7 +164,7 @@ Signed-off-by: Vinod Koul srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE)); -@@ -785,27 +790,40 @@ static u32 process_channel_irqs(struct b +@@ -786,27 +791,40 @@ static u32 process_channel_irqs(struct b writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR)); spin_lock_irqsave(&bchan->vc.lock, flags); @@ -214,7 +214,7 @@ Signed-off-by: Vinod Koul } spin_unlock_irqrestore(&bchan->vc.lock, flags); -@@ -867,6 +885,7 @@ static enum dma_status bam_tx_status(str +@@ -868,6 +886,7 @@ static enum dma_status bam_tx_status(str struct dma_tx_state *txstate) { struct bam_chan *bchan = to_bam_chan(chan); @@ -222,7 +222,7 @@ Signed-off-by: Vinod Koul struct virt_dma_desc *vd; int ret; size_t residue = 0; -@@ -882,11 +901,17 @@ static enum dma_status bam_tx_status(str +@@ -883,11 +902,17 @@ static enum dma_status bam_tx_status(str spin_lock_irqsave(&bchan->vc.lock, flags); vd = vchan_find_desc(&bchan->vc, cookie); @@ -244,7 +244,7 @@ Signed-off-by: Vinod Koul spin_unlock_irqrestore(&bchan->vc.lock, flags); -@@ -927,63 +952,86 @@ static void bam_start_dma(struct bam_cha +@@ -928,63 +953,86 @@ static void bam_start_dma(struct bam_cha { struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc); struct bam_device *bdev = bchan->bdev; @@ -367,7 +367,7 @@ Signed-off-by: Vinod Koul /* ensure descriptor writes and dma start not reordered */ wmb(); -@@ -1012,7 +1060,7 @@ static void dma_tasklet(unsigned long da +@@ -1013,7 +1061,7 @@ static void dma_tasklet(unsigned long da bchan = &bdev->channels[i]; spin_lock_irqsave(&bchan->vc.lock, flags); @@ -376,7 +376,7 @@ Signed-off-by: Vinod Koul bam_start_dma(bchan); spin_unlock_irqrestore(&bchan->vc.lock, flags); } -@@ -1033,7 +1081,7 @@ static void bam_issue_pending(struct dma +@@ -1034,7 +1082,7 @@ static void bam_issue_pending(struct dma spin_lock_irqsave(&bchan->vc.lock, flags); /* if work pending and idle, start a transaction */ @@ -385,7 +385,7 @@ Signed-off-by: Vinod Koul bam_start_dma(bchan); spin_unlock_irqrestore(&bchan->vc.lock, flags); -@@ -1133,6 +1181,7 @@ static void bam_channel_init(struct bam_ +@@ -1138,6 +1186,7 @@ static void bam_channel_init(struct bam_ vchan_init(&bchan->vc, &bdev->common); bchan->vc.desc_free = bam_dma_free_desc; diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index 4ae3a9ab0..2180b8394 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -12,7 +12,7 @@ FEATURES:=squashfs SUBTARGETS:=xrx200 xway xway_legacy falcon ase MAINTAINER:=John Crispin -KERNEL_PATCHVER:=4.9 +KERNEL_PATCHVER:=4.14 define Target/Description Build firmware images for Lantiq SoC diff --git a/target/linux/lantiq/ase/config-4.9 b/target/linux/lantiq/ase/config-4.9 deleted file mode 100644 index 0dfd21436..000000000 --- a/target/linux/lantiq/ase/config-4.9 +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_CPU_MIPS32_R1=y -# CONFIG_CPU_MIPS32_R2 is not set -CONFIG_CPU_MIPSR1=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_GPIO_GENERIC=y -CONFIG_GPIO_GENERIC_PLATFORM=y -# CONFIG_ISDN is not set -# CONFIG_LBDAF is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_NLS=y -# CONFIG_PSB6970_PHY is not set -# CONFIG_RTL8366_SMI is not set -CONFIG_SOC_AMAZON_SE=y -# CONFIG_SOC_XWAY is not set -CONFIG_USB=y -CONFIG_USB_COMMON=y -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_SUPPORT=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/base-files/etc/board.d/01_leds b/target/linux/lantiq/base-files/etc/board.d/01_leds index 0426fb18e..4476a7eb4 100755 --- a/target/linux/lantiq/base-files/etc/board.d/01_leds +++ b/target/linux/lantiq/base-files/etc/board.d/01_leds @@ -53,6 +53,10 @@ bt,homehub-v5a) netgear,dm200) ucidef_set_led_netdev "lan" "lan" "dm200:green:lan" "eth0" ;; +avm,fritz3370-rev2-hynix|\ +avm,fritz3370-rev2-micron) + ucidef_set_led_switch "lan" "LAN" "fritz3370:green:lan" "switch0" "0x17" + ;; avm,fritz7320) ucidef_set_led_netdev "wifi" "wifi" "fritz7320:green:wlan" "wlan0" ;; diff --git a/target/linux/lantiq/base-files/etc/board.d/02_network b/target/linux/lantiq/base-files/etc/board.d/02_network index ca974b071..9da01d14c 100755 --- a/target/linux/lantiq/base-files/etc/board.d/02_network +++ b/target/linux/lantiq/base-files/etc/board.d/02_network @@ -135,10 +135,13 @@ lantiq,easy80920-nand|lantiq,easy80920-nor) "0:lan:4" "1:lan:3" "2:lan:2" "4:lan:1" "5:wan:5" "6t@eth0" ;; -avm,fritz3370) +avm,fritz3370-rev2-hynix|\ +avm,fritz3370-rev2-micron) annex="b" - wan_mac=$(macaddr_add "$(mtd_get_mac_binary urlader 2439)" 1) - ucidef_set_interface_lan 'eth0' + lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)")) + wan_mac=$(macaddr_add "$lan_mac" 3) + ucidef_add_switch "switch0" \ + "0:lan:3" "1:lan:4" "2:lan:2" "4:lan:1" "6t@eth0" ;; avm,fritz7320) diff --git a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom b/target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom index 498a50901..75b763076 100644 --- a/target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom +++ b/target/linux/lantiq/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom @@ -47,6 +47,24 @@ ath9k_eeprom_extract_raw() { ath9k_eeprom_die "failed to extract from $mtd" } +ath9k_eeprom_extract_reverse() { + local part=$1 + local offset=$2 + local count=$3 + local mtd + local reversed + local caldata + + mtd=$(find_mtd_chardev "$part") + reversed=$(hexdump -v -s $offset -n $count -e '/1 "%02x "' $mtd) + + for byte in $reversed; do + caldata="\x${byte}${caldata}" + done + + printf "%b" "$caldata" > /lib/firmware/$FIRMWARE +} + ath9k_eeprom_extract() { local part=$1 local offset=$2 @@ -138,7 +156,11 @@ case "$FIRMWARE" in ath9k_eeprom_extract "calibration" 61440 0 ath9k_patch_fw_mac_crc $(macaddr_add $(mtd_get_mac_ascii uboot-env ethaddr) +2) 524 ;; - avm,fritz3370|avm,fritz7320|avm,fritz7360sl) + avm,fritz3370-rev2-hynix|\ + avm,fritz3370-rev2-micron) + ath9k_eeprom_extract_reverse "urlader" 5441 1088 + ;; + avm,fritz7320|avm,fritz7360sl) ath9k_eeprom_extract "urlader" 2437 0 ;; tplink,tdw8970|tplink,tdw8980) diff --git a/target/linux/lantiq/base-files/lib/upgrade/platform.sh b/target/linux/lantiq/base-files/lib/upgrade/platform.sh index 2e58cb799..ecbb939e3 100755 --- a/target/linux/lantiq/base-files/lib/upgrade/platform.sh +++ b/target/linux/lantiq/base-files/lib/upgrade/platform.sh @@ -9,7 +9,13 @@ platform_do_upgrade() { local board=$(board_name) case "$board" in - bt,homehub-v2b|bt,homehub-v3a|bt,homehub-v5a|zyxel,p-2812hnu-f1|zyxel,p-2812hnu-f3) + avm,fritz3370-rev2-hynix|\ + avm,fritz3370-rev2-micron|\ + bt,homehub-v2b|\ + bt,homehub-v3a|\ + bt,homehub-v5a|\ + zyxel,p-2812hnu-f1|\ + zyxel,p-2812hnu-f3) nand_do_upgrade $1 ;; *) diff --git a/target/linux/lantiq/config-4.14 b/target/linux/lantiq/config-4.14 index 063f2ba3e..12264413d 100644 --- a/target/linux/lantiq/config-4.14 +++ b/target/linux/lantiq/config-4.14 @@ -19,7 +19,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -# CONFIG_ARCH_WANTS_THP_SWAP is not set CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y @@ -47,16 +46,11 @@ CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y -# CONFIG_DMA_NOOP_OPS is not set -# CONFIG_DMA_VIRT_OPS is not set -# CONFIG_DRM_LIB_RANDOM is not set CONFIG_DTC=y # CONFIG_DT_EASY50712 is not set CONFIG_EARLY_PRINTK=y CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_EXPORTFS=y CONFIG_FIXED_PHY=y -CONFIG_FUTEX_PI=y CONFIG_GENERIC_ATOMIC64=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CMOS_UPDATE=y @@ -227,7 +221,6 @@ CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_MIPS16=y CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_THIN_ARCHIVES=y CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TINY_SRCU=y CONFIG_USE_OF=y diff --git a/target/linux/lantiq/config-4.9 b/target/linux/lantiq/config-4.9 deleted file mode 100644 index a98509e5d..000000000 --- a/target/linux/lantiq/config-4.9 +++ /dev/null @@ -1,199 +0,0 @@ -CONFIG_ARCH_BINFMT_ELF_STATE=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_ARCH_DISCARD_MEMBLOCK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set -CONFIG_ARCH_HAS_RESET_CONTROLLER=y -# CONFIG_ARCH_HAS_SG_CHAIN is not set -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_CEVT_R4K=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CPU_BIG_ENDIAN=y -CONFIG_CPU_GENERIC_DUMP_TLB=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_RIXI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -CONFIG_CPU_MIPSR2=y -CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y -CONFIG_CPU_R4K_CACHE_TLB=y -CONFIG_CPU_R4K_FPU=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_CPU_SUPPORTS_MSA=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DTC=y -# CONFIG_DT_EASY50712 is not set -CONFIG_EARLY_PRINTK=y -CONFIG_ETHERNET_PACKET_MANGLE=y -CONFIG_FIXED_PHY=y -CONFIG_GENERIC_ATOMIC64=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_IO=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_MM_LANTIQ=y -CONFIG_GPIO_STP_XWAY=y -CONFIG_GPIO_SYSFS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -# CONFIG_HAVE_ARCH_BITREVERSE is not set -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_CBPF_JIT=y -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_HAVE_DEBUG_KMEMLEAK=y -CONFIG_HAVE_DEBUG_STACKOVERFLOW=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_HAVE_IDE=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_KVM=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_HAVE_NET_DSA=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -CONFIG_HZ_PERIODIC=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_MIPS_CPU=y -CONFIG_IRQ_WORK=y -CONFIG_LANTIQ=y -CONFIG_LANTIQ_DT_NONE=y -CONFIG_LANTIQ_ETOP=y -CONFIG_LANTIQ_WDT=y -# CONFIG_LANTIQ_XRX200 is not set -CONFIG_LEDS_GPIO=y -CONFIG_LIBFDT=y -CONFIG_MDIO_BOARDINFO=y -CONFIG_MIPS=y -CONFIG_MIPS_ASID_BITS=8 -CONFIG_MIPS_ASID_SHIFT=0 -CONFIG_MIPS_CLOCK_VSYSCALL=y -# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set -# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set -CONFIG_MIPS_CMDLINE_FROM_DTB=y -# CONFIG_MIPS_ELF_APPENDED_DTB is not set -# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_NO_APPENDED_DTB is not set -CONFIG_MIPS_RAW_APPENDED_DTB=y -CONFIG_MIPS_SPRAM=y -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_LANTIQ=y -CONFIG_MTD_M25P80=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_BRNIMAGE_FW=y -CONFIG_MTD_SPLIT_EVA_FW=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_TPLINK_FW=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_PER_CPU_KM=y -CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y -# CONFIG_NO_IOPORT_MAP is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_PCI_DRIVERS_LEGACY=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_LANTIQ=y -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_XWAY=y -CONFIG_PSB6970_PHY=y -# CONFIG_RCU_STALL_COMMON is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RTL8366RB_PHY=y -CONFIG_RTL8366_SMI=y -# CONFIG_SCHED_INFO is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SENSORS_LTQ_CPUTEMP is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_LANTIQ=y -# CONFIG_SOC_AMAZON_SE is not set -# CONFIG_SOC_FALCON is not set -CONFIG_SOC_TYPE_XWAY=y -CONFIG_SOC_XWAY=y -CONFIG_SPI=y -CONFIG_SPI_LANTIQ_SSC=y -CONFIG_SPI_MASTER=y -CONFIG_SRCU=y -CONFIG_SWAP_IO_SPACE=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MIPS16=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_USE_OF=y -# CONFIG_XRX200_PHY_FW is not set diff --git a/target/linux/lantiq/falcon/config-4.9 b/target/linux/lantiq/falcon/config-4.9 deleted file mode 100644 index de4fa3686..000000000 --- a/target/linux/lantiq/falcon/config-4.9 +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux" -CONFIG_PINCTRL_FALCON=y -# CONFIG_PSB6970_PHY is not set -# CONFIG_RTL8366_SMI is not set -CONFIG_SOC_FALCON=y -# CONFIG_SOC_TYPE_XWAY is not set -# CONFIG_SOC_XWAY is not set -CONFIG_SPI_FALCON=y diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ACMP252.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ACMP252.dts index 5e1f27160..5a2d86719 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ACMP252.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ACMP252.dts @@ -101,11 +101,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4518PWR01.dtsi b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4518PWR01.dtsi index 458a38753..e95c40368 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4518PWR01.dtsi +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4518PWR01.dtsi @@ -192,11 +192,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4519PW.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4519PW.dts index 5733d2ce1..690c12f42 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4519PW.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4519PW.dts @@ -189,11 +189,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4520PW.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4520PW.dts index aa4269305..68d6dc3e7 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4520PW.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV4520PW.dts @@ -213,11 +213,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV452CQW.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV452CQW.dts index 1e1183d1b..3854ac2db 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV452CQW.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV452CQW.dts @@ -231,11 +231,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7510PW22.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7510PW22.dts index 337f969b3..2c52ec62b 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7510PW22.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7510PW22.dts @@ -195,11 +195,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7518PW.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7518PW.dts index 1d6f404ee..a033b0de7 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7518PW.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7518PW.dts @@ -227,11 +227,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7519RW22.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7519RW22.dts index 40607aebd..2d557f473 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7519RW22.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV7519RW22.dts @@ -236,18 +236,18 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb_phy1 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &usb1 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW.dts index 7b337b4f5..911e71a2c 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW.dts @@ -232,11 +232,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW22.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW22.dts index feb92d4d9..88d9d7fdc 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW22.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV752DPW22.dts @@ -254,11 +254,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV8539PW22.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV8539PW22.dts index 1e39380f6..7b201ff8d 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV8539PW22.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/ARV8539PW22.dts @@ -178,11 +178,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV3A.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV3A.dts index 6bba7e420..d3e2bf761 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV3A.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV3A.dts @@ -207,9 +207,9 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV5A.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV5A.dts index a3be0a5c9..90228667f 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV5A.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/BTHOMEHUBV5A.dts @@ -291,9 +291,9 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi index 464ab5bd4..b7cfc03a1 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi @@ -304,9 +304,9 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts new file mode 100644 index 000000000..225a4f3e8 --- /dev/null +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2-HYNIX.dts @@ -0,0 +1,55 @@ +/dts-v1/; + +#include "FRITZ3370-REV2.dtsi" + +/ { + compatible = "avm,fritz3370-rev2-hynix", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; + model = "AVM Fritz!Box WLAN 3370 Rev. 2 (Hynix NAND)"; +}; + +&localbus { + nand@1 { + compatible = "lantiq,nand-xway"; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-mode = "soft"; + nand-ecc-strength = <3>; + nand-ecc-step-size = <256>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x400000 0x3000000>; + }; + + partition@3400000 { + label = "reserved-kernel"; + reg = <0x3400000 0x400000>; + }; + partition@3800000 { + label = "reserved-filesystem"; + reg = <0x3800000 0x3000000>; + }; + partition@6800000 { + label = "config"; + reg = <0x6800000 0x200000>; + }; + partition@6a00000 { + label = "nand-filesystem"; + reg = <0x6a00000 0x1600000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts new file mode 100644 index 000000000..3346310b1 --- /dev/null +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2-MICRON.dts @@ -0,0 +1,53 @@ +/dts-v1/; + +#include "FRITZ3370-REV2.dtsi" + +/ { + compatible = "avm,fritz3370-rev2-micron", "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; + model = "AVM Fritz!Box WLAN 3370 Rev. 2 (Micron NAND)"; +}; + +&localbus { + nand@1 { + compatible = "lantiq,nand-xway"; + bank-width = <2>; + reg = <1 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-mode = "on-die"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x400000>; + }; + + partition@400000 { + label = "ubi"; + reg = <0x400000 0x3000000>; + }; + + partition@3400000 { + label = "reserved-kernel"; + reg = <0x3400000 0x400000>; + }; + partition@3800000 { + label = "reserved-filesystem"; + reg = <0x3800000 0x3000000>; + }; + partition@6800000 { + label = "config"; + reg = <0x6800000 0x200000>; + }; + partition@6a00000 { + label = "nand-filesystem"; + reg = <0x6a00000 0x1600000>; + }; + }; + }; +}; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2.dtsi similarity index 78% rename from target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370.dts rename to target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2.dtsi index a958fc67a..815c01f89 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/FRITZ3370-REV2.dtsi @@ -1,16 +1,14 @@ -/dts-v1/; - #include "vr9.dtsi" #include #include / { - compatible = "avm,fritz3370", "lantiq,xway", "lantiq,vr9"; - model = "Fritz!Box WLAN 3370"; + compatible = "avm,fritz3370-rev2", "lantiq,xway", "lantiq,vr9"; + model = "AVM Fritz!Box WLAN 3370 Rev. 2"; chosen { - bootargs = "console=ttyLTQ0,115200 ubi.mtd=1,512 root=/dev/mtdblock9"; + bootargs = "console=ttyLTQ0,115200"; }; aliases { @@ -27,21 +25,28 @@ reg = <0x0 0x8000000>; }; + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; #size-cells = <0>; poll-interval = <100>; + power { label = "power"; gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; linux,code = ; }; -/* wifi { - label = "wifi"; + + wifi { + label = "wlan"; gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - };*/ + linux,code = ; + }; }; gpio-leds { @@ -52,31 +57,61 @@ gpios = <&gpio 32 GPIO_ACTIVE_LOW>; default-state = "keep"; }; + power_red: power2 { label = "fritz3370:red:power"; gpios = <&gpio 33 GPIO_ACTIVE_LOW>; }; + info_red { label = "fritz3370:red:info"; gpios = <&gpio 34 GPIO_ACTIVE_LOW>; }; + wifi: wifi { label = "fritz3370:green:wlan"; gpios = <&gpio 35 GPIO_ACTIVE_LOW>; }; + dsl: dsl { label = "fritz3370:green:dsl"; gpios = <&gpio 36 GPIO_ACTIVE_LOW>; }; + lan { label = "fritz3370:green:lan"; gpios = <&gpio 38 GPIO_ACTIVE_LOW>; }; + info_green: info_green { label = "fritz3370:green:info"; gpios = <&gpio 47 GPIO_ACTIVE_LOW>; }; }; + + usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + + regulator-name = "USB1_VBUS"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; ð0 { @@ -85,8 +120,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - mtd-mac-address = <&urlader 0x987>; - mtd-mac-address-increment = <(-2)>; lantiq,switch; ethernet@0 { @@ -96,6 +129,7 @@ phy-handle = <&phy0>; gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; }; + ethernet@1 { compatible = "lantiq,xrx200-pdi-port"; reg = <1>; @@ -103,13 +137,15 @@ phy-handle = <&phy1>; gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; + ethernet@2 { compatible = "lantiq,xrx200-pdi-port"; reg = <2>; phy-mode = "gmii"; phy-handle = <&phy11>; }; - ethernet@3 { + + ethernet@4 { compatible = "lantiq,xrx200-pdi-port"; reg = <4>; phy-mode = "gmii"; @@ -127,14 +163,17 @@ reg = <0x0>; compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; }; + phy1: ethernet-phy@1 { reg = <0x1>; compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; }; + phy11: ethernet-phy@11 { reg = <0x11>; compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; }; + phy13: ethernet-phy@13 { reg = <0x13>; compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; @@ -159,29 +198,34 @@ lantiq,groups = "mdio"; lantiq,function = "mdio"; }; + nand { lantiq,groups = "nand cle", "nand ale", "nand rd", "nand cs1", "nand rdy"; lantiq,function = "ebu"; lantiq,pull = <1>; }; + phy-rst { lantiq,pins = "io37", "io44"; lantiq,pull = <0>; lantiq,open-drain = <0>; lantiq,output = <1>; }; + pcie-rst { - lantiq,pins = "io38"; + lantiq,pins = "io21"; lantiq,pull = <0>; lantiq,output = <1>; }; }; + pins_spi_default: pins_spi_default { spi_in { lantiq,groups = "spi_di"; lantiq,function = "spi"; }; + spi_out { lantiq,groups = "spi_do", "spi_clk", "spi_cs4"; @@ -191,50 +235,9 @@ }; }; -&localbus { - nand@1 { - compatible = "lantiq,nand-xway"; - bank-width = <2>; - reg = <1 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "rootfs_ubi"; - reg = <0x400000 0x3000000>; - }; - - partition@3400000 { - label = "vr9_firmware"; - reg = <0x3400000 0x400000>; - }; - partition@3800000 { - label = "reserved"; - reg = <0x3800000 0x3000000>; - }; - partition@6800000 { - label = "config"; - reg = <0x6800000 0x200000>; - }; - partition@6a00000 { - label = "nand-filesystem"; - reg = <0x6a00000 0x1600000>; - }; - }; - }; -}; - &pcie0 { + gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; + pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; @@ -283,14 +286,20 @@ }; }; -/* - * TODO: add phy-supply, gpio 5 GPIO_ACTIVE_HIGH and gpio 14 GPIO_ACTIVE_HIGH are - * related - */ &usb_phy0 { status = "okay"; }; +&usb_phy1 { + status = "okay"; +}; + &usb0 { status = "okay"; + vbus-supply = <&usb0_vbus>; +}; + +&usb1 { + status = "okay"; + vbus-supply = <&usb1_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/GIGASX76X.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/GIGASX76X.dts index fc028bb5f..36b82515d 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/GIGASX76X.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/GIGASX76X.dts @@ -117,11 +117,11 @@ &usb_phy { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/H201L.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/H201L.dts index 43a4b42d8..90f74bb38 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/H201L.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/H201L.dts @@ -165,10 +165,10 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2601HNFX.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2601HNFX.dts index 267a4f3a7..444dc563b 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2601HNFX.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2601HNFX.dts @@ -186,9 +186,9 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2812HNUFX.dtsi b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2812HNUFX.dtsi index 03858afef..579e562c3 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2812HNUFX.dtsi +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/P2812HNUFX.dtsi @@ -280,18 +280,18 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb_phy1 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &usb1 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/TDW89X0.dtsi b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/TDW89X0.dtsi index e176bca30..233b7e333 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/TDW89X0.dtsi +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/TDW89X0.dtsi @@ -281,18 +281,18 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb_phy1 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &usb1 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7510KW22.dtsi b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7510KW22.dtsi index 8f22380cc..ab558372e 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7510KW22.dtsi +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7510KW22.dtsi @@ -253,11 +253,11 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7519.dtsi b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7519.dtsi index 297f5f7f4..b9276025b 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7519.dtsi +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VGV7519.dtsi @@ -288,20 +288,20 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb_phy1 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &usb1 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &vmmc { diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200v.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200v.dts index d0fcd6fcd..331f08ed5 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200v.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200v.dts @@ -288,18 +288,18 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb_phy1 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &usb1 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR.dts index 6bee3308a..02c118230 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR.dts @@ -191,9 +191,9 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR300.dts b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR300.dts index 4092b6b6e..df7bc9fce 100644 --- a/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR300.dts +++ b/target/linux/lantiq/files-4.14/arch/mips/boot/dts/WBMR300.dts @@ -312,18 +312,18 @@ &usb_phy0 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb_phy1 { status = "okay"; - phy-supply = <&usb_vbus>; }; &usb0 { status = "okay"; + vbus-supply = <&usb_vbus>; }; &usb1 { status = "okay"; + vbus-supply = <&usb_vbus>; }; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ACMP252.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ACMP252.dts deleted file mode 100644 index 729472011..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ACMP252.dts +++ /dev/null @@ -1,102 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -/ { - compatible = "audiocodes,mp-252", "lantiq,xway", "lantiq,danube"; - model = "AudioCodes MediaPack MP-252"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x20000>; - read-only; - }; - - partition@20000 { - label = "uboot_env"; - reg = <0x20000 0x20000>; - }; - - partition@40000 { - label = "boardconfig"; - reg = <0x40000 0x60000>; - read-only; - }; - - partition@a0000 { - label = "firmware"; - reg = <0xa0000 0xf20000>; - }; - - partition@fc0000 { - label = "sysconfig"; - reg = <0xfc0000 0x40000>; - }; - - partition@0x1000000 { - label = "rootfs_data"; - reg = <0x1000000 0x1000000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - - pci@E105400 { - status = "okay"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ALL0333CJ.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ALL0333CJ.dts deleted file mode 100644 index 16c5facb3..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ALL0333CJ.dts +++ /dev/null @@ -1,120 +0,0 @@ -/dts-v1/; - -#include "amazonse.dtsi" - -/ { - compatible = "allnet,all0333cj", "lantiq,xway", "lantiq,ase"; - model = "Allnet ALL0333CJ DSL Modem"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - - led-dsl = &dsl; - led-internet = &online_green; - }; - - }; - - memory@0 { - reg = <0x0 0x1000000>; - }; - - fpi@b0000000 { - etop@E180000 { - phy-mode = "mii"; - }; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - asc { - lantiq,groups = "asc"; - lantiq,function = "asc"; - }; - keys_in { - lantiq,pins = "io0",/* "io25", */"io29"; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; - }; - - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "firmware"; - reg = <0x10000 0x3ef200>; - }; - - partition@3ff200 { - label = "uboot_env"; - reg = <0x3ff200 0xc00>; - read-only; - }; - - partition@3ffe00 { - label = "dummy_bits"; - reg = <0x3ffe00 0x200>; - read-only; - }; - }; - }; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - /* power led: red=off, green=on */ - power: power { - label = "all0333cj:green:power"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - lan: lan { - label = "all0333cj:green:lan"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - - dsl: dsl { - label = "all0333cj:green:dsl"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - - online_green: online { - label = "all0333cj:green:online"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - online_red { - label = "all0333cj:red:online"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4510PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4510PW.dts deleted file mode 100644 index 4720b57dd..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4510PW.dts +++ /dev/null @@ -1,232 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4510pw", "lantiq,xway", "lantiq,danube"; - model = "Wippies, Elisa"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power2; - led-running = &power; - - led-dsl = &adsl; - led-internet = &internet; - led-usb = &usb; - led-usb2 = &usb2; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - lantiq,noxip; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xfa0000>; - }; - }; - }; - }; - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu a23"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - exin { - lantiq,groups = "exin1", "exin2"; - lantiq,function = "exin"; - lantiq,output = <0>; - }; - pci_in { - lantiq,groups = "req1", "req2"; - lantiq,function = "pci"; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1", "gnt2"; - lantiq,function = "pci"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - buttons { - lantiq,pins = "io3", "io14"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - }; - }; - - gpios: stp@E100BB0 { - status = "okay"; - lantiq,groups = <0x7>; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - - pci@E105400 { - status = "okay"; - lantiq,external-clock; - interrupt-map = < - 0x6000 0 0 1 &icu0 135 - 0x7800 0 0 1 &icu0 66 - 0x7800 0 0 2 &icu0 66 - 0x7800 0 0 3 &icu0 66 - >; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0x7>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpios 21 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power2: power2 { - label = "power2"; - gpios = <&gpios 20 GPIO_ACTIVE_HIGH>; - }; - lan1 { - label = "lan1"; - gpios = <&gpios 19 GPIO_ACTIVE_HIGH>; - }; - lan2 { - label = "lan2"; - gpios = <&gpios 18 GPIO_ACTIVE_HIGH>; - }; - lan3 { - label = "lan3"; - gpios = <&gpios 17 GPIO_ACTIVE_HIGH>; - }; - lan4 { - label = "lan4"; - gpios = <&gpios 16 GPIO_ACTIVE_HIGH>; - }; - wifi: wifi { - label = "wifi"; - gpios = <&gpios 15 GPIO_ACTIVE_HIGH>; - }; - adsl: adsl { - label = "adsl"; - gpios = <&gpios 14 GPIO_ACTIVE_HIGH>; - }; - internet: internet { - label = "internet"; - gpios = <&gpios 13 GPIO_ACTIVE_HIGH>; - }; - internet2 { - label = "internet2"; - gpios = <&gpios 12 GPIO_ACTIVE_HIGH>; - }; - voip { - label = "voip"; - gpios = <&gpios 11 GPIO_ACTIVE_HIGH>; - }; - phone { - label = "phone"; - gpios = <&gpios 10 GPIO_ACTIVE_HIGH>; - }; - phone2 { - label = "phone2"; - gpios = <&gpios 9 GPIO_ACTIVE_HIGH>; - }; - usb: usb { - label = "usb"; - gpios = <&gpios 8 GPIO_ACTIVE_HIGH>; - }; - usb2: usb2 { - label = "usb2"; - gpios = <&gpios 7 GPIO_ACTIVE_HIGH>; - }; - usb3 { - label = "usb3"; - gpios = <&gpios 6 GPIO_ACTIVE_HIGH>; - }; - unlabeled { - label = "unlabeled"; - gpios = <&gpios 5 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01.dts deleted file mode 100644 index 34f868f48..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "ARV4518PWR01.dtsi" - -/ { - compatible = "arcadyan,arv4518pwr01", "lantiq,xway", "lantiq,danube"; - model = "SMC7908A-ISP"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01.dtsi deleted file mode 100644 index 8e712bfec..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -#include "danube.dtsi" - -#include - -/ { - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - - led-dsl = &dsl; - led-internet = &online; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; /* 64 KB */ - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; /* 64 KB */ - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@400000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x0>; - }; - - ath5k_eep { - compatible = "ath5k,eeprom"; - ath,eep-flash = <&boardconfig 0x400>; - ath,mac-offset = <0x16>; - ath,mac-increment = <1>; - ath,eep-swap; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_in { - lantiq,groups = "req1", "req2"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1", "gnt2"; - lantiq,function = "pci"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - }; - - pci@E105400 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0xf>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - dsl: dsl { - label = "dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "online"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "wifi"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - dsl2 { - label = "dsl2"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "usb"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - voice { - label = "voice"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "fxs1"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "fxs2"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "fxo"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01A.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01A.dts deleted file mode 100644 index 771d0146d..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4518PWR01A.dts +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; - -#include "ARV4518PWR01.dtsi" - -/ { - compatible = "arcadyan,arv4518pwr01a", "lantiq,xway", "lantiq,danube"; - model = "SMC7908A-ISP, Airties WAV-221"; - - fpi@10000000 { - pci@E105400 { - lantiq,external-clock; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4519PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4519PW.dts deleted file mode 100644 index 8f781760f..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4519PW.dts +++ /dev/null @@ -1,195 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4519pw", "lantiq,xway", "lantiq,danube"; - model = "Vodafone Netfaster IAD 2, Pirelli P.RG A4201G"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &internet_green; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@3f0000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x400>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - }; - - pci@E105400 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0xf>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power { - label = "arv4519pw:green:power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "arv4519pw:red:power"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv4519pw:green:wlan"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "arv4519pw:green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet_green: online { - label = "arv4519pw:green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "arv4519pw:red:internet"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "arv4519pw:green:usb"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - voip { - label = "arv4519pw:green:voip"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "arv4519pw:green:phone1"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "arv4519pw:green:phone2"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "arv4519pw:green:line"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "arv4519pw:green:wps"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - wps { - label = "arv4519pw:orange:wps"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wps3 { - label = "arv4519pw:red:wps"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4520PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4520PW.dts deleted file mode 100644 index 05e0dfe04..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4520PW.dts +++ /dev/null @@ -1,221 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4520pw", "lantiq,xway", "lantiq,danube"; - model = "Easybox 800, WAV-281"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_blue; - led-failsafe = &power_red; - led-running = &power_blue; - - led-dsl = &dsl; - led-internet = &internet_blue; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH - &gpiomm 7 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "uboot_env"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "firmware"; - reg = <0x30000 0x3c0000>; - }; - - boardconfig: partition@7f0000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x400>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - }; - - etop@E180000 { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; - }; - - pci@E105400 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - -// gpiomm 10 - switch - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_blue: power { - label = "arv4520pw:blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "arv4520pw:blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet_blue: internet { - label = "arv4520pw:blue:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power2 { - label = "arv4520pw:red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wps { - label = "arv4520pw:yellow:wps"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "arv4520pw:red:wps"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - /* - wps green is missing - */ - fxs1 { - label = "arv4520pw:blue:telefon1"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "arv4520pw:blue:telefon2"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - isdn { - label = "arv4520pw:blue:isdn"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "arv4520pw:blue:line"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - voice { - label = "arv4520pw:blue:sprache"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "arv4520pw:blue:usb"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv4520pw:blue:wifi"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "arv4520pw:red:internet"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - /* - info is missing - */ - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4525PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4525PW.dts deleted file mode 100644 index 61548c793..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV4525PW.dts +++ /dev/null @@ -1,169 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv4525pw", "lantiq,xway", "lantiq,danube"; - model = "Speedport W501V Typ A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - /* we dont have a power led, lets use the online led */ - led-boot = &online; - led-failsafe = &online; - - led-dsl = &dsl; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@400000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - ath5k_eep { - compatible = "ath5k,eeprom"; - ath,eep-flash = <&boardconfig 0x400>; - ath,mac-offset = <0x0>; - ath,eep-swap; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - relay { - lantiq,pins = "io31"; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - pci@E105400 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - -/* -#define ARV4525PW_PHYRESET 13 -#define ARV4525PW_RELAY 31 -*/ - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - fxo { - label = "arv4525pw:green:festnetz"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - fxs { - label = "arv4525pw:green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "arv4525pw:green:t-dsl"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv4525pw:green:wlan"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "arv4525pw:green:online"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV452CQW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV452CQW.dts deleted file mode 100644 index d996e8b66..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV452CQW.dts +++ /dev/null @@ -1,237 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv452cqw", "lantiq,xway", "lantiq,danube"; - model = "Arcor 801"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_blue; - led-failsafe = &power_red; - led-running = &power_blue; - - led-dsl = &dsl_blue; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH - &gpiomm 7 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@3f0000 { - label = "boardconfig"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - - ath5k_eep { - compatible = "ath5k,eeprom"; - ath,eep-flash = <&boardconfig 0x400>; - ath,mac-offset = <0x0>; - ath,eep-swap; - }; - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10>; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x77f>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io3", "io5", "io6", "io7", "io9"; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; - }; - - etop@E180000 { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - pci@E105400 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - -/* -#define ARV452CPW_SWITCH_RESET 110 -*/ - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power_blue: power0 { - label = "arv452cqw:blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl_blue: dsl { - label = "arv452cqw:blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - isdn { - label = "arv452cqw:blue:isdn"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power1 { - label = "arv452cqw:red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wps { - label = "arv452cqw:blue:wps"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wps1 { - label = "arv452cqw:yellow:wps"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "arv452cqw:blue:telefon1"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "arv452cqw:blue:telefon2"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "arv452cqw:red:wps"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "arv452cqw:blue:line"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - voice { - label = "arv452cqw:blue:sprache"; - gpios = <&gpiomm 4 1>; - }; - usb: usb { - label = "arv452cqw:blue:usb"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv452cqw:blue:wlan"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - /* - internet blue and internet red are missing - dsl2 and dsl3 are not referenced in manual - */ - dsl2 { - label = "arv452cqw:yellow:dsl"; - gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; - }; - dsl3 { - label = "arv452cqw:red:dsl"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7506PW11.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7506PW11.dts deleted file mode 100644 index 3ec4bf41a..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7506PW11.dts +++ /dev/null @@ -1,165 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7506pw11", "lantiq,xway", "lantiq,danube"; - model = "Alice/O2 IAD 4421"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power_red; - led-running = &power; - - led-dsl = &dsl; - led-internet = &internet; - led-wifi = &wlan; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x10000>; - read-only; - }; - - partition@50000 { - label = "firmware"; - reg = <0x50000 0x7a0000>; - }; - - boardconfig: partition@7f0000 { - label = "board_config"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - }; - - /* GPIO 19: switch reset */ - etop@E180000 { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - wlan: wlan { - label = "arv7506pw11:green:wlan"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - power: power { - label = "arv7506pw11:green:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "arv7506pw11:green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet: internet { - label = "arv7506pw11:green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power_red { - label = "arv7506pw11:red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - internet_red { - label = "arv7506pw11:red:internet"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - info { - label = "arv7506pw11:green:info"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - telefon { - label = "arv7506pw11:green:telefon"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - info_red { - label = "arv7506pw11:red:info"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7510PW22.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7510PW22.dts deleted file mode 100644 index dc3f614b9..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7510PW22.dts +++ /dev/null @@ -1,196 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7510pw22", "lantiq,xway", "lantiq,danube"; - model = "Astoria Networks ARV7510PW22"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - - led-dsl = &internet; - led-usb = &umts; - led-wifi = &wlan; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xf80000>; - }; - - boardconfig: partition@fe0000 { - label = "board_config"; - reg = <0xfe0000 0x20000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_in { - lantiq,groups = "req1", "req2"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - pins_out { - lantiq,pins = "io2", "io4", "io8", "io9", "io10", "io15", "io20"; - lantiq,output = <1>; - }; - pins_in { - lantiq,pins = "io11", "io12", "io28"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; - - etop@E180000 { - /* Switch reset 19 */ - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - internet: internet { - label = "internet"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - wlan: wlan { - label = "wlan"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - umts: 3g { - label = "3g"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - message { - label = "message"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - lantiq,external-clock; - interrupt-map = < - 0x7000 0 0 1 &icu0 30 - 0x7800 0 0 1 &icu0 135 - 0x7800 0 0 2 &icu0 135 - 0x7800 0 0 3 &icu0 135 - >; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0x3>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7518PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7518PW.dts deleted file mode 100644 index 41b124932..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7518PW.dts +++ /dev/null @@ -1,232 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7518pw", "lantiq,xway", "lantiq,danube"; - model = "Astoria Networks ARV7518PW"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &online_green; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7d0000>; - }; - - boardconfig: partition@400000 { - label = "boardconfig"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x0>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io2", "io4", "io5", "io6", "io7", "io8", "io19"; - lantiq,output = <1>; - }; - keys { - lantiq,pins = "io28", "io30"; - lantiq,output = <0>; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - }; - }; - -/* -#define SWITCH_RESET 13 -*/ - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power_green: power { - label = "arv7518pw:green:power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - dsl: dsl { - label = "arv7518pw:green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - online_green: online { - label = "arv7518pw:green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv7518pw:green:wlan"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - power_red: power2 { - label = "arv7518pw:red:power"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "arv7518pw:red:internet"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "arv7518pw:green:usb"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - voice { - label = "arv7518pw:green:voip"; - gpios = <&gpiomm 0 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "arv7518pw:green:phone1"; - gpios = <&gpiomm 1 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "arv7518pw:green:phone2"; - gpios = <&gpiomm 2 GPIO_ACTIVE_LOW>; - }; - unlabeled { - label = "arv7518pw:amber:unlabeled"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wps { - label = "arv7518pw:amber:wps"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "arv7518pw:green:wps"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - wps3 { - label = "arv7518pw:red:wps"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - lantiq,external-clock; - req-mask = <0xf>; - - wifi@168c,0029 { - compatible = "pci168c,0029"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7519PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7519PW.dts deleted file mode 100644 index 9983a7906..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7519PW.dts +++ /dev/null @@ -1,229 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7519pw", "lantiq,xway", "lantiq,danube"; - model = "Astoria Networks ARV7519PW"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power2; - led-running = &power; - - led-dsl = &dsl; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x20000>; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xf80000>; - }; - - boardconfig: partition@fe0000 { - label = "board_config"; - reg = <0xfe0000 0x20000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - switch_rst { - lantiq,pins = "io19"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - - /* warning: passive port - only works with active devices */ - ifxhcd@E101000 { - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power: power { - label = "power"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power2: power2 { - label = "power2"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "online"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "online2"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "wifi"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "wifi2"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - wifi3 { - label = "wifi3"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - voice { - label = "voice"; - gpios = <&gpio 31 GPIO_ACTIVE_LOW>; - }; - wps { - label = "wps"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - wps2 { - label = "wps2"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - }; - wps3 { - label = "wps3"; - gpios = <&gpio 23 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - lan { - label = "lan"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - tv { - label = "tv"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - upgrade { - label = "upgrade"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; - - /* is there another way to "reserve" the GPIO? */ - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pci0 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0xf>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7519RW22.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7519RW22.dts deleted file mode 100644 index 0bdc150a1..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7519RW22.dts +++ /dev/null @@ -1,231 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7519rw22", "lantiq,xway", "lantiq,vr9"; - model = "Orange Livebox 2.1"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_green; - led-running = &power_green; - - led-dsl = &internet_green; - }; - - memory@0 { - reg = <0x0 0x8000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x60000>; - read-only; - }; - - partition@60000 { - label = "uboot-env"; - reg = <0x60000 0x20000>; - read-only; - }; - - partition@80000 { - label = "firmware"; - reg = <0x80000 0x1f00000>; - }; - - boardconfig: partition@1f80000 { - label = "boardconfig"; - reg = <0x1f80000 0x80000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - pcie-rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; - }; - - ifxhcd@E106000 { - status = "okay"; - gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; - }; - - pcie@d900000 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy22f_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy22f_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 33 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - lan_green { - label = "arv7519rw22:green:lan"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - internet_red { - label = "arv7519rw22:red:internet"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - power_green: power_green { - label = "arv7519rw22:green:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - alarm_blue { - label = "arv7519rw22:blue:alarm"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - internet_orange { - label = "arv7519rw22:orange:internet"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - internet_green: internet_green { - label = "arv7519rw22:green:internet"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - }; - voice_green { - label = "arv7519rw22:green:voice"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&boardconfig 0x16>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy12>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy12: ethernet-phy@12 { - reg = <0x12>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7525PW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7525PW.dts deleted file mode 100644 index 000753589..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV7525PW.dts +++ /dev/null @@ -1,155 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv7525pw", "lantiq,xway", "lantiq,danube"; - model = "Speedport W303V Typ A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &power_green; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - boardconfig: partition@400000 { - label = "board_config"; - reg = <0x3f0000 0x10000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power_green: power { - label = "arv7525pw:green:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power1 { - label = "arv7525pw:red:power"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "arv7525pw:green:online"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - voice { - label = "arv7525pw:green:telefonie"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - voice2 { - label = "arv7525pw:red:telefonie"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv7525pw:green:wlan"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - interrupt-map = <0x7000 0 0 1 &icu0 135 1>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV752DPW.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV752DPW.dts deleted file mode 100644 index 3591b4367..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV752DPW.dts +++ /dev/null @@ -1,238 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv752dpw", "lantiq,xway", "lantiq,danube"; - model = "Arcor 802"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_red; - led-failsafe = &power_blue; - led-running = &power_red; - - led-dsl = &internet_red; - led-usb = &umts; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7d0000>; - }; - - boardconfig: partition@7f0000 { - label = "board_config"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x3>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_in { - lantiq,groups = "req2", "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io3", "io5", "io6", "io8"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - keys { - lantiq,pins = "io11", "io12", "io13", "io28"; - lantiq,output = <0>; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpiomm 0 GPIO_ACTIVE_HIGH>; - }; - - etop@E180000 { - phy-mode = "rmii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dsl { - label = "dsl"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power_blue: power1 { - label = "arv752dpw:blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - internet_red: internet { - label = "arv752dpw:red:internet"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - message { - label = "arv752dpw:red:message"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power { - label = "arv752dpw:red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice1 { - label = "arv752dpw:red:voice"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - umts: umts { - label = "arv752dpw:red:umts"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv752dpw:red:wifi"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "arv752dpw:green:tae-n"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "arv752dpw:green:tae-u"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "arv752dpw:green:isdn"; - gpios = <&gpiomm 7 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "arv752dpw:blue:internet"; - gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; - }; - voice2 { - label = "arv752dpw:blue:voice"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - lantiq,external-clock; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - interrupt-map = <0x7000 0 0 1 &icu0 135>; - req-mask = <0x3>; - - wifi@1814,0601 { - compatible = "pci1814,0601"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV752DPW22.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV752DPW22.dts deleted file mode 100644 index 8b5be8b76..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV752DPW22.dts +++ /dev/null @@ -1,259 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv752dpw22", "lantiq,xway", "lantiq,danube"; - model = "Arcor 803"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_red; - led-failsafe = &power_blue; - led-running = &power_red; - - led-dsl = &internet_red; - led-usb = &umts; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x30000>; - read-only; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x30000 0x10000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x40000 0x7b0000>; - }; - - boardconfig: partition@7f0000 { - label = "board_config"; - reg = <0x7f0000 0x10000>; - read-only; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <3>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ebu { - lantiq,groups = "ebu cs1"; - lantiq,function = "ebu"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; - leds { - lantiq,pins = "io3", "io5", "io6", "io8"; - lantiq,open-drain = <1>; - lantiq,output = <1>; - }; - buttons { - lantiq,pins = "io11", "io12", "io13", "io28"; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpiomm 0 GPIO_ACTIVE_HIGH>; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&boardconfig 0x16>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dsl { - label = "dsl"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power_blue: power1 { - label = "arv752dpw22:blue:power"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - internet_red: internet { - label = "arv752dpw22:red:internet"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - message { - label = "arv752dpw22:red:message"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - power_red: power { - label = "arv752dpw22:red:power"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice1 { - label = "arv752dpw22:red:voice"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - umts: umts { - label = "arv752dpw22:red:umts"; - gpios = <&gpiomm 3 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "arv752dpw22:red:wifi"; - gpios = <&gpiomm 4 GPIO_ACTIVE_LOW>; - }; - fxs1 { - label = "arv752dpw22:green:tae-n"; - gpios = <&gpiomm 5 GPIO_ACTIVE_LOW>; - }; - fxs2 { - label = "arv752dpw22:green:tae-u"; - gpios = <&gpiomm 6 GPIO_ACTIVE_LOW>; - }; - fxo { - label = "arv752dpw22:green:isdn"; - gpios = <&gpiomm 7 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "arv752dpw22:blue:internet"; - gpios = <&gpiomm 8 GPIO_ACTIVE_LOW>; - }; - voice2 { - label = "arv752dpw22:blue:voice"; - gpios = <&gpiomm 9 GPIO_ACTIVE_LOW>; - }; - eth1 { - label = "arv752dpw22:green:lan1"; - gpios = <&gpiomm 11 GPIO_ACTIVE_LOW>; - }; - eth2 { - label = "arv752dpw22:green:lan2"; - gpios = <&gpiomm 12 GPIO_ACTIVE_LOW>; - }; - eth3 { - label = "arv752dpw22:green:lan3"; - gpios = <&gpiomm 13 GPIO_ACTIVE_LOW>; - }; - eth4 { - label = "arv752dpw22:green:lan4"; - gpios = <&gpiomm 14 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - lantiq,external-clock; - interrupt-map = < - 0x7000 0 0 1 &icu0 30 - 0x7800 0 0 1 &icu0 135 - 0x7800 0 0 2 &icu0 135 - 0x7800 0 0 3 &icu0 135 - >; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - req-mask = <0x3>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV8539PW22.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV8539PW22.dts deleted file mode 100644 index 4edcde976..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ARV8539PW22.dts +++ /dev/null @@ -1,180 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "arcadyan,arv8539pw22", "lantiq,xway", "lantiq,danube"; - model = "Speedport W 504V Typ A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl_green; - led-internet = &online_green; - led-wifi = &wireless_green; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x30000>; /* 192 KiB */ - read-only; - }; - - partition@30000 { - label = "uboot"; - reg = <0x30000 0x10000>; /* 64 KiB */ - read-only; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x7B0000>; /* 7872 KiB */ - }; - - art: partition@7F0000 { - label = "art"; - reg = <0x7F0000 0x10000>; /* 64 KiB*/ - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - lantiq,output = <0>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - relay { - lantiq,pins = "io31"; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&art 0x16>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wlan { - label = "wlan"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - /* key DECT is missing */ - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power-green { - label = "arv8539pw22:green:power"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power-red { - label = "arv8539pw22:red:power"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - - dsl_green: dsl-green { - label = "arv8539pw22:green:dsl"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - - online_green: online-green { - label = "arv8539pw22:green:online"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - wireless_green: wireless-green { - label = "arv8539pw22:green:wlan"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - /* - telefonie green is missing - */ - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,0029 { - compatible = "pci168c,0029"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - mtd-mac-address = <&art 0x16>; - mtd-mac-address-increment = <1>; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ASL56026.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ASL56026.dts deleted file mode 100644 index 2037f40f0..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ASL56026.dts +++ /dev/null @@ -1,171 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "alphanetworks,asl56026", "lantiq,xway", "lantiq,vr9"; - model = "BT OpenReach VDSL Modem"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x0800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - }; - - partition@30000 { - label = "uboot_env"; - reg = <0x30000 0x10000>; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x750000>; - }; - - partition@790000 { - label = "ddrconfig"; - reg = <0x790000 0x70000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy22f_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy22f_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 40 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - dsl: dsl { - label = "asl56026:green:dsl"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - /* power-* is a bicolour led */ - power_green: power_green { - label = "asl56026:green:power"; - gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - - power_red: power_red { - label = "asl56026:red:power"; - gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - power_led_blink { - gpio-export,name = "power_led_blink"; - gpio-export,output = <0>; - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV2B.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV2B.dts deleted file mode 100644 index 961fd9b92..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV2B.dts +++ /dev/null @@ -1,262 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "bt,homehub-v2b", "lantiq,xway", "lantiq,danube"; - model = "BT Home Hub 2B"; /* SoC: Lantiq Danube-S PSB 50712 @ 333MHz V1.3/1.5 */ - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_orange; - led-failsafe = &power_red; - led-running = &power_blue; - - led-dsl = &broadband_blue; - led-wifi = &wireless_blue; - }; - - memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { /* NOR Flash: Spansion S29AL004D 512KB */ - compatible = "lantiq,nor"; /* "AMD AM29LV400BB" compatible on 3.3.8 */ - lantiq,cs = <0>; - bank-width = <2>; - reg = <0 0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; /* 256KB */ - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x10000>; /* 64KB */ - }; - - partition@50000 { - label = "rg_conf_1"; - reg = <0x50000 0x10000>; - }; - - partition@60000 { - label = "rg_conf_2"; - reg = <0x60000 0x10000>; - }; - - partition@70000 { - label = "rg_conf_factory"; - reg = <0x70000 0x10000>; - }; - }; - }; - - nand-parts@0 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <1 0x0 0x2000000 >; - #address-cells = <1>; - #size-cells = <1>; - req-mask = <0x1>; /* PCI request lines to mask during NAND access */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ath9k_cal: partition@0 { - label = "art"; /* Atheros 9160 wifi b/g/n radio EEPROM */ - reg = <0x00000 0x4000>; - read-only; - }; - - partition@4000 { - label = "kernel"; - reg = <0x4000 0x200000>; - }; - - partition@164000 { - label = "ubi"; - reg = <0x204000 0x1DFC000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - }; - - btn_in { - lantiq,pins = "io2", "io15", "io22"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - }; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - - ifxhcd@E101000 { - status = "okay"; - }; - - gpios: stp@E100BB0 { - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - findhandset { - label = "findhandset"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - upgrading-orange { - label = "bthomehubv2b:orange:upgrading"; - gpios = <&gpios 5 GPIO_ACTIVE_HIGH>; - }; - - phone-orange { - label = "bthomehubv2b:orange:phone"; - gpios = <&gpios 6 GPIO_ACTIVE_HIGH>; - }; - phone-blue { - label = "bthomehubv2b:blue:phone"; - gpios = <&gpios 7 GPIO_ACTIVE_HIGH>; - }; - - wireless-orange { - label = "bthomehubv2b:orange:wireless"; - gpios = <&gpios 8 GPIO_ACTIVE_HIGH>; - }; - wireless_blue: wireless-blue { - label = "bthomehubv2b:blue:wireless"; - gpios = <&gpios 9 GPIO_ACTIVE_HIGH>; - }; - - broadband-red { - label = "bthomehubv2b:red:broadband"; - gpios = <&gpios 10 GPIO_ACTIVE_HIGH>; - }; - broadband-orange { - label = "bthomehubv2b:orange:broadband"; - gpios = <&gpios 11 GPIO_ACTIVE_HIGH>; - }; - broadband_blue: broadband-blue { - label = "bthomehubv2b:blue:broadband"; - gpios = <&gpios 12 GPIO_ACTIVE_HIGH>; - }; - - power_red: power-red { - label = "bthomehubv2b:red:power"; - gpios = <&gpios 13 GPIO_ACTIVE_HIGH>; - }; - power_orange: power-orange { - label = "bthomehubv2b:orange:power"; - gpios = <&gpios 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - power_blue: power-blue { - label = "bthomehubv2b:blue:power"; - gpios = <&gpios 15 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,0027 { - compatible = "pci168c,0027"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV3A.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV3A.dts deleted file mode 100644 index d37b9728d..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV3A.dts +++ /dev/null @@ -1,208 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "bt,homehub-v3a", "lantiq,xway", "lantiq,ar9"; - model = "BT Home Hub 3A"; /* SoC: Lantiq ar9 @ 333MHz */ - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_orange; - led-failsafe = &power_red; - led-running = &power_blue; - - led-dsl = &broadband_blue; - led-wifi = &wireless_blue; - }; - - memory@0 { /* RAM: Samsung K4H511638F-LC 64MB */ - reg = <0x0 0x4000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 31 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nand-parts@0 { /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */ - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <1 0x0 0x2000000 >; - #address-cells = <1>; - #size-cells = <1>; - req-mask = <0x1>; /* PCI request lines to mask during NAND access */ - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "preboot"; - reg = <0x00000 0x8000>; - read-only; - }; - partition@8000 { - label = "u-boot"; - reg = <0x8000 0x05c000>; - read-only; - }; - partition@64000 { - label = "uboot_env"; - reg = <0x64000 0x004000>; - }; - ath9k_cal: partition@68000 { - label = "art-copy"; - reg = <0x68000 0x004000>; - }; - partition@6c000 { - label = "kernel"; - reg = <0x6c000 0x200000>; - }; - partition@26c000 { - label = "ubi"; - reg = <0x26c000 0x1d94000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - - pci_in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci_out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - }; - }; - }; - - etop@E180000 { - phy-mode = "rgmii"; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - restart { - label = "restart"; - gpios = <&gpio 52 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - wireless-red { - label = "bthomehubv3a:red:wireless"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - wireless-orange { - label = "bthomehubv3a:orange:wireless"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - wireless_blue: wireless-blue { - label = "bthomehubv3a:blue:wireless"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - - broadband-red { - label = "bthomehubv3a:red:broadband"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - }; - broadband-orange { - label = "bthomehubv3a:orange:broadband"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - }; - broadband_blue: broadband-blue { - label = "bthomehubv3a:blue:broadband"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - - power_red: power-red { - label = "bthomehubv3a:red:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - power_orange: power-orange { - label = "bthomehubv3a:orange:power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_blue: power-blue { - label = "bthomehubv3a:blue:power"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - ath9k@7000 { - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV5A.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV5A.dts deleted file mode 100644 index 2f7507469..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/BTHOMEHUBV5A.dts +++ /dev/null @@ -1,282 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "bt,homehub-v5a", "lantiq,xway", "lantiq,vr9"; - model = "BT Home Hub 5A"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_blue; - - led-dsl = &broadband_blue; - led-wifi = &wireless_blue; - }; - - memory@0 { - reg = <0x0 0x8000000>; - }; - - fpi@10000000 { - localbus@0 { - nand-parts@0 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <0x1 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - nand-on-flash-bbt; - nand-ecc-strength = <3>; - nand-ecc-step-size = <256>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0xa0000>; - read-only; - }; - partition@a0000 { - label = "uboot-env"; - reg = <0xa0000 0x20000>; - read-only; - }; - partition@c0000 { - label = "unused"; - reg = <0xc0000 0x40000>; - }; - partition@100000 { - label = "ubi"; - reg = <0x100000 0x7e80000>; - }; - /* - * last 512 KiB are for the bad block table, not writable - */ - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain; - }; - pcie_rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - lantiq,open-drain; - }; - usb_vbus { - lantiq,pins = "io33"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy11g_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy11g_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - restart { - label = "restart"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - /* broadband-* is a single RGB led */ - broadband-red { - label = "bthomehubv5a:red:broadband"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - }; - broadband-green { - label = "bthomehubv5a:green:broadband"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - }; - broadband_blue: broadband-blue { - label = "bthomehubv5a:blue:broadband"; - gpios = <&gpio 8 GPIO_ACTIVE_LOW>; - }; - - /* wireless-* is a single RGB led */ - wireless-red { - label = "bthomehubv5a:red:wireless"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - }; - wireless-green { - label = "bthomehubv5a:green:wireless"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - wireless_blue: wireless-blue { - label = "bthomehubv5a:blue:wireless"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - }; - - /* power-* is a single RGB led */ - power_red: power-red { - label = "bthomehubv5a:red:power"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - power_green: power-green { - label = "bthomehubv5a:green:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_blue: power-blue { - label = "bthomehubv5a:blue:power"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - - dimmed { - label = "dimmed"; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,002d { - compatible = "pci168c,002d"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - qca,disable-5ghz; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN1000B.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN1000B.dts deleted file mode 100644 index e5637efca..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN1000B.dts +++ /dev/null @@ -1,171 +0,0 @@ -/dts-v1/; - -#include "amazonse.dtsi" - -#include - -/ { - compatible = "netgear,dgn1000b", "lantiq,xway", "lantiq,ase"; - model = "Netgear DGN1000B"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - - led-dsl = &dsl; - led-internet = &online_green; - }; - - memory@0 { - reg = <0x0 0x1000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - asc { - lantiq,groups = "asc"; - lantiq,function = "asc"; - }; - keys_in { - lantiq,pins = "io0",/* "io25", */"io29"; - lantiq,pull = <2>; - lantiq,open-drain = <1>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs1"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mac-address = [ 00 11 22 33 44 55 ]; - }; - - spi@E100800 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <1 0>; - spi-max-frequency = <5000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "SPI (RO) U-Boot Image"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "ENV_MAC"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x10000>; - label = "DPF"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x10000>; - label = "NVRAM"; - read-only; - }; - - partition@500000 { - reg = <0x50000 0x003a0000>; - label = "kernel"; - }; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - dsl: dsl { - label = "dgn1000b:green:dsl"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - online_green: online { - label = "dgn1000b:green:online"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - online2 { - label = "dgn1000b:red:online"; - gpios = <&gpio 3 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - wps { - label = "dgn1000b:green:wps"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - power: power { - label = "dgn1000b:green:power"; - gpios = <&gpio 13 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - /* - power red is missing - */ - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500.dts deleted file mode 100644 index 98a2ebd98..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "DGN3500.dtsi" - -/ { - compatible = "netgear,dgn3500", "lantiq,xway", "lantiq,ar9"; - model = "Netgear DGN3500"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500.dtsi deleted file mode 100644 index d58d71753..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500.dtsi +++ /dev/null @@ -1,213 +0,0 @@ -#include "ar9.dtsi" - -#include - -/ { - chosen { - bootargs = "root= console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &internet; - led-usb = &usb; - led-wifi = &wifi_green; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; - pci-in { - lantiq,groups = "req1"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - }; - - ifxhcd@E101000 { - status = "okay"; - }; - }; - - rtl8366rb { - compatible = "realtek,rtl8366rb"; - gpio-sda = <&gpio 35 GPIO_ACTIVE_HIGH>; - gpio-sck = <&gpio 37 GPIO_ACTIVE_HIGH>; - - realtek,initvals = < - 0x0000 0x0830 - 0x0400 0x8130 - 0x000A 0x83ED - 0x0F51 0x0017 - 0x02F5 0x0048 - 0x02FA 0xFFDF - 0x02FB 0xFFE0 - 0x0450 0x0000 - 0x0401 0x0000 - 0x0431 0x0960 - >; - }; - - - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - internet: internet { - label = "dgn3500:green:internet"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - internet2 { - label = "dgn3500:red:internet"; - gpios = <&gpio 30 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "dgn3500:green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "dgn3500:green:usb"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; - power_green: power { - label = "dgn3500:green:power"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "dgn3500:red:power"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - }; - wifi_green: wifi { - label = "dgn3500:green:wireless"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "dgn3500:amber:wireless"; - gpios = <&gpio 51 GPIO_ACTIVE_LOW>; - }; - wps { - label = "dgn3500:green:wps"; - gpios = <&gpio 52 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@168c,0029 { - compatible = "pci168c,0029"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <20000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x10000>; - label = "uboot"; - read-only; - }; - - partition@10000 { - reg = <0x10000 0x10000>; - label = "uboot-env"; - read-only; - }; - - ath9k_cal: partition@20000 { - reg = <0x20000 0x10000>; - label = "calibration"; - read-only; - }; - - partition@50000 { - reg = <0x50000 0xfa0000>; - label = "firmware"; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500B.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500B.dts deleted file mode 100644 index d1d788cc7..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DGN3500B.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "DGN3500.dtsi" - -/ { - compatible = "netgear,dgn3500b", "lantiq,xway", "lantiq,ar9"; - model = "Netgear DGN3500B"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DM200.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DM200.dts deleted file mode 100644 index 3c8a2a1fa..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/DM200.dts +++ /dev/null @@ -1,215 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "netgear,dm200", "lantiq,xway", "lantiq,vr9"; - model = "Netgear DM200"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_amber; - led-running = &power_green; - - led-dsl = &dsl_green; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - pcie@d900000 { - status = "disabled"; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware = "lantiq/xrx200_phy22f_a22.bin"; - phys = [ 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - annexa { - gpio-export,name = "annexa"; - gpio-export,output = <0>; - gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; - }; - annexb { - gpio-export,name = "annexb"; - gpio-export,output = <0>; - gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_amber: power_amber { - label = "dm200:amber:power"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - }; - power_green: power_green { - label = "dm200:green:power"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; - - lan_amber { - label = "dm200:amber:lan"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - lan_green { - label = "dm200:green:lan"; - gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; - }; - - dsl_amber { - label = "dm200:amber:dsl"; - gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; - dsl_green: dsl_green { - label = "dm200:green:dsl"; - gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "uboot"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "gphyfirmware"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x7b0000>; - label = "firmware"; - }; - - partition@7e0000 { - reg = <0x7e0000 0x10000>; - label = "sysconfig"; - read-only; - }; - - partition@7f0000 { - reg = <0x7f0000 0x2000>; - label = "ubootconfig"; - read-only; - }; - - partition@7f2000 { - reg = <0x7f2000 0x1000>; - label = "ART"; - read-only; - }; - - partition@7f3000 { - reg = <0x7f3000 0x1000>; - label = "pot"; - read-only; - }; - - partition@7f4000 { - reg = <0x7f4000 0xc000>; - label = "ret"; - read-only; - }; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY50712.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY50712.dts deleted file mode 100644 index ebd30a7c0..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY50712.dts +++ /dev/null @@ -1,83 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -/ { - compatible = "lantiq,easy50712", "lantiq,xway", "lantiq,danube"; - model = "Intel EASY50712 Nand"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; /* 64 KB */ - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; /* 64 KB */ - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x400000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY50810.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY50810.dts deleted file mode 100644 index 605eb826a..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY50810.dts +++ /dev/null @@ -1,93 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -/ { - compatible = "lantiq,easy50810", "lantiq,xway", "lantiq,ar9"; - model = "Lantiq EASY50810"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; /* 64 KB */ - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; /* 64 KB */ - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x3d0000>; - }; - - partition@400000 { - label = "rootfs"; - reg = <0x400000 0x400000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; /* stp */ - lantiq,open-drain; - lantiq,pull = <0>; - }; - }; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - - stp0: stp@E100BB0 { - #gpio-cells = <2>; - compatible = "lantiq,gpio-stp-xway"; - gpio-controller; - reg = <0xE100BB0 0x40>; - - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920.dtsi deleted file mode 100644 index b19b9713f..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920.dtsi +++ /dev/null @@ -1,298 +0,0 @@ -#include "vr9.dtsi" - -#include - -/ { - compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - - led-usb = &usb1; - led-usb2 = &usb2; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin3 { - lantiq,groups = "exin3"; - lantiq,function = "exin"; - }; - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - nand { - lantiq,groups = "nand cle", "nand ale", - "nand rd", "nand rdy"; - lantiq,function = "ebu"; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - pci { - lantiq,groups = "gnt1", "req1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */ - "io4", "io5", "io6", /* stp */ - "io21", - "io33"; - lantiq,open-drain; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - conf_in { - lantiq,pins = "io39", /* exin3 */ - "io48"; /* nand rdy */ - lantiq,pull = <2>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - stp: stp@E100BB0 { - compatible = "lantiq,gpio-stp-xway"; - reg = <0xE100BB0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - lantiq,shadow = <0xffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x3>; - lantiq,phy1 = <0x7>; - lantiq,phy2 = <0x7>; - /* lantiq,rising; */ - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy11g_a14.bin"; - firmware2 = "lantiq/xrx200_phy11g_a22.bin"; - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; -/* reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - };*/ - paging { - label = "paging"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power: power { - label = "easy80920:green:power"; - gpios = <&stp 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - warning { - label = "easy80920:green:warning"; - gpios = <&stp 22 GPIO_ACTIVE_HIGH>; - }; - fxs1 { - label = "easy80920:green:fxs1"; - gpios = <&stp 21 GPIO_ACTIVE_HIGH>; - }; - fxs2 { - label = "easy80920:green:fxs2"; - gpios = <&stp 20 GPIO_ACTIVE_HIGH>; - }; - fxo { - label = "easy80920:green:fxo"; - gpios = <&stp 19 GPIO_ACTIVE_HIGH>; - }; - usb1: usb1 { - label = "easy80920:green:usb1"; - gpios = <&stp 18 GPIO_ACTIVE_HIGH>; - }; - usb2: usb2 { - label = "easy80920:green:usb2"; - gpios = <&stp 15 GPIO_ACTIVE_HIGH>; - }; - sd { - label = "easy80920:green:sd"; - gpios = <&stp 14 GPIO_ACTIVE_HIGH>; - }; - wps { - label = "easy80920:green:wps"; - gpios = <&stp 12 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <1000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "SPI (RO) U-Boot Image"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "ENV_MAC"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x10000>; - label = "DPF"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x10000>; - label = "NVRAM"; - read-only; - }; - - partition@500000 { - reg = <0x50000 0x003a0000>; - label = "kernel"; - }; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - }; - - wan: interface@1 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - lantiq,wan; - - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920NAND.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920NAND.dts deleted file mode 100644 index 095bd564d..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920NAND.dts +++ /dev/null @@ -1,68 +0,0 @@ -/dts-v1/; - - -#include "EASY80920.dtsi" - -/ { - compatible = "lantiq,easy80920-nand", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; - model = "Intel EASY80920 Nand"; - - chosen { - bootargs = "ubi.mtd=ubi ubi.block=0,rootfsA root=/dev/ubiblock0_1"; - }; - - fpi@10000000 { - localbus@0 { - ranges = <0 0 0x4000000 0x3ffffff>; - nand-parts@0 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x100000>; /* 1024 KB */ - }; - - partition@100000 { - label = "uboot_env"; - reg = <0x100000 0x40000>; /* 256 KB */ - }; - - partition@140000 { - label = "ubootconfigB"; - reg = <0x140000 0x40000>; /* 256 KB */ - }; - - partition@180000 { - label = "gphyfirmware"; - reg = <0x180000 0x40000>; /* 256 KB */ - }; - - partition@1c0000 { - label = "ubi"; - reg = <0x1c0000 0xc800000>; - }; - - partition@c9c0000 { - label = "calibration"; - reg = <0xc9c0000 0x100000>; - }; - - partition@cac0000 { - label = "res"; - reg = <0xcac0000 0x13540000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920NOR.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920NOR.dts deleted file mode 100644 index e273138d8..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY80920NOR.dts +++ /dev/null @@ -1,43 +0,0 @@ -/dts-v1/; - - -#include "EASY80920.dtsi" - -/ { - compatible = "lantiq,easy80920-nor", "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; - model = "Intel EASY80920 Nor"; - - fpi@10000000 { - localbus@0 { - ranges = <0 0 0x0 0x3ffffff>; - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x10000>; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x10000 0x10000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7e0000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY88388.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY88388.dts deleted file mode 100644 index a9c5b3c24..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY88388.dts +++ /dev/null @@ -1,106 +0,0 @@ -/dts-v1/; - -#include -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon FTTDP8 Reference Board"; - compatible = "lantiq,easy88388", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io34", "io35", "io36", "io37", "io38", - "io39", "io40", "io41"; - lantiq,function = "gpio"; - }; - }; - - easy88388-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "easy88388:green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - TEST { - label = "easy88388:green:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - STATUS { - label = "easy88388:green:status"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - ERROR { - label = "easy88388:red:error"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - DSL1 { - label = "easy88388:dsl:1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL2 { - label = "easy88388:dsl:2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL3 { - label = "easy88388:dsl:3"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL4 { - label = "easy88388:dsl:4"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL5 { - label = "easy88388:dsl:5"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL6 { - label = "easy88388:dsl:6"; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL7 { - label = "easy88388:dsl:7"; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - DSL8 { - label = "easy88388:dsl:8"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; -}; - diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY88444.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY88444.dts deleted file mode 100644 index ceb81ea13..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY88444.dts +++ /dev/null @@ -1,80 +0,0 @@ -/dts-v1/; - -#include -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon FTTdp G.FAST Reference Board"; - compatible = "lantiq,easy88444", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io34", "io35", "io37"; - lantiq,function = "gpio"; - }; - }; - - easy88444-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "easy88444:green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - TEST { - label = "easy88444:green:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - STATUS { - label = "easy88444:green:status"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - GFAST1 { - label = "easy88444:gfast:1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - GFAST2 { - label = "easy88444:gfast:2"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - GFAST3 { - label = "easy88444:gfast:3"; - gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - GFAST4 { - label = "easy88444:gfast:4"; - gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - }; -}; - diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000-base.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000-base.dtsi deleted file mode 100644 index cfe1140ac..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000-base.dtsi +++ /dev/null @@ -1,110 +0,0 @@ - -#include -#include - -/ { - compatible = "lantiq,easy98000", "lantiq,falcon"; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; - }; - - easy98000-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&bootled_pins>; - - LED_0 { - label = "easy98000:green:gpon"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_1 { - label = "easy98000:red:gpon"; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_2 { - label = "easy98000:green:gpon_tx"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_3 { - label = "easy98000:green:gpon_rx"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_4 { - label = "easy98000:green:voice"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_5 { - label = "easy98000:green:status"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - -&ebu_cs1 { - eth0: ethernet@0000000 { - compatible = "davicom,dm9000"; - device_type = "network"; - reg = <0x0000003 0x1>, <0x0000001 0x1>; - reg-names = "addr", "data"; - interrupt-parent = <&gpio1>; - #interrupt-cells = <2>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - - cpld@3c00000 { - compatible = "lantiq,easy98000_addon"; - reg = <0x3c00000 0x2>; - }; - - cpld@3c0000c { - compatible = "lantiq,easy98000_cpld_led"; - reg = <0x3c0000c 0x2>, <0x3c00012 0x2>; - }; -}; - -/* // enable this for second uart: -&serial1 { - status = "okay"; -};*/ - -&spi { - status = "okay"; - - eeprom@1 { - compatible = "atmel,at25", "atmel,at25160n"; - reg = <2>; - spi-max-frequency = <1000000>; - spi-cpha; - spi-cpol; - - pagesize = <32>; - size = <2048>; - address-width = <16>; - }; -}; - -&i2c { - status = "okay"; - - clock-frequency = <100000>; - - /* eeprom-emulation by OMU */ - eeprom@50 { - compatible = "at,24c02"; - reg = <0x50>; - }; - eeprom@51 { - compatible = "at,24c02"; - reg = <0x51>; - }; -}; - diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000NAND.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000NAND.dts deleted file mode 100644 index a40cef393..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000NAND.dts +++ /dev/null @@ -1,40 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "EASY98000-base.dtsi" - -/ { - model = "Lantiq Falcon (NAND)"; - compatible = "lantiq,easy98000-nand", "lantiq,easy98000", "lantiq,falcon"; - - aliases { - spi0 = &spi; - }; -}; - -&ebu_cs0 { - gen_nand@0 { - compatible = "gen_nand", "lantiq,nand-falcon"; - bank-width = <1>; - reg = <0x0 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - linux,mtd-name = "gen_nand"; - bbt-use-flash; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x40000 0x40000>; - }; - - partition@20000 { - label = "linux"; - reg = <0x80000 0x3d0000>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000NOR.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000NOR.dts deleted file mode 100644 index ad53bf96e..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000NOR.dts +++ /dev/null @@ -1,38 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "EASY98000-base.dtsi" - -/ { - model = "Lantiq Falcon (NOR)"; - compatible = "lantiq,easy98000-nor", "lantiq,easy98000", "lantiq,falcon"; - - aliases { - spi0 = &spi; - }; -}; - -&ebu_cs0 { - cfi@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0x0 0x4000000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x40000 0x40000>; - }; - - partition@20000 { - label = "linux"; - reg = <0x80000 0x3d0000>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000SFLASH.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000SFLASH.dts deleted file mode 100644 index bbe524e94..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98000SFLASH.dts +++ /dev/null @@ -1,16 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "EASY98000-base.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon (SFLASH)"; - compatible = "lantiq,easy98000-sflash", "lantiq,easy98000", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - spi1 = &spi; - }; -}; - diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98020.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98020.dts deleted file mode 100644 index c0970ef48..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98020.dts +++ /dev/null @@ -1,95 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon Reference Board"; - compatible = "lantiq,easy98020", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: phy-led-pins { - lantiq,pins = "io42", "io41", "io38", "io37"; - lantiq,function = "gpio"; - }; - }; - - easy98020-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&bootled_pins>; - - GPON { - label = "easy98020:green:gpon"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - TEST { - label = "easy98020:green:test"; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - ETH { - label = "easy98020:green:status"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VOICE { - label = "easy98020:green:voice"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VIDEO { - label = "easy98020:green:video"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; - - easy98020-phy-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - GE0_ACT { - label = "easy98020:ge0_act"; - gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - GE0_LINK { - label = "easy98020:ge0_link"; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - GE1_ACT { - label = "easy98020:ge1_act"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - GE1_LINK { - label = "easy98020:ge1_link"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98020V18.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98020V18.dts deleted file mode 100644 index 9aa1be91e..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98020V18.dts +++ /dev/null @@ -1,68 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon Reference Board V1.8"; - compatible = "lantiq,easy98020-v18", "lantiq,easy98020", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io11", "io14", "io36", "io37", "io38"; - lantiq,function = "gpio"; - }; - }; - - easy98020-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "easy98020:green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - TEST { - label = "easy98020:green:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - ETH { - label = "easy98020:green:status"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VOICE { - label = "easy98020:green:voice"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VIDEO { - label = "easy98020:green:video"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98021.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98021.dts deleted file mode 100644 index 7b2e490fc..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98021.dts +++ /dev/null @@ -1,81 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon HGU Reference Board"; - compatible = "lantiq,easy98021", "lantiq,easy98020", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - gpio-keys { - compatible = "gpio-keys"; - reset { - label = "reset"; - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - linux,code = <0x198>; - }; - }; - - gpio-mmc { - /* Place-holder for SIM-Card connector, - to list the used GPIOs, no official binding */ - compatible = "gpio-mmc"; - gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>, - <&gpio0 3 GPIO_ACTIVE_HIGH>, - <&gpio0 2 GPIO_ACTIVE_HIGH>, - <0>; /* no CS */ - gpio-names = "di", "do", "clk", "cs"; - reset-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; - }; - - pinctrl { - led_pins: led-pins { - lantiq,pins = "io11", "io14", "io36", "io37", "io38"; - lantiq,function = "gpio"; - }; - }; - - easy98021-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins &bootled_pins>; - - GPON { - label = "easy98021:green:gpon"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - TEST { - label = "easy98021:red:test"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - ETH { - label = "easy98021:green:status"; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - VOICE { - label = "easy98021:green:voice"; - gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - SIMCARD { - label = "easy98021:green:simcard"; - gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98035SYNCE.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98035SYNCE.dts deleted file mode 100644 index df941cdb6..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98035SYNCE.dts +++ /dev/null @@ -1,76 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon SFP Stick with SyncE"; - compatible = "lantiq,easy98035synce", "lantiq,falcon-sfp", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - - asc0_func1: func1 { - func1_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func1_rx { - lantiq,pins = "io33"; - lantiq,mux = <0>; - }; - }; - asc0_func2: func2 { - func2_tx { - lantiq,pins = "io32"; - lantiq,mux = <0>; - }; - func2_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - asc0_func3: func3 { - func3_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func3_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - }; - - pinselect-asc0 { - compatible = "lantiq,pinselect-asc0"; - pinctrl-names = "asc0", "func1", "func2", "func3"; - pinctrl-0 = <&asc0_pins>; - pinctrl-1 = <&asc0_func1>; - pinctrl-2 = <&asc0_func2>; - pinctrl-3 = <&asc0_func3>; - }; -}; - -&serial0 { - pinctrl-names = "default"; - /* use "empty" pinctrl to leave setting from u-boot enabled */ - pinctrl-0 = < >; -}; - -&i2c { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98035SYNCE1588.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98035SYNCE1588.dts deleted file mode 100644 index a3abc6e70..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/EASY98035SYNCE1588.dts +++ /dev/null @@ -1,76 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon SFP Stick with SyncE/1588"; - compatible = "lantiq,easy98035synce1588", "lantiq,falcon-sfp", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - - asc0_func1: func1 { - func1_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func1_rx { - lantiq,pins = "io33"; - lantiq,mux = <0>; - }; - }; - asc0_func2: func2 { - func2_tx { - lantiq,pins = "io32"; - lantiq,mux = <0>; - }; - func2_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - asc0_func3: func3 { - func3_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - func3_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - }; - - pinselect-asc0 { - compatible = "lantiq,pinselect-asc0"; - pinctrl-names = "asc0", "func1", "func2", "func3"; - pinctrl-0 = <&asc0_pins>; - pinctrl-1 = <&asc0_func1>; - pinctrl-2 = <&asc0_func2>; - pinctrl-3 = <&asc0_func3>; - }; -}; - -&serial0 { - pinctrl-names = "default"; - /* use "empty" pinctrl to leave setting from u-boot enabled */ - pinctrl-0 = < >; -}; - -&i2c { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FALCON-MDU.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FALCON-MDU.dts deleted file mode 100644 index 6710bbe98..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FALCON-MDU.dts +++ /dev/null @@ -1,53 +0,0 @@ -/dts-v1/; - -#include - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon / Vinax MDU Board"; - compatible = "lantiq,falcon-mdu", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - mdu-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&bootled_pins>; - - LED_0 { - label = "mdu:green:gpon"; - gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_1 { - label = "mdu:green:status"; - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_2 { - label = "mdu:green:2"; - gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_3 { - label = "mdu:green:3"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - LED_4 { - label = "mdu:green:4"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - }; - }; -}; - diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FALCON-SFP.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FALCON-SFP.dts deleted file mode 100644 index 8d45de4eb..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FALCON-SFP.dts +++ /dev/null @@ -1,76 +0,0 @@ -/dts-v1/; - -#include "falcon.dtsi" -#include "falcon-sflash-16M.dtsi" - -/ { - model = "Lantiq Falcon SFP Stick"; - compatible = "lantiq,falcon-sfp", "lantiq,falcon"; - - aliases { - spi0 = &ebu_cs0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x4000000>; // 64M at 0x0 - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - - asc0_func1: func1 { - func1_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,output = <0>; - }; - func1_rx { - lantiq,pins = "io33"; - lantiq,mux = <0>; - }; - }; - asc0_func2: func2 { - func2_tx { - lantiq,pins = "io32"; - lantiq,mux = <0>; - }; - func2_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - asc0_func3: func3 { - func3_tx { - lantiq,pins = "io32"; - lantiq,mux = <1>; - lantiq,output = <0>; - }; - func3_rx { - lantiq,pins = "io33"; - lantiq,mux = <1>; - lantiq,input = <0>; - }; - }; - }; - - pinselect-asc0 { - compatible = "lantiq,pinselect-asc0"; - pinctrl-names = "asc0", "func1", "func2", "func3"; - pinctrl-0 = <&asc0_pins>; - pinctrl-1 = <&asc0_func1>; - pinctrl-2 = <&asc0_func2>; - pinctrl-3 = <&asc0_func3>; - }; -}; - -&serial0 { - pinctrl-names = "default"; - /* use "empty" pinctrl to leave setting from u-boot enabled */ - pinctrl-0 = < >; -}; - -&i2c { - status = "okay"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ3370.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ3370.dts deleted file mode 100644 index ef3655de6..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ3370.dts +++ /dev/null @@ -1,288 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "avm,fritz3370", "lantiq,xway", "lantiq,vr9"; - model = "Fritz!Box WLAN 3370"; - - chosen { - bootargs = "console=ttyLTQ0,115200 ubi.mtd=1,512 root=/dev/mtdblock9"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &info_green; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x8000000>; - }; - - fpi@10000000 { - localbus@0 { - nand-parts@0 { - compatible = "lantiq,nand-xway"; - bank-width = <2>; - reg = <1 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x400000>; - }; - - partition@400000 { - label = "rootfs_ubi"; - reg = <0x400000 0x3000000>; - }; - - partition@3400000 { - label = "vr9_firmware"; - reg = <0x3400000 0x400000>; - }; - partition@3800000 { - label = "reserved"; - reg = <0x3800000 0x3000000>; - }; - partition@6800000 { - label = "config"; - reg = <0x6800000 0x200000>; - }; - partition@6a00000 { - label = "nand-filesystem"; - reg = <0x6a00000 0x1600000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - nand { - lantiq,groups = "nand cle", "nand ale", - "nand rd", "nand cs1", "nand rdy"; - lantiq,function = "ebu"; - lantiq,pull = <1>; - }; - phy-rst { - lantiq,pins = "io37", "io44"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 5 GPIO_ACTIVE_HIGH - &gpio 14 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware = "lantiq/xrx200_phy11g_a14.bin"; - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - power { - label = "power"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; -/* wifi { - label = "wifi"; - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - };*/ - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power { - label = "fritz3370:green:power"; - gpios = <&gpio 32 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "fritz3370:red:power"; - gpios = <&gpio 33 GPIO_ACTIVE_LOW>; - }; - info_red { - label = "fritz3370:red:info"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "fritz3370:green:wlan"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "fritz3370:green:dsl"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - lan { - label = "fritz3370:green:lan"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - info_green: info_green { - label = "fritz3370:green:info"; - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <1000000>; - - urlader: partition@0 { - reg = <0x0 0x20000>; - label = "urlader"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x10000>; - label = "tffs (1)"; - read-only; - }; - - partition@30000 { - reg = <0x30000 0x10000>; - label = "tffs (2)"; - read-only; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&urlader 0x987>; - mtd-mac-address-increment = <(-2)>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&pcie0 { - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ7320.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ7320.dts deleted file mode 100644 index 34d0df9b3..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ7320.dts +++ /dev/null @@ -1,161 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "avm,fritz7320", "lantiq,xway", "lantiq,ar9"; - model = "1&1 HomeServer"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - led-running = &power; - - led-internet = &info_green; - led-dsl = &power; - led-wifi = &wlan; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - ath9k_cal: partition@0 { - label = "urlader"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0xf60000>; - }; - - partition@f80000 { - label = "tffs (1)"; - reg = <0xf80000 0x40000>; - read-only; - }; - - partition@fc0000 { - label = "tffs (2)"; - reg = <0xfc0000 0x40000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci { - lantiq,groups = "gnt1", "req1", "req2", "req3", "req4", "gnt2", "gnt3", "gnt4"; - lantiq,function = "pci"; - }; - pci-in { - lantiq,groups = "req1", "req2", "req3", "req4"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1", "gnt2", "gnt3", "gnt4"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - }; - }; - - etop@E180000 { - phy-mode = "mii"; - mtd-mac-address = <&ath9k_cal 0xa91>; - mtd-mac-address-increment = <(-2)>; - }; - - ifxhcd@E101000 { - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - rfkill { - label = "rfkill"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - dect { - label = "dect"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power: power { - label = "fritz7320:green:power"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - voice { - label = "fritz7320:green:fon"; - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - dect { - label = "fritz7320:green:dect"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - wlan: wlan { - label = "fritz7320:green:wlan"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - info_green: info_green { - label = "fritz7320:green:info"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - info_red { - label = "fritz7320:red:info"; - gpios = <&gpio 45 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - req-mask = <0xf>; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@0,0 { - compatible = "pci0,0"; - reg = <0x7000 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */ - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ7360SL.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ7360SL.dts deleted file mode 100644 index b16487110..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/FRITZ7360SL.dts +++ /dev/null @@ -1,228 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "avm,fritz7360sl", "lantiq,xway", "lantiq,vr9"; - model = "1&1 HomeServer"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &info_green; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x8000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - urlader: partition@0 { - label = "urlader"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0xf60000>; - }; - - partition@f80000 { - label = "tffs (1)"; - reg = <0xf80000 0x40000>; - read-only; - }; - - partition@fc0000 { - label = "tffs (2)"; - reg = <0xfc0000 0x40000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - phy-rst { - lantiq,pins = "io37", "io44"; - lantiq,pull = <0>; - lantiq,open-drain; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - lantiq,portmask = <0x3>; - }; - - ifxhcd@E106000 { - status = "okay"; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware = "lantiq/xrx200_phy11g_a22.bin"; - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - dect { - label = "dect"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - wifi { - label = "wifi"; - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power { - label = "fritz7360sl:green:power"; - gpios = <&gpio 32 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "fritz7360sl:red:power"; - gpios = <&gpio 33 GPIO_ACTIVE_LOW>; - }; - info_red { - label = "fritz7360sl:red:info"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - }; - info_green: info_green { - label = "fritz7360sl:green:info"; - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "fritz7360sl:green:wlan"; - gpios = <&gpio 36 GPIO_ACTIVE_LOW>; - }; - dect { - label = "fritz7360sl:green:dect"; - gpios = <&gpio 35 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&urlader 0xa91>; - mtd-mac-address-increment = <(-2)>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x00>; - compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - phy1: ethernet-phy@1 { - reg = <0x01>; - compatible = "ethernet-phy-ieee802.3-c22"; - reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&pcie0 { - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - wifi@168c,002e { - compatible = "pci168c,002e"; - reg = <0 0 0 0 0>; - qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */ - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/GIGASX76X.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/GIGASX76X.dts deleted file mode 100644 index 99ccbce29..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/GIGASX76X.dts +++ /dev/null @@ -1,122 +0,0 @@ -/dts-v1/; - -#include "danube.dtsi" - -#include - -/ { - compatible = "siemens,gigaset-sx76x", "lantiq,xway", "lantiq,danube"; - model = "Gigaset SX761,SX762,SX763"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x30000>; - }; - - partition@10000 { - label = "uboot_env"; - reg = <0x30000 0x10000>; - }; - - partition@40000 { - label = "firmware"; - reg = <0x40000 0x7c0000>; - }; - }; - }; - - gpiomm: gpiomm@4000000 { - compatible = "lantiq,gpio-mm"; - reg = <1 0x0 0x10 >; - #address-cells = <1>; - #size-cells = <1>; - #gpio-cells = <2>; - gpio-controller; - lantiq,shadow = <0x3>; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - }; - }; - }; - - gpios: stp@E100BB0 { - status = "okay"; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - pci@E105400 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - linux,code = ; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/H201L.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/H201L.dts deleted file mode 100644 index 01016f45c..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/H201L.dts +++ /dev/null @@ -1,159 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "zte,h201l", "lantiq,xway", "lantiq,ar9"; - model = "ZTE H210L"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_green; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &online; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x20000>; - read-only; - }; - - partition@20000 { - label = "uboot_env"; - reg = <0x20000 0x10000>; - read-only; - }; - - partition@30000 { - label = "firmware"; - reg = <0x30000 0x7d0000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - }; - }; - - etop@E180000 { - phy-mode = "rgmii"; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 55 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power { - label = "h201l:green:power"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - online: online { - label = "h201l:green:internet"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "h201l:green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - phone { - label = "h201l:green:phone"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - }; - wps { - label = "h201l:green:wps"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "h201l:green:wlan"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "h201l:green:usb"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; - }; - usb { - gpio-export,name = "usb"; - gpio-export,output = <1>; - gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; - }; - wifi { - gpio-export,name = "wifi"; - gpio-export,output = <1>; - gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2601HNFX.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2601HNFX.dts deleted file mode 100644 index 1b885ad84..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2601HNFX.dts +++ /dev/null @@ -1,190 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "zyxel,p-2601hn", "lantiq,xway", "lantiq,ar9"; - model = "ZyXEL P-2601HN-Fx"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &online; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@60000 { - label = "firmware"; - reg = <0x60000 0xfa0000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - exin { - lantiq,groups = "exin1"; - lantiq,function = "exin"; - }; - pci { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - }; - conf_out { - lantiq,pins = "io4", "io5", "io6"; - lantiq,open-drain; - lantiq,pull = <0>; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - }; - }; - - etop@E180000 { - phy-mode = "rmii"; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - }; - - stp: stp@E100BB0 { - #gpio-cells = <2>; - compatible = "lantiq,gpio-stp-xway"; - gpio-controller; - reg = <0xE100BB0 0x40>; - - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 53 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 54 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power { - label = "p2601hnfx:green:power"; - gpios = <&stp 11 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "p2601hnfx:red:power"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - online: online { - label = "p2601hnfx:green:internet"; - gpios = <&stp 13 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "p2601hnfx:red:internet"; - gpios = <&stp 12 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "p2601hnfx:green:dsl"; - gpios = <&stp 14 GPIO_ACTIVE_LOW>; - }; - phone { - label = "p2601hnfx:green:phone"; - gpios = <&stp 9 GPIO_ACTIVE_LOW>; - }; - phone2 { - label = "p2601hnfx:orange:phone"; - gpios = <&stp 8 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "p2601hnfx:green:wireless"; - gpios = <&stp 15 GPIO_ACTIVE_LOW>; - }; - wifi2 { - label = "p2601hnfx:orange:wireless"; - gpios = <&stp 10 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_export { - compatible = "gpio-export"; - #size-cells = <0>; - - switch { - gpio-export,name = "switch"; - gpio-export,output = <1>; - gpios = <&gpio 50 GPIO_ACTIVE_HIGH>; - }; - usb { - gpio-export,name = "wifi"; - gpio-export,output = <1>; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUF1.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUF1.dts deleted file mode 100644 index 4a29cd929..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUF1.dts +++ /dev/null @@ -1,72 +0,0 @@ -/dts-v1/; - -#include "P2812HNUFX.dtsi" - -/ { - compatible = "zyxel,p-2812hnu-f1", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; - model = "ZyXEL P-2812HNU-F1"; - - aliases { - led-usb = &usb1; - led-usb2 = &usb2; - }; - - fpi@10000000 { - localbus@0 { - nand-parts@0 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - }; - partition@40000 { - label = "uboot-env"; - reg = <0x40000 0x20000>; - }; - partition@60000 { - label = "kernel"; - reg = <0x60000 0x200000>; - }; - partition@260000 { - label = "ubi"; - reg = <0x260000 0x7da0000>; - }; - }; - }; - }; - - pcie@d900000 { - status = "disabled"; - }; - }; - - gpio-leds { - usb1: usb1 { - label = "p2812hnuf1:green:usb1"; - gpios = <&gpio 38 GPIO_ACTIVE_LOW>; - }; - usb2: usb2 { - label = "p2812hnuf1:green:usb2"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - wifi@1814,3062 { - compatible = "pci1814,3062"; - reg = <0x7000 0 0 0 0>; - ralink,eeprom = "RT3062.eeprom"; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUF3.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUF3.dts deleted file mode 100644 index d37ad0a8e..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUF3.dts +++ /dev/null @@ -1,66 +0,0 @@ -/dts-v1/; - -#include "P2812HNUFX.dtsi" - -/ { - compatible = "zyxel,p-2812hnu-f3", "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; - model = "ZyXEL P-2812HNU-F3"; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x0 0x50000>; - read-only; - }; - partition@50000 { - label = "uboot-env"; - reg = <0x50000 0x10000>; - }; - partition@60000 { - label = "unused"; - reg = <0x60000 0x7a0000>; - }; - }; - }; - - nand-parts@0 { - compatible = "lantiq,nand-xway"; - lantiq,cs = <1>; - bank-width = <2>; - reg = <1 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "kernel"; - reg = <0x0 0x200000>; - }; - partition@200000 { - label = "ubi"; - reg = <0x200000 0x7e00000>; - }; - }; - }; - }; -}; - -&pci0 { - wifi@1814,3092 { - compatible = "pci1814,3092"; - reg = <0x7000 0 0 0 0>; - ralink,eeprom = "RT3092.eeprom"; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUFX.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUFX.dtsi deleted file mode 100644 index ec3bd1033..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/P2812HNUFX.dtsi +++ /dev/null @@ -1,280 +0,0 @@ -#include "vr9.dtsi" - -#include - -/ { - compatible = "zyxel,p-2812hnu", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl_green; - led-internet = &internet_green; - led-wifi = &wireless_green; - }; - - memory@0 { - reg = <0x0 0x8000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - exin3 { - lantiq,groups = "exin3"; - lantiq,function = "exin"; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led1", - "gphy0 led2", "gphy1 led2"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pci-in { - lantiq,groups = "req1"; - lantiq,function = "pci"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1"; - lantiq,function = "pci"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - ifxhcd-rst { - lantiq,pins = "io33"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - nand_out { - lantiq,groups = "nand cle", "nand ale"; - lantiq,function = "ebu"; - lantiq,output = <1>; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - nand_cs1 { - lantiq,groups = "nand cs1"; - lantiq,function = "ebu"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - }; - }; - }; - - stp: stp@E100BB0 { - compatible = "lantiq,gpio-stp-xway"; - reg = <0xE100BB0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - lantiq,shadow = <0xffffff>; - lantiq,groups = <0x7>; - lantiq,dsl = <0x0>; - lantiq,phy1 = <0x0>; - lantiq,phy2 = <0x0>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - - ifxhcd@E106000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - - pci@E105400 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy11g_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy11g_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - rfkill { - label = "rfkill"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - internet_red { - label = "p2812hnufx:red:internet"; - gpios = <&stp 16 GPIO_ACTIVE_LOW>; - }; - internet_green: internet_green { - label = "p2812hnufx:green:internet"; - gpios = <&stp 17 GPIO_ACTIVE_LOW>; - }; - dsl_green: dsl_green { - label = "p2812hnufx:green:dsl"; - gpios = <&stp 18 GPIO_ACTIVE_LOW>; - }; - dsl_orange { - label = "p2812hnufx:orange:dsl"; - gpios = <&stp 19 GPIO_ACTIVE_LOW>; - }; - wireless_orange { - label = "p2812hnufx:orange:wlan"; - gpios = <&stp 20 GPIO_ACTIVE_LOW>; - }; - wireless_green: wireless_green { - label = "p2812hnufx:green:wlan"; - gpios = <&stp 21 GPIO_ACTIVE_LOW>; - }; - power_red: power { - label = "p2812hnufx:red:power"; - gpios = <&stp 22 GPIO_ACTIVE_LOW>; - }; - power_green: power2 { - label = "p2812hnufx:green:power"; - gpios = <&stp 23 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - phone1 { - label = "p2812hnufx:green:phone"; - gpios = <&gpio 11 GPIO_ACTIVE_LOW>; - }; - phone1warn { - label = "p2812hnufx:orange:phone"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - phone2warn { - label = "p2812hnufx:orange:phone2"; - gpios = <&gpio 26 GPIO_ACTIVE_LOW>; - }; - phone2 { - label = "p2812hnufx:green:phone2"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mac-address = [ 00 11 22 33 44 55 ]; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW8970.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW8970.dts deleted file mode 100644 index 25eb3dac6..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW8970.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "TDW89X0.dtsi" - -/ { - compatible = "tplink,tdw8970", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK TD-W8970"; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW8980.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW8980.dts deleted file mode 100644 index def34b55b..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW8980.dts +++ /dev/null @@ -1,35 +0,0 @@ -/dts-v1/; - -#include "TDW89X0.dtsi" - -/ { - compatible = "tplink,tdw8980", "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK TD-W8980"; - - fpi@10000000 { - gpio: pinmux@E100B10 { - state_default: pinmux { - pci_rst { - lantiq,pins = "io21"; - lantiq,output = <1>; - lantiq,open-drain; - }; - }; - }; - - pci@E105400 { - status = "okay"; - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - - gpio-leds { - wifi2 { - label = "tdw8980:green:wlan5ghz"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW89X0.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW89X0.dtsi deleted file mode 100644 index a629d92e4..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/TDW89X0.dtsi +++ /dev/null @@ -1,274 +0,0 @@ -#include "vr9.dtsi" - -#include - -/ { - compatible = "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - /* the power led can't be controlled, use the wps led instead */ - led-boot = &wps; - led-failsafe = &wps; - - led-dsl = &dsl; - led-internet = &internet; - led-wifi = &wifi; - led-usb = &usb0; - led-usb2 = &usb2; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - phy-rst { - lantiq,pins = "io42"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - - ifxhcd@E106000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware = "lantiq/xrx200_phy11g_a22.bin"; - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wifi { - label = "wifi"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - /* - power is not controllable via gpio - */ - dsl: dsl { - label = "tdw89x0:green:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - }; - internet: internet { - label = "tdw89x0:green:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; - }; - usb0: usb0 { - label = "tdw89x0:green:usb"; - gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; - }; - usb2: usb2 { - label = "tdw89x0:green:usb2"; - gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; - }; - wps: wps { - label = "tdw89x0:green:wps"; - gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; - }; - }; - - wifi-leds { - compatible = "gpio-leds"; - - wifi: wifi { - label = "tdw89x0:green:wifi"; - gpios = <&ath9k 0 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <33250000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "u-boot"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x7a0000>; - label = "firmware"; - }; - - partition@7c0000 { - reg = <0x7c0000 0x10000>; - label = "config"; - read-only; - }; - - ath9k_cal: partition@7d0000 { - reg = <0x7d0000 0x30000>; - label = "boardconfig"; - read-only; - }; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&ath9k_cal 0xf100>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; - -&pcie0 { - pcie@0 { - reg = <0 0 0 0 0>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - device_type = "pci"; - - ath9k: wifi@168c,002e { - compatible = "pci168c,002e"; - reg = <0 0 0 0 0>; - #gpio-cells = <2>; - gpio-controller; - qca,no-eeprom; - qca,disable-5ghz; - mtd-mac-address = <&ath9k_cal 0xf100>; - mtd-mac-address-increment = <2>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VG3503J.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VG3503J.dts deleted file mode 100644 index 8a73de9a2..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VG3503J.dts +++ /dev/null @@ -1,163 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "arcadyan,vg3503j", "lantiq,xway", "lantiq,vr9"; - model = "BT OpenReach VDSL Modem"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - }; - - memory@0 { - reg = <0x0 0x2000000>; - }; - - fpi@10000000 { - localbus@0 { - ranges = <0 0 0x0 0x3ffffff>; - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x20000>; - }; - - partition@20000 { - label = "firmware"; - reg = <0x20000 0x7d0000>; - }; - - partition@7f0000 { - label = "uboot-env"; - reg = <0x7f0000 0x10000>; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led0", "gphy0 led1", - "gphy0 led2", "gphy1 led0", - "gphy1 led1", "gphy1 led2"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - }; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy11g_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy11g_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_red: power2 { - label = "vg3503j:red:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "vg3503j:green:dsl"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - power_green: power { - label = "vg3503j:green:power"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - }; -}; - -ð0 { - interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - lantiq,switch; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - lantiq,led1h = <0x70>; - lantiq,led1l = <0x00>; - lantiq,led2h = <0x00>; - lantiq,led2l = <0x03>; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - lantiq,led1h = <0x70>; - lantiq,led1l = <0x00>; - lantiq,led2h = <0x00>; - lantiq,led2l = <0x03>; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22.dtsi deleted file mode 100644 index fb4486aca..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22.dtsi +++ /dev/null @@ -1,253 +0,0 @@ -#include "vr9.dtsi" - -#include - -/ { - compatible = "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &internet_green; - led-wifi = &wifi; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay - &gpio 31 GPIO_ACTIVE_HIGH //still unknown - &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? - }; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boardconfig: partition@fe0000 { - label = "board_config"; - reg = <0xfe0000 0x20000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - gphy-leds { - lantiq,groups = "gphy0 led0", "gphy0 led1", - "gphy1 led0", "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <2>; - lantiq,output = <1>; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - pci-rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - pcie@d900000 { - status = "disabled"; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy22f_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy22f_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - reset { - label = "reset"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - dsl: dsl { - label = "vgv7510kw22:green:dsl"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; - - internet_red { - label = "vgv7510kw22:red:internet"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; - - info_red { - label = "vgv7510kw22:red:info"; - gpios = <&gpio 12 GPIO_ACTIVE_LOW>; - }; - - power_green: power { - label = "vgv7510kw22:green:power"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - - info_green { - label = "vgv7510kw22:green:info"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - - internet_green: internet_green { - label = "vgv7510kw22:green:internet"; - gpios = <&gpio 19 GPIO_ACTIVE_LOW>; - }; - - wifi: wifi { - label = "vgv7510kw22:green:wlan"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - - power_red: power2 { - label = "vgv7510kw22:red:power"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - }; - - phone { - label = "vgv7510kw22:green:telefon"; - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@1814,3592 { - compatible = "pci1814,3592"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&boardconfig 0x16>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "mii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy12>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c22"; - }; - - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy12: ethernet-phy@12 { - reg = <0x12>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22BRN.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22BRN.dts deleted file mode 100644 index d0be62f63..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22BRN.dts +++ /dev/null @@ -1,67 +0,0 @@ -/dts-v1/; - -#include "VGV7510KW22.dtsi" - -/ { - compatible = "arcadyan,vgv7510kw22-brn", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; - model = "o2 Box 6431"; - - sram@1F000000 { - cgu@103000 { - lantiq,phy-clk-src = <0x2>; - }; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - partitions { - partition@0 { - label = "Boot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "Configuration"; - reg = <0x40000 0x40000>; - read-only; - }; - - partition@80000 { - label = "Certificate"; - reg = <0x80000 0x20000>; - read-only; - }; - - partition@a0000 { - label = "Special_Area"; - reg = <0xa0000 0x20000>; - read-only; - }; - - partition@c0000 { - compatible = "brnboot,root-selector"; - label = "Primary_Setting"; - reg = <0xc0000 0x20000>; - read-only; - }; - - partition@e0000 { - label = "Code_Image_0"; - reg = <0xe0000 0x780000>; - brnboot,root-id = <0x00>; - read-only; - }; - - partition@860000 { - label = "Code_Image_1"; - reg = <0x860000 0x780000>; - brnboot,root-id = <0x01>; - read-only; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22NOR.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22NOR.dts deleted file mode 100644 index 1d21e14f0..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7510KW22NOR.dts +++ /dev/null @@ -1,33 +0,0 @@ -/dts-v1/; - -#include "VGV7510KW22.dtsi" - -/ { - compatible = "arcadyan,vgv7510kw22-nor", "arcadyan,vgv7510kw22", "lantiq,xway", "lantiq,vr9"; - model = "o2 Box 6431"; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - partitions { - partition@0 { - label = "uboot"; - reg = <0x0 0x60000>; /* 384 KiB */ - read-only; - }; - - partition@60000 { - label = "uboot-env"; - reg = <0x60000 0x20000>; /* 128 KiB */ - read-only; - }; - - partition@80000 { - label = "firmware"; - reg = <0x80000 0xf60000>; /* 15744 KiB */ - }; - }; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519.dtsi deleted file mode 100644 index e807b5271..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519.dtsi +++ /dev/null @@ -1,298 +0,0 @@ -#include "vr9.dtsi" - -#include - -/ { - compatible = "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; - - chosen { - bootargs = "console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &broadband_green; - led-internet = &internet_green; - led-wifi = &wireless_green; - }; - - sram@1F000000 { - vmmc@107000 { - status = "okay"; - gpios = <&gpio 30 GPIO_ACTIVE_HIGH //fxs relay - &gpio 31 GPIO_ACTIVE_HIGH //still unknown - &gpio 3 GPIO_ACTIVE_HIGH>; //reset_slic? - }; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x800000>, <1 0x800000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boardconfig: partition@40000 { - label = "board_config"; - reg = <0x40000 0x10000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - stp { - lantiq,groups = "stp"; - lantiq,function = "stp"; - lantiq,open-drain = <0>; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - pci-rst { - lantiq,pins = "io21"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led0"; - lantiq,function = "gphy"; - lantiq,open-drain = <0>; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - }; - - stp: stp@E100BB0 { - compatible = "lantiq,gpio-stp-xway"; - reg = <0xE100BB0 0x40>; - #gpio-cells = <2>; - gpio-controller; - - lantiq,shadow = <0xffff>; - lantiq,groups = <0x3>; - lantiq,dsl = <0x0>; - lantiq,phy1 = <0x0>; - lantiq,phy2 = <0x0>; - /* lantiq,rising; */ - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - - ifxhcd@E106000 { - status = "okay"; - gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; - }; - - pcie@d900000 { - status = "disabled"; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware1 = "lantiq/xrx200_phy11g_a14.bin"; /*VR9 1.1*/ - firmware2 = "lantiq/xrx200_phy11g_a22.bin"; /*VR9 1.2*/ - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 9 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - eco { - label = "eco"; - gpios = <&gpio 41 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - rfkill { - label = "rfkill"; - gpios = <&gpio 45 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - wps { - label = "wps"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - eco { - label = "vgv7519:blue:eco"; - gpios = <&stp 2 GPIO_ACTIVE_LOW>; - }; - wps_red { - label = "vgv7519:red:wps"; - gpios = <&stp 3 GPIO_ACTIVE_LOW>; - }; - wps_green { - label = "vgv7519:green:wps"; - gpios = <&stp 4 GPIO_ACTIVE_LOW>; - }; - upgrade { - label = "vgv7519:blue:upgrade"; - gpios = <&stp 5 GPIO_ACTIVE_LOW>; - }; - tv { - label = "vgv7519:green:tv"; - gpios = <&stp 6 GPIO_ACTIVE_LOW>; - }; - internet_green: internet_green { - label = "vgv7519:green:internet"; - gpios = <&stp 7 GPIO_ACTIVE_LOW>; - }; - internet_red { - label = "vgv7519:red:internet"; - gpios = <&stp 8 GPIO_ACTIVE_LOW>; - }; - broadband_red { - label = "vgv7519:red:broadband"; - gpios = <&stp 9 GPIO_ACTIVE_LOW>; - }; - broadband_green: broadband_green { - label = "vgv7519:green:broadband"; - gpios = <&stp 10 GPIO_ACTIVE_LOW>; - }; - voice { - label = "vgv7519:green:voice"; - gpios = <&stp 11 GPIO_ACTIVE_LOW>; - }; - wireless_red { - label = "vgv7519:red:wireless"; - gpios = <&stp 12 GPIO_ACTIVE_LOW>; - }; - wireless_green: wireless_green { - label = "vgv7519:green:wireless"; - gpios = <&stp 13 GPIO_ACTIVE_LOW>; - }; - power_green: power2 { - label = "vgv7519:green:power"; - gpios = <&stp 14 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power { - label = "vgv7519:red:power"; - gpios = <&stp 15 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&pci0 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - - wifi@1814,3091 { - compatible = "pci1814,3091"; - reg = <0x7000 0 0 0 0>; - ralink,mtd-eeprom = <&boardconfig 0x410>; - ralink,mtd-eeprom-swap; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&boardconfig 0x16>; - mtd-mac-address-increment = <1>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - }; - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <1>; - phy-mode = "rgmii"; - phy-handle = <&phy1>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy1: ethernet-phy@1 { - reg = <0x1>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519BRN.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519BRN.dts deleted file mode 100644 index f30d2f920..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519BRN.dts +++ /dev/null @@ -1,73 +0,0 @@ -/dts-v1/; - - -#include "VGV7519.dtsi" - -/ { - compatible = "arcadyan,vgv7519-brn", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; - model = "KPN Experiabox V8"; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - partitions { - partition@0 { - label = "Boot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@50000 { - label = "Certificate"; - reg = <0x50000 0x10000>; - read-only; - }; - partition@60000 { - label = "Special_Area"; - reg = <0x60000 0x10000>; - read-only; - }; - - partition@70000 { - label = " Reserve_0"; - reg = <0x70000 0x10000>; - read-only; - }; - - partition@80000 { - label = "Code_Image_0"; - reg = <0x80000 0x780000>; - brnboot,root-id = <0x00>; - read-only; - }; - - partition@4000000 { - compatible = "brnboot,root-selector"; - label = "Primary_Setting"; - reg = <0x4000000 0x10000>; - read-only; - }; - - partition@4010000 { - label = "Configuration"; - reg = <0x4010000 0x60000>; - read-only; - }; - - partition@4070000 { - label = " Reserve_1"; - reg = <0x4070000 0x10000>; - read-only; - }; - - partition@4080000 { - label = "Code_Image_1"; - reg = <0x4080000 0x780000>; - brnboot,root-id = <0x01>; - read-only; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519NOR.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519NOR.dts deleted file mode 100644 index ec548fbe7..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VGV7519NOR.dts +++ /dev/null @@ -1,32 +0,0 @@ -/dts-v1/; - - -#include "VGV7519.dtsi" - -/ { - compatible = "arcadyan,vgv7519-nor", "arcadyan,vgv7519", "lantiq,xway", "lantiq,vr9"; - model = "KPN Experiabox V8"; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - partitions { - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - partition@60000 { - label = "uboot_env"; - reg = <0x60000 0x10000>; - read-only; - }; - partition@80000 { - label = "firmware"; - reg = <0x80000 0xf80000>; - }; - }; - }; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VR200v.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VR200v.dts deleted file mode 100644 index 6eccc5bdd..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/VR200v.dts +++ /dev/null @@ -1,283 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "tplink,vr200v", "lantiq,xway", "lantiq,vr9"; - model = "TP-LINK Archer VR200v"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power; - led-failsafe = &power; - - led-dsl = &dsl; - led-internet = &internet; - led-usb = &usb; - led-usb2 = &usb; - }; - - memory@0 { - reg = <0x0 0x7f00000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - gphy-leds { - lantiq,groups = "gphy0 led1", "gphy1 led1"; - lantiq,function = "gphy"; - lantiq,pull = <2>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - phy-rst { - lantiq,pins = "io42"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - - ifxhcd@E106000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - - pci0: pci@E105400 { - status = "okay"; - gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware = "lantiq/xrx200_phy11g_a22.bin"; - phys = [ 00 01 ]; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - reset { - label = "reset"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wifi { - label = "wifi"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - dect_paging { - label = "dect_paging"; - gpios = <&gpio 39 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - power: power { - label = "vr200v:blue:power"; - gpios = <&gpio 46 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "vr200v:blue:dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_LOW>; - }; - internet: internet { - label = "vr200v:blue:internet"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "vr200v:blue:usb"; - gpios = <&gpio 25 GPIO_ACTIVE_LOW>; - }; - eth { - label = "vr200v:blue:lan"; - gpios = <&gpio 40 GPIO_ACTIVE_LOW>; - }; - wlan { - label = "vr200v:blue:wlan"; - gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - }; - wlan5g { - label = "vr200v:blue:wlan5g"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - phone { - label = "vr200v:blue:phone"; - gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <33250000>; - m25p,fast-read; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x0 0x20000>; - label = "u-boot"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0xf90000>; - label = "firmware"; - }; - - partition@fb0000 { - reg = <0xfb0000 0x10000>; - label = "radioDECT"; - read-only; - }; - - partition@fc0000 { - reg = <0xfc0000 0x10000>; - label = "config"; - read-only; - }; - - romfile: partition@fd0000 { - reg = <0xfd0000 0x10000>; - label = "romfile"; - read-only; - }; - - partition@fe0000 { - reg = <0xfe0000 0x10000>; - label = "rom"; - read-only; - }; - - partition@ff0000 { - reg = <0xff0000 0x10000>; - label = "radio"; - read-only; - }; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - mtd-mac-address = <&romfile 0xf100>; - lantiq,switch; - - ethernet@0 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <0>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; - }; - ethernet@5 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "rgmii"; - phy-handle = <&phy5>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "gmii"; - phy-handle = <&phy11>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "gmii"; - phy-handle = <&phy13>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy0: ethernet-phy@0 { - reg = <0x0>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy5: ethernet-phy@5 { - reg = <0x5>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/WBMR.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/WBMR.dts deleted file mode 100644 index fab99d00e..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/WBMR.dts +++ /dev/null @@ -1,185 +0,0 @@ -/dts-v1/; - -#include "ar9.dtsi" - -#include - -/ { - compatible = "buffalo,wbmr-hp-g300h", "lantiq,xway", "lantiq,ar9"; - model = "Buffalo WBMR-HP-G300H"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_green; - led-failsafe = &power_red; - led-running = &power_green; - - led-dsl = &dsl; - led-internet = &online_green; - led-usb = &usb; - led-wifi = &wifi; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - localbus@0 { - nor-boot@0 { - compatible = "lantiq,nor"; - bank-width = <2>; - reg = <0 0x0 0x2000000>; - #address-cells = <1>; - #size-cells = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "uboot"; - reg = <0x00000 0x40000>; - read-only; - }; - - partition@40000 { - label = "uboot_env"; - reg = <0x40000 0x20000>; - read-only; - }; - - partition@20000 { - label = "firmware"; - reg = <0x60000 0x1f20000>; - }; - - boardconfig: partition@1fc0000 { - label = "board"; - reg = <0x1fc0000 0x20000>; - read-only; - }; - - partition@1fe0000 { - label = "calibration"; - reg = <0x1fe0000 0x20000>; - read-only; - }; - }; - }; - }; - - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - pci-in { - lantiq,groups = "req1"; - lantiq,output = <0>; - lantiq,open-drain = <1>; - lantiq,pull = <2>; - }; - pci-out { - lantiq,groups = "gnt1"; - lantiq,output = <1>; - lantiq,pull = <0>; - }; - pci_rst { - lantiq,pins = "io21"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - }; - - etop@E180000 { - phy-mode = "rgmii"; - mtd-mac-address = <&boardconfig 0x10024>; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - - pci@E105400 { - status = "okay"; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - wps { - label = "wps"; - gpios = <&gpio 0 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - reset { - label = "reset"; - gpios = <&gpio 37 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - eject { - label = "eject"; - gpios = <&gpio 34 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - movie { - label = "movie"; - gpios = <&gpio 22 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - power_green: power { - label = "wbmr:green:power"; - gpios = <&gpio 1 GPIO_ACTIVE_LOW>; - default-state = "keep"; - }; - power_red: power2 { - label = "wbmr:red:power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - }; - security { - label = "wbmr:yellow:security"; - gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - }; - wifi: wifi { - label = "wbmr:green:wireless"; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; - dsl: dsl { - label = "wbmr:green:dsl"; - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - online_green: online { - label = "wbmr:green:internet"; - gpios = <&gpio 17 GPIO_ACTIVE_LOW>; - }; - online2 { - label = "wbmr:red:internet"; - gpios = <&gpio 18 GPIO_ACTIVE_LOW>; - }; - movie { - label = "wbmr:blue:movie"; - gpios = <&gpio 20 GPIO_ACTIVE_LOW>; - }; - usb: usb { - label = "wbmr:green:usb"; - gpios = <&gpio 28 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/WBMR300.dts b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/WBMR300.dts deleted file mode 100644 index 2ecfe4bc9..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/WBMR300.dts +++ /dev/null @@ -1,306 +0,0 @@ -/dts-v1/; - -#include "vr9.dtsi" - -#include - -/ { - compatible = "buffalo,wbmr-300hpd", "lantiq,xway", "lantiq,vr9"; - model = "Buffalo WBMR-300HPD"; - - chosen { - bootargs = "console=ttyLTQ0,115200"; - }; - - aliases { - led-boot = &power_g; - led-failsafe = &diag_r; - led-running = &power_g; - - led-dsl = &dsl; - led-internet = &router_g; - led-wifi = &wifi_g; - }; - - memory@0 { - reg = <0x0 0x4000000>; - }; - - fpi@10000000 { - gpio: pinmux@E100B10 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - mdio { - lantiq,groups = "mdio"; - lantiq,function = "mdio"; - }; - phy-rst { - lantiq,pins = "io42"; - lantiq,pull = <0>; - lantiq,open-drain = <0>; - lantiq,output = <1>; - }; - pcie-rst { - lantiq,pins = "io38"; - lantiq,pull = <0>; - lantiq,output = <1>; - }; - }; - pins_spi_default: pins_spi_default { - spi_in { - lantiq,groups = "spi_di"; - lantiq,function = "spi"; - }; - spi_out { - lantiq,groups = "spi_do", "spi_clk", - "spi_cs4"; - lantiq,function = "spi"; - lantiq,output = <1>; - }; - }; - }; - - ifxhcd@E101000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - lantiq,portmask = <0x3>; - }; - - ifxhcd@E106000 { - status = "okay"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - }; - - gphy-xrx200 { - compatible = "lantiq,phy-xrx200"; - firmware = "lantiq/xrx200_phy22f_a22.bin"; - phys = [ 00 01 ]; - }; - - gpio_poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 6 GPIO_ACTIVE_LOW>; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&gpio 5 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - reset { - label = "reset"; - gpios = <&gpio 7 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - wps { - label = "wps"; - gpios = <&gpio 31 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - auto { - label = "auto"; - gpios = <&gpio 48 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - - router { - label = "router"; - gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - linux,input-type = ; - }; - }; - - gpio-leds { - compatible = "gpio-leds"; - - diag_r: diag_r { - label = "wbmr300:red:diag"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - default_state = "off"; - }; - - wifi_g: wifi_g { - label = "wbmr300:green:wifi"; - gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; - }; - - dsl: dsl { - label = "dsl"; - gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - }; - - router_y: router_y { - label = "wbmr300:yellow:router"; - gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; - }; - - wifi_y: wifi_y { - label = "wbmr300:yellow:wifi"; - gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; - }; - - lan1: lan1 { - label = "wbmr300:green:lan1"; - gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; - }; - - wan: wan { - label = "wbmr300:green:wan"; - gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; - }; - - lan3: lan3 { - label = "wbmr300:green:lan3"; - gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; - }; - - lan2: lan2 { - label = "wbmr300:green:lan2"; - gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; - }; - - internet_g: internet_g { - label = "wbmr300:green:internet"; - gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; - }; - - internet_y: internet_y { - label = "wbmr300:yellow:internet"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - }; - - router_g: router_g { - label = "wbmr300:green:router"; - gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - - power_g: power_g { - label = "wbmr300:green:power"; - gpios = <&gpio 49 GPIO_ACTIVE_HIGH>; - }; - }; -}; - -&spi { - pinctrl-names = "default"; - pinctrl-0 = <&pins_spi_default>; - - status = "ok"; - m25p80@4 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <4 0>; - spi-max-frequency = <20000000>; - - partition@0 { - reg = <0x0 0x10000>; - label = "u-boot"; - read-only; - }; - - partition@10000 { - reg = <0x10000 0x10000>; - label = "gphyfirmware"; - read-only; - }; - - partition@20000 { - reg = <0x20000 0x80000>; - label = "dsl_fw"; - }; - - partition@de0000 { - reg = <0xa0000 0xf40000>; - label = "firmware"; - }; - - partition@fe0000 { - reg = <0xfe0000 0x10000>; - label = "sysconfig"; - read-only; - }; - - partition@ff0000 { - reg = <0xff0000 0x2000>; - label = "ubootconfig"; - }; - - partition@ff3000 { - reg = <0xff3000 0x2000>; - label = "board_config"; - read-only; - }; - }; -}; - -ð0 { - lan: interface@0 { - compatible = "lantiq,xrx200-pdi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - lantiq,switch; - - ethernet@1 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <4>; - phy-mode = "mii"; - phy-handle = <&phy13>; - }; - ethernet@2 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <5>; - phy-mode = "mii"; - phy-handle = <&phy14>; - }; - ethernet@3 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <2>; - phy-mode = "mii"; - phy-handle = <&phy11>; - }; - ethernet@4 { - compatible = "lantiq,xrx200-pdi-port"; - reg = <3>; - phy-mode = "mii"; - phy-handle = <&phy12>; - }; - }; - - mdio@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-mdio"; - phy11: ethernet-phy@11 { - reg = <0x11>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy12: ethernet-phy@12 { - reg = <0x12>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy13: ethernet-phy@13 { - reg = <0x13>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - phy14: ethernet-phy@14 { - reg = <0x14>; - compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/amazonse.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/amazonse.dtsi deleted file mode 100644 index e6925a3ad..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/amazonse.dtsi +++ /dev/null @@ -1,174 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,ase"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - cpu@0 { - compatible = "mips,mips4Kc"; - }; - }; - - memory@0 { - device_type = "memory"; - }; - - biu@1F800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1F800000 0x800000>; - ranges = <0x0 0x1F800000 0x7FFFFF>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803F0 { - compatible = "lantiq,wdt"; - reg = <0x803F0 0x10>; - }; - }; - - sram@1F000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1F000000 0x800000>; - ranges = <0x0 0x1F000000 0x7FFFFF>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <29 30 31>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - rcu0: rcu@203000 { - compatible = "lantiq,rcu-xway"; - reg = <0x203000 0x1000>; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xEEFFFFF>; - reg = <0x10000000 0xEF00000>; - - localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - spi@E100800 { - compatible = "lantiq,ase-spi"; - reg = <0xE100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <24 25 26>; - interrupt-names = "spi_rx", "spi_tx", "spi_err", - "spi_frm"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - gptu@E100A00 { - compatible = "lantiq,gptu-xway"; - reg = <0xE100A00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <33 34 35 36 37 38>; - }; - - gpio: pinmux@E100B10 { - compatible = "lantiq,ase-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - }; - - asc1: serial@E100C00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <72 74 75>; - }; - - mei@E116000 { - compatible = "lantiq,mei-xway"; - interrupt-parent = <&icu0>; - interrupts = <81>; - }; - - ifxhcd@E101000 { - compatible = "lantiq,ase-usb", "lantiq,ifxhcd-ase"; - reg = <0xE101000 0x1000 - 0xE120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <39>; - dr_mode = "host"; - status = "disabled"; - }; - - dma0: dma@E104100 { - compatible = "lantiq,dma-xway"; - reg = <0xE104100 0x800>; - }; - - ebu0: ebu@E105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xE105300 0x100>; - }; - - ppe@E234000 { - compatible = "lantiq,ppe-ase"; - interrupt-parent = <&icu0>; - interrupts = <85>; - }; - - etop@E180000 { - compatible = "lantiq,etop-xway"; - reg = <0xE180000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <105 109>; - }; - }; - - adsl { - compatible = "lantiq,adsl-ase"; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ar9.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ar9.dtsi deleted file mode 100644 index 2638a4b26..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/ar9.dtsi +++ /dev/null @@ -1,216 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,ar9"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - cpu@0 { - compatible = "mips,mips34K"; - }; - }; - - memory@0 { - device_type = "memory"; - }; - - biu@1F800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1F800000 0x800000>; - ranges = <0x0 0x1F800000 0x7FFFFF>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803F0 { - compatible = "lantiq,wdt"; - reg = <0x803F0 0x10>; - }; - }; - - sram@1F000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1F000000 0x800000>; - ranges = <0x0 0x1F000000 0x7FFFFF>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <166 135 66 40 41 42>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - rcu0: rcu@203000 { - compatible = "lantiq,rcu-xway"; - reg = <0x203000 0x1000>; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xEEFFFFF>; - reg = <0x10000000 0xEF00000>; - - localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - gptu@E100A00 { - compatible = "lantiq,gptu-xway"; - reg = <0xE100A00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <126 127 128 129 130 131>; - }; - - asc0: serial@E100400 { - compatible = "lantiq,asc"; - reg = <0xE100400 0x400>; - interrupt-parent = <&icu0>; - interrupts = <104 105 106>; - status = "disabled"; - }; - - spi: spi@E100800 { - compatible = "lantiq,xrx100-spi"; - reg = <0xE100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <22 23 24>; - interrupt-names = "spi_rx", "spi_tx", "spi_err", - "spi_frm"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - gpio: pinmux@E100B10 { - compatible = "lantiq,xrx100-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - }; - - asc1: serial@E100C00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - ifxhcd@E101000 { - compatible = "lantiq,arx100-usb", "lantiq,ifxhcd-arx100"; - reg = <0xE101000 0x1000 - 0xE120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <62 91>; - dr_mode = "host"; - status = "disabled"; - }; - - ifxhcd@E106000 { - compatible = "lantiq,arx100-usb"; - reg = <0xE106000 0x1000 - 0xE1E0000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <91>; - dr_mode = "host"; - status = "disabled"; - }; - - deu@E103100 { - compatible = "lantiq,deu-arx100"; - reg = <0xE103100 0xf00>; - }; - - dma0: dma@E104100 { - compatible = "lantiq,dma-xway"; - reg = <0xE104100 0x800>; - }; - - ebu0: ebu@E105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xE105300 0x100>; - }; - - mei@E116000 { - compatible = "lantiq,mei-xway"; - interrupt-parent = <&icu0>; - interrupts = <63>; - }; - - etop@E180000 { - compatible = "lantiq,etop-xway"; - reg = <0xE180000 0x40000 - 0xE108000 0x200>; - interrupt-parent = <&icu0>; - interrupts = <73 72>; - mac-address = [ 00 11 22 33 44 55 ]; - }; - - ppe@E234000 { - compatible = "lantiq,ppe-arx100"; - interrupt-parent = <&icu0>; - interrupts = <96>; - }; - - pci0: pci@E105400 { - status = "disabled"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xE105400 0x400>; /* pci bridge */ - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; - req-mask = <0x1>; - }; - }; - - adsl { - compatible = "lantiq,adsl-arx100"; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/danube.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/danube.dtsi deleted file mode 100644 index 83e85c36a..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/danube.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,danube"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - cpu@0 { - compatible = "mips,mips24Kc"; - }; - }; - - memory@0 { - device_type = "memory"; - }; - - biu@1F800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1F800000 0x800000>; - ranges = <0x0 0x1F800000 0x7FFFFF>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803F0 { - compatible = "lantiq,wdt"; - reg = <0x803F0 0x10>; - }; - }; - - sram@1F000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1F000000 0x800000>; - ranges = <0x0 0x1F000000 0x7FFFFF>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <166 135 66>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - #clock-cells = <1>; - }; - - vmmc@107000 { - status = "disabled"; - compatible = "lantiq,vmmc-xway"; - reg = <0x103000 0x400>; - interrupt-parent = <&icu0>; - interrupts = <150 151 152 153 154 155>; - }; - - rcu0: rcu@203000 { - compatible = "lantiq,rcu-xway"; - reg = <0x203000 0x1000>; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xEEFFFFF>; - reg = <0x10000000 0xEF00000>; - - localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - gptu@E100A00 { - compatible = "lantiq,gptu-xway"; - reg = <0xE100A00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <126 127 128 129 130 131>; - }; - - gpios: stp@E100BB0 { - #gpio-cells = <2>; - compatible = "lantiq,gpio-stp-xway"; - gpio-controller; - reg = <0xE100BB0 0x40>; - lantiq,shadow = <0xfff>; - lantiq,groups = <0x3>; - status = "disabled"; - }; - - asc0: serial@E100400 { - compatible = "lantiq,asc"; - reg = <0xE100400 0x400>; - interrupt-parent = <&icu0>; - interrupts = <104 105 106>; - status = "disabled"; - }; - - gpio: pinmux@E100B10 { - compatible = "lantiq,danube-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - }; - - asc1: serial@E100C00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - ifxhcd@E101000 { - compatible = "lantiq,danube-usb", "lantiq,ifxhcd-danube"; - reg = <0xE101000 0x1000 - 0xE120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <62>; - dr_mode = "host"; - status = "disabled"; - }; - - deu@E103100 { - compatible = "lantiq,deu-danube"; - reg = <0xE103100 0xf00>; - }; - - dma0: dma@E104100 { - compatible = "lantiq,dma-xway"; - reg = <0xE104100 0x800>; - }; - - ebu0: ebu@E105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xE105300 0x100>; - }; - - mei@E116000 { - compatible = "lantiq,mei-xway"; - interrupt-parent = <&icu0>; - interrupts = <63>; - }; - - etop@E180000 { - compatible = "lantiq,etop-xway"; - reg = <0xE180000 0x40000>; - interrupt-parent = <&icu0>; - interrupts = <73 78>; - mac-address = [ 00 11 22 33 44 55 ]; - }; - - ppe@E234000 { - compatible = "lantiq,ppe-danube"; - interrupt-parent = <&icu0>; - interrupts = <96>; - }; - - pci0: pci@E105400 { - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xE105400 0x400>; /* pci bridge */ - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */ - req-mask = <0x1>; /* GNT1 */ - }; - }; - - adsl { - compatible = "lantiq,adsl-danube"; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/falcon-sflash-16M.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/falcon-sflash-16M.dtsi deleted file mode 100644 index d95acc21e..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/falcon-sflash-16M.dtsi +++ /dev/null @@ -1,37 +0,0 @@ - -&ebu_cs0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sflash-falcon", "simple-bus"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spansion,s25fl129p0", "spansion,s25fl129p1"; - reg = <0 0>; - linux,mtd-name = "sflash"; - spi-max-frequency = <80000000>; - m25p,fast-read; - - partition@0 { - reg = <0x0 0x40000>; - label = "uboot"; - read-only; - }; - - partition@40000 { - reg = <0x40000 0x80000>; - label = "uboot_env"; - }; - - partition@C0000 { - reg = <0xC0000 0x740000>; - label = "image0"; - }; - - partition@800000 { - reg = <0x800000 0x800000>; - label = "image1"; - }; - }; -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/falcon.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/falcon.dtsi deleted file mode 100644 index 98f71819a..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/falcon.dtsi +++ /dev/null @@ -1,392 +0,0 @@ -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,falcon"; - - cpus { - cpu@0 { - compatible = "mips,mips34kc"; - }; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clocks { - compatible = "simple-bus"; - - cpu_clk: cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <400000000>; - clock-output-names = "cpu"; - }; - - io_clk: io { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "io"; - }; - - fpi_clk: fpi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "fpi"; - }; - }; - - ebu_cs0: localbus@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,localbus", "simple-bus"; - reg = <0x10000000 0x4000000>; - ranges = <0x0 0x10000000 0x4000000>; - }; - ebu_cs1: localbus@14000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,localbus", "simple-bus"; - reg = <0x14000000 0x4000000>; - ranges = <0x0 0x14000000 0x4000000>; - }; - - ebu@18000000 { - compatible = "lantiq,ebu-falcon"; - reg = <0x18000000 0x100>; - }; - - sbs2@1D000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sysb2", "simple-bus"; - reg = <0x1D000000 0x1000000>; - ranges = <0x0 0x1D000000 0x1000000>; - - clock_sysgpe: clock-controller@700000 { - compatible = "lantiq,sysgpe-falcon"; - reg = <0x700000 0x100>; - #clock-cells = <1>; - }; - - mps@4000 { - compatible = "lantiq,mps-falcon", "lantiq,mps-xrx100"; - reg = <0x4000 0x1000>; - interrupt-parent = <&icu0>; - interrupts = <154 155>; - lantiq,mbx = <&mpsmbx>; - }; - - gpio0: gpio@810000 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <44>; - reg = <0x810000 0x80>; - clocks = <&clock_syseth 16>; - }; - - gpio2: gpio@810100 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <46>; - reg = <0x810100 0x80>; - clocks = <&clock_syseth 17>; - }; - - clock_syseth: clock-controller@B00000 { - compatible = "lantiq,syseth-falcon"; - reg = <0xB00000 0x100>; - #clock-cells = <1>; - }; - - pad@B01000 { - compatible = "lantiq,pad-falcon"; - reg = <0xB01000 0x100>; - lantiq,bank = <0>; - clocks = <&clock_syseth 20>; - }; - - pad@B02000 { - compatible = "lantiq,pad-falcon"; - reg = <0xB02000 0x100>; - lantiq,bank = <2>; - clocks = <&clock_syseth 21>; - }; - }; - - fpi@1E000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - reg = <0x1E000000 0x1000000>; - ranges = <0x0 0x1E000000 0x1000000>; - - serial1: serial@100B00 { - status = "disabled"; - compatible = "lantiq,asc"; - reg = <0x100B00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - line = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&asc1_pins>; - clocks = <&clock_sys1 11>; - }; - - serial0: serial@100C00 { - compatible = "lantiq,asc"; - reg = <0x100C00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <104 105 106>; - line = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&asc0_pins>; - clocks = <&clock_sys1 12>; - }; - - spi: spi@100D00 { - status = "disabled"; - compatible = "lantiq,falcon-spi", "lantiq,xrx100-spi", "lantiq,spi-lantiq-ssc"; - interrupts = <22 23 24 25>; - interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100D00 0x100>; - interrupt-parent = <&icu0>; - clocks = <&clock_sys1 13>; - base_cs = <1>; - num_cs = <2>; - }; - - gptc@100E00 { - compatible = "lantiq,gptc-falcon"; - reg = <0x100E00 0x100>; - }; - - i2c: i2c@200000 { - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,lantiq-i2c"; - reg = <0x200000 0x10000>; - interrupt-parent = <&icu0>; - interrupts = <18 19 20 21>; - gpios = <&gpio1 7 0 &gpio1 8 0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_pins>; - clocks = <&clock_sys1 14>; - }; - - gpio1: gpio@800100 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <45>; - reg = <0x800100 0x100>; - clocks = <&clock_sys1 16>; - }; - - gpio3: gpio@800200 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <47>; - reg = <0x800200 0x100>; - clocks = <&clock_sys1 17>; - }; - - gpio4: gpio@800300 { - compatible = "lantiq,falcon-gpio"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&icu0>; - interrupts = <48>; - reg = <0x800300 0x100>; - clocks = <&clock_sys1 18>; - }; - - pad@800400 { - compatible = "lantiq,pad-falcon"; - reg = <0x800400 0x100>; - lantiq,bank = <1>; - clocks = <&clock_sys1 20>; - }; - - pad@800500 { - compatible = "lantiq,pad-falcon"; - reg = <0x800500 0x100>; - lantiq,bank = <3>; - clocks = <&clock_sys1 21>; - }; - - pad@800600 { - compatible = "lantiq,pad-falcon"; - reg = <0x800600 0x100>; - lantiq,bank = <4>; - clocks = <&clock_sys1 22>; - }; - - status@802000 { - compatible = "lantiq,status-falcon"; - reg = <0x802000 0x80>; - }; - - clock_sys1: clock-controller@F00000 { - compatible = "lantiq,sys1-falcon"; - reg = <0xF00000 0x100>; - #clock-cells = <1>; - }; - }; - - sbs0@1F000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - reg = <0x1F000000 0x400000>; - ranges = <0x0 0x1F000000 0x400000>; - - mpsmbx: mpsmbx@200000 { - reg = <0x200000 0x200>; - }; - }; - - sbs1@1F700000 { - - }; - - biu@1F800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1F800000 0x800000>; - ranges = <0x0 0x1F800000 0x800000>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803F0 { - compatible = "lantiq,wdt"; - reg = <0x803F0 0x10>; - clocks = <&io_clk>; /* currently no effect */ - }; - }; - - pinctrl { - compatible = "lantiq,pinctrl-falcon"; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinctrl0 { - /*ntr { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - };*/ - hrst { - lantiq,groups = "hrst"; - lantiq,function = "rst"; - }; - }; - - asc0_pins: asc0 { - asc0 { - lantiq,groups = "asc0"; - lantiq,function = "asc"; - }; - }; - asc1_pins: asc1 { - asc1 { - lantiq,groups = "asc1"; - lantiq,function = "asc"; - }; - }; - i2c_pins: i2c { - i2c { - lantiq,groups = "i2c"; - lantiq,function = "i2c"; - }; - }; - bootled_pins: bootled { - bootled { - lantiq,groups = "bootled"; - lantiq,function = "led"; - }; - }; - ntr_ntr8k: ntr8k { - ntr8k { - lantiq,groups = "ntr8k"; - lantiq,function = "ntr"; - }; - }; - ntr_pps: pps { - pps { - lantiq,groups = "pps"; - lantiq,function = "ntr"; - }; - }; - ntr_gpio: gpio { - gpio { - lantiq,pins = "io5"; - lantiq,mux = <1>; - lantiq,output = <0>; - }; - }; - slic_pins: slic { - slic { - lantiq,groups = "slic"; - lantiq,function = "slic"; - }; - }; - }; - - pinselect-ntr { - compatible = "lantiq,onu-ntr","lantiq,pinselect-ntr"; - pinctrl-names = "ntr8k", "pps", "gpio"; - pinctrl-0 = <&ntr_ntr8k>; - pinctrl-1 = <&ntr_pps>; - pinctrl-2 = <&ntr_gpio>; - }; - - pinselect-asc1 { - compatible = "lantiq,onu-asc1","lantiq,pinselect-asc1"; - pinctrl-names = "default", "asc1"; - pinctrl-0 = <&slic_pins>; - pinctrl-1 = <&asc1_pins>; - }; - -}; diff --git a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/vr9.dtsi b/target/linux/lantiq/files-4.9/arch/mips/boot/dts/vr9.dtsi deleted file mode 100644 index dbcbb3dce..000000000 --- a/target/linux/lantiq/files-4.9/arch/mips/boot/dts/vr9.dtsi +++ /dev/null @@ -1,260 +0,0 @@ -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,xway", "lantiq,vr9"; - - aliases { - serial0 = &asc1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - cpu@0 { - compatible = "mips,mips34Kc"; - }; - }; - - memory@0 { - device_type = "memory"; - }; - - cputemp@0 { - compatible = "lantiq,cputemp"; - }; - - biu@1F800000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,biu", "simple-bus"; - reg = <0x1F800000 0x800000>; - ranges = <0x0 0x1F800000 0x7FFFFF>; - - icu0: icu@80200 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,icu"; - reg = <0x80200 0x28 - 0x80228 0x28 - 0x80250 0x28 - 0x80278 0x28 - 0x802a0 0x28>; - }; - - watchdog@803F0 { - compatible = "lantiq,wdt"; - reg = <0x803F0 0x10>; - }; - }; - - sram@1F000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,sram", "simple-bus"; - reg = <0x1F000000 0x800000>; - ranges = <0x0 0x1F000000 0x7FFFFF>; - - eiu0: eiu@101000 { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "lantiq,eiu-xway"; - reg = <0x101000 0x1000>; - interrupt-parent = <&icu0>; - lantiq,eiu-irqs = <166 135 66 40 41 42>; - }; - - pmu0: pmu@102000 { - compatible = "lantiq,pmu-xway"; - reg = <0x102000 0x1000>; - }; - - cgu0: cgu@103000 { - compatible = "lantiq,cgu-xway"; - reg = <0x103000 0x1000>; - }; - - dcdc@106a00 { - compatible = "lantiq,dcdc-xrx200"; - reg = <0x106a00 0x200>; - }; - - vmmc@107000 { - status = "disabled"; - compatible = "lantiq,vmmc-xway"; - reg = <0x103000 0x400>; - interrupt-parent = <&icu0>; - interrupts = <150 151 152 153 154 155>; - }; - - rcu0: rcu@203000 { - compatible = "lantiq,rcu-xrx200"; - reg = <0x203000 0x1000>; - /* irq for thermal sensor */ - interrupt-parent = <&icu0>; - interrupts = <115>; - }; - - xbar0: xbar@400000 { - compatible = "lantiq,xbar-xway"; - reg = <0x400000 0x1000>; - }; - }; - - fpi@10000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lantiq,fpi", "simple-bus"; - ranges = <0x0 0x10000000 0xEEFFFFF>; - reg = <0x10000000 0xEF00000>; - - localbus@0 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ - 1 0 0x4000000 0x4000010>; /* addsel1 */ - compatible = "lantiq,localbus", "simple-bus"; - }; - - gptu@E100A00 { - compatible = "lantiq,gptu-xway"; - reg = <0xE100A00 0x100>; - interrupt-parent = <&icu0>; - interrupts = <126 127 128 129 130 131>; - }; - - usif: usif@da00000 { - compatible = "lantiq,usif"; - reg = <0xda00000 0x1000000>; - interrupt-parent = <&icu0>; - interrupts = <29 125 107 108 109 110>; - status = "disabled"; - }; - - spi: spi@E100800 { - compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; - reg = <0xE100800 0x100>; - interrupt-parent = <&icu0>; - interrupts = <22 23 24>; - interrupt-names = "spi_rx", "spi_tx", "spi_err", - "spi_frm"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - }; - - gpio: pinmux@E100B10 { - compatible = "lantiq,xrx200-pinctrl"; - #gpio-cells = <2>; - gpio-controller; - reg = <0xE100B10 0xA0>; - }; - - asc1: serial@E100C00 { - compatible = "lantiq,asc"; - reg = <0xE100C00 0x400>; - interrupt-parent = <&icu0>; - interrupts = <112 113 114>; - }; - - deu@E103100 { - compatible = "lantiq,deu-xrx200"; - reg = <0xE103100 0xf00>; - }; - - dma0: dma@E104100 { - compatible = "lantiq,dma-xway"; - reg = <0xE104100 0x800>; - }; - - ebu0: ebu@E105300 { - compatible = "lantiq,ebu-xway"; - reg = <0xE105300 0x100>; - }; - - ifxhcd@E101000 { - status = "disabled"; - compatible = "lantiq,xrx200-usb", "lantiq,ifxhcd-xrx200"; - reg = <0xE101000 0x1000 - 0xE120000 0x3f000>; - interrupt-parent = <&icu0>; - interrupts = <62 91>; - dr_mode = "host"; - }; - - ifxhcd@E106000 { - status = "disabled"; - compatible = "lantiq,xrx200-usb"; - reg = <0xE106000 0x1000>; - interrupt-parent = <&icu0>; - interrupts = <91>; - dr_mode = "host"; - }; - - eth0: eth@E108000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "lantiq,xrx200-net"; - reg = < 0xE108000 0x3000 /* switch */ - 0xE10B100 0x70 /* mdio */ - 0xE10B1D8 0x30 /* mii */ - 0xE10B308 0x30 /* pmac */ - >; - interrupt-parent = <&icu0>; - interrupts = <75 73 72>; - }; - - mei@E116000 { - compatible = "lantiq,mei-xrx200"; - reg = <0xE116000 0x9c>; - interrupt-parent = <&icu0>; - interrupts = <63>; - }; - - ppe@E234000 { - compatible = "lantiq,ppe-xrx200"; - interrupt-parent = <&icu0>; - interrupts = <96>; - }; - - pcie0: pcie@d900000 { - compatible = "lantiq,pcie-xrx200"; - - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - - interrupt-parent = <&icu0>; - interrupts = <161 144>; - - device_type = "pci"; - - gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>; - }; - - pci0: pci@E105400 { - status = "disabled"; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "lantiq,pci-xway"; - bus-range = <0x0 0x0>; - ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ - 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ - reg = <0x7000000 0x8000 /* config space */ - 0xE105400 0x400>; /* pci bridge */ - lantiq,bus-clock = <33333333>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */ - req-mask = <0x1>; /* GNT1 */ - }; - }; - - vdsl { - compatible = "lantiq,vdsl-vrx200"; - }; -}; diff --git a/target/linux/lantiq/image/Makefile b/target/linux/lantiq/image/Makefile index 031c3fcb8..c4419ce62 100644 --- a/target/linux/lantiq/image/Makefile +++ b/target/linux/lantiq/image/Makefile @@ -617,13 +617,29 @@ TARGET_DEVICES += lantiq_easy80920-nor define Device/avm_fritz3370 $(Device/AVM) $(Device/NAND) - BOARD_NAME := FRITZ3370 DEVICE_DTS := FRITZ3370 - DEVICE_TITLE := Fritz!Box WLan - FRITZ3370 - DEVICE_PACKAGES := kmod-ath9k wpad-mini kmod-usb-dwc2 - SUPPORTED_DEVICES += FRITZ3370 + DEVICE_TITLE := AVM Fritz!Box WLan 3370 Rev. 2 + KERNEL_SIZE := 4096k + UBINIZE_OPTS := -E 5 + IMAGES += eva-kernel.bin eva-filesystem.bin + IMAGE/eva-kernel.bin := append-kernel + IMAGE/eva-filesystem.bin := append-ubi + DEVICE_PACKAGES := kmod-ath9k wpad-mini kmod-usb-dwc2 fritz-tffs endef -TARGET_DEVICES += avm_fritz3370 + +define Device/avm_fritz3370-rev2-hynix + $(Device/avm_fritz3370) + DEVICE_DTS := FRITZ3370-REV2-HYNIX + DEVICE_TITLE := AVM Fritz!Box WLan 3370 Rev. 2 (Hynix NAND) +endef +TARGET_DEVICES += avm_fritz3370-rev2-hynix + +define Device/avm_fritz3370-rev2-micron + $(Device/avm_fritz3370) + DEVICE_DTS := FRITZ3370-REV2-MICRON + DEVICE_TITLE := AVM Fritz!Box WLan 3370 Rev. 2 (Micron NAND) +endef +TARGET_DEVICES += avm_fritz3370-rev2-micron define Device/avm_fritz7360sl $(Device/AVM) diff --git a/target/linux/lantiq/patches-4.14/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch b/target/linux/lantiq/patches-4.14/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch index 68643cc05..7fbd97fec 100644 --- a/target/linux/lantiq/patches-4.14/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch +++ b/target/linux/lantiq/patches-4.14/0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch @@ -18,7 +18,7 @@ Signed-off-by: Mathias Kresin --- a/drivers/soc/lantiq/gphy.c +++ b/drivers/soc/lantiq/gphy.c -@@ -56,6 +56,7 @@ static const struct xway_gphy_match_data +@@ -55,6 +55,7 @@ static const struct xway_gphy_match_data }; static const struct of_device_id xway_gphy_match[] = { @@ -26,7 +26,7 @@ Signed-off-by: Mathias Kresin { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data }, { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data }, { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data }, -@@ -130,6 +131,16 @@ static int xway_gphy_of_probe(struct pla +@@ -111,6 +112,16 @@ static int xway_gphy_of_probe(struct pla gphy_fw_name_cfg = of_device_get_match_data(dev); diff --git a/target/linux/lantiq/patches-4.9/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-4.9/0001-MIPS-lantiq-add-pcie-driver.patch deleted file mode 100644 index 91a6acce3..000000000 --- a/target/linux/lantiq/patches-4.9/0001-MIPS-lantiq-add-pcie-driver.patch +++ /dev/null @@ -1,5520 +0,0 @@ -From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:12:28 +0200 -Subject: [PATCH 01/36] MIPS: lantiq: add pcie driver - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/Kconfig | 10 + - arch/mips/lantiq/xway/sysctrl.c | 2 + - arch/mips/pci/Makefile | 2 + - arch/mips/pci/fixup-lantiq-pcie.c | 82 +++ - arch/mips/pci/fixup-lantiq.c | 5 +- - arch/mips/pci/ifxmips_pci_common.h | 57 ++ - arch/mips/pci/ifxmips_pcie.c | 1099 ++++++++++++++++++++++++++++++ - arch/mips/pci/ifxmips_pcie.h | 135 ++++ - arch/mips/pci/ifxmips_pcie_ar10.h | 290 ++++++++ - arch/mips/pci/ifxmips_pcie_msi.c | 392 +++++++++++ - arch/mips/pci/ifxmips_pcie_phy.c | 478 +++++++++++++ - arch/mips/pci/ifxmips_pcie_pm.c | 176 +++++ - arch/mips/pci/ifxmips_pcie_pm.h | 36 + - arch/mips/pci/ifxmips_pcie_reg.h | 1001 +++++++++++++++++++++++++++ - arch/mips/pci/ifxmips_pcie_vr9.h | 271 ++++++++ - arch/mips/pci/pci.c | 25 + - arch/mips/pci/pcie-lantiq.h | 1305 ++++++++++++++++++++++++++++++++++++ - drivers/pci/pcie/aer/Kconfig | 2 +- - include/linux/pci.h | 2 + - include/linux/pci_ids.h | 6 + - 20 files changed, 5374 insertions(+), 2 deletions(-) - create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c - create mode 100644 arch/mips/pci/ifxmips_pci_common.h - create mode 100644 arch/mips/pci/ifxmips_pcie.c - create mode 100644 arch/mips/pci/ifxmips_pcie.h - create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h - create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c - create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c - create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c - create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h - create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h - create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h - create mode 100644 arch/mips/pci/pcie-lantiq.h - ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -17,6 +17,7 @@ config SOC_XWAY - bool "XWAY" - select SOC_TYPE_XWAY - select HW_HAS_PCI -+ select ARCH_SUPPORTS_MSI - - config SOC_FALCON - bool "FALCON" -@@ -47,6 +48,15 @@ config PCI_LANTIQ - bool "PCI Support" - depends on SOC_XWAY && PCI - -+config PCIE_LANTIQ -+ bool "PCIE Support" -+ depends on SOC_XWAY && PCI -+ -+config PCIE_LANTIQ_MSI -+ bool -+ depends on PCIE_LANTIQ && PCI_MSI -+ default y -+ - config XRX200_PHY_FW - bool "XRX200 PHY firmware loader" - depends on SOC_XWAY ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -48,6 +48,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o - obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o - obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o - obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o -+obj-$(CONFIG_PCIE_LANTIQ) += ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o - obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o ---- /dev/null -+++ b/arch/mips/pci/fixup-lantiq-pcie.c -@@ -0,0 +1,74 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_fixup_pcie.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_fixup_pcie.c -+ \ingroup IFX_PCIE -+ \brief PCIe Fixup functions source file -+*/ -+#include -+#include -+#include -+ -+#include -+ -+#include "pcie-lantiq.h" -+ -+static void -+ifx_pcie_fixup_resource(struct pci_dev *dev) -+{ -+ u32 reg; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ printk("%s: fixup host controller %s (%04x:%04x)\n", -+ __func__, pci_name(dev), dev->vendor, dev->device); -+ -+ /* Setup COMMAND register */ -+ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | -+ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; -+ pci_write_config_word(dev, PCI_COMMAND, reg); -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); -+ -+static void -+ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ if (dev->devfn == PCI_DEVFN(0, 0) && -+ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { -+ -+ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); -+ -+ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+ mdelay(10); -+} -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, -+ ifx_pcie_rc_class_early_fixup); -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, -+ ifx_pcie_rc_class_early_fixup); ---- a/arch/mips/pci/fixup-lantiq.c -+++ b/arch/mips/pci/fixup-lantiq.c -@@ -8,12 +8,18 @@ - - #include - #include -+#include "ifxmips_pci_common.h" - - int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL; - int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL; - - int pcibios_plat_dev_init(struct pci_dev *dev) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ ifx_pcie_bios_plat_dev_init(dev); -+#endif -+ - if (ltq_pci_plat_arch_init) - return ltq_pci_plat_arch_init(dev); - -@@ -25,5 +31,10 @@ int pcibios_plat_dev_init(struct pci_dev - - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) - { -+#ifdef CONFIG_PCIE_LANTIQ -+ if (pci_find_capability(dev, PCI_CAP_ID_EXP)) -+ return ifx_pcie_bios_map_irq(dev, slot, pin); -+#endif -+ - return of_irq_parse_and_map_pci(dev, slot, pin); - } ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pci_common.h -@@ -0,0 +1,57 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pci_common.h -+** PROJECT : IFX UEIP -+** MODULES : PCI subsystem -+** -+** DATE : 30 June 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 30 June,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+ -+#ifndef IFXMIPS_PCI_COMMON_H -+#define IFXMIPS_PCI_COMMON_H -+#include -+/*! -+ \defgroup IFX_PCI_COM IFX PCI/PCIe common parts for OS integration -+ \brief PCI/PCIe common parts -+*/ -+ -+/*! -+ \defgroup IFX_PCI_COM_OS OS APIs -+ \ingroup IFX_PCI_COM -+ \brief PCI/PCIe bus driver OS interface functions -+*/ -+/*! -+ \file ifxmips_pci_common.h -+ \ingroup IFX_PCI_COM -+ \brief PCI/PCIe bus driver common OS header file -+*/ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+#define IFX_PCI_CONST -+#else -+#define IFX_PCI_CONST const -+#endif -+#ifdef CONFIG_IFX_PCI -+extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); -+extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev); -+#endif /* COFNIG_IFX_PCI */ -+ -+#ifdef CONFIG_PCIE_LANTIQ -+extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin); -+extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev); -+#endif -+ -+#endif /* IFXMIPS_PCI_COMMON_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie.c -@@ -0,0 +1,1092 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2009 Lei Chuanhua -+ * Copyright (C) 2013 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie.h" -+#include "ifxmips_pcie_reg.h" -+ -+/* Enable 32bit io due to its mem mapped io nature */ -+#define IFX_PCIE_ERROR_INT -+#define IFX_PCIE_IO_32BIT -+ -+#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) -+#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) -+#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) -+#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) -+#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) -+#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) -+#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -+#define IFX_REG_SET_BIT(_f, _r) \ -+ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) -+ -+#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 -+ -+static DEFINE_SPINLOCK(ifx_pcie_lock); -+ -+u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+ -+static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .ir_irq = { -+ .irq = IFX_PCIE_IR, -+ .name = "ifx_pcie_rc0", -+ }, -+ -+ .legacy_irq = { -+ { -+ .irq_bit = PCIE_IRN_INTA, -+ .irq = IFX_PCIE_INTA, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTB, -+ .irq = IFX_PCIE_INTB, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTC, -+ .irq = IFX_PCIE_INTC, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTD, -+ .irq = IFX_PCIE_INTD, -+ }, -+ }, -+ }, -+ -+}; -+ -+void ifx_pcie_debug(const char *fmt, ...) -+{ -+ static char buf[256] = {0}; /* XXX */ -+ va_list ap; -+ -+ va_start(ap, fmt); -+ vsnprintf(buf, sizeof(buf), fmt, ap); -+ va_end(ap); -+ -+ printk("%s", buf); -+} -+ -+ -+static inline int pcie_ltssm_enable(int pcie_port) -+{ -+ int i; -+ -+ /* Enable LTSSM */ -+ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); -+ -+ /* Wait for the link to come up */ -+ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) -+ return 0; -+ udelay(10); -+ } -+ -+ printk("%s link timeout!!!!!\n", __func__); -+ return -1; -+} -+ -+static inline void pcie_status_register_clear(int pcie_port) -+{ -+ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); -+ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_UESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_RESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); -+ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_QSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); -+} -+ -+static inline int ifx_pcie_link_up(int pcie_port) -+{ -+ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; -+} -+ -+ -+static inline void pcie_mem_io_setup(int pcie_port) -+{ -+ u32 reg; -+ /* -+ * BAR[0:1] readonly register -+ * RC contains only minimal BARs for packets mapped to this device -+ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that -+ * reside on the downstream side fo the bridge. -+ */ -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); -+ -+ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); -+ -+ -+#ifdef IFX_PCIE_PREFETCH_MEM_64BIT -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT) -+ | PCIE_PMBL_64BIT_ADDR; -+ IFX_REG_W32(reg, PCIE_PMBL(pcie_port)); -+ -+ /* Must configure upper 32bit */ -+ IFX_REG_W32(0, PCIE_PMBU32(pcie_port)); -+ IFX_REG_W32(0, PCIE_PMLU32(pcie_port)); -+#else -+ /* PCIe_PBML, same as MBML */ -+ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); -+#endif -+ -+ /* IO Address Range */ -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); -+#ifdef IFX_PCIE_IO_32BIT -+ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; -+#endif /* IFX_PCIE_IO_32BIT */ -+ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); -+ -+#ifdef IFX_PCIE_IO_32BIT -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); -+ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); -+ -+#endif /* IFX_PCIE_IO_32BIT */ -+} -+ -+static inline void -+pcie_device_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Device capability register, set up Maximum payload size */ -+ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); -+ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); -+ -+ /* Only available for EP */ -+ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); -+ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); -+ -+ /* Device control and status register */ -+ /* Set Maximum Read Request size for the device as a Requestor */ -+ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); -+ -+ /* -+ * Request size can be larger than the MPS used, but the completions returned -+ * for the read will be bounded by the MPS size. -+ * In our system, Max request size depends on AHB burst size. It is 64 bytes. -+ * but we set it as 128 as minimum one. -+ */ -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) -+ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); -+ -+ /* Enable relaxed ordering, no snoop, and all kinds of errors */ -+ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; -+ -+ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); -+} -+ -+static inline void -+pcie_link_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* -+ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM -+ * L0s is reported during link training via TS1 order set by N_FTS -+ */ -+ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); -+ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; -+ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); -+ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); -+ -+ /* Link control and status register */ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ /* Link Enable, ASPM enabled */ -+ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; -+ -+#ifdef CONFIG_PCIEASPM -+ /* -+ * We use the same physical reference clock that the platform provides on the connector -+ * It paved the way for ASPM to calculate the new exit Latency -+ */ -+ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; -+ reg |= PCIE_LCTLSTS_COM_CLK_CFG; -+ /* -+ * We should disable ASPM by default except that we have dedicated power management support -+ * Enable ASPM will cause the system hangup/instability, performance degration -+ */ -+ reg |= PCIE_LCTLSTS_ASPM_ENABLE; -+#else -+ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; -+#endif /* CONFIG_PCIEASPM */ -+ -+ /* -+ * The maximum size of any completion with data packet is bounded by the MPS setting -+ * in device control register -+ */ -+ -+ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ -+ reg &= ~ PCIE_LCTLSTS_RCB128; -+ -+ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); -+} -+ -+static inline void pcie_error_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* -+ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone -+ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE -+ */ -+ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); -+ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; -+ -+ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); -+ -+ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ -+ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); -+ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); -+ -+ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ -+ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); -+ -+ /* Correctable Error Mask Register, unmask all bits */ -+ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); -+ reg &= ~PCIE_CORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); -+ -+ /* Advanced Error Capabilities and Control Registr */ -+ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); -+ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; -+ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); -+ -+ /* Root Error Command Register, Report all types of errors */ -+ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); -+ reg |= PCIE_RECR_ERR_REPORT_EN; -+ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); -+ -+ /* Clear the Root status register */ -+ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); -+ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); -+} -+ -+static inline void pcie_port_logic_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ -+ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); -+ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); -+ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) -+ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); -+ /* L0s and L1 entry latency */ -+ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); -+ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) -+ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); -+ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); -+ -+ -+ /* Port Link Control Register */ -+ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); -+ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ -+ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); -+ -+ /* Lane Skew Register */ -+ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); -+ /* Enable ACK/NACK and FC */ -+ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); -+ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); -+ -+ /* Symbol Timer Register and Filter Mask Register 1 */ -+ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); -+ -+ /* Default SKP interval is very accurate already, 5us */ -+ /* Enable IO/CFG transaction */ -+ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; -+ /* Disable FC WDT */ -+ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; -+ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); -+ -+ /* Filter Masker Register 2 */ -+ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); -+ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; -+ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); -+ -+ /* VC0 Completion Receive Queue Control Register */ -+ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); -+ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; -+ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); -+ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); -+} -+ -+static inline void pcie_rc_cfg_reg_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Disable LTSSM */ -+ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */ -+ -+ pcie_mem_io_setup(pcie_port); -+ -+ /* XXX, MSI stuff should only apply to EP */ -+ /* MSI Capability: Only enable 32-bit addresses */ -+ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); -+ reg &= ~PCIE_MCAPR_ADDR64_CAP; -+ -+ reg |= PCIE_MCAPR_MSI_ENABLE; -+ -+ /* Disable multiple message */ -+ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); -+ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); -+ -+ -+ /* Enable PME, Soft reset enabled */ -+ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); -+ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; -+ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); -+ -+ /* setup the bus */ -+ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); -+ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); -+ -+ -+ pcie_device_setup(pcie_port); -+ pcie_link_setup(pcie_port); -+ pcie_error_setup(pcie_port); -+ -+ /* Root control and capabilities register */ -+ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); -+ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; -+ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); -+ -+ /* Port VC Capability Register 2 */ -+ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); -+ reg &= ~PCIE_PVC2_VC_ARB_WRR; -+ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; -+ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); -+ -+ /* VC0 Resource Capability Register */ -+ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); -+ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; -+ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); -+ -+ pcie_port_logic_setup(pcie_port); -+} -+ -+static int ifx_pcie_wait_phy_link_up(int pcie_port) -+{ -+#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 /* XXX, tunable */ -+ int i; -+ -+ /* Wait for PHY link is up */ -+ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { -+ if (ifx_pcie_link_up(pcie_port)) { -+ break; -+ } -+ udelay(100); -+ } -+ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { -+ printk(KERN_ERR "%s timeout\n", __func__); -+ return -1; -+ } -+ -+ /* Check data link up or not */ -+ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { -+ printk(KERN_ERR "%s DLL link is still down\n", __func__); -+ return -1; -+ } -+ -+ /* Check Data link active or not */ -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { -+ printk(KERN_ERR "%s DLL is not active\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static inline int pcie_app_loigc_setup(int pcie_port) -+{ -+ /* supress ahb bus errrors */ -+ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); -+ -+ /* Pull PCIe EP out of reset */ -+ pcie_device_rst_deassert(pcie_port); -+ -+ /* Start LTSSM training between RC and EP */ -+ pcie_ltssm_enable(pcie_port); -+ -+ /* Check PHY status after enabling LTSSM */ -+ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) -+ return -1; -+ -+ return 0; -+} -+ -+/* -+ * The numbers below are directly from the PCIe spec table 3-4/5. -+ */ -+static inline void pcie_replay_time_update(int pcie_port) -+{ -+ u32 reg; -+ int nlw; -+ int rtl; -+ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); -+ switch (nlw) { -+ case PCIE_MAX_LENGTH_WIDTH_X1: -+ rtl = 1677; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X2: -+ rtl = 867; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X4: -+ rtl = 462; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X8: -+ rtl = 258; -+ break; -+ default: -+ rtl = 1677; -+ break; -+ } -+ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); -+ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; -+ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); -+ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); -+} -+ -+/* -+ * Table 359 Enhanced Configuration Address Mapping1) -+ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 -+ * Memory Address PCI Express Configuration Space -+ * A[(20+n-1):20] Bus Number 1 < n < 8 -+ * A[19:15] Device Number -+ * A[14:12] Function Number -+ * A[11:8] Extended Register Number -+ * A[7:2] Register Number -+ * A[1:0] Along with size of the access, used to generate Byte Enables -+ * For VR9, only the address bits [22:0] are mapped to the configuration space: -+ * . Address bits [22:20] select the target bus (1-of-8)1) -+ * . Address bits [19:15] select the target device (1-of-32) on the bus -+ * . Address bits [14:12] select the target function (1-of-8) within the device. -+ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space -+ * . Address bits [1:0] define the start byte location within the selected dword. -+ */ -+static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where) -+{ -+ u32 addr; -+ u8 bus; -+ -+ if (!bus_num) { -+ /* type 0 */ -+ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); -+ } else { -+ bus = bus_num; -+ /* type 1, only support 8 buses */ -+ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | -+ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); -+ } -+ return addr; -+} -+ -+static int pcie_valid_config(int pcie_port, int bus, int dev) -+{ -+ /* RC itself */ -+ if ((bus == 0) && (dev == 0)) { -+ return 1; -+ } -+ -+ /* No physical link */ -+ if (!ifx_pcie_link_up(pcie_port)) { -+ return 0; -+ } -+ -+ /* Bus zero only has RC itself -+ * XXX, check if EP will be integrated -+ */ -+ if ((bus == 0) && (dev != 0)) { -+ return 0; -+ } -+ -+ /* Maximum 8 buses supported for VRX */ -+ if (bus > 9) { -+ return 0; -+ } -+ -+ /* -+ * PCIe is PtP link, one bus only supports only one device -+ * except bus zero and PCIe switch which is virtual bus device -+ * The following two conditions really depends on the system design -+ * and attached the device. -+ * XXX, how about more new switch -+ */ -+ if ((bus == 1) && (dev != 0)) { -+ return 0; -+ } -+ -+ if ((bus >= 3) && (dev != 0)) { -+ return 0; -+ } -+ return 1; -+} -+ -+static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg) -+{ -+ return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val) -+{ -+ IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg) -+{ -+ return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val) -+{ -+ IFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+u32 ifx_pcie_bus_enum_read_hack(int where, u32 value) -+{ -+ u32 tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ primary += pcibios_1st_host_bus_nr(); -+ secondary += pcibios_1st_host_bus_nr(); -+ subordinate += pcibios_1st_host_bus_nr(); -+ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); -+ } -+ return tvalue; -+} -+ -+u32 ifx_pcie_bus_enum_write_hack(int where, u32 value) -+{ -+ u32 tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ if (primary > 0 && primary != 0xFF) { -+ primary -= pcibios_1st_host_bus_nr(); -+ } -+ -+ if (secondary > 0 && secondary != 0xFF) { -+ secondary -= pcibios_1st_host_bus_nr(); -+ } -+ if (subordinate > 0 && subordinate != 0xFF) { -+ subordinate -= pcibios_1st_host_bus_nr(); -+ } -+ tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16); -+ } -+ else if (where == PCI_SUBORDINATE_BUS) { -+ u8 subordinate = tvalue & 0xFF; -+ -+ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; -+ tvalue = subordinate; -+ } -+ return tvalue; -+} -+ -+static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 *value) -+{ -+ u32 data = 0; -+ int bus_number = bus->number; -+ static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ if (unlikely(size != 1 && size != 2 && size != 4)){ -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) { -+ bus_number = 0; -+ } -+ -+ /* -+ * PCIe only has a single device connected to it. It is -+ * always device ID 0. Don't bother doing reads for other -+ * device IDs on the first segment. -+ */ -+ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { -+ ret = PCIBIOS_FUNC_NOT_SUPPORTED; -+ goto out; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ *value = 0xffffffff; -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ if (bus_number == 0) { /* RC itself */ -+ u32 t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ } else { -+ u32 addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+ #ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+ #endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } -+ /* To get a correct PCI topology, we have to restore the bus number to OS */ -+ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); -+ -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+out: -+ return ret; -+} -+ -+static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value) -+{ -+ u32 shift; -+ u32 tdata = data; -+ -+ switch (size) { -+ case 1: -+ shift = (where & 0x3) << 3; -+ tdata &= ~(0xffU << shift); -+ tdata |= ((value & 0xffU) << shift); -+ break; -+ case 2: -+ shift = (where & 3) << 3; -+ tdata &= ~(0xffffU << shift); -+ tdata |= ((value & 0xffffU) << shift); -+ break; -+ case 4: -+ tdata = value; -+ break; -+ } -+ return tdata; -+} -+ -+static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn, -+ int where, int size, u32 value) -+{ -+ int bus_number = bus->number; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ u32 tvalue = value; -+ u32 data; -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) { -+ bus_number = 0; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ /* XXX, some PCIe device may need some delay */ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ -+ /* -+ * To configure the correct bus topology using native way, we have to cheat Os so that -+ * it can configure the PCIe hardware correctly. -+ */ -+ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); -+ -+ if (bus_number == 0) { /* RC itself */ -+ u32 t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+ -+ ifx_pcie_rc_cfg_wr(pcie_port, t, data); -+ } else { -+ u32 addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+#endif -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = cpu_to_le32(data); -+#endif -+ ifx_pcie_cfg_wr(pcie_port, addr, data); -+ } -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+out: -+ return ret; -+} -+ -+static struct resource ifx_pcie_io_resource = { -+ .name = "PCIe0 I/O space", -+ .start = PCIE_IO_PHY_BASE, -+ .end = PCIE_IO_PHY_END, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ifx_pcie_mem_resource = { -+ .name = "PCIe0 Memory space", -+ .start = PCIE_MEM_PHY_BASE, -+ .end = PCIE_MEM_PHY_END, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct pci_ops ifx_pcie_ops = { -+ .read = ifx_pcie_read_config, -+ .write = ifx_pcie_write_config, -+}; -+ -+static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { -+ { -+ .pcic = { -+ .pci_ops = &ifx_pcie_ops, -+ .mem_resource = &ifx_pcie_mem_resource, -+ .io_resource = &ifx_pcie_io_resource, -+ }, -+ .port = IFX_PCIE_PORT0, -+ }, -+}; -+ -+#ifdef IFX_PCIE_ERROR_INT -+ -+static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) -+{ -+ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; -+ int pcie_port = ctrl->port; -+ u32 reg; -+ -+ pr_debug("PCIe RC error intr %d\n", irq); -+ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); -+ reg &= PCIE_RC_CORE_COMBINED_INT; -+ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); -+ -+ return IRQ_HANDLED; -+} -+ -+static int -+pcie_rc_core_int_init(int pcie_port) -+{ -+ int ret; -+ -+ /* Enable core interrupt */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); -+ -+ /* Clear it first */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); -+ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0, -+ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); -+ if (ret) -+ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); -+ -+ return ret; -+} -+#endif -+ -+int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ u32 irq_bit = 0; -+ int irq = 0; -+ struct ifx_pci_controller *ctrl = dev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ printk("%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); -+ -+ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { -+ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); -+ return -1; -+ } -+ -+ /* Pin index so minus one */ -+ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; -+ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); -+ printk("%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); -+ return irq; -+} -+ -+int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) -+{ -+ u16 config; -+#ifdef IFX_PCIE_ERROR_INT -+ u32 dconfig; -+ int pos; -+#endif -+ -+ /* Enable reporting System errors and parity errors on all devices */ -+ /* Enable parity checking and error reporting */ -+ pci_read_config_word(dev, PCI_COMMAND, &config); -+ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_FAST_BACK*/; -+ pci_write_config_word(dev, PCI_COMMAND, config); -+ -+ if (dev->subordinate) { -+ /* Set latency timers on sub bridges */ -+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ -+ /* More bridge error detection */ -+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); -+ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; -+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); -+ } -+#ifdef IFX_PCIE_ERROR_INT -+ /* Enable the PCIe normal error reporting */ -+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); -+ if (pos) { -+ -+ /* Disable system error generation in response to error messages */ -+ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); -+ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); -+ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); -+ -+ /* Clear PCIE Capability's Device Status */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); -+ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); -+ -+ /* Update Device Control */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); -+ /* Correctable Error Reporting */ -+ config |= PCI_EXP_DEVCTL_CERE; -+ /* Non-Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_NFERE; -+ /* Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_FERE; -+ /* Unsupported Request */ -+ config |= PCI_EXP_DEVCTL_URRE; -+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); -+ } -+ -+ /* Find the Advanced Error Reporting capability */ -+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); -+ if (pos) { -+ /* Clear Uncorrectable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); -+ /* Enable reporting of all uncorrectable errors */ -+ /* Uncorrectable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); -+ /* -+ * Leave severity at HW default. This only controls if -+ * errors are reported as uncorrectable or -+ * correctable, not if the error is reported. -+ */ -+ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ -+ /* Clear Correctable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); -+ /* Enable reporting of all correctable errors */ -+ /* Correctable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); -+ /* Advanced Error Capabilities */ -+ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); -+ /* ECRC Generation Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_GENC) { -+ dconfig |= PCI_ERR_CAP_ECRC_GENE; -+ } -+ /* ECRC Check Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) { -+ dconfig |= PCI_ERR_CAP_ECRC_CHKE; -+ } -+ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); -+ -+ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ -+ /* Enable Root Port's interrupt in response to error messages */ -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, -+ PCI_ERR_ROOT_CMD_COR_EN | -+ PCI_ERR_ROOT_CMD_NONFATAL_EN | -+ PCI_ERR_ROOT_CMD_FATAL_EN); -+ /* Clear the Root status register */ -+ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); -+ } -+#endif /* IFX_PCIE_ERROR_INT */ -+ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ -+ pcie_set_readrq(dev, 128); -+ return 0; -+} -+ -+static int -+pcie_rc_initialize(int pcie_port) -+{ -+ int i; -+#define IFX_PCIE_PHY_LOOP_CNT 5 -+ -+ pcie_rcu_endian_setup(pcie_port); -+ -+ pcie_ep_gpio_rst_init(pcie_port); -+ -+ /* -+ * XXX, PCIe elastic buffer bug will cause not to be detected. One more -+ * reset PCIe PHY will solve this issue -+ */ -+ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { -+ /* Disable PCIe PHY Analog part for sanity check */ -+ pcie_phy_pmu_disable(pcie_port); -+ -+ pcie_phy_rst_assert(pcie_port); -+ pcie_phy_rst_deassert(pcie_port); -+ -+ /* Make sure PHY PLL is stable */ -+ udelay(20); -+ -+ /* PCIe Core reset enabled, low active, sw programmed */ -+ pcie_core_rst_assert(pcie_port); -+ -+ /* Put PCIe EP in reset status */ -+ pcie_device_rst_assert(pcie_port); -+ -+ /* PCI PHY & Core reset disabled, high active, sw programmed */ -+ pcie_core_rst_deassert(pcie_port); -+ -+ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ -+ pcie_phy_clock_mode_setup(pcie_port); -+ -+ /* Enable PCIe PHY and Clock */ -+ pcie_core_pmu_setup(pcie_port); -+ -+ /* Clear status registers */ -+ pcie_status_register_clear(pcie_port); -+ -+#ifdef CONFIG_PCI_MSI -+ pcie_msi_init(pcie_port); -+#endif /* CONFIG_PCI_MSI */ -+ pcie_rc_cfg_reg_setup(pcie_port); -+ -+ /* Once link is up, break out */ -+ if (pcie_app_loigc_setup(pcie_port) == 0) -+ break; -+ } -+ if (i >= IFX_PCIE_PHY_LOOP_CNT) { -+ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); -+ return -EIO; -+ } -+ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ -+ pcie_replay_time_update(pcie_port); -+ return 0; -+} -+ -+static int __init ifx_pcie_bios_init(void) -+{ -+ void __iomem *io_map_base; -+ int pcie_port; -+ int startup_port; -+ -+ /* Enable AHB Master/ Slave */ -+ pcie_ahb_pmu_setup(); -+ -+ startup_port = IFX_PCIE_PORT0; -+ -+ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ -+ if (pcie_rc_initialize(pcie_port) == 0) { -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -+ __func__, PCIE_CFG_PORT_TO_BASE(pcie_port)); -+ /* Otherwise, warning will pop up */ -+ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); -+ if (io_map_base == NULL) { -+ IFX_PCIE_PRINT(PCIE_MSG_ERR, "%s io space ioremap failed\n", __func__); -+ return -ENOMEM; -+ } -+ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ -+ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); -+ /* XXX, clear error status */ -+ -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: mem_resource 0x%p, io_resource 0x%p\n", -+ __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, -+ &ifx_pcie_controller[pcie_port].pcic.io_resource); -+ -+ #ifdef IFX_PCIE_ERROR_INT -+ pcie_rc_core_int_init(pcie_port); -+ #endif /* IFX_PCIE_ERROR_INT */ -+ } -+ } -+ -+ return 0; -+} -+arch_initcall(ifx_pcie_bios_init); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon builtin PCIe RC module"); -+MODULE_DESCRIPTION("Infineon builtin PCIe RC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie.h -@@ -0,0 +1,135 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_H -+#define IFXMIPS_PCIE_H -+#include -+#include -+#include -+#include -+#include "ifxmips_pci_common.h" -+#include "ifxmips_pcie_reg.h" -+ -+/*! -+ \defgroup IFX_PCIE PCI Express bus driver module -+ \brief PCI Express IP module support VRX200 -+*/ -+ -+/*! -+ \defgroup IFX_PCIE_OS OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module common header file -+*/ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+#define CONFIG_VR9 -+ -+#ifdef CONFIG_VR9 -+#include "ifxmips_pcie_vr9.h" -+#elif defined (CONFIG_AR10) -+#include "ifxmips_pcie_ar10.h" -+#else -+#error "PCIE: platform not defined" -+#endif /* CONFIG_VR9 */ -+ -+#endif /* IFXMIPS_PCIE_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_ar10.h -@@ -0,0 +1,290 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+/*! -+ \file ifxmips_pcie_ar10.h -+ \ingroup IFX_PCIE -+ \brief PCIe RC driver ar10 specific file -+*/ -+ -+#ifndef IFXMIPS_PCIE_AR10_H -+#define IFXMIPS_PCIE_AR10_H -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+ -+/* Project header file */ -+#include -+#include -+#include -+#include -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ ifx_ebu_led_enable(); -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 1); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 1); -+ } -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ /* XXX, moved to CGU to control AHBM */ -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ /* Inbound, big endian */ -+ reg |= IFX_RCU_BE_AHB4S; -+ if (pcie_port == 0) { -+ reg |= IFX_RCU_BE_PCIE0M; -+ -+ #ifdef CONFIG_IFX_PCIE_HW_SWAP -+ /* Outbound, software swap needed */ -+ reg |= IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE0S; -+ #else -+ /* Outbound little endian */ -+ reg &= ~IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE0S; -+ #endif -+ } -+ else { -+ reg |= IFX_RCU_BE_PCIE1M; -+ #ifdef CONFIG_IFX_PCIE1_HW_SWAP -+ /* Outbound, software swap needed */ -+ reg |= IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE1S; -+ #else -+ /* Outbound little endian */ -+ reg &= ~IFX_RCU_BE_AHB3M; -+ reg &= ~IFX_RCU_BE_PCIE1S; -+ #endif -+ } -+ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ if (pcie_port == 0) { /* XXX, should use macro*/ -+ PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_phy_pmu_disable(int pcie_port) -+{ -+ if (pcie_port == 0) { /* XXX, should use macro*/ -+ PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ } -+ else { -+ PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ } -+} -+ -+static inline void pcie_pdi_big_endian(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ if (pcie_port == 0) { -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_BE_PCIE0_PDI; -+ } -+ else { -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_BE_PCIE1_PDI; -+ } -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ /* Enable PDI to access PCIe PHY register */ -+ PDI0_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PDI1_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_core_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ -+ /* Reset Core, bit 22 */ -+ if (pcie_port == 0) { -+ reg |= 0x00400000; -+ } -+ else { -+ reg |= 0x08000000; /* Bit 27 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_core_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg &= ~0x00400000; /* bit 22 */ -+ } -+ else { -+ reg &= ~0x08000000; /* Bit 27 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg |= 0x00001000; /* Bit 12 */ -+ } -+ else { -+ reg |= 0x00002000; /* Bit 13 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ if (pcie_port == 0) { -+ reg &= ~0x00001000; /* Bit 12 */ -+ } -+ else { -+ reg &= ~0x00002000; /* Bit 13 */ -+ } -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 0); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 0); -+ } -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ if (pcie_port == 0) { -+ ifx_ebu_led_set_data(11, 1); -+ } -+ else { -+ ifx_ebu_led_set_data(12, 1); -+ } -+ ifx_ebu_led_disable(); -+} -+ -+static inline void pcie_core_pmu_setup(int pcie_port) -+{ -+ if (pcie_port == 0) { -+ PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline void pcie_msi_init(int pcie_port) -+{ -+ pcie_msi_pic_init(pcie_port); -+ if (pcie_port == 0) { -+ MSI0_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+ else { -+ MSI1_PMU_SETUP(IFX_PMU_ENABLE); -+ } -+} -+ -+static inline u32 -+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -+{ -+ u32 tbus_number = bus_number; -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+ } -+#endif /* CONFIG_IFX_PCI */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ } -+ #endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_IFX_PCIE_2ND_CORE -+ if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_AR10_H */ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_msi.c -@@ -0,0 +1,392 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_msi.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCI MSI sub module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe MSI Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 02 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_MSI MSI OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_msi.c -+ \ingroup IFX_PCIE -+ \brief PCIe MSI OS interface file -+*/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie_reg.h" -+#include "ifxmips_pcie.h" -+ -+#define IFX_MSI_IRQ_NUM 16 -+ -+enum { -+ IFX_PCIE_MSI_IDX0 = 0, -+ IFX_PCIE_MSI_IDX1, -+ IFX_PCIE_MSI_IDX2, -+ IFX_PCIE_MSI_IDX3, -+}; -+ -+typedef struct ifx_msi_irq_idx { -+ const int irq; -+ const int idx; -+}ifx_msi_irq_idx_t; -+ -+struct ifx_msi_pic { -+ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; -+ volatile u32 pic_endian; /* 0x40 */ -+}; -+typedef struct ifx_msi_pic *ifx_msi_pic_t; -+ -+typedef struct ifx_msi_irq { -+ const volatile ifx_msi_pic_t msi_pic_p; -+ const u32 msi_phy_base; -+ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; -+ /* -+ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is -+ * in use. -+ */ -+ u16 msi_free_irq_bitmask; -+ -+ /* -+ * Each bit in msi_multiple_irq_bitmask tells that the device using -+ * this bit in msi_free_irq_bitmask is also using the next bit. This -+ * is used so we can disable all of the MSI interrupts when a device -+ * uses multiple. -+ */ -+ u16 msi_multiple_irq_bitmask; -+}ifx_msi_irq_t; -+ -+static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, -+ .msi_phy_base = PCIE_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ }, -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, -+ .msi_phy_base = PCIE1_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ -+ }, -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+}; -+ -+/* -+ * This lock controls updates to msi_free_irq_bitmask, -+ * msi_multiple_irq_bitmask and pic register settting -+ */ -+static DEFINE_SPINLOCK(ifx_pcie_msi_lock); -+ -+void pcie_msi_pic_init(int pcie_port) -+{ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; -+ spin_unlock(&ifx_pcie_msi_lock); -+} -+ -+/** -+ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+ * \brief Called when a driver request MSI interrupts instead of the -+ * legacy INT A-D. This routine will allocate multiple interrupts -+ * for MSI devices that support them. A device can override this by -+ * programming the MSI control bits [6:4] before calling -+ * pci_enable_msi(). -+ * -+ * \param[in] pdev Device requesting MSI interrupts -+ * \param[in] desc MSI descriptor -+ * -+ * \return -EINVAL Invalid pcie root port or invalid msi bit -+ * \return 0 OK -+ * \ingroup IFX_PCIE_MSI -+ */ -+int -+arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+{ -+ int irq, pos; -+ u16 control; -+ int irq_idx; -+ int irq_step; -+ int configured_private_bits; -+ int request_private_bits; -+ struct msi_msg msg; -+ u16 search_mask; -+ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); -+ -+ /* XXX, skip RC MSI itself */ -+ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* -+ * Read the MSI config to figure out how many IRQs this device -+ * wants. Most devices only want 1, which will give -+ * configured_private_bits and request_private_bits equal 0. -+ */ -+ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); -+ -+ /* -+ * If the number of private bits has been configured then use -+ * that value instead of the requested number. This gives the -+ * driver the chance to override the number of interrupts -+ * before calling pci_enable_msi(). -+ */ -+ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; -+ if (configured_private_bits == 0) { -+ /* Nothing is configured, so use the hardware requested size */ -+ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; -+ } -+ else { -+ /* -+ * Use the number of configured bits, assuming the -+ * driver wanted to override the hardware request -+ * value. -+ */ -+ request_private_bits = configured_private_bits; -+ } -+ -+ /* -+ * The PCI 2.3 spec mandates that there are at most 32 -+ * interrupts. If this device asks for more, only give it one. -+ */ -+ if (request_private_bits > 5) { -+ request_private_bits = 0; -+ } -+again: -+ /* -+ * The IRQs have to be aligned on a power of two based on the -+ * number being requested. -+ */ -+ irq_step = (1 << request_private_bits); -+ -+ /* Mask with one bit for each IRQ */ -+ search_mask = (1 << irq_step) - 1; -+ -+ /* -+ * We're going to search msi_free_irq_bitmask_lock for zero -+ * bits. This represents an MSI interrupt number that isn't in -+ * use. -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { -+ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; -+ break; -+ } -+ } -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ /* Make sure the search for available interrupts didn't fail */ -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ if (request_private_bits) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " -+ "interrupts, trying just one", __func__, 1 << request_private_bits); -+ request_private_bits = 0; -+ goto again; -+ } -+ else { -+ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ } -+ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; -+ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); -+ -+ /* -+ * Initialize MSI. This has to match the memory-write endianess from the device -+ * Address bits [23:12] -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | -+ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | -+ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ -+ /* Enable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", -+ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); -+ -+ /* Update the number of IRQs the device has available to it */ -+ control &= ~PCI_MSI_FLAGS_QSIZE; -+ control |= (request_private_bits << 4); -+ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); -+ -+ set_irq_msi(irq, desc); -+ msg.address_hi = 0x0; -+ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; -+ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); -+ -+ write_msi_msg(irq, &msg); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+ return 0; -+} -+ -+static int -+pcie_msi_irq_to_port(unsigned int irq, int *port) -+{ -+ int ret = 0; -+ -+ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || -+ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { -+ *port = IFX_PCIE_PORT0; -+ } -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || -+ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { -+ *port = IFX_PCIE_PORT1; -+ } -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ else { -+ printk(KERN_ERR "%s: Attempted to teardown illegal " -+ "MSI interrupt (%d)\n", __func__, irq); -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+/** -+ * \fn void arch_teardown_msi_irq(unsigned int irq) -+ * \brief Called when a device no longer needs its MSI interrupts. All -+ * MSI interrupts for the device are freed. -+ * -+ * \param irq The devices first irq number. There may be multple in sequence. -+ * \return none -+ * \ingroup IFX_PCIE_MSI -+ */ -+void -+arch_teardown_msi_irq(unsigned int irq) -+{ -+ int pos; -+ int number_irqs; -+ u16 bitmask; -+ int pcie_port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); -+ -+ BUG_ON(irq > INT_NUM_IM4_IRL31); -+ -+ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { -+ return; -+ } -+ -+ /* Shift the mask to the correct bit location, not always correct -+ * Probally, the first match will be chosen. -+ */ -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { -+ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) -+ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { -+ break; -+ } -+ } -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); -+ return; -+ } -+ spin_lock(&ifx_pcie_msi_lock); -+ /* Disable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); -+ spin_unlock(&ifx_pcie_msi_lock); -+ /* -+ * Count the number of IRQs we need to free by looking at the -+ * msi_multiple_irq_bitmask. Each bit set means that the next -+ * IRQ is also owned by this device. -+ */ -+ number_irqs = 0; -+ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && -+ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { -+ number_irqs++; -+ } -+ number_irqs++; -+ -+ /* Mask with one bit for each IRQ */ -+ bitmask = (1 << number_irqs) - 1; -+ -+ bitmask <<= pos; -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { -+ printk(KERN_ERR "%s: Attempted to teardown MSI " -+ "interrupt (%d) not in use\n", __func__, irq); -+ return; -+ } -+ /* Checks are done, update the in use bitmask */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); -+ spin_unlock(&ifx_pcie_msi_lock); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+} -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); -+MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_phy.c -@@ -0,0 +1,478 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_phy.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe PHY sub module -+** -+** DATE : 14 May 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 14 May,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_phy.c -+ \ingroup IFX_PCIE -+ \brief PCIe PHY PLL register programming source file -+*/ -+#include -+#include -+#include -+#include -+ -+#include "ifxmips_pcie_reg.h" -+#include "ifxmips_pcie.h" -+ -+/* PCIe PDI only supports 16 bit operation */ -+ -+#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ -+ ((*(volatile u16 *) (__addr)) = (__data)) -+ -+#define IFX_PCIE_PHY_REG_READ16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ -+ u16 read_data; \ -+ u16 write_data; \ -+ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ -+ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ -+ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ -+} while (0) -+ -+#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ -+ -+//#define IFX_PCI_PHY_REG_DUMP -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+static void -+pcie_phy_reg_dump(int pcie_port) -+{ -+ printk("PLL REGFILE\n"); -+ printk("PCIE_PHY_PLL_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL4 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL5 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL6 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port))); -+ printk("PCIE_PHY_PLL_CTRL7 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_PLL_A_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port))); -+ printk("PCIE_PHY_PLL_STATUS 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port))); -+ -+ printk("TX1 REGFILE\n"); -+ printk("PCIE_PHY_TX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX1_CTRL3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port))); -+ printk("PCIE_PHY_TX1_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX1_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port))); -+ printk("PCIE_PHY_TX1_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port))); -+ -+ printk("TX2 REGFILE\n"); -+ printk("PCIE_PHY_TX2_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX2_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX2_A_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port))); -+ printk("PCIE_PHY_TX2_A_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port))); -+ printk("PCIE_PHY_TX2_MOD3 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port))); -+ -+ printk("RX1 REGFILE\n"); -+ printk("PCIE_PHY_RX1_CTRL1 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port))); -+ printk("PCIE_PHY_RX1_CTRL2 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port))); -+ printk("PCIE_PHY_RX1_CDR 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port))); -+ printk("PCIE_PHY_RX1_EI 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port))); -+ printk("PCIE_PHY_RX1_A_CTRL 0x%04x\n", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port))); -+} -+#endif /* IFX_PCI_PHY_REG_DUMP */ -+ -+static void -+pcie_phy_comm_setup(int pcie_port) -+{ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* Improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* Reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+} -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+static void -+pcie_phy_36mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE -+static void -+pcie_phy_36mhz_ssc_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* Increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* Force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* Predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); -+ -+ /* improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE -+static void -+pcie_phy_25mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); -+ -+ /* en_ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE -+static void -+pcie_phy_100mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Initial PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ -+ -+static int -+pcie_phy_wait_startup_ready(int pcie_port) -+{ -+ int i; -+ -+ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { -+ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { -+ break; -+ } -+ udelay(10); -+ } -+ if (i >= IFX_PCIE_PLL_TIMEOUT) { -+ printk(KERN_ERR "%s PLL Link timeout\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static void -+pcie_phy_load_enable(int pcie_port, int slice) -+{ -+ /* Set the load_en of tx/rx slice to '1' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_disable(int pcie_port, int slice) -+{ -+ /* set the load_en of tx/rx slice to '0' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_war(int pcie_port) -+{ -+ int slice; -+ -+ for (slice = 1; slice < 4; slice++) { -+ pcie_phy_load_enable(pcie_port, slice); -+ udelay(1); -+ pcie_phy_load_disable(pcie_port, slice); -+ } -+} -+ -+static void -+pcie_phy_tx2_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void -+pcie_phy_tx1_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void -+pcie_phy_tx_modulation_war(int pcie_port) -+{ -+ int i; -+ -+#define PCIE_PHY_MODULATION_NUM 5 -+ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { -+ pcie_phy_tx2_modulation(pcie_port); -+ pcie_phy_tx1_modulation(pcie_port); -+ } -+#undef PCIE_PHY_MODULATION_NUM -+} -+ -+void -+pcie_phy_clock_mode_setup(int pcie_port) -+{ -+ pcie_pdi_big_endian(pcie_port); -+ -+ /* Enable PDI to access PCIe PHY register */ -+ pcie_pdi_pmu_enable(pcie_port); -+ -+ /* Configure PLL and PHY clock */ -+ pcie_phy_comm_setup(pcie_port); -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ pcie_phy_36mhz_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) -+ pcie_phy_36mhz_ssc_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) -+ pcie_phy_25mhz_mode_setup(pcie_port); -+#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) -+ pcie_phy_100mhz_mode_setup(pcie_port); -+#else -+ #error "PCIE PHY Clock Mode must be chosen first!!!!" -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+ /* Enable PCIe PHY and make PLL setting take effect */ -+ pcie_phy_pmu_enable(pcie_port); -+ -+ /* Check if we are in startup_ready status */ -+ pcie_phy_wait_startup_ready(pcie_port); -+ -+ pcie_phy_load_war(pcie_port); -+ -+ /* Apply TX modulation workarounds */ -+ pcie_phy_tx_modulation_war(pcie_port); -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+} -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_pm.c -@@ -0,0 +1,176 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_pm.c -+** PROJECT : IFX UEIP -+** MODULES : PCIE Root Complex Driver -+** -+** DATE : 21 Dec 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIE Root Complex Driver Power Managment -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 Dec,2009 Lei Chuanhua First UEIP release -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_PM Power Management functions -+ \ingroup IFX_PCIE -+ \brief IFX PCIE Root Complex Driver power management functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_pm.c -+ \ingroup IFX_PCIE -+ \brief source file for PCIE Root Complex Driver Power Management -+*/ -+ -+#ifndef EXPORT_SYMTAB -+#define EXPORT_SYMTAB -+#endif -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif /* AUTOCONF_INCLUDED */ -+#include -+#include -+#include -+#include -+#include -+ -+/* Project header */ -+#include -+#include -+#include -+#include -+#include "ifxmips_pcie_pm.h" -+ -+/** -+ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) -+ * \brief the callback function to request pmcu state in the power management hardware-dependent module -+ * -+ * \param pmcuState This parameter is a PMCU state. -+ * -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState) -+{ -+ switch(pmcuState) -+ { -+ case IFX_PMCU_STATE_D0: -+ return IFX_PMCU_RETURN_SUCCESS; -+ case IFX_PMCU_STATE_D1: // Not Applicable -+ return IFX_PMCU_RETURN_DENIED; -+ case IFX_PMCU_STATE_D2: // Not Applicable -+ return IFX_PMCU_RETURN_DENIED; -+ case IFX_PMCU_STATE_D3: // Module clock gating and Power gating -+ return IFX_PMCU_RETURN_SUCCESS; -+ default: -+ return IFX_PMCU_RETURN_DENIED; -+ } -+} -+ -+/** -+ * \fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) -+ * \brief the callback function to get pmcu state in the power management hardware-dependent module -+ -+ * \param pmcuState Pointer to return power state. -+ * -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \return IFX_PMCU_RETURN_DENIED Not allowed to operate power state -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule -+ * -+ * \param pmcuModule Module -+ * \param newState New state -+ * \param oldState Old state -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+ * \brief Apply all callbacks registered to be executed before a state change for pmcuModule -+ * -+ * \param pmcuModule Module -+ * \param newState New state -+ * \param oldState Old state -+ * \return IFX_PMCU_RETURN_SUCCESS Set Power State successfully -+ * \return IFX_PMCU_RETURN_ERROR Failed to set power state. -+ * \ingroup IFX_PCIE_PM -+ */ -+static IFX_PMCU_RETURN_t -+ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState) -+{ -+ return IFX_PMCU_RETURN_SUCCESS; -+} -+ -+/** -+ * \fn static void ifx_pcie_pmcu_init(void) -+ * \brief Register with central PMCU module -+ * \return none -+ * \ingroup IFX_PCIE_PM -+ */ -+void -+ifx_pcie_pmcu_init(void) -+{ -+ IFX_PMCU_REGISTER_t pmcuRegister; -+ -+ /* XXX, hook driver context */ -+ -+ /* State function register */ -+ memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t)); -+ pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; -+ pmcuRegister.pmcuModuleNr = 0; -+ pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change; -+ pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get; -+ pmcuRegister.pre = ifx_pcie_pmcu_prechange; -+ pmcuRegister.post= ifx_pcie_pmcu_postchange; -+ ifx_pmcu_register(&pmcuRegister); -+} -+ -+/** -+ * \fn static void ifx_pcie_pmcu_exit(void) -+ * \brief Unregister with central PMCU module -+ * -+ * \return none -+ * \ingroup IFX_PCIE_PM -+ */ -+void -+ifx_pcie_pmcu_exit(void) -+{ -+ IFX_PMCU_REGISTER_t pmcuUnRegister; -+ -+ /* XXX, hook driver context */ -+ -+ pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE; -+ pmcuUnRegister.pmcuModuleNr = 0; -+ ifx_pmcu_unregister(&pmcuUnRegister); -+} -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_pm.h -@@ -0,0 +1,36 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_pm.h -+** PROJECT : IFX UEIP -+** MODULES : PCIe Root Complex Driver -+** -+** DATE : 21 Dec 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver Power Managment -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 Dec,2009 Lei Chuanhua First UEIP release -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_pm.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe Root Complex Driver Power Management -+*/ -+ -+#ifndef IFXMIPS_PCIE_PM_H -+#define IFXMIPS_PCIE_PM_H -+ -+void ifx_pcie_pmcu_init(void); -+void ifx_pcie_pmcu_exit(void); -+ -+#endif /* IFXMIPS_PCIE_PM_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_reg.h -@@ -0,0 +1,1001 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#endif /* IFXMIPS_PCIE_REG_H */ -+ ---- /dev/null -+++ b/arch/mips/pci/ifxmips_pcie_vr9.h -@@ -0,0 +1,269 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+/*! -+ \file ifxmips_pcie_vr9.h -+ \ingroup IFX_PCIE -+ \brief PCIe RC driver vr9 specific file -+*/ -+ -+#ifndef IFXMIPS_PCIE_VR9_H -+#define IFXMIPS_PCIE_VR9_H -+ -+#include -+#include -+ -+#include -+#include -+ -+#define IFX_PCIE_GPIO_RESET 494 -+ -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+#define ALT0 ((volatile u32*)(IFX_GPIO + 0x007c)) -+#define ALT1 ((volatile u32*)(IFX_GPIO + 0x0080)) -+#define OD ((volatile u32*)(IFX_GPIO + 0x0084)) -+#define DIR ((volatile u32*)(IFX_GPIO + 0x0078)) -+#define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ -+ gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); -+ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -+ gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -+ -+/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+ ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ /* Enable AHB bus master/slave */ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "ahb"); -+ clk_enable(clk); -+ -+ //AHBM_PMU_SETUP(IFX_PMU_ENABLE); -+ //AHBS_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "phy"); -+ clk_enable(clk); -+ -+ //PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_phy_pmu_disable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "phy"); -+ clk_disable(clk); -+ -+// PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+} -+ -+static inline void pcie_pdi_big_endian(int pcie_port) -+{ -+ u32 reg; -+ -+ /* SRAM2PDI endianness control. */ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+ /* Config AHB->PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ /* Enable PDI to access PCIe PHY register */ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "pdi"); -+ clk_enable(clk); -+ //PDI_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_core_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ -+ /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly */ -+ reg |= 0x00400000; -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_core_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ /* Reset PCIe PHY & Core, bit 22 */ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg &= ~0x00400000; -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_assert(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg |= 0x00001000; /* Bit 12 */ -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_phy_rst_deassert(int pcie_port) -+{ -+ u32 reg; -+ -+ /* Make sure one micro-second delay */ -+ udelay(1); -+ -+ reg = IFX_REG_R32(IFX_RCU_RST_REQ); -+ reg &= ~0x00001000; /* Bit 12 */ -+ IFX_REG_W32(reg, IFX_RCU_RST_REQ); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ gpio_set_value(IFX_PCIE_GPIO_RESET, 0); -+// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -+// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -+ //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -+} -+ -+static inline void pcie_core_pmu_setup(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("1d900000.pcie", "ctl"); -+ clk_enable(clk); -+ clk = clk_get_sys("1d900000.pcie", "bus"); -+ clk_enable(clk); -+ -+ /* PCIe Core controller enabled */ -+// PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ -+ /* Enable PCIe L0 Clock */ -+// PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline void pcie_msi_init(int pcie_port) -+{ -+ struct clk *clk; -+ pcie_msi_pic_init(pcie_port); -+ clk = clk_get_sys("ltq_pcie", "msi"); -+ clk_enable(clk); -+// MSI_PMU_SETUP(IFX_PMU_ENABLE); -+} -+ -+static inline u32 -+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port) -+{ -+ u32 tbus_number = bus_number; -+ -+#ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_PCI_LANTIQ */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_PCI_LANTIQ */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ ---- a/arch/mips/pci/pci-legacy.c -+++ b/arch/mips/pci/pci-legacy.c -@@ -300,3 +300,30 @@ char *__init pcibios_setup(char *str) - return pcibios_plat_setup(str); - return str; - } -+ -+int pcibios_host_nr(void) -+{ -+ int count = 0; -+ struct pci_controller *hose; -+ list_for_each_entry(hose, &controllers, list) { -+ count++; -+ } -+ return count; -+} -+EXPORT_SYMBOL(pcibios_host_nr); -+ -+int pcibios_1st_host_bus_nr(void) -+{ -+ int bus_nr = 0; -+ struct pci_controller *hose; -+ -+ hose = list_first_entry_or_null(&controllers, struct pci_controller, list); -+ -+ if (hose != NULL) { -+ if (hose->bus != NULL) { -+ bus_nr = hose->bus->number + 1; -+ } -+ } -+ return bus_nr; -+} -+EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq.h -@@ -0,0 +1,1305 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+#include -+#include -+#include -+#include -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+//#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ if (g_pcie_debug_flag & (_m)) { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+ } \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define IFX_PCIE_GPIO_RESET 38 -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "ahb"); -+ clk_enable(clk); -+ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "phy"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1<PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "pdi"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1< 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_PCI_LANTIQ */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_PCI_LANTIQ */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_PCI_LANTIQ -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ ---- a/drivers/pci/pcie/aer/Kconfig -+++ b/drivers/pci/pcie/aer/Kconfig -@@ -19,6 +19,7 @@ config PCIEAER - config PCIE_ECRC - bool "PCI Express ECRC settings control" - depends on PCIEAER -+ default n - help - Used to override firmware/bios settings for PCI Express ECRC - (transaction layer end-to-end CRC checking). ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -1250,6 +1250,8 @@ void pci_walk_bus(struct pci_bus *top, i - void *userdata); - int pci_cfg_space_size(struct pci_dev *dev); - unsigned char pci_bus_max_busnr(struct pci_bus *bus); -+int pcibios_host_nr(void); -+int pcibios_1st_host_bus_nr(void); - void pci_setup_bridge(struct pci_bus *bus); - resource_size_t pcibios_window_alignment(struct pci_bus *bus, - unsigned long type); ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -1056,6 +1056,12 @@ - #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 - #define PCI_DEVICE_ID_SGI_IOC4 0x100a - -+#define PCI_VENDOR_ID_INFINEON 0x15D1 -+#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -+#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -+#define PCI_VENDOR_ID_LANTIQ 0x1BEF -+#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 -+ - #define PCI_VENDOR_ID_WINBOND 0x10ad - #define PCI_DEVICE_ID_WINBOND_82C105 0x0105 - #define PCI_DEVICE_ID_WINBOND_83C553 0x0565 diff --git a/target/linux/lantiq/patches-4.9/0004-MIPS-lantiq-add-atm-hack.patch b/target/linux/lantiq/patches-4.9/0004-MIPS-lantiq-add-atm-hack.patch deleted file mode 100644 index 479decd6a..000000000 --- a/target/linux/lantiq/patches-4.9/0004-MIPS-lantiq-add-atm-hack.patch +++ /dev/null @@ -1,500 +0,0 @@ -From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Aug 2012 10:27:25 +0200 -Subject: [PATCH 04/36] MIPS: lantiq: add atm hack - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++ - arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++ - arch/mips/lantiq/irq.c | 2 + - arch/mips/mm/cache.c | 2 + - include/uapi/linux/atm.h | 6 + - net/atm/common.c | 6 + - net/atm/proc.c | 2 +- - 7 files changed, 416 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h -@@ -0,0 +1,196 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_atm.h -+** PROJECT : UEIP -+** MODULES : ATM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global ATM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_ATM_H -+#define IFX_ATM_H -+ -+ -+ -+/*! -+ \defgroup IFX_ATM UEIP Project - ATM driver module -+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_IOCTL IOCTL Commands -+ \ingroup IFX_ATM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_STRUCT Structures -+ \ingroup IFX_ATM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_atm.h -+ \ingroup IFX_ATM -+ \brief ATM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ATM MIB -+ */ -+ -+/*! -+ \struct atm_cell_ifEntry_t -+ \brief Structure used for Cell Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifInErrors; /*!< counter of error ingress cells */ -+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ -+ __u32 ifOutErrors; /*!< counter of error egress cells */ -+} atm_cell_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_ifEntry_t -+ \brief Structure used for AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifInUcastPkts; /*!< counter of ingress packets */ -+ __u32 ifOutUcastPkts; /*!< counter of egress packets */ -+ __u32 ifInErrors; /*!< counter of error ingress packets */ -+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ -+ __u32 ifOutErros; /*!< counter of error egress packets */ -+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -+} atm_aal5_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_vcc_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ This structure is a part of structure "atm_aal5_vcc_x_t". -+ */ -+typedef struct { -+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ -+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet -+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -+} atm_aal5_vcc_t; -+ -+/*! -+ \struct atm_aal5_vcc_x_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". -+ */ -+typedef struct { -+ int vpi; /*!< VPI of the VCC to get MIB counters */ -+ int vci; /*!< VCI of the VCC to get MIB counters */ -+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -+} atm_aal5_vcc_x_t; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief ATM IOCTL Magic Number -+ */ -+#define PPE_ATM_IOC_MAGIC 'o' -+/*! -+ \brief ATM IOCTL Command - Get Cell Level MIB Counters -+ -+ This command is obsolete. User can get cell level MIB from DSL API. -+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters -+ -+ Get AAL5 packet counters. -+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get Per PVC MIB Counters -+ -+ Get AAL5 packet counters for each PVC. -+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. -+ */ -+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -+/*! -+ \brief Total Number of ATM IOCTL Commands -+ */ -+#define PPE_ATM_IOC_MAXNR 3 -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_ATM_H -+ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h -@@ -0,0 +1,203 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ptm.h -+** PROJECT : UEIP -+** MODULES : PTM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global PTM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_PTM_H -+#define IFX_PTM_H -+ -+ -+ -+/*! -+ \defgroup IFX_PTM UEIP Project - PTM driver module -+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_IOCTL IOCTL Commands -+ \ingroup IFX_PTM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_STRUCT Structures -+ \ingroup IFX_PTM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_ptm.h -+ \ingroup IFX_PTM -+ \brief PTM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_PTM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief PTM IOCTL Command - Get codeword MIB counters. -+ -+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. -+ */ -+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 -+/*! -+ \brief PTM IOCTL Command - Get packet MIB counters. -+ -+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. -+ */ -+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 -+/*! -+ \brief PTM IOCTL Command - Get firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 -+/*! -+ \brief PTM IOCTL Command - Set firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 -+/*! -+ \brief PTM IOCTL Command - Program priority value to TX queue mapping. -+ -+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. -+ */ -+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_PTM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Data Type -+ */ -+ -+/*! -+ \typedef PTM_CW_IF_ENTRY_T -+ \brief Wrapping of structure "ptm_cw_ifEntry_t". -+ */ -+/*! -+ \struct ptm_cw_ifEntry_t -+ \brief Structure used for CodeWord level MIB counters. -+ */ -+typedef struct ptm_cw_ifEntry_t { -+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ -+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ -+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ -+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ -+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ -+} PTM_CW_IF_ENTRY_T; -+ -+/*! -+ \typedef PTM_FRAME_MIB_T -+ \brief Wrapping of structure "ptm_frame_mib_t". -+ */ -+/*! -+ \struct ptm_frame_mib_t -+ \brief Structure used for packet level MIB counters. -+ */ -+typedef struct ptm_frame_mib_t { -+ uint32_t RxCorrect; /*!< output, number of ingress packet */ -+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ -+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ -+ uint32_t TxSend; /*!< output, number of egress packet */ -+} PTM_FRAME_MIB_T; -+ -+/*! -+ \typedef IFX_PTM_CFG_T -+ \brief Wrapping of structure "ptm_cfg_t". -+ */ -+/*! -+ \struct ptm_cfg_t -+ \brief Structure used for ETH/TC CRC configuration. -+ */ -+typedef struct ptm_cfg_t { -+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ -+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ -+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ -+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ -+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ -+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ -+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ -+} IFX_PTM_CFG_T; -+ -+/*! -+ \typedef IFX_PTM_PRIO_Q_MAP_T -+ \brief Wrapping of structure "ppe_prio_q_map". -+ */ -+/*! -+ \struct ppe_prio_q_map -+ \brief Structure used for Priority Value to TX Queue mapping. -+ */ -+typedef struct ppe_prio_q_map { -+ int pkt_prio; -+ int qid; -+ int vpi; // ignored in eth interface -+ int vci; // ignored in eth interface -+} IFX_PTM_PRIO_Q_MAP_T; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_PTM_H -+ ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -100,6 +101,7 @@ void ltq_mask_and_ack_irq(struct irq_dat - ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); - ltq_icu_w32(im, BIT(offset), isr); - } -+EXPORT_SYMBOL(ltq_mask_and_ack_irq); - - static void ltq_ack_irq(struct irq_data *d) - { ---- a/arch/mips/mm/cache.c -+++ b/arch/mips/mm/cache.c -@@ -63,6 +63,8 @@ void (*_dma_cache_wback)(unsigned long s - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - - EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_wback); -+EXPORT_SYMBOL(_dma_cache_inv); - - #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */ - ---- a/include/uapi/linux/atm.h -+++ b/include/uapi/linux/atm.h -@@ -130,8 +130,14 @@ - #define ATM_ABR 4 - #define ATM_ANYCLASS 5 /* compatible with everything */ - -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ - #define ATM_MAX_PCR -1 /* maximum available PCR */ - -+ - struct atm_trafprm { - unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ - int max_pcr; /* maximum PCR in cells per second */ ---- a/net/atm/common.c -+++ b/net/atm/common.c -@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc - write_unlock_irq(&vcc_sklist_lock); - } - -+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; -+EXPORT_SYMBOL(ifx_atm_alloc_tx); -+ - static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size) - { - struct sk_buff *skb; - struct sock *sk = sk_atm(vcc); - -+ if (ifx_atm_alloc_tx != NULL) -+ return ifx_atm_alloc_tx(vcc, size); -+ - if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { - pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", - sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); ---- a/net/atm/proc.c -+++ b/net/atm/proc.c -@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { - static const char *const class_name[] = { -- "off", "UBR", "CBR", "VBR", "ABR"}; -+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; - static const char *const aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ diff --git a/target/linux/lantiq/patches-4.9/0008-MIPS-lantiq-backport-old-timer-code.patch b/target/linux/lantiq/patches-4.9/0008-MIPS-lantiq-backport-old-timer-code.patch deleted file mode 100644 index 335a1e261..000000000 --- a/target/linux/lantiq/patches-4.9/0008-MIPS-lantiq-backport-old-timer-code.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:30:56 +0200 -Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++ - 3 files changed, 1001 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h - create mode 100644 arch/mips/lantiq/xway/timer.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h -@@ -0,0 +1,155 @@ -+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+ -+ -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * Available Timer/Counter Index -+ */ -+#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -+#define TIMER_ANY 0x00 -+#define TIMER1A TIMER(1, 0) -+#define TIMER1B TIMER(1, 1) -+#define TIMER2A TIMER(2, 0) -+#define TIMER2B TIMER(2, 1) -+#define TIMER3A TIMER(3, 0) -+#define TIMER3B TIMER(3, 1) -+ -+/* -+ * Flag of Timer/Counter -+ * These flags specify the way in which timer is configured. -+ */ -+/* Bit size of timer/counter. */ -+#define TIMER_FLAG_16BIT 0x0000 -+#define TIMER_FLAG_32BIT 0x0001 -+/* Switch between timer and counter. */ -+#define TIMER_FLAG_TIMER 0x0000 -+#define TIMER_FLAG_COUNTER 0x0002 -+/* Stop or continue when overflowing/underflowing. */ -+#define TIMER_FLAG_ONCE 0x0000 -+#define TIMER_FLAG_CYCLIC 0x0004 -+/* Count up or counter down. */ -+#define TIMER_FLAG_UP 0x0000 -+#define TIMER_FLAG_DOWN 0x0008 -+/* Count on specific level or edge. */ -+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -+#define TIMER_FLAG_RISE_EDGE 0x0010 -+#define TIMER_FLAG_FALL_EDGE 0x0020 -+#define TIMER_FLAG_ANY_EDGE 0x0030 -+/* Signal is syncronous to module clock or not. */ -+#define TIMER_FLAG_UNSYNC 0x0000 -+#define TIMER_FLAG_SYNC 0x0080 -+/* Different interrupt handle type. */ -+#define TIMER_FLAG_NO_HANDLE 0x0000 -+#if defined(__KERNEL__) -+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -+#endif // defined(__KERNEL__) -+#define TIMER_FLAG_SIGNAL 0x0300 -+/* Internal clock source or external clock source */ -+#define TIMER_FLAG_INT_SRC 0x0000 -+#define TIMER_FLAG_EXT_SRC 0x1000 -+ -+ -+/* -+ * ioctl Command -+ */ -+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ -+ -+/* -+ * Data Type Used to Call ioctl -+ */ -+struct gptu_ioctl_param { -+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field is ID of expected * -+ * timer/counter. If it's zero, a timer/counter would * -+ * be dynamically allocated and ID would be stored in * -+ * this field. * -+ * In command GPTU_GET_COUNT_VALUE, this field is * -+ * ignored. * -+ * In other command, this field is ID of timer/counter * -+ * allocated. */ -+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field contains flags to * -+ * specify how to configure timer/counter. * -+ * In command GPTU_START_TIMER, zero indicate start * -+ * and non-zero indicate resume timer/counter. * -+ * In other command, this field is ignored. */ -+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * -+ * init/reload value. * -+ * In command GPTU_SET_TIMER, this field contains * -+ * frequency (0.001Hz) of timer. * -+ * In command GPTU_GET_COUNT_VALUE, current count * -+ * value would be stored in this field. * -+ * In command GPTU_CALCULATE_DIVIDER, this field * -+ * contains frequency wanted, and after calculation, * -+ * divider would be stored in this field to overwrite * -+ * the frequency. * -+ * In other command, this field is ignored. */ -+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains process * -+ * ID to which signal would be sent. * -+ * In other command, this field is ignored. */ -+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains signal * -+ * number which would be sent. * -+ * In other command, this field is ignored. */ -+}; -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+typedef void (*timer_callback)(unsigned long arg); -+ -+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -+extern int lq_free_timer(unsigned int); -+extern int lq_start_timer(unsigned int, int); -+extern int lq_stop_timer(unsigned int); -+extern int lq_reset_counter_flags(u32 timer, u32 flags); -+extern int lq_get_count_value(unsigned int, unsigned long *); -+extern u32 lq_cal_divider(unsigned long); -+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -+extern int lq_set_counter(unsigned int timer, unsigned int flag, -+ u32 reload, unsigned long arg1, unsigned long arg2); -+ -+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,4 +1,10 @@ --obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o -+obj-y := prom.o sysctrl.o clk.o reset.o dma.o dcdc.o -+ -+ifdef CONFIG_SOC_AMAZON_SE -+obj-y += gptu.o -+else -+obj-y += timer.o -+endif - - obj-y += vmmc.o - ---- /dev/null -+++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,845 @@ -+#ifndef CONFIG_SOC_AMAZON_SE -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "../clk.h" -+ -+#include -+#include -+#include -+ -+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 -+ -+#ifdef TIMER1A -+#define FIRST_TIMER TIMER1A -+#else -+#define FIRST_TIMER 2 -+#endif -+ -+/* -+ * GPTC divider is set or not. -+ */ -+#define GPTU_CLC_RMC_IS_SET 0 -+ -+/* -+ * Timer Interrupt (IRQ) -+ */ -+/* Must be adjusted when ICU driver is available */ -+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) -+ -+/* -+ * Bits Operation -+ */ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ -+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+/* -+ * GPTU Register Mapping -+ */ -+#define LQ_GPTU (KSEG1 + 0x1E100A00) -+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) -+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) -+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) -+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) -+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) -+ -+/* -+ * Clock Control Register -+ */ -+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) -+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) -+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) -+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) -+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) -+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) -+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) -+ -+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) -+ -+/* -+ * ID Register -+ */ -+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) -+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) -+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) -+ -+/* -+ * Control Register of Timer/Counter nX -+ * n is the index of block (1 based index) -+ * X is either A or B -+ */ -+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) -+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) -+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) -+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) -+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) -+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) -+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) -+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) -+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) -+ -+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) -+ -+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) -+ -+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+ -+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -+#define TIMER_FLAG_NONE_EDGE 0x0000 -+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -+#define TIMER_FLAG_REAL 0x0000 -+#define TIMER_FLAG_INVERT 0x0040 -+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) -+ -+struct timer_dev_timer { -+ unsigned int f_irq_on; -+ unsigned int irq; -+ unsigned int flag; -+ unsigned long arg1; -+ unsigned long arg2; -+}; -+ -+struct timer_dev { -+ struct mutex gptu_mutex; -+ unsigned int number_of_timers; -+ unsigned int occupation; -+ unsigned int f_gptu_on; -+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -+}; -+ -+ -+unsigned int ltq_get_fpi_bus_clock(int fpi) { -+ struct clk *clk = clk_get_fpi(); -+ return clk_get_rate(clk); -+} -+ -+ -+static long gptu_ioctl(struct file *, unsigned int, unsigned long); -+static int gptu_open(struct inode *, struct file *); -+static int gptu_release(struct inode *, struct file *); -+ -+static struct file_operations gptu_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = gptu_ioctl, -+ .open = gptu_open, -+ .release = gptu_release -+}; -+ -+static struct miscdevice gptu_miscdev = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "gptu", -+ .fops = &gptu_fops, -+}; -+ -+static struct timer_dev timer_dev; -+ -+static irqreturn_t timer_irq_handler(int irq, void *p) -+{ -+ unsigned int timer; -+ unsigned int flag; -+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; -+ -+ timer = irq - TIMER_INTERRUPT; -+ if (timer < timer_dev.number_of_timers -+ && dev_timer == &timer_dev.timer[timer]) { -+ /* Clear interrupt. */ -+ ltq_w32(1 << timer, LQ_GPTU_IRNCR); -+ -+ /* Call user hanler or signal. */ -+ flag = dev_timer->flag; -+ if (!(timer & 0x01) -+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ /* 16-bit timer or timer A of 32-bit timer */ -+ switch (TIMER_FLAG_MASK_HANDLE(flag)) { -+ case TIMER_FLAG_CALLBACK_IN_IRQ: -+ case TIMER_FLAG_CALLBACK_IN_HB: -+ if (dev_timer->arg1) -+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); -+ break; -+ case TIMER_FLAG_SIGNAL: -+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); -+ break; -+ } -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+static inline void lq_enable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ clk_enable(clk); -+ -+ //ltq_pmu_enable(PMU_GPT); -+ -+ /* Set divider as 1, disable write protection for SPEN, enable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x01) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(1) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(0); -+} -+ -+static inline void lq_disable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("1e100a00.gptu", NULL); -+ ltq_w32(0x00, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ /* Set divider as 0, enable write protection for SPEN, disable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x00) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(0) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(1); -+ -+ clk_enable(clk); -+} -+ -+int lq_request_timer(unsigned int timer, unsigned int flag, -+ unsigned long value, unsigned long arg1, unsigned long arg2) -+{ -+ int ret = 0; -+ unsigned int con_reg, irnen_reg; -+ int n, X; -+ -+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", -+ timer, flag, value); -+ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) -+ value &= 0xFFFF; -+ else -+ timer &= ~0x01; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ /* -+ * Allocate timer. -+ */ -+ if (timer < FIRST_TIMER) { -+ unsigned int mask; -+ unsigned int shift; -+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ -+ unsigned int offset = TIMER2A; -+ -+ /* -+ * Pick up a free timer. -+ */ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ mask = 1 << offset; -+ shift = 1; -+ } else { -+ mask = 3 << offset; -+ shift = 2; -+ } -+ for (timer = offset; -+ timer < offset + timer_dev.number_of_timers; -+ timer += shift, mask <<= shift) -+ if (!(timer_dev.occupation & mask)) { -+ timer_dev.occupation |= mask; -+ break; -+ } -+ if (timer >= offset + timer_dev.number_of_timers) { -+ printk("failed![%d]\n", __LINE__); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } else -+ ret = timer; -+ } else { -+ register unsigned int mask; -+ -+ /* -+ * Check if the requested timer is free. -+ */ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if ((timer_dev.occupation & mask)) { -+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", -+ __LINE__, mask, timer_dev.occupation); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EBUSY; -+ } else { -+ timer_dev.occupation |= mask; -+ ret = 0; -+ } -+ } -+ -+ /* -+ * Prepare control register value. -+ */ -+ switch (TIMER_FLAG_MASK_EDGE(flag)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : -+ GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : -+ GPTU_CON_SRC_EG_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_SYNC(flag) == -+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : -+ GPTU_CON_SYNC_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_INVERT(flag) == -+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : -+ GPTU_CON_EXT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_STOP(flag) == -+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_TYPE(flag) == -+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : -+ GPTU_CON_CNT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_DIR(flag) == -+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ /* -+ * Fill up running data. -+ */ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flag; -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; -+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; -+ -+ /* -+ * Enable GPTU module. -+ */ -+ if (!timer_dev.f_gptu_on) { -+ lq_enable_gptu(); -+ timer_dev.f_gptu_on = 1; -+ } -+ -+ /* -+ * Enable IRQ. -+ */ -+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = -+ (unsigned long) find_task_by_vpid((int) arg1); -+ -+ irnen_reg = 1 << (timer - FIRST_TIMER); -+ -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL -+ || (TIMER_FLAG_MASK_HANDLE(flag) == -+ TIMER_FLAG_CALLBACK_IN_IRQ -+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { -+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; -+ } -+ } else -+ irnen_reg = 0; -+ -+ /* -+ * Write config register, reload value and enable interrupt. -+ */ -+ n = timer >> 1; -+ X = timer & 0x01; -+ *LQ_GPTU_CON(n, X) = con_reg; -+ *LQ_GPTU_RELOAD(n, X) = value; -+ /* printk("reload value = %d\n", (u32)value); */ -+ *LQ_GPTU_IRNEN |= irnen_reg; -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ printk("successful!\n"); -+ return ret; -+} -+EXPORT_SYMBOL(lq_request_timer); -+ -+int lq_free_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ if (GPTU_CON_EN(n, X)) -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); -+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); -+ -+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { -+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; -+ } -+ -+ timer_dev.occupation &= ~mask; -+ if (!timer_dev.occupation && timer_dev.f_gptu_on) { -+ lq_disable_gptu(); -+ timer_dev.f_gptu_on = 0; -+ } -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_free_timer); -+ -+int lq_start_timer(unsigned int timer, int is_resume) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_start_timer); -+ -+int lq_stop_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_stop_timer); -+ -+int lq_reset_counter_flags(u32 timer, u32 flags) -+{ -+ unsigned int oflag; -+ unsigned int mask, con_reg; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ switch (TIMER_FLAG_MASK_EDGE(flags)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); -+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); -+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flags; -+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_CON(n, X) = con_reg; -+ smp_wmb(); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return 0; -+} -+EXPORT_SYMBOL(lq_reset_counter_flags); -+ -+int lq_get_count_value(unsigned int timer, unsigned long *value) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *value = *LQ_GPTU_COUNT(n, X); -+ -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_get_count_value); -+ -+u32 lq_cal_divider(unsigned long freq) -+{ -+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); -+ u32 clock_divider = 1; -+ module_freq = fpi * 1000; -+ do_div(module_freq, clock_divider * freq); -+ return module_freq; -+} -+EXPORT_SYMBOL(lq_cal_divider); -+ -+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, -+ int is_ext_src, unsigned int handle_flag, unsigned long arg1, -+ unsigned long arg2) -+{ -+ unsigned long divider; -+ unsigned int flag; -+ -+ divider = lq_cal_divider(freq); -+ if (divider == 0) -+ return -EINVAL; -+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) -+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) -+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) -+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN -+ | TIMER_FLAG_MASK_HANDLE(handle_flag); -+ -+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", -+ timer, freq, divider); -+ return lq_request_timer(timer, flag, divider, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_timer); -+ -+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, -+ unsigned long arg1, unsigned long arg2) -+{ -+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); -+ return lq_request_timer(timer, flag, reload, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_counter); -+ -+static long gptu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret; -+ struct gptu_ioctl_param param; -+ -+ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ copy_from_user(¶m, (void *) arg, sizeof(param)); -+ -+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER -+ || GPTU_SET_COUNTER) && param.timer < 2) -+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) -+ && !access_ok(VERIFY_WRITE, arg, -+ sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case GPTU_REQUEST_TIMER: -+ ret = lq_request_timer(param.timer, param.flag, param.value, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_FREE_TIMER: -+ ret = lq_free_timer(param.timer); -+ break; -+ case GPTU_START_TIMER: -+ ret = lq_start_timer(param.timer, param.flag); -+ break; -+ case GPTU_STOP_TIMER: -+ ret = lq_stop_timer(param.timer); -+ break; -+ case GPTU_GET_COUNT_VALUE: -+ ret = lq_get_count_value(param.timer, ¶m.value); -+ if (!ret) -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ break; -+ case GPTU_CALCULATE_DIVIDER: -+ param.value = lq_cal_divider(param.value); -+ if (param.value == 0) -+ ret = -EINVAL; -+ else { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_TIMER: -+ ret = lq_set_timer(param.timer, param.value, -+ TIMER_FLAG_MASK_STOP(param.flag) != -+ TIMER_FLAG_ONCE ? 1 : 0, -+ TIMER_FLAG_MASK_SRC(param.flag) == -+ TIMER_FLAG_EXT_SRC ? 1 : 0, -+ TIMER_FLAG_MASK_HANDLE(param.flag) == -+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : -+ TIMER_FLAG_NO_HANDLE, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_COUNTER: -+ lq_set_counter(param.timer, param.flag, param.value, 0, 0); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ default: -+ ret = -ENOTTY; -+ } -+ -+ return ret; -+} -+ -+static int gptu_open(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static int gptu_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+int __init lq_gptu_init(void) -+{ -+ int ret; -+ unsigned int i; -+ -+ ltq_w32(0, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ memset(&timer_dev, 0, sizeof(timer_dev)); -+ mutex_init(&timer_dev.gptu_mutex); -+ -+ lq_enable_gptu(); -+ timer_dev.number_of_timers = GPTU_ID_CFG * 2; -+ lq_disable_gptu(); -+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) -+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; -+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); -+ -+ ret = misc_register(&gptu_miscdev); -+ if (ret) { -+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); -+ return ret; -+ } else { -+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); -+ } -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); -+ if (ret) { -+ for (; i >= 0; i--) -+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); -+ misc_deregister(&gptu_miscdev); -+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); -+ return ret; -+ } else { -+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; -+ disable_irq(timer_dev.timer[i].irq); -+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); -+ } -+ } -+ -+ return 0; -+} -+ -+void __exit lq_gptu_exit(void) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ if (timer_dev.timer[i].f_irq_on) -+ disable_irq(timer_dev.timer[i].irq); -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ } -+ lq_disable_gptu(); -+ misc_deregister(&gptu_miscdev); -+} -+ -+module_init(lq_gptu_init); -+module_exit(lq_gptu_exit); -+ -+#endif diff --git a/target/linux/lantiq/patches-4.9/0018-MTD-nand-lots-of-xrx200-fixes.patch b/target/linux/lantiq/patches-4.9/0018-MTD-nand-lots-of-xrx200-fixes.patch deleted file mode 100644 index b97967d20..000000000 --- a/target/linux/lantiq/patches-4.9/0018-MTD-nand-lots-of-xrx200-fixes.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 23:12:15 +0200 -Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes - -Signed-off-by: John Crispin ---- - drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 63 insertions(+) - ---- a/drivers/mtd/nand/xway_nand.c -+++ b/drivers/mtd/nand/xway_nand.c -@@ -63,6 +63,24 @@ - #define NAND_CON_CSMUX (1 << 1) - #define NAND_CON_NANDM 1 - -+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr)) -+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400) -+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080) -+ -+/* -+ * req_mask provides a mechanism to prevent interference between -+ * nand and pci (probably only relevant for the BT Home Hub 2B). -+ * Setting it causes the corresponding pci req pins to be masked -+ * during nand access, and also moves ebu locking from the read/write -+ * functions to the chip select function to ensure that the whole -+ * operation runs with interrupts disabled. -+ * In addition it switches on some extra waiting in xway_cmd_ctrl(). -+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled, -+ * which in turn seems to be necessary for the nor chip to be recognised -+ * reliably, on a board (Home Hub 2B again) which has both nor and nand. -+ */ -+static __be32 req_mask = 0; -+ - struct xway_nand_data { - struct nand_chip chip; - unsigned long csflags; -@@ -94,10 +112,22 @@ static void xway_select_chip(struct mtd_ - case -1: - ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON); - ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON); -+ -+ if (req_mask) { -+ /* Unmask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16); -+ } -+ - spin_unlock_irqrestore(&ebu_lock, data->csflags); - break; - case 0: - spin_lock_irqsave(&ebu_lock, data->csflags); -+ -+ if (req_mask) { -+ /* Mask all external PCI request */ -+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16); -+ } -+ - ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON); - ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON); - break; -@@ -108,6 +138,12 @@ static void xway_select_chip(struct mtd_ - - static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) - { -+ -+ if (req_mask) { -+ if (cmd != NAND_CMD_STATUS) -+ ltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */ -+ } -+ - if (cmd == NAND_CMD_NONE) - return; - -@@ -118,6 +154,24 @@ static void xway_cmd_ctrl(struct mtd_inf - - while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; -+ -+ if (req_mask) { -+ /* -+ * program and erase have their own busy handlers -+ * status and sequential in needs no delay -+ */ -+ switch (cmd) { -+ case NAND_CMD_ERASE1: -+ case NAND_CMD_SEQIN: -+ case NAND_CMD_STATUS: -+ case NAND_CMD_READID: -+ return; -+ } -+ -+ /* wait until command is processed */ -+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0) -+ ; -+ } - } - - static int xway_dev_ready(struct mtd_info *mtd) -@@ -157,6 +211,7 @@ static int xway_nand_probe(struct platfo - int err; - u32 cs; - u32 cs_flag = 0; -+ const __be32 *req_mask_ptr; - - /* Allocate memory for the device structure (and zero it) */ - data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data), -@@ -192,6 +247,15 @@ static int xway_nand_probe(struct platfo - if (!err && cs == 1) - cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; - -+ req_mask_ptr = of_get_property(pdev->dev.of_node, -+ "req-mask", NULL); -+ -+ /* -+ * Load the PCI req lines to mask from the device tree. If the -+ * property is not present, setting req_mask to 0 disables masking. -+ */ -+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0); -+ - /* setup the EBU to run in NAND mode on our base addr */ - ltq_ebu_w32(CPHYSADDR(data->nandaddr) - | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); diff --git a/target/linux/lantiq/patches-4.9/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch b/target/linux/lantiq/patches-4.9/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch deleted file mode 100644 index 64bf2aaca..000000000 --- a/target/linux/lantiq/patches-4.9/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch +++ /dev/null @@ -1,25 +0,0 @@ -From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:18:00 +0200 -Subject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash - -Signed-off-by: John Crispin ---- - drivers/mtd/maps/lantiq-flash.c | 6 +++++- - 1 file changed, 5 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -137,7 +137,11 @@ ltq_mtd_probe(struct platform_device *pd - if (!ltq_mtd->map) - return -ENOMEM; - -- ltq_mtd->map->phys = ltq_mtd->res->start; -+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -+ ltq_mtd->map->phys = NO_XIP; -+ else -+ ltq_mtd->map->phys = ltq_mtd->res->start; -+ ltq_mtd->res->start; - ltq_mtd->map->size = resource_size(ltq_mtd->res); - ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); - if (IS_ERR(ltq_mtd->map->virt)) diff --git a/target/linux/lantiq/patches-4.9/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch b/target/linux/lantiq/patches-4.9/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch deleted file mode 100644 index 7617c14dd..000000000 --- a/target/linux/lantiq/patches-4.9/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Sep 2014 22:40:18 +0200 -Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF - -In accordance with the physmap flash we should honour the linux,mtd-name -property when deciding what name the mtd device has. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - drivers/mtd/devices/m25p80.c | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -200,6 +201,10 @@ static int m25p_probe(struct spi_device - enum read_mode mode = SPI_NOR_NORMAL; - char *flash_name; - int ret; -+ const char __maybe_unused *of_mtd_name = NULL; -+ -+ of_property_read_string(spi->dev.of_node, -+ "linux,mtd-name", &of_mtd_name); - - data = dev_get_platdata(&spi->dev); - -@@ -229,6 +234,8 @@ static int m25p_probe(struct spi_device - - if (data && data->name) - nor->mtd.name = data->name; -+ else if (of_mtd_name) -+ nor->mtd.name = of_mtd_name; - - /* For some (historical?) reason many platforms provide two different - * names in flash_platform_data: "name" and "type". Quite often name is diff --git a/target/linux/lantiq/patches-4.9/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-4.9/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch deleted file mode 100644 index e91527759..000000000 --- a/target/linux/lantiq/patches-4.9/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch +++ /dev/null @@ -1,294 +0,0 @@ -From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:15:36 +0200 -Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G - -Signed-off-by: John Crispin ---- - drivers/net/phy/Kconfig | 5 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 237 insertions(+) - create mode 100644 drivers/net/phy/lantiq.c - ---- a/drivers/net/phy/intel-xway.c -+++ b/drivers/net/phy/intel-xway.c -@@ -152,6 +152,51 @@ - #define PHY_ID_PHY11G_VR9 0xD565A409 - #define PHY_ID_PHY22F_VR9 0xD565A419 - -+#if IS_ENABLED(CONFIG_OF_MDIO) -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ u32 tmp; -+ -+ /* store the led values if one was passed by the devicetree */ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCH, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCL, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED0H, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED0L, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED1H, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED1L, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3H, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3L, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3H, MDIO_MMD_VEND2, tmp); -+ -+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp)) -+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3L, MDIO_MMD_VEND2, tmp); -+ -+ return 0; -+} -+#else -+static int vr9_gphy_of_reg_init(struct phy_device *phydev) -+{ -+ return 0; -+} -+#endif /* CONFIG_OF_MDIO */ -+ - static int xway_gphy_config_init(struct phy_device *phydev) - { - int err; -@@ -190,6 +235,7 @@ static int xway_gphy_config_init(struct - phy_write_mmd_indirect(phydev, XWAY_MMD_LED2H, MDIO_MMD_VEND2, ledxh); - phy_write_mmd_indirect(phydev, XWAY_MMD_LED2L, MDIO_MMD_VEND2, ledxl); - -+ vr9_gphy_of_reg_init(phydev); - return 0; - } - ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt -@@ -0,0 +1,216 @@ -+Lanitq PHY binding -+============================================ -+ -+This devicetree binding controls the lantiq ethernet phys led functionality. -+ -+Example: -+ mdio@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "lantiq,xrx200-mdio"; -+ phy5: ethernet-phy@5 { -+ reg = <0x1>; -+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; -+ }; -+ phy11: ethernet-phy@11 { -+ reg = <0x11>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy12: ethernet-phy@12 { -+ reg = <0x12>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ phy13: ethernet-phy@13 { -+ reg = <0x13>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led2h = <0x00>; -+ lantiq,led2l = <0x03>; -+ }; -+ phy14: ethernet-phy@14 { -+ reg = <0x14>; -+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; -+ lantiq,led1h = <0x00>; -+ lantiq,led1l = <0x03>; -+ }; -+ }; -+ -+Register Description -+============================================ -+ -+LEDCH: -+ -+Name Hardware Reset Value -+LEDCH 0x00C5 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| FBF | SBF |RES | NACS | -+========================================= -+ -+Field Bits Type Description -+FBF 7:6 RW Fast Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+SBF 5:4 RW Slow Blink Frequency -+ --- -+ 0x0 (00b) F02HZ 2 Hz blinking frequency -+ 0x1 (01b) F04HZ 4 Hz blinking frequency -+ 0x2 (10b) F08HZ 8 Hz blinking frequency -+ 0x3 (11b) F16HZ 16 Hz blinking frequency -+ -+NACS 2:0 RW Inverse of Scan Function -+ --- -+ 0x0 (000b) NONE No Function -+ 0x1 (001b) LINK Complex function enabled when link is up -+ 0x2 (010b) PDOWN Complex function enabled when device is powered-down -+ 0x3 (011b) EEE Complex function enabled when device is in EEE mode -+ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running -+ 0x5 (101b) ABIST Complex function enabled when analog self-test is running -+ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running -+ 0x7 (111b) TEST Complex function enabled when test mode is running -+ -+LEDCL: -+ -+Name Hardware Reset Value -+LEDCL 0x0067 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+|RES | SCAN |RES | CBLINK | -+========================================= -+ -+Field Bits Type Description -+SCAN 6:4 RW Complex Scan Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+CBLINK 2:0 RW Complex Blinking Configuration -+ --- -+ 000 B NONE No Function -+ 001 B LINK Complex function enabled when link is up -+ 010 B PDOWN Complex function enabled when device is powered-down -+ 011 B EEE Complex function enabled when device is in EEE mode -+ 100 B ANEG Complex function enabled when auto-negotiation is running -+ 101 B ABIST Complex function enabled when analog self-test is running -+ 110 B CDIAG Complex function enabled when cable diagnostics are running -+ 111 B TEST Complex function enabled when test mode is running -+ -+LEDxH: -+ -+Name Hardware Reset Value -+LED0H 0x0070 -+LED1H 0x0020 -+LED2H 0x0040 -+LED3H 0x0040 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| CON | BLINKF | -+========================================= -+ -+Field Bits Type Description -+CON 7:4 RW Constant On Configuration -+ --- -+ 0x0 (0000b) NONE LED does not light up constantly -+ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN LED is on when device is powered-down -+ 0x9 (1001b) EEE LED is on when device is in EEE mode -+ 0xA (1010b) ANEG LED is on when auto-negotiation is running -+ 0xB (1011b) ABIST LED is on when analog self-test is running -+ 0xC (1100b) CDIAG LED is on when cable diagnostics are running -+ -+BLINKF 3:0 RW Fast Blinking Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are running -+ -+LEDxL: -+ -+Name Hardware Reset Value -+LED0L 0x0003 -+LED1L 0x0000 -+LED2L 0x0000 -+LED3L 0x0020 -+ -+| 15 | | | | | | | 8 | -+========================================= -+| RES | -+========================================= -+ -+| 7 | | | | | | | 0 | -+========================================= -+| BLINKS | PULSE | -+========================================= -+ -+Field Bits Type Description -+BLINKS 7:4 RW Slow Blinkin Configuration -+ --- -+ 0x0 (0000b) NONE No Blinking -+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s -+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s -+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s -+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s -+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s -+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s -+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s -+ 0x8 (1000b) PDOWN Blink when device is powered-down -+ 0x9 (1001b) EEE Blink when device is in EEE mode -+ 0xA (1010b) ANEG Blink when auto-negotiation is running -+ 0xB (1011b) ABIST Blink when analog self-test is running -+ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning -+ -+PULSE 3:0 RW Pulsing Configuration -+ The pulse field is a mask field by which certain events can be combined -+ --- -+ 0x0 (0000b) NONE No pulsing -+ 0x1 (0001b) TXACT Transmit activity -+ 0x2 (0010b) RXACT Receive activity -+ 0x4 (0100b) COL Collision -+ 0x8 (1000b) RES Reserved diff --git a/target/linux/lantiq/patches-4.9/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch b/target/linux/lantiq/patches-4.9/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch deleted file mode 100644 index e62ff2f69..000000000 --- a/target/linux/lantiq/patches-4.9/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch +++ /dev/null @@ -1,364 +0,0 @@ -From 77e89d5a28be35058041c79e9874ab26f222c603 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 22 Oct 2012 09:26:24 +0200 -Subject: [PATCH 24/36] NET: lantiq: adds PHY11G firmware blobs - -Signed-off-by: John Crispin ---- - firmware/Makefile | 4 + - firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++ - firmware/lantiq/README | 45 ++++++++ - 3 files changed, 335 insertions(+) - create mode 100644 firmware/lantiq/COPYING - create mode 100644 firmware/lantiq/README - ---- a/firmware/Makefile -+++ b/firmware/Makefile -@@ -134,6 +134,10 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_P - fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw - fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw - fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin -+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy11g_a14.bin -+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy11g_a22.bin -+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy22f_a14.bin -+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy22f_a22.bin - fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin - - fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-) ---- /dev/null -+++ b/firmware/lantiq/COPYING -@@ -0,0 +1,286 @@ -+All firmware files are copyrighted by Lantiq Deutschland GmbH. -+The files have been extracted from header files found in Lantiq BSPs. -+If not stated otherwise all files are licensed under GPL. -+ -+======================================================================= -+ -+ GNU GENERAL PUBLIC LICENSE -+ Version 2, June 1991 -+ -+ Copyright (C) 1989, 1991 Free Software Foundation, Inc. -+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ Everyone is permitted to copy and distribute verbatim copies -+ of this license document, but changing it is not allowed. -+ -+ Preamble -+ -+ The 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR -+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, -+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING -+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED -+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY -+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER -+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE -+POSSIBILITY OF SUCH DAMAGES. -+ -+ END OF TERMS AND CONDITIONS ---- /dev/null -+++ b/firmware/lantiq/README -@@ -0,0 +1,45 @@ -+# -+# This program is free software; you can redistribute it and/or -+# modify it under the terms of the GNU General Public License as -+# published by the Free Software Foundation; either version 2 of -+# the License, or (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+# MA 02111-1307 USA -+# -+# (C) Copyright 2007 - 2012 -+# Lantiq Deutschland GmbH -+# -+# (C) Copyright 2012 -+# Daniel Schwierzeck -+# -+ -+# -+# How to use -+# -+Configure kernel with: -+CONFIG_FW_LOADER=y -+CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR" -+CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES" -+ -+where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list -+of space separated files from list below. -+ -+# -+# Firmware files -+# -+ -+# GPHY core on Lantiq XWAY VR9 v1.1 -+lantiq/xrx200_phy11g_a14.bin -+lantiq/xrx200_phy22f_a14.bin -+ -+# GPHY core on Lantiq XWAY VR9 v1.2 -+lantiq/xrx200_phy11g_a22.bin -+lantiq/xrx200_phy22f_a22.bin diff --git a/target/linux/lantiq/patches-4.9/0025-NET-MIPS-lantiq-adds-xrx200-net.patch b/target/linux/lantiq/patches-4.9/0025-NET-MIPS-lantiq-adds-xrx200-net.patch deleted file mode 100644 index 5224e7a00..000000000 --- a/target/linux/lantiq/patches-4.9/0025-NET-MIPS-lantiq-adds-xrx200-net.patch +++ /dev/null @@ -1,3394 +0,0 @@ -From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 22 Oct 2012 12:22:23 +0200 -Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net - ---- - drivers/net/ethernet/Kconfig | 8 +- - drivers/net/ethernet/Makefile | 1 + - drivers/net/ethernet/lantiq_pce.h | 163 +++ - drivers/net/ethernet/lantiq_xrx200.c | 1798 +++++++++++++++++++++++++++++++ - drivers/net/ethernet/lantiq_xrx200_sw.h | 1328 +++++++++++++++++++++++ - 5 files changed, 3297 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/ethernet/lantiq_pce.h - create mode 100644 drivers/net/ethernet/lantiq_xrx200.c - create mode 100644 drivers/net/ethernet/lantiq_xrx200_sw.h - ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -104,7 +104,13 @@ config LANTIQ_ETOP - tristate "Lantiq SoC ETOP driver" - depends on SOC_TYPE_XWAY - ---help--- -- Support for the MII0 inside the Lantiq SoC -+ Support for the MII0 inside the Lantiq ADSL SoC -+ -+config LANTIQ_XRX200 -+ tristate "Lantiq SoC XRX200 driver" -+ depends on SOC_TYPE_XWAY -+ ---help--- -+ Support for the MII0 inside the Lantiq VDSL SoC - - source "drivers/net/ethernet/marvell/Kconfig" - source "drivers/net/ethernet/mediatek/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_NET_VENDOR_XSCALE) += xscal - obj-$(CONFIG_JME) += jme.o - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o -+obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o - obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ - obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/ - obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_pce.h -@@ -0,0 +1,163 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2012 John Crispin -+ * -+ * PCE microcode extracted from UGW5.2 switch api -+ */ -+ -+/* Switch API Micro Code V0.3 */ -+enum { -+ OUT_MAC0 = 0, -+ OUT_MAC1, -+ OUT_MAC2, -+ OUT_MAC3, -+ OUT_MAC4, -+ OUT_MAC5, -+ OUT_ETHTYP, -+ OUT_VTAG0, -+ OUT_VTAG1, -+ OUT_ITAG0, -+ OUT_ITAG1, /*10 */ -+ OUT_ITAG2, -+ OUT_ITAG3, -+ OUT_IP0, -+ OUT_IP1, -+ OUT_IP2, -+ OUT_IP3, -+ OUT_SIP0, -+ OUT_SIP1, -+ OUT_SIP2, -+ OUT_SIP3, /*20*/ -+ OUT_SIP4, -+ OUT_SIP5, -+ OUT_SIP6, -+ OUT_SIP7, -+ OUT_DIP0, -+ OUT_DIP1, -+ OUT_DIP2, -+ OUT_DIP3, -+ OUT_DIP4, -+ OUT_DIP5, /*30*/ -+ OUT_DIP6, -+ OUT_DIP7, -+ OUT_SESID, -+ OUT_PROT, -+ OUT_APP0, -+ OUT_APP1, -+ OUT_IGMP0, -+ OUT_IGMP1, -+ OUT_IPOFF, /*39*/ -+ OUT_NONE = 63 -+}; -+ -+/* parser's microcode length type */ -+#define INSTR 0 -+#define IPV6 1 -+#define LENACCU 2 -+ -+/* parser's microcode flag type */ -+enum { -+ FLAG_ITAG = 0, -+ FLAG_VLAN, -+ FLAG_SNAP, -+ FLAG_PPPOE, -+ FLAG_IPV6, -+ FLAG_IPV6FL, -+ FLAG_IPV4, -+ FLAG_IGMP, -+ FLAG_TU, -+ FLAG_HOP, -+ FLAG_NN1, /*10 */ -+ FLAG_NN2, -+ FLAG_END, -+ FLAG_NO, /*13*/ -+}; -+ -+/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */ -+#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ -+ { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }} -+struct pce_microcode { -+ unsigned short val[4]; -+/* unsigned short val_2; -+ unsigned short val_1; -+ unsigned short val_0;*/ -+} pce_microcode[] = { -+ /* value mask ns fields L type flags ipv4_len */ -+ MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), -+ MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), -+ MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), -+ MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), -+ MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), -+ MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), -+ MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0), -+ MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0), -+ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0), -+ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0), -+ MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0), -+ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0), -+ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0), -+}; ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_xrx200.c -@@ -0,0 +1,1851 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq Deutschland -+ * Copyright (C) 2012 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "lantiq_pce.h" -+#include "lantiq_xrx200_sw.h" -+ -+#define SW_POLLING -+#define SW_ROUTING -+ -+#ifdef SW_ROUTING -+#define XRX200_MAX_DEV 2 -+#else -+#define XRX200_MAX_DEV 1 -+#endif -+ -+#define XRX200_MAX_VLAN 64 -+#define XRX200_PCE_ACTVLAN_IDX 0x01 -+#define XRX200_PCE_VLANMAP_IDX 0x02 -+ -+#define XRX200_MAX_PORT 7 -+#define XRX200_MAX_DMA 8 -+ -+#define XRX200_HEADROOM 4 -+ -+#define XRX200_TX_TIMEOUT (10 * HZ) -+ -+/* port type */ -+#define XRX200_PORT_TYPE_PHY 1 -+#define XRX200_PORT_TYPE_MAC 2 -+ -+/* DMA */ -+#define XRX200_DMA_DATA_LEN 0x600 -+#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0 -+#define XRX200_DMA_RX 0 -+#define XRX200_DMA_TX 1 -+#define XRX200_DMA_TX_2 3 -+#define XRX200_DMA_IS_TX(x) (x%2) -+#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x)) -+ -+/* fetch / store dma */ -+#define FDMA_PCTRL0 0x2A00 -+#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18)) -+#define SDMA_PCTRL0 0x2F00 -+#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18)) -+ -+/* buffer management */ -+#define BM_PCFG0 0x200 -+#define BM_PCFGx(x) (BM_PCFG0 + (x * 8)) -+ -+/* MDIO */ -+#define MDIO_GLOB 0x0000 -+#define MDIO_CTRL 0x0020 -+#define MDIO_READ 0x0024 -+#define MDIO_WRITE 0x0028 -+#define MDIO_PHY0 0x0054 -+#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned))) -+#define MDIO_CLK_CFG0 0x002C -+#define MDIO_CLK_CFG1 0x0030 -+ -+#define MDIO_GLOB_ENABLE 0x8000 -+#define MDIO_BUSY BIT(12) -+#define MDIO_RD BIT(11) -+#define MDIO_WR BIT(10) -+#define MDIO_MASK 0x1f -+#define MDIO_ADDRSHIFT 5 -+#define MDIO1_25MHZ 9 -+ -+#define MDIO_PHY_LINK_DOWN 0x4000 -+#define MDIO_PHY_LINK_UP 0x2000 -+ -+#define MDIO_PHY_SPEED_M10 0x0000 -+#define MDIO_PHY_SPEED_M100 0x0800 -+#define MDIO_PHY_SPEED_G1 0x1000 -+ -+#define MDIO_PHY_FDUP_EN 0x0200 -+#define MDIO_PHY_FDUP_DIS 0x0600 -+ -+#define MDIO_PHY_LINK_MASK 0x6000 -+#define MDIO_PHY_SPEED_MASK 0x1800 -+#define MDIO_PHY_FDUP_MASK 0x0600 -+#define MDIO_PHY_ADDR_MASK 0x001f -+#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \ -+ MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK -+ -+/* MII */ -+#define MII_CFG(p) (p * 8) -+ -+#define MII_CFG_EN BIT(14) -+ -+#define MII_CFG_MODE_MIIP 0x0 -+#define MII_CFG_MODE_MIIM 0x1 -+#define MII_CFG_MODE_RMIIP 0x2 -+#define MII_CFG_MODE_RMIIM 0x3 -+#define MII_CFG_MODE_RGMII 0x4 -+#define MII_CFG_MODE_MASK 0xf -+ -+#define MII_CFG_RATE_M2P5 0x00 -+#define MII_CFG_RATE_M25 0x10 -+#define MII_CFG_RATE_M125 0x20 -+#define MII_CFG_RATE_M50 0x30 -+#define MII_CFG_RATE_AUTO 0x40 -+#define MII_CFG_RATE_MASK 0x70 -+ -+/* cpu port mac */ -+#define PMAC_HD_CTL 0x0000 -+#define PMAC_RX_IPG 0x0024 -+#define PMAC_EWAN 0x002c -+ -+#define PMAC_IPG_MASK 0xf -+#define PMAC_HD_CTL_AS 0x0008 -+#define PMAC_HD_CTL_AC 0x0004 -+#define PMAC_HD_CTL_RC 0x0010 -+#define PMAC_HD_CTL_RXSH 0x0040 -+#define PMAC_HD_CTL_AST 0x0080 -+#define PMAC_HD_CTL_RST 0x0100 -+ -+/* PCE */ -+#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4)) -+#define PCE_TBL_MASK 0x1120 -+#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4)) -+#define PCE_TBL_ADDR 0x1138 -+#define PCE_TBL_CTRL 0x113c -+#define PCE_PMAP1 0x114c -+#define PCE_PMAP2 0x1150 -+#define PCE_PMAP3 0x1154 -+#define PCE_GCTRL_REG(x) (0x1158 + (x * 4)) -+#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4)) -+ -+#define PCE_TBL_BUSY BIT(15) -+#define PCE_TBL_CFG_ADDR_MASK 0x1f -+#define PCE_TBL_CFG_ADWR 0x20 -+#define PCE_TBL_CFG_ADWR_MASK 0x60 -+#define PCE_INGRESS BIT(11) -+ -+/* MAC */ -+#define MAC_FLEN_REG (0x2314) -+#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4)) -+ -+/* buffer management */ -+#define BM_PCFG(p) (0x200 + (p * 8)) -+ -+/* special tag in TX path header */ -+#define SPID_SHIFT 24 -+#define DPID_SHIFT 16 -+#define DPID_ENABLE 1 -+#define SPID_CPU_PORT 2 -+#define PORT_MAP_SEL BIT(15) -+#define PORT_MAP_EN BIT(14) -+#define PORT_MAP_SHIFT 1 -+#define PORT_MAP_MASK 0x3f -+ -+#define SPPID_MASK 0x7 -+#define SPPID_SHIFT 4 -+ -+/* MII regs not yet in linux */ -+#define MDIO_DEVAD_NONE (-1) -+#define ADVERTIZE_MPD (1 << 10) -+ -+struct xrx200_port { -+ u8 num; -+ u8 phy_addr; -+ u16 flags; -+ phy_interface_t phy_if; -+ -+ int link; -+ int gpio; -+ enum of_gpio_flags gpio_flags; -+ -+ struct phy_device *phydev; -+ struct device_node *phy_node; -+}; -+ -+struct xrx200_chan { -+ int idx; -+ int refcount; -+ int tx_free; -+ -+ struct net_device dummy_dev; -+ struct net_device *devs[XRX200_MAX_DEV]; -+ -+ struct tasklet_struct tasklet; -+ struct napi_struct napi; -+ struct ltq_dma_channel dma; -+ struct sk_buff *skb[LTQ_DESC_NUM]; -+ -+ spinlock_t lock; -+}; -+ -+struct xrx200_hw { -+ struct clk *clk; -+ struct mii_bus *mii_bus; -+ -+ struct xrx200_chan chan[XRX200_MAX_DMA]; -+ u16 vlan_vid[XRX200_MAX_VLAN]; -+ u16 vlan_port_map[XRX200_MAX_VLAN]; -+ -+ struct net_device *devs[XRX200_MAX_DEV]; -+ int num_devs; -+ -+ int port_map[XRX200_MAX_PORT]; -+ unsigned short wan_map; -+ -+ struct switch_dev swdev; -+}; -+ -+struct xrx200_priv { -+ struct net_device_stats stats; -+ int id; -+ -+ struct xrx200_port port[XRX200_MAX_PORT]; -+ int num_port; -+ bool wan; -+ bool sw; -+ unsigned short port_map; -+ unsigned char mac[6]; -+ -+ struct xrx200_hw *hw; -+}; -+ -+static __iomem void *xrx200_switch_membase; -+static __iomem void *xrx200_mii_membase; -+static __iomem void *xrx200_mdio_membase; -+static __iomem void *xrx200_pmac_membase; -+ -+#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x)) -+#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y)) -+#define ltq_switch_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_switch_membase + (z)) -+ -+#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x)) -+#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y)) -+#define ltq_mdio_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_mdio_membase + (z)) -+ -+#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x)) -+#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y)) -+#define ltq_mii_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_mii_membase + (z)) -+ -+#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x)) -+#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y)) -+#define ltq_pmac_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, xrx200_pmac_membase + (z)) -+ -+#define XRX200_GLOBAL_REGATTR(reg) \ -+ .id = reg, \ -+ .type = SWITCH_TYPE_INT, \ -+ .set = xrx200_set_global_attr, \ -+ .get = xrx200_get_global_attr -+ -+#define XRX200_PORT_REGATTR(reg) \ -+ .id = reg, \ -+ .type = SWITCH_TYPE_INT, \ -+ .set = xrx200_set_port_attr, \ -+ .get = xrx200_get_port_attr -+ -+static int xrx200sw_read_x(int reg, int x) -+{ -+ int value, mask, addr; -+ -+ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); -+ value = ltq_switch_r32(addr); -+ mask = (1 << xrx200sw_reg[reg].size) - 1; -+ value = (value >> xrx200sw_reg[reg].shift); -+ -+ return (value & mask); -+} -+ -+static int xrx200sw_read(int reg) -+{ -+ return xrx200sw_read_x(reg, 0); -+} -+ -+static void xrx200sw_write_x(int value, int reg, int x) -+{ -+ int mask, addr; -+ -+ addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x); -+ mask = (1 << xrx200sw_reg[reg].size) - 1; -+ mask = (mask << xrx200sw_reg[reg].shift); -+ value = (value << xrx200sw_reg[reg].shift) & mask; -+ -+ ltq_switch_w32_mask(mask, value, addr); -+} -+ -+static void xrx200sw_write(int value, int reg) -+{ -+ xrx200sw_write_x(value, reg, 0); -+} -+ -+struct xrx200_pce_table_entry { -+ int index; // PCE_TBL_ADDR.ADDR = pData->table_index -+ int table; // PCE_TBL_CTRL.ADDR = pData->table -+ unsigned short key[8]; -+ unsigned short val[5]; -+ unsigned short mask; -+ unsigned short type; -+ unsigned short valid; -+ unsigned short gmap; -+}; -+ -+static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl) -+{ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ // prepare the table access: -+ // PCE_TBL_ADDR.ADDR = pData->table_index -+ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); -+ // PCE_TBL_CTRL.ADDR = pData->table -+ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); -+ -+ //(address-based read) -+ xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD -+ -+ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access -+ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ // read the keys -+ tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7); -+ tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6); -+ tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5); -+ tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4); -+ tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3); -+ tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2); -+ tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1); -+ tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0); -+ -+ // read the values -+ tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4); -+ tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3); -+ tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2); -+ tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1); -+ tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0); -+ -+ // read the mask -+ tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0); -+ // read the type -+ tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE); -+ // read the valid flag -+ tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD); -+ // read the group map -+ tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP); -+ -+ return 0; -+} -+ -+static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl) -+{ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ // prepare the table access: -+ // PCE_TBL_ADDR.ADDR = pData->table_index -+ xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR); -+ // PCE_TBL_CTRL.ADDR = pData->table -+ xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR); -+ -+ //(address-based write) -+ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD -+ -+ // read the keys -+ xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7); -+ xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6); -+ xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5); -+ xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4); -+ xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3); -+ xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2); -+ xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1); -+ xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0); -+ -+ // read the values -+ xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4); -+ xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3); -+ xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2); -+ xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1); -+ xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0); -+ -+ // read the mask -+ xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0); -+ // read the type -+ xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE); -+ // read the valid flag -+ xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD); -+ // read the group map -+ xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP); -+ -+ xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access -+ -+ // wait until hardware is ready -+ while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {}; -+ -+ return 0; -+} -+ -+static void xrx200sw_fixup_pvids(void) -+{ -+ int index, p, portmap, untagged; -+ struct xrx200_pce_table_entry tem; -+ struct xrx200_pce_table_entry tev; -+ -+ portmap = 0; -+ for (p = 0; p < XRX200_MAX_PORT; p++) -+ portmap |= BIT(p); -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ -+ for (index = XRX200_MAX_VLAN; index-- > 0;) -+ { -+ tev.index = index; -+ xrx200_pce_table_entry_read(&tev); -+ -+ if (tev.valid == 0) -+ continue; -+ -+ tem.index = index; -+ xrx200_pce_table_entry_read(&tem); -+ -+ if (tem.val[0] == 0) -+ continue; -+ -+ untagged = portmap & (tem.val[1] ^ tem.val[2]); -+ -+ for (p = 0; p < XRX200_MAX_PORT; p++) -+ if (untagged & BIT(p)) -+ { -+ portmap &= ~BIT(p); -+ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); -+ } -+ -+ for (p = 0; p < XRX200_MAX_PORT; p++) -+ if (portmap & BIT(p)) -+ xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p); -+ } -+} -+ -+// swconfig interface -+static void xrx200_hw_init(struct xrx200_hw *hw); -+ -+// global -+static int xrx200sw_reset_switch(struct switch_dev *dev) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ -+ xrx200_hw_init(hw); -+ -+ return 0; -+} -+ -+static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ int p; -+ -+ if ((attr->max > 0) && (val->value.i > attr->max)) -+ return -EINVAL; -+ -+ for (p = 0; p < XRX200_MAX_PORT; p++) { -+ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p); -+ xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p); -+ } -+ -+ xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN); -+ return 0; -+} -+ -+static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ val->value.i = xrx200sw_read(attr->id); -+ return 0; -+} -+ -+static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if ((attr->max > 0) && (val->value.i > attr->max)) -+ return -EINVAL; -+ -+ xrx200sw_write(val->value.i, attr->id); -+ return 0; -+} -+ -+static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ val->value.i = xrx200sw_read(attr->id); -+ return 0; -+} -+ -+// vlan -+static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ int i; -+ struct xrx200_pce_table_entry tev; -+ struct xrx200_pce_table_entry tem; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ -+ for (i = 0; i < XRX200_MAX_VLAN; i++) -+ { -+ tev.index = i; -+ xrx200_pce_table_entry_read(&tev); -+ if (tev.key[0] == val->value.i && i != val->port_vlan) -+ return -EINVAL; -+ } -+ -+ hw->vlan_vid[val->port_vlan] = val->value.i; -+ -+ tev.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tev); -+ tev.key[0] = val->value.i; -+ tev.valid = val->value.i > 0; -+ xrx200_pce_table_entry_write(&tev); -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ tem.val[0] = val->value.i; -+ xrx200_pce_table_entry_write(&tem); -+ -+ xrx200sw_fixup_pvids(); -+ return 0; -+} -+ -+static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_pce_table_entry te; -+ -+ te.table = XRX200_PCE_ACTVLAN_IDX; -+ te.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&te); -+ val->value.i = te.key[0]; -+ -+ return 0; -+} -+ -+static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev); -+ int i, portmap, tagmap, untagged; -+ struct xrx200_pce_table_entry tem; -+ -+ portmap = 0; -+ tagmap = 0; -+ for (i = 0; i < val->len; i++) -+ { -+ struct switch_port *p = &val->value.ports[i]; -+ -+ portmap |= (1 << p->id); -+ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) -+ tagmap |= (1 << p->id); -+ } -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ -+ untagged = portmap ^ tagmap; -+ for (i = 0; i < XRX200_MAX_VLAN; i++) -+ { -+ tem.index = i; -+ xrx200_pce_table_entry_read(&tem); -+ -+ if (tem.val[0] == 0) -+ continue; -+ -+ if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i)) -+ return -EINVAL; -+ } -+ -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ -+ // auto-enable this vlan if not enabled already -+ if (tem.val[0] == 0) -+ { -+ struct switch_val v; -+ v.port_vlan = val->port_vlan; -+ v.value.i = val->port_vlan; -+ if(xrx200sw_set_vlan_vid(dev, NULL, &v)) -+ return -EINVAL; -+ -+ //read updated tem -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ } -+ -+ tem.val[1] = portmap; -+ tem.val[2] = tagmap; -+ xrx200_pce_table_entry_write(&tem); -+ -+ ltq_switch_w32_mask(0, portmap, PCE_PMAP2); -+ ltq_switch_w32_mask(0, portmap, PCE_PMAP3); -+ hw->vlan_port_map[val->port_vlan] = portmap; -+ -+ xrx200sw_fixup_pvids(); -+ -+ return 0; -+} -+ -+static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ int i; -+ unsigned short ports, tags; -+ struct xrx200_pce_table_entry tem; -+ -+ tem.table = XRX200_PCE_VLANMAP_IDX; -+ tem.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tem); -+ -+ ports = tem.val[1]; -+ tags = tem.val[2]; -+ -+ for (i = 0; i < XRX200_MAX_PORT; i++) { -+ struct switch_port *p; -+ -+ if (!(ports & (1 << i))) -+ continue; -+ -+ p = &val->value.ports[val->len++]; -+ p->id = i; -+ if (tags & (1 << i)) -+ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); -+ else -+ p->flags = 0; -+ } -+ -+ return 0; -+} -+ -+static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_pce_table_entry tev; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ tev.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tev); -+ -+ if (tev.key[0] == 0) -+ return -EINVAL; -+ -+ tev.valid = val->value.i; -+ xrx200_pce_table_entry_write(&tev); -+ -+ xrx200sw_fixup_pvids(); -+ return 0; -+} -+ -+static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct xrx200_pce_table_entry tev; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ tev.index = val->port_vlan; -+ xrx200_pce_table_entry_read(&tev); -+ val->value.i = tev.valid; -+ -+ return 0; -+} -+ -+// port -+static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val) -+{ -+ struct xrx200_pce_table_entry tev; -+ -+ if (port >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ tev.table = XRX200_PCE_ACTVLAN_IDX; -+ tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port); -+ xrx200_pce_table_entry_read(&tev); -+ -+ *val = tev.key[0]; -+ return 0; -+} -+ -+static int xrx200sw_get_port_link(struct switch_dev *dev, -+ int port, -+ struct switch_port_link *link) -+{ -+ if (port >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port); -+ if (!link->link) -+ return 0; -+ -+ link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port); -+ -+ link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010); -+ link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020); -+ link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port)); -+ -+ link->speed = SWITCH_PORT_SPEED_10; -+ if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port)) -+ link->speed = SWITCH_PORT_SPEED_100; -+ if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port)) -+ link->speed = SWITCH_PORT_SPEED_1000; -+ -+ return 0; -+} -+ -+static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if (val->port_vlan >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ if ((attr->max > 0) && (val->value.i > attr->max)) -+ return -EINVAL; -+ -+ xrx200sw_write_x(val->value.i, attr->id, val->port_vlan); -+ return 0; -+} -+ -+static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if (val->port_vlan >= XRX200_MAX_PORT) -+ return -EINVAL; -+ -+ val->value.i = xrx200sw_read_x(attr->id, val->port_vlan); -+ return 0; -+} -+ -+// attributes -+static struct switch_attr xrx200sw_globals[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .set = xrx200_set_vlan_mode_enable, -+ .get = xrx200_get_vlan_mode_enable, -+ .name = "enable_vlan", -+ .description = "Enable VLAN mode", -+ .max = 1}, -+}; -+ -+static struct switch_attr xrx200sw_port[] = { -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR), -+ .name = "uvr", -+ .description = "Unknown VLAN Rule", -+ .max = 1, -+ }, -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR), -+ .name = "vsr", -+ .description = "VLAN Security Rule", -+ .max = 1, -+ }, -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR), -+ .name = "vinr", -+ .description = "VLAN Ingress Tag Rule", -+ .max = 2, -+ }, -+ { -+ XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM), -+ .name = "tvm", -+ .description = "Transparent VLAN Mode", -+ .max = 1, -+ }, -+}; -+ -+static struct switch_attr xrx200sw_vlan[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "vid", -+ .description = "VLAN ID (0-4094)", -+ .set = xrx200sw_set_vlan_vid, -+ .get = xrx200sw_get_vlan_vid, -+ .max = 4094, -+ }, -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "enable", -+ .description = "Enable VLAN", -+ .set = xrx200sw_set_vlan_enable, -+ .get = xrx200sw_get_vlan_enable, -+ .max = 1, -+ }, -+}; -+ -+static const struct switch_dev_ops xrx200sw_ops = { -+ .attr_global = { -+ .attr = xrx200sw_globals, -+ .n_attr = ARRAY_SIZE(xrx200sw_globals), -+ }, -+ .attr_port = { -+ .attr = xrx200sw_port, -+ .n_attr = ARRAY_SIZE(xrx200sw_port), -+ }, -+ .attr_vlan = { -+ .attr = xrx200sw_vlan, -+ .n_attr = ARRAY_SIZE(xrx200sw_vlan), -+ }, -+ .get_vlan_ports = xrx200sw_get_vlan_ports, -+ .set_vlan_ports = xrx200sw_set_vlan_ports, -+ .get_port_pvid = xrx200sw_get_port_pvid, -+ .reset_switch = xrx200sw_reset_switch, -+ .get_port_link = xrx200sw_get_port_link, -+// .get_port_stats = xrx200sw_get_port_stats, //TODO -+}; -+ -+static int xrx200sw_init(struct xrx200_hw *hw) -+{ -+ int netdev_num; -+ -+ for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++) -+ { -+ struct switch_dev *swdev; -+ struct net_device *dev = hw->devs[netdev_num]; -+ struct xrx200_priv *priv = netdev_priv(dev); -+ if (!priv->sw) -+ continue; -+ -+ swdev = &hw->swdev; -+ -+ swdev->name = "Lantiq XRX200 Switch"; -+ swdev->vlans = XRX200_MAX_VLAN; -+ swdev->ports = XRX200_MAX_PORT; -+ swdev->cpu_port = 6; -+ swdev->ops = &xrx200sw_ops; -+ -+ register_switch(swdev, dev); -+ return 0; // enough switches -+ } -+ return 0; -+} -+ -+static int xrx200_open(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ for (i = 0; i < XRX200_MAX_DMA; i++) { -+ if (!priv->hw->chan[i].dma.irq) -+ continue; -+ spin_lock_bh(&priv->hw->chan[i].lock); -+ if (!priv->hw->chan[i].refcount) { -+ if (XRX200_DMA_IS_RX(i)) -+ napi_enable(&priv->hw->chan[i].napi); -+ ltq_dma_open(&priv->hw->chan[i].dma); -+ } -+ priv->hw->chan[i].refcount++; -+ spin_unlock_bh(&priv->hw->chan[i].lock); -+ } -+ for (i = 0; i < priv->num_port; i++) -+ if (priv->port[i].phydev) -+ phy_start(priv->port[i].phydev); -+ netif_wake_queue(dev); -+ -+ return 0; -+} -+ -+static int xrx200_close(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ netif_stop_queue(dev); -+ -+ for (i = 0; i < priv->num_port; i++) -+ if (priv->port[i].phydev) -+ phy_stop(priv->port[i].phydev); -+ -+ for (i = 0; i < XRX200_MAX_DMA; i++) { -+ if (!priv->hw->chan[i].dma.irq) -+ continue; -+ -+ priv->hw->chan[i].refcount--; -+ if (!priv->hw->chan[i].refcount) { -+ if (XRX200_DMA_IS_RX(i)) -+ napi_disable(&priv->hw->chan[i].napi); -+ spin_lock_bh(&priv->hw->chan[i].lock); -+ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma); -+ spin_unlock_bh(&priv->hw->chan[i].lock); -+ } -+ } -+ -+ return 0; -+} -+ -+static int xrx200_alloc_skb(struct xrx200_chan *ch) -+{ -+#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD) -+ ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD); -+ if (!ch->skb[ch->dma.desc]) -+ goto skip; -+ -+ skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD); -+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, -+ ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, -+ DMA_FROM_DEVICE); -+ ch->dma.desc_base[ch->dma.desc].addr = -+ CPHYSADDR(ch->skb[ch->dma.desc]->data); -+ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); -+ -+skip: -+ ch->dma.desc_base[ch->dma.desc].ctl = -+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | -+ XRX200_DMA_DATA_LEN; -+ -+ return 0; -+} -+ -+static void xrx200_hw_receive(struct xrx200_chan *ch, int id) -+{ -+ struct net_device *dev = ch->devs[id]; -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ int len = (desc->ctl & LTQ_DMA_SIZE_MASK); -+ int ret; -+ -+ ret = xrx200_alloc_skb(ch); -+ -+ ch->dma.desc++; -+ ch->dma.desc %= LTQ_DESC_NUM; -+ -+ if (ret) { -+ netdev_err(dev, -+ "failed to allocate new rx buffer\n"); -+ return; -+ } -+ -+ skb_put(skb, len); -+#ifdef SW_ROUTING -+ skb_pull(skb, 8); -+#endif -+ skb->dev = dev; -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_receive_skb(skb); -+ priv->stats.rx_packets++; -+ priv->stats.rx_bytes+=len; -+} -+ -+static int xrx200_poll_rx(struct napi_struct *napi, int budget) -+{ -+ struct xrx200_chan *ch = container_of(napi, -+ struct xrx200_chan, napi); -+ struct xrx200_priv *priv = netdev_priv(ch->devs[0]); -+ int rx = 0; -+ int complete = 0; -+ -+ while ((rx < budget) && !complete) { -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+#ifdef SW_ROUTING -+ struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ u8 *special_tag = (u8*)skb->data; -+ int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK; -+ xrx200_hw_receive(ch, priv->hw->port_map[port]); -+#else -+ xrx200_hw_receive(ch, 0); -+#endif -+ rx++; -+ } else { -+ complete = 1; -+ } -+ } -+ -+ if (complete || !rx) { -+ napi_complete(&ch->napi); -+ ltq_dma_enable_irq(&ch->dma); -+ } -+ -+ return rx; -+} -+ -+static void xrx200_tx_housekeeping(unsigned long ptr) -+{ -+ struct xrx200_chan *ch = (struct xrx200_chan *) ptr; -+ int pkts = 0; -+ int i; -+ -+ spin_lock_bh(&ch->lock); -+ ltq_dma_ack_irq(&ch->dma); -+ while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ struct sk_buff *skb = ch->skb[ch->tx_free]; -+ -+ pkts++; -+ ch->skb[ch->tx_free] = NULL; -+ dev_kfree_skb(skb); -+ memset(&ch->dma.desc_base[ch->tx_free], 0, -+ sizeof(struct ltq_dma_desc)); -+ ch->tx_free++; -+ ch->tx_free %= LTQ_DESC_NUM; -+ } -+ ltq_dma_enable_irq(&ch->dma); -+ spin_unlock_bh(&ch->lock); -+ -+ if (!pkts) -+ return; -+ -+ for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++) -+ netif_wake_queue(ch->devs[i]); -+} -+ -+static struct net_device_stats *xrx200_get_stats (struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ -+ return &priv->stats; -+} -+ -+static void xrx200_tx_timeout(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ -+ printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name); -+ -+ priv->stats.tx_errors++; -+ netif_wake_queue(dev); -+} -+ -+static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct xrx200_chan *ch; -+ struct ltq_dma_desc *desc; -+ u32 byte_offset; -+ int ret = NETDEV_TX_OK; -+ int len; -+#ifdef SW_ROUTING -+ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE; -+#endif -+ if(priv->id) -+ ch = &priv->hw->chan[XRX200_DMA_TX_2]; -+ else -+ ch = &priv->hw->chan[XRX200_DMA_TX]; -+ -+ desc = &ch->dma.desc_base[ch->dma.desc]; -+ -+ skb->dev = dev; -+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; -+ -+#ifdef SW_ROUTING -+ if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) { -+ u16 port_map = priv->port_map; -+ -+ if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) { -+ u16 vid; -+ int i; -+ -+ port_map = 0; -+ if (!__vlan_get_tag(skb, &vid)) { -+ for (i = 0; i < XRX200_MAX_VLAN; i++) { -+ if (priv->hw->vlan_vid[i] != vid) -+ continue; -+ port_map = priv->hw->vlan_port_map[i]; -+ break; -+ } -+ } -+ } -+ -+ special_tag |= (port_map << PORT_MAP_SHIFT) | -+ PORT_MAP_SEL | PORT_MAP_EN; -+ } -+ if(priv->wan) -+ special_tag |= (1 << DPID_SHIFT); -+ if(skb_headroom(skb) < 4) { -+ struct sk_buff *tmp = skb_realloc_headroom(skb, 4); -+ dev_kfree_skb_any(skb); -+ skb = tmp; -+ } -+ skb_push(skb, 4); -+ memcpy(skb->data, &special_tag, sizeof(u32)); -+ len += 4; -+#endif -+ -+ /* dma needs to start on a 16 byte aligned address */ -+ byte_offset = CPHYSADDR(skb->data) % 16; -+ -+ spin_lock_bh(&ch->lock); -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -+ netdev_err(dev, "tx ring full\n"); -+ netif_stop_queue(dev); -+ ret = NETDEV_TX_BUSY; -+ goto out; -+ } -+ -+ ch->skb[ch->dma.desc] = skb; -+ -+ netif_trans_update(dev); -+ -+ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, -+ DMA_TO_DEVICE)) - byte_offset; -+ wmb(); -+ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | -+ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -+ ch->dma.desc++; -+ ch->dma.desc %= LTQ_DESC_NUM; -+ if (ch->dma.desc == ch->tx_free) -+ netif_stop_queue(dev); -+ -+ -+ priv->stats.tx_packets++; -+ priv->stats.tx_bytes+=len; -+ -+out: -+ spin_unlock_bh(&ch->lock); -+ -+ return ret; -+} -+ -+static irqreturn_t xrx200_dma_irq(int irq, void *priv) -+{ -+ struct xrx200_hw *hw = priv; -+ int chnr = irq - XRX200_DMA_IRQ; -+ struct xrx200_chan *ch = &hw->chan[chnr]; -+ -+ ltq_dma_disable_irq(&ch->dma); -+ ltq_dma_ack_irq(&ch->dma); -+ -+ if (chnr % 2) -+ tasklet_schedule(&ch->tasklet); -+ else -+ napi_schedule(&ch->napi); -+ -+ return IRQ_HANDLED; -+} -+ -+static int xrx200_dma_init(struct xrx200_hw *hw) -+{ -+ int i, err = 0; -+ -+ ltq_dma_init_port(DMA_PORT_ETOP); -+ -+ for (i = 0; i < 8 && !err; i++) { -+ int irq = XRX200_DMA_IRQ + i; -+ struct xrx200_chan *ch = &hw->chan[i]; -+ -+ spin_lock_init(&ch->lock); -+ -+ ch->idx = ch->dma.nr = i; -+ -+ if (i == XRX200_DMA_TX) { -+ ltq_dma_alloc_tx(&ch->dma); -+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw); -+ } else if (i == XRX200_DMA_TX_2) { -+ ltq_dma_alloc_tx(&ch->dma); -+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw); -+ } else if (i == XRX200_DMA_RX) { -+ ltq_dma_alloc_rx(&ch->dma); -+ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -+ ch->dma.desc++) -+ if (xrx200_alloc_skb(ch)) -+ err = -ENOMEM; -+ ch->dma.desc = 0; -+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw); -+ } else -+ continue; -+ -+ if (!err) -+ ch->dma.irq = irq; -+ else -+ pr_err("net-xrx200: failed to request irq %d\n", irq); -+ } -+ -+ return err; -+} -+ -+#ifdef SW_POLLING -+static void xrx200_gmac_update(struct xrx200_port *port) -+{ -+ u16 phyaddr = port->phydev->mdio.addr & MDIO_PHY_ADDR_MASK; -+ u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK; -+ u16 miirate = 0; -+ -+ switch (port->phydev->speed) { -+ case SPEED_1000: -+ phyaddr |= MDIO_PHY_SPEED_G1; -+ miirate = MII_CFG_RATE_M125; -+ break; -+ -+ case SPEED_100: -+ phyaddr |= MDIO_PHY_SPEED_M100; -+ switch (miimode) { -+ case MII_CFG_MODE_RMIIM: -+ case MII_CFG_MODE_RMIIP: -+ miirate = MII_CFG_RATE_M50; -+ break; -+ default: -+ miirate = MII_CFG_RATE_M25; -+ break; -+ } -+ break; -+ -+ default: -+ phyaddr |= MDIO_PHY_SPEED_M10; -+ miirate = MII_CFG_RATE_M2P5; -+ break; -+ } -+ -+ if (port->phydev->link) -+ phyaddr |= MDIO_PHY_LINK_UP; -+ else -+ phyaddr |= MDIO_PHY_LINK_DOWN; -+ -+ if (port->phydev->duplex == DUPLEX_FULL) -+ phyaddr |= MDIO_PHY_FDUP_EN; -+ else -+ phyaddr |= MDIO_PHY_FDUP_DIS; -+ -+ ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num)); -+ ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num)); -+ udelay(1); -+} -+#else -+static void xrx200_gmac_update(struct xrx200_port *port) -+{ -+ -+} -+#endif -+ -+static void xrx200_mdio_link(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ bool link = false; -+ int i; -+ -+ for (i = 0; i < priv->num_port; i++) { -+ if (!priv->port[i].phydev) -+ continue; -+ -+ if (priv->port[i].phydev->link) -+ link = true; -+ -+ if (priv->port[i].link != priv->port[i].phydev->link) { -+ xrx200_gmac_update(&priv->port[i]); -+ priv->port[i].link = priv->port[i].phydev->link; -+ netdev_info(dev, "port %d %s link\n", -+ priv->port[i].num, -+ (priv->port[i].link)?("got"):("lost")); -+ } -+ } -+ if (netif_carrier_ok(dev) && !link) -+ netif_carrier_off(dev); -+} -+ -+static inline int xrx200_mdio_poll(struct mii_bus *bus) -+{ -+ unsigned cnt = 10000; -+ -+ while (likely(cnt--)) { -+ unsigned ctrl = ltq_mdio_r32(MDIO_CTRL); -+ if ((ctrl & MDIO_BUSY) == 0) -+ return 0; -+ } -+ -+ return 1; -+} -+ -+static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) -+{ -+ if (xrx200_mdio_poll(bus)) -+ return 1; -+ -+ ltq_mdio_w32(val, MDIO_WRITE); -+ ltq_mdio_w32(MDIO_BUSY | MDIO_WR | -+ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | -+ (reg & MDIO_MASK), -+ MDIO_CTRL); -+ -+ return 0; -+} -+ -+static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg) -+{ -+ if (xrx200_mdio_poll(bus)) -+ return -1; -+ -+ ltq_mdio_w32(MDIO_BUSY | MDIO_RD | -+ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) | -+ (reg & MDIO_MASK), -+ MDIO_CTRL); -+ -+ if (xrx200_mdio_poll(bus)) -+ return -1; -+ -+ return ltq_mdio_r32(MDIO_READ); -+} -+ -+static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ unsigned val; -+ -+ phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr); -+ -+ if (!phydev) { -+ netdev_err(dev, "no PHY found\n"); -+ return -ENODEV; -+ } -+ -+ phydev = phy_connect(dev, phydev_name(phydev), &xrx200_mdio_link, -+ port->phy_if); -+ -+ if (IS_ERR(phydev)) { -+ netdev_err(dev, "Could not attach to PHY\n"); -+ return PTR_ERR(phydev); -+ } -+ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full -+ | SUPPORTED_Autoneg -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ phydev->advertising = phydev->supported; -+ port->phydev = phydev; -+ phydev->no_auto_carrier_off = true; -+ -+ phy_attached_info(phydev); -+ -+#ifdef SW_POLLING -+ phy_read_status(phydev); -+ -+ val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); -+ val |= ADVERTIZE_MPD; -+ xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); -+ xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040); -+ -+ phy_start_aneg(phydev); -+#endif -+ return 0; -+} -+ -+static void xrx200_port_config(struct xrx200_priv *priv, -+ const struct xrx200_port *port) -+{ -+ u16 miimode = 0; -+ -+ switch (port->num) { -+ case 0: /* xMII0 */ -+ case 1: /* xMII1 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ if (port->flags & XRX200_PORT_TYPE_PHY) -+ /* MII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_MIIM; -+ else -+ /* MII PHY mode, connected to external MAC */ -+ miimode = MII_CFG_MODE_MIIP; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ if (port->flags & XRX200_PORT_TYPE_PHY) -+ /* RMII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_RMIIM; -+ else -+ /* RMII PHY mode, connected to external MAC */ -+ miimode = MII_CFG_MODE_RMIIP; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ /* RGMII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_RGMII; -+ break; -+ default: -+ break; -+ } -+ break; -+ case 2: /* internal GPHY0 */ -+ case 3: /* internal GPHY0 */ -+ case 4: /* internal GPHY1 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ case PHY_INTERFACE_MODE_GMII: -+ /* MII MAC mode, connected to internal GPHY */ -+ miimode = MII_CFG_MODE_MIIM; -+ break; -+ default: -+ break; -+ } -+ break; -+ case 5: /* internal GPHY1 or xMII2 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ /* MII MAC mode, connected to internal GPHY */ -+ miimode = MII_CFG_MODE_MIIM; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ /* RGMII MAC mode, connected to external PHY */ -+ miimode = MII_CFG_MODE_RGMII; -+ break; -+ default: -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN, -+ MII_CFG(port->num)); -+} -+ -+static int xrx200_init(struct net_device *dev) -+{ -+ struct xrx200_priv *priv = netdev_priv(dev); -+ struct sockaddr mac; -+ int err, i; -+ -+#ifndef SW_POLLING -+ unsigned int reg = 0; -+ -+ /* enable auto polling */ -+ for (i = 0; i < priv->num_port; i++) -+ reg |= BIT(priv->port[i].num); -+ ltq_mdio_w32(reg, MDIO_CLK_CFG0); -+ ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1); -+#endif -+ -+ /* setup each port */ -+ for (i = 0; i < priv->num_port; i++) -+ xrx200_port_config(priv, &priv->port[i]); -+ -+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); -+ if (!is_valid_ether_addr(mac.sa_data)) { -+ pr_warn("net-xrx200: invalid MAC, using random\n"); -+ eth_random_addr(mac.sa_data); -+ dev->addr_assign_type |= NET_ADDR_RANDOM; -+ } -+ -+ err = eth_mac_addr(dev, &mac); -+ if (err) -+ goto err_netdev; -+ -+ for (i = 0; i < priv->num_port; i++) -+ if (xrx200_mdio_probe(dev, &priv->port[i])) -+ pr_warn("xrx200-mdio: probing phy of port %d failed\n", -+ priv->port[i].num); -+ -+ return 0; -+ -+err_netdev: -+ unregister_netdev(dev); -+ free_netdev(dev); -+ return err; -+} -+ -+static void xrx200_pci_microcode(void) -+{ -+ int i; -+ -+ ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK, -+ PCE_TBL_CFG_ADWR, PCE_TBL_CTRL); -+ ltq_switch_w32(0, PCE_TBL_MASK); -+ -+ for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) { -+ ltq_switch_w32(i, PCE_TBL_ADDR); -+ ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0)); -+ ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1)); -+ ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2)); -+ ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3)); -+ -+ // start the table access: -+ ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL); -+ while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY); -+ } -+ -+ /* tell the switch that the microcode is loaded */ -+ ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0)); -+} -+ -+static void xrx200_hw_init(struct xrx200_hw *hw) -+{ -+ int i; -+ -+ /* enable clock gate */ -+ clk_enable(hw->clk); -+ -+ ltq_switch_w32(1, 0); -+ mdelay(100); -+ ltq_switch_w32(0, 0); -+ /* -+ * TODO: we should really disbale all phys/miis here and explicitly -+ * enable them in the device secific init function -+ */ -+ -+ /* disable port fetch/store dma */ -+ for (i = 0; i < 7; i++ ) { -+ ltq_switch_w32(0, FDMA_PCTRLx(i)); -+ ltq_switch_w32(0, SDMA_PCTRLx(i)); -+ } -+ -+ /* enable Switch */ -+ ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB); -+ -+ /* load the pce microcode */ -+ xrx200_pci_microcode(); -+ -+ /* Default unknown Broadcat/Multicast/Unicast port maps */ -+ ltq_switch_w32(0x40, PCE_PMAP1); -+ ltq_switch_w32(0x40, PCE_PMAP2); -+ ltq_switch_w32(0x40, PCE_PMAP3); -+ -+ /* RMON Counter Enable for all physical ports */ -+ for (i = 0; i < 7; i++) -+ ltq_switch_w32(0x1, BM_PCFG(i)); -+ -+ /* disable auto polling */ -+ ltq_mdio_w32(0x0, MDIO_CLK_CFG0); -+ -+ /* enable port statistic counters */ -+ for (i = 0; i < 7; i++) -+ ltq_switch_w32(0x1, BM_PCFGx(i)); -+ -+ /* set IPG to 12 */ -+ ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG); -+ -+#ifdef SW_ROUTING -+ /* enable status header, enable CRC */ -+ ltq_pmac_w32_mask(0, -+ PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, -+ PMAC_HD_CTL); -+#else -+ /* disable status header, enable CRC */ -+ ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS, -+ PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, -+ PMAC_HD_CTL); -+#endif -+ -+ /* enable port fetch/store dma & VLAN Modification */ -+ for (i = 0; i < 7; i++ ) { -+ ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i)); -+ ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i)); -+ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0)); -+ } -+ -+ /* enable special tag insertion on cpu port */ -+ ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6)); -+ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0)); -+ ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2)); -+ ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG); -+ xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0); -+ -+ for (i = 0; i < XRX200_MAX_VLAN; i++) -+ hw->vlan_vid[i] = i; -+} -+ -+static void xrx200_hw_cleanup(struct xrx200_hw *hw) -+{ -+ int i; -+ -+ /* disable the switch */ -+ ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB); -+ -+ /* free the channels and IRQs */ -+ for (i = 0; i < 2; i++) { -+ ltq_dma_free(&hw->chan[i].dma); -+ if (hw->chan[i].dma.irq) -+ free_irq(hw->chan[i].dma.irq, hw); -+ } -+ -+ /* free the allocated RX ring */ -+ for (i = 0; i < LTQ_DESC_NUM; i++) -+ dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]); -+ -+ /* clear the mdio bus */ -+ mdiobus_unregister(hw->mii_bus); -+ mdiobus_free(hw->mii_bus); -+ -+ /* release the clock */ -+ clk_disable(hw->clk); -+ clk_put(hw->clk); -+} -+ -+static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np) -+{ -+ hw->mii_bus = mdiobus_alloc(); -+ if (!hw->mii_bus) -+ return -ENOMEM; -+ -+ hw->mii_bus->read = xrx200_mdio_rd; -+ hw->mii_bus->write = xrx200_mdio_wr; -+ hw->mii_bus->name = "lantiq,xrx200-mdio"; -+ snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); -+ -+ if (of_mdiobus_register(hw->mii_bus, np)) { -+ mdiobus_free(hw->mii_bus); -+ return -ENXIO; -+ } -+ -+ return 0; -+} -+ -+static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port) -+{ -+ const __be32 *addr, *id = of_get_property(port, "reg", NULL); -+ struct xrx200_port *p = &priv->port[priv->num_port]; -+ -+ if (!id) -+ return; -+ -+ memset(p, 0, sizeof(struct xrx200_port)); -+ p->phy_node = of_parse_phandle(port, "phy-handle", 0); -+ addr = of_get_property(p->phy_node, "reg", NULL); -+ if (!addr) -+ return; -+ -+ p->num = *id; -+ p->phy_addr = *addr; -+ p->phy_if = of_get_phy_mode(port); -+ if (p->phy_addr > 0x10) -+ p->flags = XRX200_PORT_TYPE_MAC; -+ else -+ p->flags = XRX200_PORT_TYPE_PHY; -+ priv->num_port++; -+ -+ p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags); -+ if (gpio_is_valid(p->gpio)) -+ if (!gpio_request(p->gpio, "phy-reset")) { -+ gpio_direction_output(p->gpio, -+ (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0)); -+ udelay(100); -+ gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); -+ } -+ /* is this port a wan port ? */ -+ if (priv->wan) -+ priv->hw->wan_map |= BIT(p->num); -+ -+ priv->port_map |= BIT(p->num); -+ -+ /* store the port id in the hw struct so we can map ports -> devices */ -+ priv->hw->port_map[p->num] = priv->hw->num_devs; -+} -+ -+static const struct net_device_ops xrx200_netdev_ops = { -+ .ndo_init = xrx200_init, -+ .ndo_open = xrx200_open, -+ .ndo_stop = xrx200_close, -+ .ndo_start_xmit = xrx200_start_xmit, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_get_stats = xrx200_get_stats, -+ .ndo_tx_timeout = xrx200_tx_timeout, -+}; -+ -+static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev) -+{ -+ struct xrx200_priv *priv; -+ struct device_node *port; -+ const __be32 *wan; -+ const u8 *mac; -+ -+ /* alloc the network device */ -+ hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv)); -+ if (!hw->devs[hw->num_devs]) -+ return; -+ -+ /* setup the network device */ -+ strcpy(hw->devs[hw->num_devs]->name, "eth%d"); -+ hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops; -+ hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT; -+ hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM; -+ SET_NETDEV_DEV(hw->devs[hw->num_devs], dev); -+ -+ /* setup our private data */ -+ priv = netdev_priv(hw->devs[hw->num_devs]); -+ priv->hw = hw; -+ priv->id = hw->num_devs; -+ -+ mac = of_get_mac_address(iface); -+ if (mac) -+ memcpy(priv->mac, mac, ETH_ALEN); -+ -+ /* is this the wan interface ? */ -+ wan = of_get_property(iface, "lantiq,wan", NULL); -+ if (wan && (*wan == 1)) -+ priv->wan = 1; -+ -+ /* should the switch be enabled on this interface ? */ -+ if (of_find_property(iface, "lantiq,switch", NULL)) -+ priv->sw = 1; -+ -+ /* load the ports that are part of the interface */ -+ for_each_child_of_node(iface, port) -+ if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port")) -+ xrx200_of_port(priv, port); -+ -+ /* register the actual device */ -+ if (!register_netdev(hw->devs[hw->num_devs])) -+ hw->num_devs++; -+} -+ -+static struct xrx200_hw xrx200_hw; -+ -+static int xrx200_probe(struct platform_device *pdev) -+{ -+ struct resource *res[4]; -+ struct device_node *mdio_np, *iface_np; -+ int i; -+ -+ /* load the memory ranges */ -+ for (i = 0; i < 4; i++) { -+ res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); -+ if (!res[i]) { -+ dev_err(&pdev->dev, "failed to get resources\n"); -+ return -ENOENT; -+ } -+ } -+ xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]); -+ xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]); -+ xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]); -+ xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]); -+ if (!xrx200_switch_membase || !xrx200_mdio_membase || -+ !xrx200_mii_membase || !xrx200_pmac_membase) { -+ dev_err(&pdev->dev, "failed to request and remap io ranges \n"); -+ return -ENOMEM; -+ } -+ -+ /* get the clock */ -+ xrx200_hw.clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(xrx200_hw.clk)) { -+ dev_err(&pdev->dev, "failed to get clock\n"); -+ return PTR_ERR(xrx200_hw.clk); -+ } -+ -+ /* bring up the dma engine and IP core */ -+ xrx200_dma_init(&xrx200_hw); -+ xrx200_hw_init(&xrx200_hw); -+ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]); -+ tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]); -+ -+ /* bring up the mdio bus */ -+ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL, -+ "lantiq,xrx200-mdio"); -+ if (mdio_np) -+ if (xrx200_of_mdio(&xrx200_hw, mdio_np)) -+ dev_err(&pdev->dev, "mdio probe failed\n"); -+ -+ /* load the interfaces */ -+ for_each_child_of_node(pdev->dev.of_node, iface_np) -+ if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) { -+ if (xrx200_hw.num_devs < XRX200_MAX_DEV) -+ xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev); -+ else -+ dev_err(&pdev->dev, -+ "only %d interfaces allowed\n", -+ XRX200_MAX_DEV); -+ } -+ -+ if (!xrx200_hw.num_devs) { -+ xrx200_hw_cleanup(&xrx200_hw); -+ dev_err(&pdev->dev, "failed to load interfaces\n"); -+ return -ENOENT; -+ } -+ -+ xrx200sw_init(&xrx200_hw); -+ -+ /* set wan port mask */ -+ ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN); -+ -+ for (i = 0; i < xrx200_hw.num_devs; i++) { -+ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i]; -+ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i]; -+ xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i]; -+ } -+ -+ /* setup NAPI */ -+ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev); -+ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev, -+ &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32); -+ -+ platform_set_drvdata(pdev, &xrx200_hw); -+ -+ return 0; -+} -+ -+static int xrx200_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct xrx200_priv *priv; -+ -+ if (!dev) -+ return 0; -+ -+ priv = netdev_priv(dev); -+ -+ /* free stack related instances */ -+ netif_stop_queue(dev); -+ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi); -+ -+ /* shut down hardware */ -+ xrx200_hw_cleanup(&xrx200_hw); -+ -+ /* remove the actual device */ -+ unregister_netdev(dev); -+ free_netdev(dev); -+ -+ return 0; -+} -+ -+static const struct of_device_id xrx200_match[] = { -+ { .compatible = "lantiq,xrx200-net" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, xrx200_match); -+ -+static struct platform_driver xrx200_driver = { -+ .probe = xrx200_probe, -+ .remove = xrx200_remove, -+ .driver = { -+ .name = "lantiq,xrx200-net", -+ .of_match_table = xrx200_match, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+module_platform_driver(xrx200_driver); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); -+MODULE_LICENSE("GPL"); ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_xrx200_sw.h -@@ -0,0 +1,1328 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2013 Antonios Vamporakis -+ * -+ * VR9 switch registers extracted from 310TUJ0 switch api -+ * WARNING mult values of 0x00 may not be correct -+ * -+ */ -+ -+enum { -+// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */ -+// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */ -+// XRX200_ETHSW_SWRES_R0, /* Register Configuration */ -+// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */ -+// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */ -+// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */ -+// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */ -+// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */ -+// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */ -+// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */ -+// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */ -+// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */ -+// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */ -+// XRX200_ETHSW_DBG_MODE, /* Debug Mode */ -+// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */ -+// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */ -+// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */ -+// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */ -+// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */ -+// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */ -+// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */ -+// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */ -+// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */ -+// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */ -+// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */ -+// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */ -+// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */ -+// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */ -+// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */ -+// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */ -+// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */ -+// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */ -+// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */ -+// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */ -+// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */ -+// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */ -+// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */ -+// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */ -+// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */ -+// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */ -+// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */ -+// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */ -+// XRX200_ETHSW_CAP_6_APPL, /* Application table size */ -+// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */ -+// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */ -+// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */ -+// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */ -+// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */ -+// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */ -+// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */ -+// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */ -+// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */ -+// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */ -+// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */ -+// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */ -+// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */ -+// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */ -+// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */ -+// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */ -+// XRX200_ETHSW_IER, /* Interrupt Enable Register */ -+// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */ -+// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */ -+// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */ -+// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */ -+// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */ -+// XRX200_ETHSW_ISR, /* Interrupt Status Register */ -+// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */ -+// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */ -+// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */ -+// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */ -+// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */ -+// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */ -+// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */ -+// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */ -+// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */ -+// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */ -+// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */ -+// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */ -+// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */ -+// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */ -+// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */ -+// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */ -+// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */ -+// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */ -+// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */ -+// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */ -+// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */ -+// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */ -+// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */ -+// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */ -+// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */ -+// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */ -+// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */ -+// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */ -+// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */ -+// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */ -+// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */ -+// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */ -+// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */ -+// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */ -+// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */ -+// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */ -+// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */ -+// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */ -+// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */ -+// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */ -+// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */ -+// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */ -+// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */ -+// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */ -+// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */ -+// XRX200_BM_RAM_ADDR, /* RAM Address Register */ -+// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */ -+// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */ -+// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */ -+// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ -+// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */ -+// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */ -+// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */ -+// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */ -+// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */ -+// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */ -+// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */ -+// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */ -+// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */ -+// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */ -+// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */ -+// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */ -+// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */ -+// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */ -+// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */ -+// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */ -+// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */ -+// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */ -+// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */ -+// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */ -+// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */ -+// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */ -+// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */ -+ XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */ -+// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */ -+// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */ -+// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */ -+// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */ -+// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */ -+// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */ -+// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */ -+// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */ -+// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */ -+// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */ -+// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */ -+// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */ -+// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */ -+// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */ -+// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */ -+// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */ -+// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */ -+// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */ -+// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */ -+// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */ -+// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */ -+// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */ -+// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */ -+// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ -+// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */ -+// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ -+// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */ -+// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */ -+// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */ -+// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */ -+// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */ -+// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */ -+// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */ -+// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */ -+// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */ -+// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */ -+// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */ -+// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */ -+// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */ -+// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */ -+// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */ -+// XRX200_BM_CISEL_PORT, /* Port Number */ -+// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */ -+// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */ -+// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */ -+// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */ -+// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */ -+// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */ -+// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */ -+// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */ -+// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */ -+// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */ -+// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */ -+// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */ -+// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */ -+// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */ -+// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */ -+// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */ -+// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */ -+// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */ -+// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */ -+// XRX200_RS_CBS_CBS, /* Committed Burst Size */ -+// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */ -+// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */ -+// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */ -+// XRX200_RS_CIR_EXP_EXP, /* Exponent */ -+// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */ -+// XRX200_RS_CIR_MANT_MANT, /* Mantissa */ -+ XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */ -+// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */ -+// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */ -+// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */ -+// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */ -+// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */ -+// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */ -+// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */ -+ XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */ -+// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */ -+ XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */ -+// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */ -+ XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */ -+// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */ -+// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */ -+// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */ -+// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */ -+ XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */ -+// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */ -+// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */ -+ XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */ -+// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */ -+ XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */ -+ XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */ -+ XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */ -+ XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */ -+ XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */ -+ XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */ -+// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */ -+// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */ -+// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */ -+// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */ -+// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */ -+// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */ -+// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */ -+// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */ -+// XRX200_PCE_PMAP_1, /* Port Map Register 1 */ -+// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */ -+// XRX200_PCE_PMAP_2, /* Port Map Register 2 */ -+// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */ -+// XRX200_PCE_PMAP_3, /* Port Map Register 3 */ -+// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */ -+// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */ -+// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */ -+ XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */ -+// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */ -+// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */ -+// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */ -+// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */ -+// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */ -+// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */ -+// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */ -+// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */ -+// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */ -+// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */ -+// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */ -+// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */ -+// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */ -+// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */ -+// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */ -+// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */ -+// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */ -+// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */ -+// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */ -+// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */ -+// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */ -+// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */ -+// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */ -+// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */ -+// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */ -+// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */ -+// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */ -+// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */ -+// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */ -+// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */ -+// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */ -+// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */ -+// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */ -+// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */ -+// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */ -+// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */ -+// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */ -+// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */ -+// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */ -+// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */ -+// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */ -+// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */ -+// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */ -+// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */ -+// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */ -+// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */ -+// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */ -+// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */ -+// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */ -+// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */ -+// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */ -+// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */ -+// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */ -+// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */ -+// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */ -+// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */ -+// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */ -+// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */ -+// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */ -+// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */ -+// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */ -+// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */ -+// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */ -+// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */ -+// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */ -+// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */ -+// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */ -+// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */ -+// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */ -+// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */ -+// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */ -+// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */ -+// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */ -+// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */ -+// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */ -+// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */ -+// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */ -+// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */ -+// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */ -+// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */ -+// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */ -+// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */ -+// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */ -+// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */ -+ XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */ -+// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */ -+// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */ -+// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */ -+// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */ -+// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */ -+// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */ -+// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */ -+// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */ -+// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */ -+// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */ -+// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */ -+// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */ -+// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */ -+// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */ -+// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */ -+// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */ -+// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */ -+// XRX200_WOL_CTRL_PORT, /* WoL Enable */ -+// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */ -+ XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */ -+ XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */ -+ XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */ -+ XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */ -+ XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */ -+// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */ -+ XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */ -+// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */ -+// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */ -+// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */ -+// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */ -+// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */ -+// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */ -+// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */ -+// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */ -+// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */ -+// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */ -+// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */ -+// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */ -+// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */ -+// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */ -+// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */ -+// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */ -+// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */ -+// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */ -+// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */ -+// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */ -+// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */ -+// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */ -+// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */ -+// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */ -+// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */ -+// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */ -+// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */ -+// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */ -+// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */ -+// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */ -+// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */ -+// XRX200_MAC_TEST, /* MAC Test Register */ -+// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */ -+// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */ -+// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */ -+// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */ -+// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */ -+// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */ -+// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */ -+// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */ -+// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */ -+// XRX200_MAC_FLEN, /* MAC Frame Length Register */ -+// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */ -+// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */ -+// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */ -+// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */ -+// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */ -+// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */ -+// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */ -+// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */ -+// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */ -+// XRX200_MAC_PSTAT, /* MAC Port Status Register */ -+// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */ -+ XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */ -+ XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */ -+ XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */ -+// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */ -+// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */ -+// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */ -+// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */ -+ XRX200_MAC_PSTAT_LSTAT, /* Link Status */ -+// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */ -+// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */ -+// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */ -+// XRX200_MAC_PISR, /* MAC Interrupt Status Register */ -+// XRX200_MAC_PISR_PACT, /* PHY Active Status */ -+// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */ -+// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */ -+// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */ -+// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */ -+// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */ -+// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */ -+// XRX200_MAC_PISR_JAM, /* Jam Status Detected */ -+// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */ -+// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */ -+// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */ -+// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */ -+// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */ -+// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */ -+// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */ -+// XRX200_MAC_PIER_PACT, /* PHY Active Status */ -+// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */ -+// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */ -+// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */ -+// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */ -+// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */ -+// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */ -+// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */ -+// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */ -+// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */ -+// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */ -+// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */ -+// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */ -+// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */ -+// XRX200_MAC_CTRL_0, /* MAC Control Register0 */ -+// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */ -+// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */ -+// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */ -+// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */ -+// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */ -+// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */ -+// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */ -+ XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */ -+// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */ -+// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */ -+// XRX200_MAC_CTRL_1, /* MAC Control Register1 */ -+// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */ -+// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */ -+// XRX200_MAC_CTRL_2, /* MAC Control Register2 */ -+// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */ -+// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */ -+// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */ -+// XRX200_MAC_CTRL_3, /* MAC Control Register3 */ -+// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */ -+// XRX200_MAC_CTRL_4, /* MAC Control Register4 */ -+// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */ -+// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */ -+// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */ -+// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */ -+// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */ -+// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */ -+// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */ -+// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */ -+// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */ -+// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */ -+// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */ -+// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */ -+// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */ -+// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */ -+// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */ -+// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */ -+// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */ -+// XRX200_MAC_TESTEN, /* MAC Test Enable Register */ -+// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */ -+// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */ -+// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */ -+// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */ -+// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */ -+// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */ -+// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */ -+// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */ -+// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */ -+// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */ -+// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */ -+// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */ -+// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */ -+// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */ -+// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */ -+// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */ -+// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */ -+// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */ -+// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */ -+// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */ -+// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */ -+// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */ -+// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */ -+// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */ -+// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */ -+// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */ -+// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */ -+// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */ -+// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */ -+// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */ -+// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */ -+// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */ -+// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */ -+// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */ -+// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */ -+// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */ -+// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */ -+// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ -+// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */ -+// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ -+// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */ -+// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */ -+// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */ -+// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */ -+// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */ -+// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */ -+// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */ -+// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */ -+// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */ -+// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */ -+// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */ -+// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */ -+// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */ -+// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */ -+// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */ -+// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */ -+// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */ -+// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */ -+// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */ -+// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */ -+// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */ -+// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */ -+// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */ -+// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */ -+// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */ -+// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */ -+// XRX200_SDMA_IER_BFULL, /* Buffer Full */ -+// XRX200_SDMA_IER_FERR, /* Frame Error */ -+// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */ -+// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */ -+// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */ -+// XRX200_SDMA_ISR_BFULL, /* Buffer Full */ -+// XRX200_SDMA_ISR_FERR, /* Frame Error */ -+// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */ -+// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */ -+// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */ -+// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */ -+// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */ -+// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */ -+// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */ -+// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */ -+// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */ -+// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */ -+// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */ -+// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */ -+// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */ -+// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */ -+// XRX200_SDMA_PCTRL_PEN, /* Port Enable */ -+// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */ -+// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */ -+// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */ -+// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */ -+// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */ -+// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */ -+// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */ -+// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */ -+// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */ -+// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */ -+}; -+ -+ -+struct xrx200sw_reg { -+ int offset; -+ int shift; -+ int size; -+ int mult; -+} xrx200sw_reg[] = { -+// offeset shift size mult -+// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */ -+// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */ -+// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */ -+// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */ -+// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */ -+// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */ -+// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */ -+// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */ -+// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */ -+// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */ -+// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */ -+// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */ -+// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */ -+// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */ -+// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */ -+// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */ -+// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */ -+// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */ -+// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */ -+// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */ -+// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */ -+// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */ -+// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */ -+// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */ -+// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */ -+// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */ -+// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */ -+// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */ -+// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */ -+// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */ -+// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */ -+// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */ -+// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */ -+// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */ -+// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */ -+// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */ -+// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */ -+// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */ -+// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */ -+// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */ -+// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */ -+// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */ -+// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */ -+// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */ -+// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */ -+// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */ -+// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */ -+// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */ -+// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */ -+// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */ -+// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */ -+// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */ -+// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */ -+// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */ -+// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */ -+// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */ -+// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */ -+// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */ -+// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */ -+// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */ -+// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */ -+// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */ -+// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */ -+// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */ -+// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */ -+// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */ -+// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */ -+// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */ -+// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */ -+// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */ -+// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */ -+// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */ -+// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */ -+// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */ -+// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */ -+// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */ -+// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */ -+// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */ -+// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */ -+// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */ -+// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */ -+// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */ -+// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */ -+// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */ -+// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */ -+// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */ -+// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */ -+// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */ -+// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */ -+// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */ -+// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */ -+// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */ -+// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */ -+// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */ -+// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */ -+// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */ -+// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */ -+// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */ -+// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */ -+// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */ -+// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */ -+// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */ -+// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */ -+// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */ -+// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */ -+// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */ -+// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */ -+// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */ -+// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */ -+// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */ -+// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */ -+// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */ -+// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */ -+// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */ -+// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */ -+// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */ -+// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */ -+// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */ -+// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */ -+// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */ -+// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */ -+// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */ -+// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */ -+// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */ -+// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */ -+// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */ -+// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */ -+// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */ -+// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */ -+// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */ -+// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */ -+// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */ -+// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */ -+// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */ -+// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */ -+// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */ -+// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */ -+// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */ -+// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */ -+// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */ -+// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */ -+// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */ -+ {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */ -+// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */ -+// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */ -+// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */ -+// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */ -+// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */ -+// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */ -+// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */ -+// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */ -+// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */ -+// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */ -+// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */ -+// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */ -+// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */ -+// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */ -+// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */ -+// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */ -+// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */ -+// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */ -+// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */ -+// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */ -+// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */ -+// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */ -+// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */ -+// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */ -+// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */ -+// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */ -+// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */ -+// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */ -+// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */ -+// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */ -+// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */ -+// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */ -+// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */ -+// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */ -+// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */ -+// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */ -+// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */ -+// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */ -+// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */ -+// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */ -+// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */ -+// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */ -+// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */ -+// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */ -+// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */ -+// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */ -+// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */ -+// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */ -+// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */ -+// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */ -+// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */ -+// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */ -+// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */ -+// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */ -+// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */ -+// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */ -+// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */ -+// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */ -+// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */ -+// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */ -+// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */ -+// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */ -+// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */ -+// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */ -+// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */ -+// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */ -+// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */ -+// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */ -+ {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */ -+// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */ -+ {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */ -+// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */ -+ {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */ -+// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */ -+ {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */ -+// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */ -+ {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */ -+// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */ -+ {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */ -+// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */ -+ {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */ -+// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */ -+ {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */ -+// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */ -+ {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */ -+// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */ -+ {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */ -+// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */ -+ {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */ -+// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */ -+ {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */ -+// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */ -+ {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */ -+// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */ -+ {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */ -+// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */ -+// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */ -+ {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */ -+// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */ -+ {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */ -+ {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */ -+ {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */ -+ {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */ -+ {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */ -+ {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */ -+// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */ -+// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */ -+// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */ -+// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */ -+// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */ -+// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */ -+// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */ -+// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */ -+// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */ -+// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */ -+// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */ -+// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */ -+// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */ -+// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */ -+// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */ -+// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */ -+ {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */ -+// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */ -+// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */ -+// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */ -+// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */ -+// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */ -+// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */ -+// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */ -+// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */ -+// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */ -+// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */ -+// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */ -+// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */ -+// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */ -+// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */ -+// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */ -+// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */ -+// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */ -+// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */ -+// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */ -+// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */ -+// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */ -+// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */ -+// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */ -+// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */ -+// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */ -+// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */ -+// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */ -+// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */ -+// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */ -+// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */ -+// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */ -+// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */ -+// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */ -+// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */ -+// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */ -+// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */ -+// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */ -+// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */ -+// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */ -+// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */ -+// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */ -+// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */ -+// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */ -+// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */ -+// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */ -+// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */ -+// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */ -+// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */ -+// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */ -+// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */ -+// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */ -+// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */ -+// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */ -+// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */ -+// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */ -+// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */ -+// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */ -+// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */ -+// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */ -+// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */ -+// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */ -+// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */ -+// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */ -+// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */ -+// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */ -+// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */ -+// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */ -+// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */ -+// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */ -+// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */ -+// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */ -+// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */ -+// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */ -+// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */ -+// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */ -+// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */ -+// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */ -+// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */ -+// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */ -+// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */ -+// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */ -+// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */ -+// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */ -+// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */ -+// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */ -+// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */ -+// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */ -+// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */ -+// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */ -+// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */ -+// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */ -+// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */ -+// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */ -+// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */ -+// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */ -+// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */ -+// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */ -+// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */ -+// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */ -+// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */ -+// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */ -+// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */ -+// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */ -+// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */ -+// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */ -+// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */ -+// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */ -+// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */ -+// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */ -+// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */ -+// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */ -+// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */ -+// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */ -+// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */ -+// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */ -+// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */ -+ {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */ -+// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */ -+// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */ -+// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */ -+// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */ -+// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */ -+// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */ -+// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */ -+// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */ -+// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */ -+// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */ -+// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */ -+// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */ -+// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */ -+// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */ -+// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */ -+// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */ -+// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */ -+// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */ -+// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */ -+// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */ -+// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */ -+// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */ -+// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */ -+// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */ -+// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */ -+// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */ -+ {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */ -+ {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */ -+ {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */ -+ {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */ -+ {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */ -+// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */ -+ {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */ -+// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */ -+// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */ -+// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */ -+// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */ -+// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */ -+// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */ -+// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */ -+// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */ -+// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */ -+// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */ -+// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */ -+// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */ -+// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */ -+// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */ -+// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */ -+// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */ -+// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */ -+// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */ -+// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */ -+// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */ -+// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */ -+// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */ -+// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */ -+// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */ -+// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */ -+// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */ -+// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */ -+// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */ -+// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */ -+// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */ -+// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */ -+// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */ -+// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */ -+// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */ -+// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */ -+// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */ -+// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */ -+// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */ -+// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */ -+// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */ -+// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */ -+// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */ -+// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */ -+// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */ -+// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */ -+// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */ -+// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */ -+// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */ -+// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */ -+// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */ -+// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */ -+// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */ -+// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */ -+ {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */ -+ {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */ -+ {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */ -+// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */ -+// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */ -+// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */ -+// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */ -+ {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */ -+// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */ -+// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */ -+// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */ -+// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */ -+// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */ -+// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */ -+// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */ -+// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */ -+// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */ -+// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */ -+// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */ -+// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */ -+// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */ -+// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */ -+// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */ -+// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */ -+// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */ -+// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */ -+// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */ -+// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */ -+// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */ -+// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */ -+// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */ -+// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */ -+// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */ -+// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */ -+// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */ -+// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */ -+// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */ -+// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */ -+// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */ -+// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */ -+// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */ -+// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */ -+// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */ -+// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */ -+// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */ -+// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */ -+// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */ -+// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */ -+// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */ -+ {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */ -+// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */ -+// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */ -+// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */ -+// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */ -+// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */ -+// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */ -+// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */ -+// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */ -+// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */ -+// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */ -+// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */ -+// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */ -+// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */ -+// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */ -+// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */ -+// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */ -+// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */ -+// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */ -+// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */ -+// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */ -+// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */ -+// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */ -+// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */ -+// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */ -+// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */ -+// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */ -+// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */ -+// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */ -+// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */ -+// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */ -+// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */ -+// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */ -+// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */ -+// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */ -+// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */ -+// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */ -+// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */ -+// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */ -+// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */ -+// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */ -+// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */ -+// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */ -+// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */ -+// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */ -+// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */ -+// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */ -+// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */ -+// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */ -+// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */ -+// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */ -+// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */ -+// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */ -+// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */ -+// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */ -+// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */ -+// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */ -+// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */ -+// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */ -+// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */ -+// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */ -+// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */ -+// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */ -+// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */ -+// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */ -+// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */ -+// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */ -+// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */ -+// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */ -+// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */ -+// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */ -+// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */ -+// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */ -+// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */ -+// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */ -+// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */ -+// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */ -+// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */ -+// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */ -+// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */ -+// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */ -+// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */ -+// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */ -+// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */ -+// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */ -+// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */ -+// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */ -+// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */ -+// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */ -+// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */ -+// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */ -+// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */ -+// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */ -+// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */ -+// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */ -+// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */ -+// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */ -+// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */ -+// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */ -+// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */ -+// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */ -+// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */ -+// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */ -+// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */ -+// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */ -+// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */ -+// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */ -+// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */ -+// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */ -+// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */ -+// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */ -+// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */ -+// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */ -+// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */ -+// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */ -+// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */ -+// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */ -+// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */ -+// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */ -+// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */ -+// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */ -+// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */ -+// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */ -+// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */ -+// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */ -+// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */ -+// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */ -+// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */ -+// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */ -+}; -+ -+ diff --git a/target/linux/lantiq/patches-4.9/0026-NET-multi-phy-support.patch b/target/linux/lantiq/patches-4.9/0026-NET-multi-phy-support.patch deleted file mode 100644 index eb6acdb2f..000000000 --- a/target/linux/lantiq/patches-4.9/0026-NET-multi-phy-support.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6feeeb407a3b8a6597ae377ba4dd138e185e3dd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 27 Jul 2014 09:38:50 +0100 -Subject: [PATCH 26/36] NET: multi phy support - -Signed-off-by: John Crispin ---- - drivers/net/phy/phy.c | 9 ++++++--- - include/linux/phy.h | 1 + - 2 files changed, 7 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/phy.c -+++ b/drivers/net/phy/phy.c -@@ -1038,7 +1038,8 @@ void phy_state_machine(struct work_struc - /* If the link is down, give up on negotiation for now */ - if (!phydev->link) { - phydev->state = PHY_NOLINK; -- netif_carrier_off(phydev->attached_dev); -+ if (!phydev->no_auto_carrier_off) -+ netif_carrier_off(phydev->attached_dev); - phydev->adjust_link(phydev->attached_dev); - break; - } -@@ -1130,7 +1131,8 @@ void phy_state_machine(struct work_struc - netif_carrier_on(phydev->attached_dev); - } else { - phydev->state = PHY_NOLINK; -- netif_carrier_off(phydev->attached_dev); -+ if (!phydev->no_auto_carrier_off) -+ netif_carrier_off(phydev->attached_dev); - } - - phydev->adjust_link(phydev->attached_dev); -@@ -1142,7 +1144,8 @@ void phy_state_machine(struct work_struc - case PHY_HALTED: - if (phydev->link) { - phydev->link = 0; -- netif_carrier_off(phydev->attached_dev); -+ if (!phydev->no_auto_carrier_off) -+ netif_carrier_off(phydev->attached_dev); - phydev->adjust_link(phydev->attached_dev); - do_suspend = true; - } ---- a/include/linux/phy.h -+++ b/include/linux/phy.h -@@ -369,6 +369,7 @@ struct phy_device { - bool is_pseudo_fixed_link; - bool has_fixups; - bool suspended; -+ bool no_auto_carrier_off; - - enum phy_state state; - diff --git a/target/linux/lantiq/patches-4.9/0027-01-net-phy-intel-xway-add-VR9-version-number.patch b/target/linux/lantiq/patches-4.9/0027-01-net-phy-intel-xway-add-VR9-version-number.patch deleted file mode 100644 index 21261b459..000000000 --- a/target/linux/lantiq/patches-4.9/0027-01-net-phy-intel-xway-add-VR9-version-number.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 5b73d9955fb4b0e3c37f8f6c71910293246c89dc Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Thu, 22 Mar 2018 23:31:38 +0100 -Subject: [PATCH 1/2] net: phy: intel-xway: add VR9 version number - -The VR9 phy ids are matching only for the SoC version 1.2. Rename the -macros and change the names to take this into account. - -Signed-off-by: Mathias Kresin -Signed-off-by: David S. Miller ---- - drivers/net/phy/intel-xway.c | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - ---- a/drivers/net/phy/intel-xway.c -+++ b/drivers/net/phy/intel-xway.c -@@ -149,8 +149,8 @@ - #define PHY_ID_PHY22F_1_4 0xD565A410 - #define PHY_ID_PHY11G_1_5 0xD565A401 - #define PHY_ID_PHY22F_1_5 0xD565A411 --#define PHY_ID_PHY11G_VR9 0xD565A409 --#define PHY_ID_PHY22F_VR9 0xD565A419 -+#define PHY_ID_PHY11G_VR9_1_2 0xD565A409 -+#define PHY_ID_PHY22F_VR9_1_2 0xD565A419 - - #if IS_ENABLED(CONFIG_OF_MDIO) - static int vr9_gphy_of_reg_init(struct phy_device *phydev) -@@ -372,9 +372,9 @@ static struct phy_driver xway_gphy[] = { - .suspend = genphy_suspend, - .resume = genphy_resume, - }, { -- .phy_id = PHY_ID_PHY11G_VR9, -+ .phy_id = PHY_ID_PHY11G_VR9_1_2, - .phy_id_mask = 0xffffffff, -- .name = "Intel XWAY PHY11G (xRX integrated)", -+ .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", - .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | - SUPPORTED_Asym_Pause), - .flags = PHY_HAS_INTERRUPT, -@@ -387,9 +387,9 @@ static struct phy_driver xway_gphy[] = { - .suspend = genphy_suspend, - .resume = genphy_resume, - }, { -- .phy_id = PHY_ID_PHY22F_VR9, -+ .phy_id = PHY_ID_PHY22F_VR9_1_2, - .phy_id_mask = 0xffffffff, -- .name = "Intel XWAY PHY22F (xRX integrated)", -+ .name = "Intel XWAY PHY22F (xRX v1.2 integrated)", - .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | - SUPPORTED_Asym_Pause), - .flags = PHY_HAS_INTERRUPT, -@@ -412,8 +412,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_PHY22F_1_4, 0xffffffff }, - { PHY_ID_PHY11G_1_5, 0xffffffff }, - { PHY_ID_PHY22F_1_5, 0xffffffff }, -- { PHY_ID_PHY11G_VR9, 0xffffffff }, -- { PHY_ID_PHY22F_VR9, 0xffffffff }, -+ { PHY_ID_PHY11G_VR9_1_2, 0xffffffff }, -+ { PHY_ID_PHY22F_VR9_1_2, 0xffffffff }, - { } - }; - MODULE_DEVICE_TABLE(mdio, xway_gphy_tbl); diff --git a/target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch b/target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch deleted file mode 100644 index 9a9253290..000000000 --- a/target/linux/lantiq/patches-4.9/0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch +++ /dev/null @@ -1,71 +0,0 @@ -From f452518c982e57538e6d49da0a2c80eef22087ab Mon Sep 17 00:00:00 2001 -From: Mathias Kresin -Date: Thu, 22 Mar 2018 23:31:39 +0100 -Subject: [PATCH 2/2] net: phy: intel-xway: add VR9 v1.1 phy ids - -The phys embedded into the v1.1 of the VR9 SoC are using different phy -ids. Add the phy ids to use the driver for this VR9 version as well. - -Signed-off-by: Mathias Kresin -Signed-off-by: David S. Miller ---- - drivers/net/phy/intel-xway.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/drivers/net/phy/intel-xway.c -+++ b/drivers/net/phy/intel-xway.c -@@ -149,6 +149,8 @@ - #define PHY_ID_PHY22F_1_4 0xD565A410 - #define PHY_ID_PHY11G_1_5 0xD565A401 - #define PHY_ID_PHY22F_1_5 0xD565A411 -+#define PHY_ID_PHY11G_VR9_1_1 0xD565A408 -+#define PHY_ID_PHY22F_VR9_1_1 0xD565A418 - #define PHY_ID_PHY11G_VR9_1_2 0xD565A409 - #define PHY_ID_PHY22F_VR9_1_2 0xD565A419 - -@@ -372,6 +374,36 @@ static struct phy_driver xway_gphy[] = { - .suspend = genphy_suspend, - .resume = genphy_resume, - }, { -+ .phy_id = PHY_ID_PHY11G_VR9_1_1, -+ .phy_id_mask = 0xffffffff, -+ .name = "Intel XWAY PHY11G (xRX v1.1 integrated)", -+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause | -+ SUPPORTED_Asym_Pause), -+ .flags = PHY_HAS_INTERRUPT, -+ .config_init = xway_gphy_config_init, -+ .config_aneg = genphy_config_aneg, -+ .read_status = genphy_read_status, -+ .ack_interrupt = xway_gphy_ack_interrupt, -+ .did_interrupt = xway_gphy_did_interrupt, -+ .config_intr = xway_gphy_config_intr, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { -+ .phy_id = PHY_ID_PHY22F_VR9_1_1, -+ .phy_id_mask = 0xffffffff, -+ .name = "Intel XWAY PHY22F (xRX v1.1 integrated)", -+ .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | -+ SUPPORTED_Asym_Pause), -+ .flags = PHY_HAS_INTERRUPT, -+ .config_init = xway_gphy_config_init, -+ .config_aneg = genphy_config_aneg, -+ .read_status = genphy_read_status, -+ .ack_interrupt = xway_gphy_ack_interrupt, -+ .did_interrupt = xway_gphy_did_interrupt, -+ .config_intr = xway_gphy_config_intr, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ }, { - .phy_id = PHY_ID_PHY11G_VR9_1_2, - .phy_id_mask = 0xffffffff, - .name = "Intel XWAY PHY11G (xRX v1.2 integrated)", -@@ -412,6 +444,8 @@ static struct mdio_device_id __maybe_unu - { PHY_ID_PHY22F_1_4, 0xffffffff }, - { PHY_ID_PHY11G_1_5, 0xffffffff }, - { PHY_ID_PHY22F_1_5, 0xffffffff }, -+ { PHY_ID_PHY11G_VR9_1_1, 0xffffffff }, -+ { PHY_ID_PHY22F_VR9_1_1, 0xffffffff }, - { PHY_ID_PHY11G_VR9_1_2, 0xffffffff }, - { PHY_ID_PHY22F_VR9_1_2, 0xffffffff }, - { } diff --git a/target/linux/lantiq/patches-4.9/0028-NET-lantiq-various-etop-fixes.patch b/target/linux/lantiq/patches-4.9/0028-NET-lantiq-various-etop-fixes.patch deleted file mode 100644 index dc99f48ea..000000000 --- a/target/linux/lantiq/patches-4.9/0028-NET-lantiq-various-etop-fixes.patch +++ /dev/null @@ -1,880 +0,0 @@ -From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 9 Sep 2014 22:45:34 +0200 -Subject: [PATCH 28/36] NET: lantiq: various etop fixes - -Signed-off-by: John Crispin ---- - drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++----------- - 1 file changed, 389 insertions(+), 166 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -11,7 +11,7 @@ - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - * -- * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011-12 John Crispin - */ - - #include -@@ -30,11 +30,16 @@ - #include - #include - #include -+#include - #include - #include - #include - #include - #include -+#include -+#include -+#include -+#include - - #include - -@@ -42,7 +47,7 @@ - #include - #include - --#define LTQ_ETOP_MDIO 0x11804 -+#define LTQ_ETOP_MDIO_ACC 0x11804 - #define MDIO_REQUEST 0x80000000 - #define MDIO_READ 0x40000000 - #define MDIO_ADDR_MASK 0x1f -@@ -51,44 +56,91 @@ - #define MDIO_REG_OFFSET 0x10 - #define MDIO_VAL_MASK 0xffff - --#define PPE32_CGEN 0x800 --#define LQ_PPE32_ENET_MAC_CFG 0x1840 -+#define LTQ_ETOP_MDIO_CFG 0x11800 -+#define MDIO_CFG_MASK 0x6 -+ -+#define LTQ_ETOP_CFG 0x11808 -+#define LTQ_ETOP_IGPLEN 0x11820 -+#define LTQ_ETOP_MAC_CFG 0x11840 - - #define LTQ_ETOP_ENETS0 0x11850 - #define LTQ_ETOP_MAC_DA0 0x1186C - #define LTQ_ETOP_MAC_DA1 0x11870 --#define LTQ_ETOP_CFG 0x16020 --#define LTQ_ETOP_IGPLEN 0x16080 -+ -+#define MAC_CFG_MASK 0xfff -+#define MAC_CFG_CGEN (1 << 11) -+#define MAC_CFG_DUPLEX (1 << 2) -+#define MAC_CFG_SPEED (1 << 1) -+#define MAC_CFG_LINK (1 << 0) - - #define MAX_DMA_CHAN 0x8 - #define MAX_DMA_CRC_LEN 0x4 - #define MAX_DMA_DATA_LEN 0x600 - - #define ETOP_FTCU BIT(28) --#define ETOP_MII_MASK 0xf --#define ETOP_MII_NORMAL 0xd --#define ETOP_MII_REVERSE 0xe - #define ETOP_PLEN_UNDER 0x40 --#define ETOP_CGEN 0x800 -+#define ETOP_CFG_MII0 0x01 - --/* use 2 static channels for TX/RX */ --#define LTQ_ETOP_TX_CHANNEL 1 --#define LTQ_ETOP_RX_CHANNEL 6 --#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) --#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) -+#define ETOP_CFG_MASK 0xfff -+#define ETOP_CFG_FEN0 (1 << 8) -+#define ETOP_CFG_SEN0 (1 << 6) -+#define ETOP_CFG_OFF1 (1 << 3) -+#define ETOP_CFG_REMII0 (1 << 1) -+#define ETOP_CFG_OFF0 (1 << 0) -+ -+#define LTQ_GBIT_MDIO_CTL 0xCC -+#define LTQ_GBIT_MDIO_DATA 0xd0 -+#define LTQ_GBIT_GCTL0 0x68 -+#define LTQ_GBIT_PMAC_HD_CTL 0x8c -+#define LTQ_GBIT_P0_CTL 0x4 -+#define LTQ_GBIT_PMAC_RX_IPG 0xa8 -+#define LTQ_GBIT_RGMII_CTL 0x78 -+ -+#define PMAC_HD_CTL_AS (1 << 19) -+#define PMAC_HD_CTL_RXSH (1 << 22) -+ -+/* Switch Enable (0=disable, 1=enable) */ -+#define GCTL0_SE 0x80000000 -+/* Disable MDIO auto polling (0=disable, 1=enable) */ -+#define PX_CTL_DMDIO 0x00400000 -+ -+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */ -+#define MDC_CLOCK_MASK 0xff000000 -+#define MDC_CLOCK_OFFSET 24 -+ -+/* register information for the gbit's MDIO bus */ -+#define MDIO_XR9_REQUEST 0x00008000 -+#define MDIO_XR9_READ 0x00000800 -+#define MDIO_XR9_WRITE 0x00000400 -+#define MDIO_XR9_REG_MASK 0x1f -+#define MDIO_XR9_ADDR_MASK 0x1f -+#define MDIO_XR9_RD_MASK 0xffff -+#define MDIO_XR9_REG_OFFSET 0 -+#define MDIO_XR9_ADDR_OFFSET 5 -+#define MDIO_XR9_WR_OFFSET 16 - -+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \ -+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) -+ -+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ - #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) - #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) - #define ltq_etop_w32_mask(x, y, z) \ - ltq_w32_mask(x, y, ltq_etop_membase + (z)) - --#define DRV_VERSION "1.0" -+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) -+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) -+#define ltq_gbit_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) -+ -+#define DRV_VERSION "1.2" - - static void __iomem *ltq_etop_membase; -+static void __iomem *ltq_gbit_membase; - - struct ltq_etop_chan { -- int idx; - int tx_free; -+ int irq; - struct net_device *netdev; - struct napi_struct napi; - struct ltq_dma_channel dma; -@@ -98,21 +150,34 @@ struct ltq_etop_chan { - struct ltq_etop_priv { - struct net_device *netdev; - struct platform_device *pdev; -- struct ltq_eth_data *pldata; - struct resource *res; - - struct mii_bus *mii_bus; - -- struct ltq_etop_chan ch[MAX_DMA_CHAN]; -- int tx_free[MAX_DMA_CHAN >> 1]; -+ struct ltq_etop_chan txch; -+ struct ltq_etop_chan rxch; -+ -+ int tx_irq; -+ int rx_irq; -+ -+ unsigned char mac[6]; -+ int mii_mode; - - spinlock_t lock; -+ -+ struct clk *clk_ppe; -+ struct clk *clk_switch; -+ struct clk *clk_ephy; -+ struct clk *clk_ephycgu; - }; - -+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data); -+ - static int - ltq_etop_alloc_skb(struct ltq_etop_chan *ch) - { -- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); -+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); - if (!ch->skb[ch->dma.desc]) - return -ENOMEM; - ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, -@@ -147,8 +212,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan - spin_unlock_irqrestore(&priv->lock, flags); - - skb_put(skb, len); -+ skb->dev = ch->netdev; - skb->protocol = eth_type_trans(skb, ch->netdev); - netif_receive_skb(skb); -+ ch->netdev->stats.rx_packets++; -+ ch->netdev->stats.rx_bytes += len; - } - - static int -@@ -156,7 +224,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - { - struct ltq_etop_chan *ch = container_of(napi, - struct ltq_etop_chan, napi); -+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - int work_done = 0; -+ unsigned long flags; - - while (work_done < budget) { - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -@@ -168,7 +238,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - } - if (work_done < budget) { - napi_complete_done(&ch->napi, work_done); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - } - return work_done; - } -@@ -180,12 +252,14 @@ ltq_etop_poll_tx(struct napi_struct *nap - container_of(napi, struct ltq_etop_chan, napi); - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - struct netdev_queue *txq = -- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); -+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); - while ((ch->dma.desc_base[ch->tx_free].ctl & - (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ ch->netdev->stats.tx_packets++; -+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len; - dev_kfree_skb_any(ch->skb[ch->tx_free]); - ch->skb[ch->tx_free] = NULL; - memset(&ch->dma.desc_base[ch->tx_free], 0, -@@ -198,7 +272,9 @@ ltq_etop_poll_tx(struct napi_struct *nap - if (netif_tx_queue_stopped(txq)) - netif_tx_start_queue(txq); - napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - return 1; - } - -@@ -206,9 +282,10 @@ static irqreturn_t - ltq_etop_dma_irq(int irq, void *_priv) - { - struct ltq_etop_priv *priv = _priv; -- int ch = irq - LTQ_DMA_CH0_INT; -- -- napi_schedule(&priv->ch[ch].napi); -+ if (irq == priv->txch.dma.irq) -+ napi_schedule(&priv->txch.napi); -+ else -+ napi_schedule(&priv->rxch.napi); - return IRQ_HANDLED; - } - -@@ -220,7 +297,7 @@ ltq_etop_free_channel(struct net_device - ltq_dma_free(&ch->dma); - if (ch->dma.irq) - free_irq(ch->dma.irq, priv); -- if (IS_RX(ch->idx)) { -+ if (ch == &priv->txch) { - int desc; - for (desc = 0; desc < LTQ_DESC_NUM; desc++) - dev_kfree_skb_any(ch->skb[ch->dma.desc]); -@@ -231,65 +308,133 @@ static void - ltq_etop_hw_exit(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; - -- ltq_pmu_disable(PMU_PPE); -- for (i = 0; i < MAX_DMA_CHAN; i++) -- if (IS_TX(i) || IS_RX(i)) -- ltq_etop_free_channel(dev, &priv->ch[i]); -+ clk_disable(priv->clk_ppe); -+ -+ if (of_machine_is_compatible("lantiq,ar9")) -+ clk_disable(priv->clk_switch); -+ -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_disable(priv->clk_ephy); -+ clk_disable(priv->clk_ephycgu); -+ } -+ -+ ltq_etop_free_channel(dev, &priv->txch); -+ ltq_etop_free_channel(dev, &priv->rxch); -+} -+ -+static void -+ltq_etop_gbit_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ -+ clk_enable(priv->clk_switch); -+ -+ /* enable gbit port0 on the SoC */ -+ ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL); -+ -+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); -+ /* disable MDIO auto polling mode */ -+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); -+ /* set 1522 packet size */ -+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); -+ /* disable pmac & dmac headers */ -+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, -+ LTQ_GBIT_PMAC_HD_CTL); -+ /* Due to traffic halt when burst length 8, -+ replace default IPG value with 0x3B */ -+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); -+ /* set mdc clock to 2.5 MHz */ -+ ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET, -+ LTQ_GBIT_RGMII_CTL); - } - - static int - ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ int mii_mode = priv->mii_mode; -+ -+ clk_enable(priv->clk_ppe); - -- ltq_pmu_enable(PMU_PPE); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ ltq_etop_gbit_init(dev); -+ /* force the etops link to the gbit to MII */ -+ mii_mode = PHY_INTERFACE_MODE_MII; -+ } -+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG); -+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX | -+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG); - -- switch (priv->pldata->mii_mode) { -+ switch (mii_mode) { - case PHY_INTERFACE_MODE_RMII: -- ltq_etop_w32_mask(ETOP_MII_MASK, -- ETOP_MII_REVERSE, LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - case PHY_INTERFACE_MODE_MII: -- ltq_etop_w32_mask(ETOP_MII_MASK, -- ETOP_MII_NORMAL, LTQ_ETOP_CFG); -+ ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 | -+ ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG); - break; - - default: -+ if (of_machine_is_compatible("lantiq,ase")) { -+ clk_enable(priv->clk_ephy); -+ /* disable external MII */ -+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); -+ /* enable clock for internal PHY */ -+ clk_enable(priv->clk_ephycgu); -+ /* we need to write this magic to the internal phy to -+ make it work */ -+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -+ pr_info("Selected EPHY mode\n"); -+ break; -+ } - netdev_err(dev, "unknown mii mode %d\n", -- priv->pldata->mii_mode); -+ mii_mode); - return -ENOTSUPP; - } - -- /* enable crc generation */ -- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); -+ return 0; -+} -+ -+static int -+ltq_etop_dma_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ int tx = priv->tx_irq - LTQ_DMA_ETOP; -+ int rx = priv->rx_irq - LTQ_DMA_ETOP; -+ int err; - - ltq_dma_init_port(DMA_PORT_ETOP); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- int irq = LTQ_DMA_CH0_INT + i; -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- ch->idx = ch->dma.nr = i; -- -- if (IS_TX(i)) { -- ltq_dma_alloc_tx(&ch->dma); -- request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); -- } else if (IS_RX(i)) { -- ltq_dma_alloc_rx(&ch->dma); -- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -- ch->dma.desc++) -- if (ltq_etop_alloc_skb(ch)) -- return -ENOMEM; -- ch->dma.desc = 0; -- request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); -+ priv->txch.dma.nr = tx; -+ ltq_dma_alloc_tx(&priv->txch.dma); -+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv); -+ if (err) { -+ netdev_err(dev, "failed to allocate tx irq\n"); -+ goto err_out; -+ } -+ priv->txch.dma.irq = priv->tx_irq; -+ -+ priv->rxch.dma.nr = rx; -+ ltq_dma_alloc_rx(&priv->rxch.dma); -+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; -+ priv->rxch.dma.desc++) { -+ if (ltq_etop_alloc_skb(&priv->rxch)) { -+ netdev_err(dev, "failed to allocate skbs\n"); -+ err = -ENOMEM; -+ goto err_out; - } -- ch->dma.irq = irq; - } -- return 0; -+ priv->rxch.dma.desc = 0; -+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv); -+ if (err) -+ netdev_err(dev, "failed to allocate rx irq\n"); -+ else -+ priv->rxch.dma.irq = priv->rx_irq; -+err_out: -+ return err; - } - - static void -@@ -303,7 +448,10 @@ ltq_etop_get_drvinfo(struct net_device * - static int - ltq_etop_nway_reset(struct net_device *dev) - { -- return phy_start_aneg(dev->phydev); -+ if (dev->phydev) -+ return phy_start_aneg(dev->phydev); -+ else -+ return 0; - } - - static const struct ethtool_ops ltq_etop_ethtool_ops = { -@@ -314,6 +462,39 @@ static const struct ethtool_ops ltq_etop - }; - - static int -+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | -+ (phy_data << MDIO_XR9_WR_OFFSET) | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ return 0; -+} -+ -+static int -+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; -+ return val; -+} -+ -+static int - ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) - { - u32 val = MDIO_REQUEST | -@@ -321,9 +502,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | - phy_data; - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); - return 0; - } - -@@ -334,12 +515,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in - ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | - ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); - -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- ltq_etop_w32(val, LTQ_ETOP_MDIO); -- while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) -+ ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC); -+ while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST) - ; -- val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; -+ val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK; - return val; - } - -@@ -354,8 +535,18 @@ ltq_etop_mdio_probe(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - struct phy_device *phydev; -+ u32 phy_supported = (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ | SUPPORTED_MII -+ | SUPPORTED_TP); - -- phydev = phy_find_first(priv->mii_bus); -+ if (of_machine_is_compatible("lantiq,ase")) -+ phydev = mdiobus_get_phy(priv->mii_bus, 8); -+ else -+ phydev = mdiobus_get_phy(priv->mii_bus, 0); - - if (!phydev) { - netdev_err(dev, "no PHY found\n"); -@@ -363,21 +554,18 @@ ltq_etop_mdio_probe(struct net_device *d - } - - phydev = phy_connect(dev, phydev_name(phydev), -- <q_etop_mdio_link, priv->pldata->mii_mode); -+ <q_etop_mdio_link, priv->mii_mode); - - if (IS_ERR(phydev)) { - netdev_err(dev, "Could not attach to PHY\n"); - return PTR_ERR(phydev); - } - -- phydev->supported &= (SUPPORTED_10baseT_Half -- | SUPPORTED_10baseT_Full -- | SUPPORTED_100baseT_Half -- | SUPPORTED_100baseT_Full -- | SUPPORTED_Autoneg -- | SUPPORTED_MII -- | SUPPORTED_TP); -+ if (of_machine_is_compatible("lantiq,ar9")) -+ phy_supported |= SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full; - -+ phydev->supported &= phy_supported; - phydev->advertising = phydev->supported; - phy_attached_info(phydev); - -@@ -398,8 +586,13 @@ ltq_etop_mdio_init(struct net_device *de - } - - priv->mii_bus->priv = dev; -- priv->mii_bus->read = ltq_etop_mdio_rd; -- priv->mii_bus->write = ltq_etop_mdio_wr; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; -+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; -+ } else { -+ priv->mii_bus->read = ltq_etop_mdio_rd; -+ priv->mii_bus->write = ltq_etop_mdio_wr; -+ } - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -@@ -436,17 +629,19 @@ static int - ltq_etop_open(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -+ napi_enable(&priv->txch.napi); -+ napi_enable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_open(&priv->txch.dma); -+ ltq_dma_open(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ if (dev->phydev) -+ phy_start(dev->phydev); - -- if (!IS_TX(i) && (!IS_RX(i))) -- continue; -- ltq_dma_open(&ch->dma); -- napi_enable(&ch->napi); -- } -- phy_start(dev->phydev); - netif_tx_start_all_queues(dev); - return 0; - } -@@ -455,18 +650,19 @@ static int - ltq_etop_stop(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - - netif_tx_stop_all_queues(dev); -- phy_stop(dev->phydev); -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- if (!IS_RX(i) && !IS_TX(i)) -- continue; -- napi_disable(&ch->napi); -- ltq_dma_close(&ch->dma); -- } -+ if (dev->phydev) -+ phy_stop(dev->phydev); -+ napi_disable(&priv->txch.napi); -+ napi_disable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_close(&priv->txch.dma); -+ ltq_dma_close(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ - return 0; - } - -@@ -476,16 +672,16 @@ ltq_etop_tx(struct sk_buff *skb, struct - int queue = skb_get_queue_mapping(skb); - struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); - struct ltq_etop_priv *priv = netdev_priv(dev); -- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; -- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -- int len; -+ struct ltq_dma_desc *desc = -+ &priv->txch.dma.desc_base[priv->txch.dma.desc]; - unsigned long flags; - u32 byte_offset; -+ int len; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - -- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -- dev_kfree_skb_any(skb); -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || -+ priv->txch.skb[priv->txch.dma.desc]) { - netdev_err(dev, "tx ring full\n"); - netif_tx_stop_queue(txq); - return NETDEV_TX_BUSY; -@@ -493,7 +689,7 @@ ltq_etop_tx(struct sk_buff *skb, struct - - /* dma needs to start on a 16 byte aligned address */ - byte_offset = CPHYSADDR(skb->data) % 16; -- ch->skb[ch->dma.desc] = skb; -+ priv->txch.skb[priv->txch.dma.desc] = skb; - - netif_trans_update(dev); - -@@ -503,11 +699,11 @@ ltq_etop_tx(struct sk_buff *skb, struct - wmb(); - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | - LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -- ch->dma.desc++; -- ch->dma.desc %= LTQ_DESC_NUM; -+ priv->txch.dma.desc++; -+ priv->txch.dma.desc %= LTQ_DESC_NUM; - spin_unlock_irqrestore(&priv->lock, flags); - -- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) -+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) - netif_tx_stop_queue(txq); - - return NETDEV_TX_OK; -@@ -522,8 +718,10 @@ ltq_etop_change_mtu(struct net_device *d - struct ltq_etop_priv *priv = netdev_priv(dev); - unsigned long flags; - -+ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN; -+ - spin_lock_irqsave(&priv->lock, flags); -- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, -+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, - LTQ_ETOP_IGPLEN); - spin_unlock_irqrestore(&priv->lock, flags); - } -@@ -592,6 +790,9 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - ltq_etop_change_mtu(dev, 1500); -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); - if (!is_valid_ether_addr(mac.sa_data)) { -@@ -609,9 +810,10 @@ ltq_etop_init(struct net_device *dev) - dev->addr_assign_type = NET_ADDR_RANDOM; - - ltq_etop_set_multicast_list(dev); -- err = ltq_etop_mdio_init(dev); -- if (err) -- goto err_netdev; -+ if (!ltq_etop_mdio_init(dev)) -+ dev->ethtool_ops = <q_etop_ethtool_ops; -+ else -+ pr_warn("etop: mdio probe failed\n");; - return 0; - - err_netdev: -@@ -631,6 +833,9 @@ ltq_etop_tx_timeout(struct net_device *d - err = ltq_etop_hw_init(dev); - if (err) - goto err_hw; -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - netif_trans_update(dev); - netif_wake_queue(dev); - return; -@@ -654,14 +859,19 @@ static const struct net_device_ops ltq_e - .ndo_tx_timeout = ltq_etop_tx_timeout, - }; - --static int __init --ltq_etop_probe(struct platform_device *pdev) -+static int ltq_etop_probe(struct platform_device *pdev) - { - struct net_device *dev; - struct ltq_etop_priv *priv; -- struct resource *res; -+ struct resource *res, *gbit_res, irqres[2]; -+ const u8 *mac; - int err; -- int i; -+ -+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2); -+ if (err != 2) { -+ dev_err(&pdev->dev, "failed to get etop irqs\n"); -+ return -EINVAL; -+ } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { -@@ -687,31 +897,62 @@ ltq_etop_probe(struct platform_device *p - goto err_out; - } - -- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); -- if (!dev) { -- err = -ENOMEM; -- goto err_out; -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (!gbit_res) { -+ dev_err(&pdev->dev, "failed to get gbit resource\n"); -+ err = -ENOENT; -+ goto err_out; -+ } -+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, -+ gbit_res->start, resource_size(gbit_res)); -+ if (!ltq_gbit_membase) { -+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", -+ pdev->id); -+ err = -ENOMEM; -+ goto err_out; -+ } - } -+ -+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); - strcpy(dev->name, "eth%d"); - dev->netdev_ops = <q_eth_netdev_ops; -- dev->ethtool_ops = <q_etop_ethtool_ops; - priv = netdev_priv(dev); - priv->res = res; - priv->pdev = pdev; -- priv->pldata = dev_get_platdata(&pdev->dev); - priv->netdev = dev; -+ priv->tx_irq = irqres[0].start; -+ priv->rx_irq = irqres[1].start; -+ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node); -+ -+ mac = of_get_mac_address(pdev->dev.of_node); -+ if (mac) -+ memcpy(priv->mac, mac, ETH_ALEN); -+ -+ priv->clk_ppe = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_ppe)) -+ return PTR_ERR(priv->clk_ppe); -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ priv->clk_switch = clk_get(&pdev->dev, "switch"); -+ if (IS_ERR(priv->clk_switch)) -+ return PTR_ERR(priv->clk_switch); -+ } -+ if (of_machine_is_compatible("lantiq,ase")) { -+ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); -+ if (IS_ERR(priv->clk_ephy)) -+ return PTR_ERR(priv->clk_ephy); -+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); -+ if (IS_ERR(priv->clk_ephycgu)) -+ return PTR_ERR(priv->clk_ephycgu); -+ } -+ - spin_lock_init(&priv->lock); - SET_NETDEV_DEV(dev, &pdev->dev); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- if (IS_TX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_tx, 8); -- else if (IS_RX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_rx, 32); -- priv->ch[i].netdev = dev; -- } -+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); -+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); -+ priv->txch.netdev = dev; -+ priv->rxch.netdev = dev; - - err = register_netdev(dev); - if (err) -@@ -740,31 +981,22 @@ ltq_etop_remove(struct platform_device * - return 0; - } - -+static const struct of_device_id ltq_etop_match[] = { -+ { .compatible = "lantiq,etop-xway" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_etop_match); -+ - static struct platform_driver ltq_mii_driver = { -+ .probe = ltq_etop_probe, - .remove = ltq_etop_remove, - .driver = { - .name = "ltq_etop", -+ .of_match_table = ltq_etop_match, - }, - }; - --int __init --init_ltq_etop(void) --{ -- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); -- -- if (ret) -- pr_err("ltq_etop: Error registering platform driver!"); -- return ret; --} -- --static void __exit --exit_ltq_etop(void) --{ -- platform_driver_unregister(<q_mii_driver); --} -- --module_init(init_ltq_etop); --module_exit(exit_ltq_etop); -+module_platform_driver(ltq_mii_driver); - - MODULE_AUTHOR("John Crispin "); - MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-4.9/0030-GPIO-add-named-gpio-exports.patch b/target/linux/lantiq/patches-4.9/0030-GPIO-add-named-gpio-exports.patch deleted file mode 100644 index e2a421b27..000000000 --- a/target/linux/lantiq/patches-4.9/0030-GPIO-add-named-gpio-exports.patch +++ /dev/null @@ -1,170 +0,0 @@ -From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 12 Aug 2014 20:49:27 +0200 -Subject: [PATCH 30/36] GPIO: add named gpio exports - -Signed-off-by: John Crispin ---- - drivers/gpio/gpiolib-of.c | 68 +++++++++++++++++++++++++++++++++++++++++ - drivers/gpio/gpiolib.c | 11 +++++-- - include/asm-generic/gpio.h | 5 +++ - include/linux/gpio/consumer.h | 8 +++++ - 4 files changed, 90 insertions(+), 2 deletions(-) - ---- a/drivers/gpio/gpiolib-of.c -+++ b/drivers/gpio/gpiolib-of.c -@@ -23,6 +23,8 @@ - #include - #include - #include -+#include -+#include - - #include "gpiolib.h" - -@@ -538,3 +540,73 @@ void of_gpiochip_remove(struct gpio_chip - gpiochip_remove_pin_ranges(chip); - of_node_put(chip->of_node); - } -+ -+#ifdef CONFIG_GPIO_SYSFS -+ -+static struct of_device_id gpio_export_ids[] = { -+ { .compatible = "gpio-export" }, -+ { /* sentinel */ } -+}; -+ -+static int __init of_gpio_export_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct device_node *cnp; -+ u32 val; -+ int nb = 0; -+ -+ for_each_child_of_node(np, cnp) { -+ const char *name = NULL; -+ int gpio; -+ bool dmc; -+ int max_gpio = 1; -+ int i; -+ -+ of_property_read_string(cnp, "gpio-export,name", &name); -+ -+ if (!name) -+ max_gpio = of_gpio_count(cnp); -+ -+ for (i = 0; i < max_gpio; i++) { -+ unsigned flags = 0; -+ enum of_gpio_flags of_flags; -+ -+ gpio = of_get_gpio_flags(cnp, i, &of_flags); -+ -+ if (of_flags == OF_GPIO_ACTIVE_LOW) -+ flags |= GPIOF_ACTIVE_LOW; -+ -+ if (!of_property_read_u32(cnp, "gpio-export,output", &val)) -+ flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ else -+ flags |= GPIOF_IN; -+ -+ if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np))) -+ continue; -+ -+ dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change"); -+ gpio_export_with_name(gpio, dmc, name); -+ nb++; -+ } -+ } -+ -+ dev_info(&pdev->dev, "%d gpio(s) exported\n", nb); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_export_driver = { -+ .driver = { -+ .name = "gpio-export", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(gpio_export_ids), -+ }, -+}; -+ -+static int __init of_gpio_export_init(void) -+{ -+ return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe); -+} -+device_initcall(of_gpio_export_init); -+ -+#endif ---- a/include/asm-generic/gpio.h -+++ b/include/asm-generic/gpio.h -@@ -126,6 +126,12 @@ static inline int gpio_export(unsigned g - return gpiod_export(gpio_to_desc(gpio), direction_may_change); - } - -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); -+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name) -+{ -+ return __gpiod_export(gpio_to_desc(gpio), direction_may_change, name); -+} -+ - static inline int gpio_export_link(struct device *dev, const char *name, - unsigned gpio) - { ---- a/include/linux/gpio/consumer.h -+++ b/include/linux/gpio/consumer.h -@@ -427,6 +427,7 @@ static inline struct gpio_desc *devm_get - - #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS) - -+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name); - int gpiod_export(struct gpio_desc *desc, bool direction_may_change); - int gpiod_export_link(struct device *dev, const char *name, - struct gpio_desc *desc); -@@ -434,6 +435,13 @@ void gpiod_unexport(struct gpio_desc *de - - #else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */ - -+static inline int _gpiod_export(struct gpio_desc *desc, -+ bool direction_may_change, -+ const char *name) -+{ -+ return -ENOSYS; -+} -+ - static inline int gpiod_export(struct gpio_desc *desc, - bool direction_may_change) - { ---- a/drivers/gpio/gpiolib-sysfs.c -+++ b/drivers/gpio/gpiolib-sysfs.c -@@ -544,7 +544,7 @@ static struct class gpio_class = { - * - * Returns zero on success, else an error. - */ --int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name) - { - struct gpio_chip *chip; - struct gpio_device *gdev; -@@ -606,6 +606,8 @@ int gpiod_export(struct gpio_desc *desc, - offset = gpio_chip_hwgpio(desc); - if (chip->names && chip->names[offset]) - ioname = chip->names[offset]; -+ if (name) -+ ioname = name; - - dev = device_create_with_groups(&gpio_class, &gdev->dev, - MKDEV(0, 0), data, gpio_groups, -@@ -627,6 +629,12 @@ err_unlock: - gpiod_dbg(desc, "%s: status %d\n", __func__, status); - return status; - } -+EXPORT_SYMBOL_GPL(__gpiod_export); -+ -+int gpiod_export(struct gpio_desc *desc, bool direction_may_change) -+{ -+ return __gpiod_export(desc, direction_may_change, NULL); -+} - EXPORT_SYMBOL_GPL(gpiod_export); - - static int match_export(struct device *dev, const void *desc) diff --git a/target/linux/lantiq/patches-4.9/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-4.9/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch deleted file mode 100644 index c275b55ef..000000000 --- a/target/linux/lantiq/patches-4.9/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch +++ /dev/null @@ -1,1034 +0,0 @@ -From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 7 Aug 2014 18:26:42 +0200 -Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master - -This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - drivers/i2c/busses/Kconfig | 10 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ - drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ - 4 files changed, 992 insertions(+) - create mode 100644 drivers/i2c/busses/i2c-lantiq.c - create mode 100644 drivers/i2c/busses/i2c-lantiq.h - ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -643,6 +643,16 @@ config I2C_MESON - If you say yes to this option, support will be included for the - I2C interface on the Amlogic Meson family of SoCs. - -+config I2C_LANTIQ -+ tristate "Lantiq I2C interface" -+ depends on LANTIQ && SOC_FALCON -+ help -+ If you say yes to this option, support will be included for the -+ Lantiq I2C core. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-lantiq. -+ - config I2C_MPC - tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" - depends on PPC ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o - obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o - obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o - obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o -+obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o - obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o - obj-$(CONFIG_I2C_MESON) += i2c-meson.o - obj-$(CONFIG_I2C_MPC) += i2c-mpc.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.c -@@ -0,0 +1,747 @@ -+ -+/* -+ * Lantiq I2C bus adapter -+ * -+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * Copyright (C) 2012 Thomas Langer -+ */ -+ -+#include -+#include -+#include -+#include /* for kzalloc, kfree */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "i2c-lantiq.h" -+ -+/* -+ * CURRENT ISSUES: -+ * - no high speed support -+ * - ten bit mode is not tested (no slave devices) -+ */ -+ -+/* access macros */ -+#define i2c_r32(reg) \ -+ __raw_readl(&(priv->membase)->reg) -+#define i2c_w32(val, reg) \ -+ __raw_writel(val, &(priv->membase)->reg) -+#define i2c_w32_mask(clear, set, reg) \ -+ i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) -+ -+#define DRV_NAME "i2c-lantiq" -+#define DRV_VERSION "1.00" -+ -+#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ -+ -+#ifdef DEBUG -+#define LTQ_I2C_XFER_TIMEOUT (25*HZ) -+#else -+#define LTQ_I2C_XFER_TIMEOUT HZ -+#endif -+ -+#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ -+ I2C_IMSC_I2C_ERR_INT_EN) -+ -+#define LTQ_I2C_ARB_LOST (1 << 0) -+#define LTQ_I2C_NACK (1 << 1) -+#define LTQ_I2C_RX_UFL (1 << 2) -+#define LTQ_I2C_RX_OFL (1 << 3) -+#define LTQ_I2C_TX_UFL (1 << 4) -+#define LTQ_I2C_TX_OFL (1 << 5) -+ -+struct ltq_i2c { -+ struct mutex mutex; -+ -+ -+ /* active clock settings */ -+ unsigned int input_clock; /* clock input for i2c hardware block */ -+ unsigned int i2c_clock; /* approximated bus clock in kHz */ -+ -+ struct clk *clk_gate; -+ struct clk *clk_input; -+ -+ -+ /* resources (memory and interrupts) */ -+ int irq_lb; /* last burst irq */ -+ -+ struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ -+ -+ struct i2c_adapter adap; -+ struct device *dev; -+ -+ struct completion cmd_complete; -+ -+ -+ /* message transfer data */ -+ struct i2c_msg *current_msg; /* current message */ -+ int msgs_num; /* number of messages to handle */ -+ u8 *msg_buf; /* current buffer */ -+ u32 msg_buf_len; /* remaining length of current buffer */ -+ int msg_err; /* error status of the current transfer */ -+ -+ -+ /* master status codes */ -+ enum { -+ STATUS_IDLE, -+ STATUS_ADDR, /* address phase */ -+ STATUS_WRITE, -+ STATUS_READ, -+ STATUS_READ_END, -+ STATUS_STOP -+ } status; -+}; -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); -+ -+static inline void enable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); -+} -+static inline void disable_burst_irq(struct ltq_i2c *priv) -+{ -+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); -+} -+ -+static void prepare_msg_send_addr(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ -+ u16 addr = msg->addr; -+ -+ /* new i2c_msg */ -+ priv->msg_buf = msg->buf; -+ priv->msg_buf_len = msg->len; -+ if (rd) -+ priv->status = STATUS_READ; -+ else -+ priv->status = STATUS_WRITE; -+ -+ /* send slave address */ -+ if (msg->flags & I2C_M_TEN) { -+ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); -+ i2c_w32(addr & 0xff, txd); -+ } else { -+ i2c_w32((addr & 0x7f) << 1 | rd, txd); -+ } -+} -+ -+static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; -+ -+ pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); -+ -+ priv->status = STATUS_ADDR; -+ -+ if (!(msg->flags & I2C_M_RD)) -+ len += msg->len; -+ else -+ /* set maximum received packet size (before rx int!) */ -+ i2c_w32(msg->len, mrps_ctrl); -+ i2c_w32(len, tps_ctrl); -+ enable_burst_irq(priv); -+} -+ -+static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ unsigned int input_clock = clk_get_rate(priv->clk_input); -+ u32 dec, inc = 1; -+ -+ /* clock changed? */ -+ if (priv->input_clock == input_clock) -+ return 0; -+ -+ /* -+ * this formula is only an approximation, found by the recommended -+ * values in the "I2C Architecture Specification 1.7.1" -+ */ -+ dec = input_clock / (priv->i2c_clock * 2); -+ if (dec <= 6) -+ return -ENXIO; -+ -+ i2c_w32(0, fdiv_high_cfg); -+ i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | -+ (dec << I2C_FDIV_CFG_DEC_OFFSET), -+ fdiv_cfg); -+ -+ dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", -+ input_clock, priv->i2c_clock, dec); -+ -+ priv->input_clock = input_clock; -+ return 0; -+} -+ -+static int ltq_i2c_hw_init(struct i2c_adapter *adap) -+{ -+ int ret = 0; -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+#ifndef DEBUG -+ /* set normal operation clock divider */ -+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); -+#else -+ /* for debugging a higher divider value! */ -+ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); -+#endif -+ -+ /* setup clock */ -+ ret = ltq_i2c_hw_set_clock(adap); -+ if (ret != 0) { -+ dev_warn(priv->dev, "invalid clock settings\n"); -+ return ret; -+ } -+ -+ /* configure fifo */ -+ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ -+ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ -+ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ -+ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ -+ fifo_cfg); -+ -+ /* configure address */ -+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in -+ the fifo */ -+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ -+ I2C_ADDR_CFG_MnS_EN | /* we are master device */ -+ 0, /* our slave address (not used!) */ -+ addr_cfg); -+ -+ /* enable bus */ -+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); -+ -+ return 0; -+} -+ -+static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) -+{ -+ unsigned long timeout; -+ -+ timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); -+ -+ do { -+ u32 stat = i2c_r32(bus_stat); -+ -+ if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) -+ return 0; -+ -+ cond_resched(); -+ } while (!time_after_eq(jiffies, timeout)); -+ -+ dev_err(priv->dev, "timeout waiting for bus ready\n"); -+ return -ETIMEDOUT; -+} -+ -+static void ltq_i2c_tx(struct ltq_i2c *priv, int last) -+{ -+ if (priv->msg_buf_len && priv->msg_buf) { -+ i2c_w32(*priv->msg_buf, txd); -+ -+ if (--priv->msg_buf_len) -+ priv->msg_buf++; -+ else -+ priv->msg_buf = NULL; -+ } else { -+ last = 1; -+ } -+ -+ if (last) -+ disable_burst_irq(priv); -+} -+ -+static void ltq_i2c_rx(struct ltq_i2c *priv, int last) -+{ -+ u32 fifo_stat, timeout; -+ if (priv->msg_buf_len && priv->msg_buf) { -+ timeout = 5000000; -+ do { -+ fifo_stat = i2c_r32(ffs_stat); -+ } while (!fifo_stat && --timeout); -+ if (!timeout) { -+ last = 1; -+ pr_debug("\nrx timeout\n"); -+ goto err; -+ } -+ while (fifo_stat) { -+ *priv->msg_buf = i2c_r32(rxd); -+ if (--priv->msg_buf_len) { -+ priv->msg_buf++; -+ } else { -+ priv->msg_buf = NULL; -+ last = 1; -+ break; -+ } -+ /* -+ * do not read more than burst size, otherwise no "last -+ * burst" is generated and the transaction is blocked! -+ */ -+ fifo_stat = 0; -+ } -+ } else { -+ last = 1; -+ } -+err: -+ if (last) { -+ disable_burst_irq(priv); -+ -+ if (priv->status == STATUS_READ_END) { -+ /* -+ * do the STATUS_STOP and complete() here, as sometimes -+ * the tx_end is already seen before this is finished -+ */ -+ priv->status = STATUS_STOP; -+ complete(&priv->cmd_complete); -+ } else { -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+ priv->status = STATUS_READ_END; -+ } -+ } -+} -+ -+static void ltq_i2c_xfer_init(struct ltq_i2c *priv) -+{ -+ /* enable interrupts */ -+ i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); -+ -+ /* trigger transfer of first msg */ -+ ltq_i2c_set_tx_len(priv); -+} -+ -+static void dump_msgs(struct i2c_msg msgs[], int num, int rx) -+{ -+#if defined(DEBUG) -+ int i, j; -+ pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); -+ for (i = 0; i < num; i++) { -+ pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, -+ (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', -+ msgs[i].len, msgs[i].addr); -+ if (!(msgs[i].flags & I2C_M_RD) || rx) { -+ for (j = 0; j < msgs[i].len; j++) -+ pr_debug("%02X ", msgs[i].buf[j]); -+ } -+ pr_debug("\n"); -+ } -+#endif -+} -+ -+static void ltq_i2c_release_bus(struct ltq_i2c *priv) -+{ -+ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+} -+ -+static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], -+ int num) -+{ -+ struct ltq_i2c *priv = i2c_get_adapdata(adap); -+ int ret; -+ -+ dev_dbg(priv->dev, "xfer %u messages\n", num); -+ dump_msgs(msgs, num, 0); -+ -+ mutex_lock(&priv->mutex); -+ -+ init_completion(&priv->cmd_complete); -+ priv->current_msg = msgs; -+ priv->msgs_num = num; -+ priv->msg_err = 0; -+ priv->status = STATUS_IDLE; -+ -+ /* wait for the bus to become ready */ -+ ret = ltq_i2c_wait_bus_not_busy(priv); -+ if (ret) -+ goto done; -+ -+ while (priv->msgs_num) { -+ /* start the transfers */ -+ ltq_i2c_xfer_init(priv); -+ -+ /* wait for transfers to complete */ -+ ret = wait_for_completion_interruptible_timeout( -+ &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); -+ if (ret == 0) { -+ dev_err(priv->dev, "controller timed out\n"); -+ ltq_i2c_hw_init(adap); -+ ret = -ETIMEDOUT; -+ goto done; -+ } else if (ret < 0) -+ goto done; -+ -+ if (priv->msg_err) { -+ if (priv->msg_err & LTQ_I2C_NACK) -+ ret = -ENXIO; -+ else -+ ret = -EREMOTEIO; -+ goto done; -+ } -+ if (--priv->msgs_num) -+ priv->current_msg++; -+ } -+ /* no error? */ -+ ret = num; -+ -+done: -+ ltq_i2c_release_bus(priv); -+ -+ mutex_unlock(&priv->mutex); -+ -+ if (ret >= 0) -+ dump_msgs(msgs, num, 1); -+ -+ pr_debug("XFER ret %d\n", ret); -+ return ret; -+} -+ -+static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) -+{ -+ struct ltq_i2c *priv = dev_id; -+ struct i2c_msg *msg = priv->current_msg; -+ int last = (irq == priv->irq_lb); -+ -+ if (last) -+ pr_debug("LB "); -+ else -+ pr_debug("B "); -+ -+ if (msg->flags & I2C_M_RD) { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("X"); -+ prepare_msg_send_addr(priv); -+ disable_burst_irq(priv); -+ break; -+ case STATUS_READ: -+ case STATUS_READ_END: -+ pr_debug("R"); -+ ltq_i2c_rx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status R %d\n", priv->status); -+ break; -+ } -+ } else { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ pr_debug("x"); -+ prepare_msg_send_addr(priv); -+ break; -+ case STATUS_WRITE: -+ pr_debug("w"); -+ ltq_i2c_tx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ pr_warn("Status W %d\n", priv->status); -+ break; -+ } -+ } -+ -+ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); -+ return IRQ_HANDLED; -+} -+ -+static void ltq_i2c_isr_prot(struct ltq_i2c *priv) -+{ -+ u32 i_pro = i2c_r32(p_irqss); -+ -+ pr_debug("i2c-p"); -+ -+ /* not acknowledge */ -+ if (i_pro & I2C_P_IRQSS_NACK) { -+ priv->msg_err |= LTQ_I2C_NACK; -+ pr_debug(" nack"); -+ } -+ -+ /* arbitration lost */ -+ if (i_pro & I2C_P_IRQSS_AL) { -+ priv->msg_err |= LTQ_I2C_ARB_LOST; -+ pr_debug(" arb-lost"); -+ } -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) -+ pr_debug(" rx"); -+ -+ /* tx end */ -+ if (i_pro & I2C_P_IRQSS_TX_END) -+ pr_debug(" txend"); -+ pr_debug("\n"); -+ -+ if (!priv->msg_err) { -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) { -+ priv->status = STATUS_READ; -+ enable_burst_irq(priv); -+ } -+ if (i_pro & I2C_P_IRQSS_TX_END) { -+ if (priv->status == STATUS_READ) -+ priv->status = STATUS_READ_END; -+ else { -+ disable_burst_irq(priv); -+ priv->status = STATUS_STOP; -+ } -+ } -+ } -+ -+ i2c_w32(i_pro, p_irqsc); -+} -+ -+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) -+{ -+ u32 i_raw, i_err = 0; -+ struct ltq_i2c *priv = dev_id; -+ -+ i_raw = i2c_r32(mis); -+ pr_debug("i_raw 0x%08X\n", i_raw); -+ -+ /* error interrupt */ -+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { -+ i_err = i2c_r32(err_irqss); -+ pr_debug("i_err 0x%08X bus_stat 0x%04X\n", -+ i_err, i2c_r32(bus_stat)); -+ -+ /* tx fifo overflow (8) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_OFL) -+ priv->msg_err |= LTQ_I2C_TX_OFL; -+ -+ /* tx fifo underflow (4) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_UFL) -+ priv->msg_err |= LTQ_I2C_TX_UFL; -+ -+ /* rx fifo overflow (2) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_OFL) -+ priv->msg_err |= LTQ_I2C_RX_OFL; -+ -+ /* rx fifo underflow (1) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_UFL) -+ priv->msg_err |= LTQ_I2C_RX_UFL; -+ -+ i2c_w32(i_err, err_irqsc); -+ } -+ -+ /* protocol interrupt */ -+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) -+ ltq_i2c_isr_prot(priv); -+ -+ if ((priv->msg_err) || (priv->status == STATUS_STOP)) -+ complete(&priv->cmd_complete); -+ -+ return IRQ_HANDLED; -+} -+ -+static u32 ltq_i2c_functionality(struct i2c_adapter *adap) -+{ -+ return I2C_FUNC_I2C | -+ I2C_FUNC_10BIT_ADDR | -+ I2C_FUNC_SMBUS_EMUL; -+} -+ -+static struct i2c_algorithm ltq_i2c_algorithm = { -+ .master_xfer = ltq_i2c_xfer, -+ .functionality = ltq_i2c_functionality, -+}; -+ -+static int ltq_i2c_probe(struct platform_device *pdev) -+{ -+ struct device_node *node = pdev->dev.of_node; -+ struct ltq_i2c *priv; -+ struct i2c_adapter *adap; -+ struct resource *mmres, irqres[4]; -+ int ret = 0; -+ -+ dev_dbg(&pdev->dev, "probing\n"); -+ -+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ ret = of_irq_to_resource_table(node, irqres, 4); -+ if (!mmres || (ret != 4)) { -+ dev_err(&pdev->dev, "no resources\n"); -+ return -ENODEV; -+ } -+ -+ /* allocate private data */ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ dev_err(&pdev->dev, "can't allocate private data\n"); -+ return -ENOMEM; -+ } -+ -+ adap = &priv->adap; -+ i2c_set_adapdata(adap, priv); -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); -+ adap->algo = <q_i2c_algorithm; -+ adap->dev.parent = &pdev->dev; -+ adap->dev.of_node = pdev->dev.of_node; -+ -+ if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { -+ dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); -+ priv->i2c_clock = 100000; -+ } -+ -+ init_completion(&priv->cmd_complete); -+ mutex_init(&priv->mutex); -+ -+ priv->membase = devm_ioremap_resource(&pdev->dev, mmres); -+ if (IS_ERR(priv->membase)) -+ return PTR_ERR(priv->membase); -+ -+ priv->dev = &pdev->dev; -+ priv->irq_lb = irqres[0].start; -+ -+ ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, -+ 0x0, "i2c lb", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", -+ irqres[0].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, -+ 0x0, "i2c b", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", -+ irqres[1].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, -+ 0x0, "i2c err", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get error IRQ %d\n", -+ irqres[2].start); -+ return -ENODEV; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, -+ 0x0, "i2c p", priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", -+ irqres[3].start); -+ return -ENODEV; -+ } -+ -+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); -+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, -+ irqres[1].start, irqres[2].start, irqres[3].start); -+ -+ priv->clk_gate = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_gate)) { -+ dev_err(&pdev->dev, "failed to get i2c clk\n"); -+ return -ENOENT; -+ } -+ -+ /* this is a static clock, which has no refcounting */ -+ priv->clk_input = clk_get_fpi(); -+ if (IS_ERR(priv->clk_input)) { -+ dev_err(&pdev->dev, "failed to get fpi clk\n"); -+ return -ENOENT; -+ } -+ -+ clk_activate(priv->clk_gate); -+ -+ /* add our adapter to the i2c stack */ -+ ret = i2c_add_numbered_adapter(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't register I2C adapter\n"); -+ goto out; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ i2c_set_adapdata(adap, priv); -+ -+ /* print module version information */ -+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", -+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, -+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); -+ -+ /* initialize HW */ -+ ret = ltq_i2c_hw_init(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't configure adapter\n"); -+ i2c_del_adapter(adap); -+ platform_set_drvdata(pdev, NULL); -+ goto out; -+ } else { -+ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); -+ } -+ -+out: -+ /* if init failed, we need to deactivate the clock gate */ -+ if (ret) -+ clk_deactivate(priv->clk_gate); -+ -+ return ret; -+} -+ -+static int ltq_i2c_remove(struct platform_device *pdev) -+{ -+ struct ltq_i2c *priv = platform_get_drvdata(pdev); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+ /* power down the core */ -+ clk_deactivate(priv->clk_gate); -+ -+ /* remove driver */ -+ i2c_del_adapter(&priv->adap); -+ kfree(priv); -+ -+ dev_dbg(&pdev->dev, "removed\n"); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+static const struct of_device_id ltq_i2c_match[] = { -+ { .compatible = "lantiq,lantiq-i2c" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_i2c_match); -+ -+static struct platform_driver ltq_i2c_driver = { -+ .probe = ltq_i2c_probe, -+ .remove = ltq_i2c_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = ltq_i2c_match, -+ }, -+}; -+ -+module_platform_driver(ltq_i2c_driver); -+ -+MODULE_DESCRIPTION("Lantiq I2C bus adapter"); -+MODULE_AUTHOR("Thomas Langer "); -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(DRV_VERSION); ---- /dev/null -+++ b/drivers/i2c/busses/i2c-lantiq.h -@@ -0,0 +1,234 @@ -+#ifndef I2C_LANTIQ_H -+#define I2C_LANTIQ_H -+ -+/* I2C register structure */ -+struct lantiq_reg_i2c { -+ /* I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /* Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /* I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /* Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /* -+ * I2C RUN Control Register -+ * This register enables and disables the I2C peripheral. Before -+ * enabling, the I2C has to be configured properly. After enabling -+ * no configuration is possible -+ */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /* -+ * I2C End Data Control Register -+ * This register is used to either turn around the data transmission -+ * direction or to address another slave without sending a stop -+ * condition. Also the software can stop the slave-transmitter by -+ * sending a not-accolade when working as master-receiver or even -+ * stop data transmission immediately when operating as -+ * master-transmitter. The writing to the bits of this control -+ * register is only effective when in MASTER RECEIVES BYTES, MASTER -+ * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state -+ */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /* -+ * I2C Fractional Divider Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_HIGH_CFG has -+ * the same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /* -+ * I2C Fractional Divider (highspeed mode) Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_CFG has the -+ * same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /* I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /* I2C Bus Status Register -+ * This register gives a status information of the I2C. This additional -+ * information can be used by the software to start proper actions. -+ */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /* I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /* I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /* I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /* I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /* I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /* Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /* I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /* Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /* I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /* I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /* I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /* Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /* I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /* I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /* I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /* Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /* I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /* I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /* I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /* I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /* I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /* I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /* Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /* I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /* Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /* I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /* Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+/* -+ * Clock Divider for Normal Run Mode -+ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long -+ * as the new divider value RMC is not valid, the register returns 0x0000 00xx -+ * on reading. -+ */ -+#define I2C_CLC_RMC_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+ -+/* Fields of "I2C Identification Register" */ -+/* Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/* Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/* field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/* Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/* Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/* Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+ -+/* Fields of "I2C Error Interrupt Request Source Status Register" */ -+/* TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+ -+/* Fields of "I2C Raw Interrupt Status Register" */ -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/* 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/* 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+/* Stop on Packet End Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/* Stop on Not Acknowledge Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/* Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+ -+/* Fields of "I2C Interrupt Clear Register" */ -+/* Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/* Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/* field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Bus Status Register" */ -+/* Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/* Read from I2C Bus. */ -+#define I2C_BUS_STAT_RNW_READ 0x00000004 -+/* I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/* -+ * The device is working as master and has claimed the control on the -+ * I2C-bus (busy master). -+ */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+ -+/* Fields of "I2C RUN Control Register" */ -+/* Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* Fields of "I2C End Data Control Register" */ -+/* -+ * Set End of Transmission -+ * Note:Do not write '1' to this bit when bus is free. This will cause an -+ * abort after the first byte when a new transfer is started. -+ */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ -+/* NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+/* RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+ -+ -+#endif /* I2C_LANTIQ_H */ diff --git a/target/linux/lantiq/patches-4.9/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch b/target/linux/lantiq/patches-4.9/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch deleted file mode 100644 index a5ecd94c4..000000000 --- a/target/linux/lantiq/patches-4.9/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch +++ /dev/null @@ -1,219 +0,0 @@ -From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Sep 2014 22:42:14 +0200 -Subject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling - -Signed-off-by: John Crispin ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + - arch/mips/lantiq/xway/Makefile | 3 + - arch/mips/lantiq/xway/ath5k_eep.c | 136 +++++++++++++++++++++ - arch/mips/lantiq/xway/eth_mac.c | 25 ++++ - drivers/net/ethernet/lantiq_etop.c | 6 +- - 5 files changed, 172 insertions(+), 1 deletion(-) - create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c - create mode 100644 arch/mips/lantiq/xway/eth_mac.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -104,5 +104,8 @@ int xrx200_gphy_boot(struct device *dev, - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); - -+/* allow the ethernet driver to load a flash mapped mac addr */ -+const u8* ltq_get_eth_mac(void); -+ - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -8,4 +8,7 @@ endif - - obj-y += vmmc.o - -+obj-y += eth_mac.o -+obj-$(CONFIG_PCI) += ath5k_eep.o -+ - obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/ath5k_eep.c -@@ -0,0 +1,136 @@ -+/* -+ * Copyright (C) 2011 Luca Olivetti -+ * Copyright (C) 2011 John Crispin -+ * Copyright (C) 2011 Andrej Vlašić -+ * Copyright (C) 2013 Álvaro Fernández Rojas -+ * Copyright (C) 2013 Daniel Gimpelevich -+ * Copyright (C) 2015 Vittorio Gambaletta -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev); -+struct ath5k_platform_data ath5k_pdata; -+static u8 athxk_eeprom_mac[6]; -+ -+static int ath5k_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ dev->dev.platform_data = &ath5k_pdata; -+ return 0; -+} -+ -+static int ath5k_eep_load; -+int __init of_ath5k_eeprom_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node, *mtd_np = NULL; -+ int mac_offset; -+ u32 mac_inc = 0; -+ int i; -+ struct mtd_info *the_mtd; -+ size_t flash_readlen; -+ const __be32 *list; -+ const char *part; -+ phandle phandle; -+ -+ list = of_get_property(np, "ath,eep-flash", &i); -+ if (!list || (i != (2 * sizeof(*list)))) -+ return -ENODEV; -+ -+ phandle = be32_to_cpup(list++); -+ if (phandle) -+ mtd_np = of_find_node_by_phandle(phandle); -+ -+ if (!mtd_np) -+ return -ENODEV; -+ -+ part = of_get_property(mtd_np, "label", NULL); -+ if (!part) -+ part = mtd_np->name; -+ -+ the_mtd = get_mtd_device_nm(part); -+ if (IS_ERR(the_mtd)) -+ return -ENODEV; -+ -+ ath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL); -+ -+ i = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1, -+ &flash_readlen, (void *) ath5k_pdata.eeprom_data); -+ -+ if (!of_property_read_u32(np, "ath,mac-offset", &mac_offset)) { -+ size_t mac_readlen; -+ mtd_read(the_mtd, mac_offset, 6, &mac_readlen, -+ (void *) athxk_eeprom_mac); -+ } -+ put_mtd_device(the_mtd); -+ -+ if (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) { -+ dev_err(&pdev->dev, "failed to load eeprom from mtd\n"); -+ return -ENODEV; -+ } -+ -+ if (of_find_property(np, "ath,eep-swap", NULL)) -+ for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++) -+ ath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac()) -+ ether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac()); -+ -+ if (!is_valid_ether_addr(athxk_eeprom_mac)) { -+ dev_warn(&pdev->dev, "using random mac\n"); -+ random_ether_addr(athxk_eeprom_mac); -+ } -+ -+ if (!of_property_read_u32(np, "ath,mac-increment", &mac_inc)) -+ athxk_eeprom_mac[5] += mac_inc; -+ -+ ath5k_pdata.macaddr = athxk_eeprom_mac; -+ ltq_pci_plat_dev_init = ath5k_pci_plat_dev_init; -+ -+ dev_info(&pdev->dev, "loaded ath5k eeprom\n"); -+ -+ return 0; -+} -+ -+static struct of_device_id ath5k_eeprom_ids[] = { -+ { .compatible = "ath5k,eeprom" }, -+ { } -+}; -+ -+static struct platform_driver ath5k_eeprom_driver = { -+ .driver = { -+ .name = "ath5k,eeprom", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(ath5k_eeprom_ids), -+ }, -+}; -+ -+static int __init of_ath5k_eeprom_init(void) -+{ -+ int ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+ -+ if (ret) -+ ath5k_eep_load = 1; -+ -+ return ret; -+} -+ -+static int __init of_ath5k_eeprom_init_late(void) -+{ -+ if (!ath5k_eep_load) -+ return 0; -+ -+ return platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe); -+} -+late_initcall(of_ath5k_eeprom_init_late); -+subsys_initcall(of_ath5k_eeprom_init); ---- /dev/null -+++ b/arch/mips/lantiq/xway/eth_mac.c -@@ -0,0 +1,25 @@ -+/* -+ * Copyright (C) 2012 John Crispin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+static u8 eth_mac[6]; -+static int eth_mac_set; -+ -+const u8* ltq_get_eth_mac(void) -+{ -+ return eth_mac; -+} -+ -+static int __init setup_ethaddr(char *str) -+{ -+ eth_mac_set = mac_pton(str, eth_mac); -+ return !eth_mac_set; -+} -+early_param("ethaddr", setup_ethaddr); ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -794,7 +794,11 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_hw; - -- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); -+ memcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN); -+ -+ if (priv->mac && !is_valid_ether_addr(mac.sa_data)) -+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN); -+ - if (!is_valid_ether_addr(mac.sa_data)) { - pr_warn("etop: invalid MAC, using random\n"); - eth_random_addr(mac.sa_data); diff --git a/target/linux/lantiq/patches-4.9/0040-USB-DWC2-enable-usb-power-gpio.patch b/target/linux/lantiq/patches-4.9/0040-USB-DWC2-enable-usb-power-gpio.patch deleted file mode 100644 index fc6312310..000000000 --- a/target/linux/lantiq/patches-4.9/0040-USB-DWC2-enable-usb-power-gpio.patch +++ /dev/null @@ -1,35 +0,0 @@ ---- a/drivers/usb/dwc2/platform.c -+++ b/drivers/usb/dwc2/platform.c -@@ -42,6 +42,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -544,6 +545,7 @@ static int dwc2_driver_probe(struct plat - struct dwc2_hsotg *hsotg; - struct resource *res; - int retval; -+ int gpio_count; - - match = of_match_device(dwc2_of_match_table, &dev->dev); - if (match && match->data) { -@@ -562,6 +564,16 @@ static int dwc2_driver_probe(struct plat - defparams.dma_desc_fs_enable = 0; - } - -+ gpio_count = of_gpio_count(dev->dev.of_node); -+ while (gpio_count > 0) { -+ enum of_gpio_flags flags; -+ int gpio = of_get_gpio_flags(dev->dev.of_node, --gpio_count, &flags); -+ if (gpio_request(gpio, "usb")) -+ continue; -+ dev_info(&dev->dev, "requested GPIO %d\n", gpio); -+ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1)); -+ } -+ - hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); - if (!hsotg) - return -ENOMEM; diff --git a/target/linux/lantiq/patches-4.9/0042-arch-mips-increase-io_space_limit.patch b/target/linux/lantiq/patches-4.9/0042-arch-mips-increase-io_space_limit.patch deleted file mode 100644 index 14b417e69..000000000 --- a/target/linux/lantiq/patches-4.9/0042-arch-mips-increase-io_space_limit.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 3 Jun 2016 13:12:20 +0200 -Subject: [PATCH] arch: mips: increase io_space_limit - -this value comes from x86 and breaks some pci devices - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/io.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/mips/include/asm/io.h -+++ b/arch/mips/include/asm/io.h -@@ -50,7 +50,7 @@ - - /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ - --#define IO_SPACE_LIMIT 0xffff -+#define IO_SPACE_LIMIT 0xffffffff - - /* - * On MIPS I/O ports are memory mapped, so we access them using normal diff --git a/target/linux/lantiq/patches-4.9/0044-pinctrl-xway-fix-copy-paste-error-in-xrx200_grps.patch b/target/linux/lantiq/patches-4.9/0044-pinctrl-xway-fix-copy-paste-error-in-xrx200_grps.patch deleted file mode 100644 index a2fc9d955..000000000 --- a/target/linux/lantiq/patches-4.9/0044-pinctrl-xway-fix-copy-paste-error-in-xrx200_grps.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/pinctrl/pinctrl-xway.c -+++ b/drivers/pinctrl/pinctrl-xway.c -@@ -1028,7 +1028,7 @@ static const struct ltq_pin_group xrx200 - GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5), - GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6), - GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx), -- GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_tx), -+ GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx), - GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts), - GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts), - GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr), diff --git a/target/linux/lantiq/patches-4.9/0047-poweroff.patch b/target/linux/lantiq/patches-4.9/0047-poweroff.patch deleted file mode 100644 index 54249bba5..000000000 --- a/target/linux/lantiq/patches-4.9/0047-poweroff.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/arch/mips/lantiq/xway/reset.c -+++ b/arch/mips/lantiq/xway/reset.c -@@ -301,12 +301,6 @@ static void ltq_machine_halt(void) - unreachable(); - } - --static void ltq_machine_power_off(void) --{ -- local_irq_disable(); -- unreachable(); --} -- - static void ltq_usb_init(void) - { - /* Power for USB cores 1 & 2 */ -@@ -379,7 +373,6 @@ static int __init mips_reboot_setup(void - - _machine_restart = ltq_machine_restart; - _machine_halt = ltq_machine_halt; -- pm_power_off = ltq_machine_power_off; - - return 0; - } diff --git a/target/linux/lantiq/patches-4.9/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup.patch b/target/linux/lantiq/patches-4.9/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup.patch deleted file mode 100644 index c0d7afc54..000000000 --- a/target/linux/lantiq/patches-4.9/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup.patch +++ /dev/null @@ -1,87 +0,0 @@ -From: Felix Fietkau -Date: Thu, 19 Jan 2017 12:14:44 +0100 -Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup - -With the IRQ stack changes integrated, the XRX200 devices started -emitting a constant stream of kernel messages like this: - -[ 565.415310] Spurious IRQ: CAUSE=0x1100c300 - -This appears to be caused by IP0 firing for some reason without being -handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and -calling do_IRQ for all MIPS CPU interrupts. - -Cc: john@phrozen.org -Cc: stable@vger.kernel.org -Signed-off-by: Felix Fietkau ---- - ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void) - DEFINE_HWx_IRQDISPATCH(5) - #endif - -+static void ltq_hw_irq_handler(struct irq_desc *desc) -+{ -+ ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2); -+} -+ - #ifdef CONFIG_MIPS_MT_SMP - void __init arch_init_ipiirq(int irq, struct irqaction *action) - { -@@ -315,23 +320,19 @@ static struct irqaction irq_call = { - asmlinkage void plat_irq_dispatch(void) - { - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; -- unsigned int i; -+ int irq; - -- if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { -- do_IRQ(MIPS_CPU_TIMER_IRQ); -- goto out; -- } else { -- for (i = 0; i < MAX_IM; i++) { -- if (pending & (CAUSEF_IP2 << i)) { -- ltq_hw_irqdispatch(i); -- goto out; -- } -- } -+ if (!pending) { -+ spurious_interrupt(); -+ return; - } -- pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); - --out: -- return; -+ pending >>= CAUSEB_IP; -+ while (pending) { -+ irq = fls(pending) - 1; -+ do_IRQ(MIPS_CPU_IRQ_BASE + irq); -+ pending &= ~BIT(irq); -+ } - } - - static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) -@@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d - .map = icu_map, - }; - --static struct irqaction cascade = { -- .handler = no_action, -- .name = "cascade", --}; -- - int __init icu_of_init(struct device_node *node, struct device_node *parent) - { - struct device_node *eiu_node; -@@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod - mips_cpu_irq_init(); - - for (i = 0; i < MAX_IM; i++) -- setup_irq(i + 2, &cascade); -+ irq_set_chained_handler(i + 2, ltq_hw_irq_handler); - - if (cpu_has_vint) { - pr_info("Setting up vectored interrupts\n"); diff --git a/target/linux/lantiq/patches-4.9/0061-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch b/target/linux/lantiq/patches-4.9/0061-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch deleted file mode 100644 index 4d1844394..000000000 --- a/target/linux/lantiq/patches-4.9/0061-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch +++ /dev/null @@ -1,130 +0,0 @@ -From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 6 Jan 2017 17:55:24 +0100 -Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs - -The size of the internal RAM of the DesignWare USB controller changed -between the different Lantiq SoCs. We have the following sizes: - -Amazon + Danube: 8 KByte -Amazon SE + arx100: 2 KByte -xrx200 + xrx300: 2.5 KByte - -For Danube SoC we do not provide the params and let the driver decide -to use sane defaults, for the Amazon SE and arx100 we use small fifos -and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo. -The auto detection of max_transfer_size and max_packet_count should -work, so remove it. - -Signed-off-by: Hauke Mehrtens ---- - drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++------- - 1 file changed, 39 insertions(+), 7 deletions(-) - ---- a/drivers/usb/dwc2/platform.c -+++ b/drivers/usb/dwc2/platform.c -@@ -151,7 +151,38 @@ static const struct dwc2_core_params par - .hibernation = -1, - }; - --static const struct dwc2_core_params params_ltq = { -+static const struct dwc2_core_params params_danube = { -+ .otg_cap = 2, /* non-HNP/non-SRP */ -+ .otg_ver = -1, -+ .dma_enable = -1, -+ .dma_desc_enable = -1, -+ .dma_desc_fs_enable = -1, -+ .speed = -1, -+ .enable_dynamic_fifo = -1, -+ .en_multiple_tx_fifo = -1, -+ .host_rx_fifo_size = -1, -+ .host_nperio_tx_fifo_size = -1, -+ .host_perio_tx_fifo_size = -1, -+ .max_transfer_size = -1, -+ .max_packet_count = -1, -+ .host_channels = -1, -+ .phy_type = -1, -+ .phy_utmi_width = -1, -+ .phy_ulpi_ddr = -1, -+ .phy_ulpi_ext_vbus = -1, -+ .i2c_enable = -1, -+ .ulpi_fs_ls = -1, -+ .host_support_fs_ls_low_power = -1, -+ .host_ls_low_power_phy_clk = -1, -+ .ts_dline = -1, -+ .reload_ctl = -1, -+ .ahbcfg = -1, -+ .uframe_sched = -1, -+ .external_id_pin_ctl = -1, -+ .hibernation = -1, -+}; -+ -+static const struct dwc2_core_params params_ase = { - .otg_cap = 2, /* non-HNP/non-SRP */ - .otg_ver = -1, - .dma_enable = -1, -@@ -163,8 +194,8 @@ static const struct dwc2_core_params par - .host_rx_fifo_size = 288, /* 288 DWORDs */ - .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ - .host_perio_tx_fifo_size = 96, /* 96 DWORDs */ -- .max_transfer_size = 65535, -- .max_packet_count = 511, -+ .max_transfer_size = -1, -+ .max_packet_count = -1, - .host_channels = -1, - .phy_type = -1, - .phy_utmi_width = -1, -@@ -176,8 +207,37 @@ static const struct dwc2_core_params par - .host_ls_low_power_phy_clk = -1, - .ts_dline = -1, - .reload_ctl = -1, -- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << -- GAHBCFG_HBSTLEN_SHIFT, -+ .ahbcfg = -1, -+ .uframe_sched = -1, -+ .external_id_pin_ctl = -1, -+ .hibernation = -1, -+}; -+ -+static const struct dwc2_core_params params_xrx200 = { -+ .otg_cap = 2, /* non-HNP/non-SRP */ -+ .otg_ver = -1, -+ .dma_enable = -1, -+ .dma_desc_enable = -1, -+ .speed = -1, -+ .enable_dynamic_fifo = -1, -+ .en_multiple_tx_fifo = -1, -+ .host_rx_fifo_size = 288, /* 288 DWORDs */ -+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ -+ .host_perio_tx_fifo_size = 136, /* 136 DWORDs */ -+ .max_transfer_size = -1, -+ .max_packet_count = -1, -+ .host_channels = -1, -+ .phy_type = -1, -+ .phy_utmi_width = -1, -+ .phy_ulpi_ddr = -1, -+ .phy_ulpi_ext_vbus = -1, -+ .i2c_enable = -1, -+ .ulpi_fs_ls = -1, -+ .host_support_fs_ls_low_power = -1, -+ .host_ls_low_power_phy_clk = -1, -+ .ts_dline = -1, -+ .reload_ctl = -1, -+ .ahbcfg = -1, - .uframe_sched = -1, - .external_id_pin_ctl = -1, - .hibernation = -1, -@@ -515,8 +575,11 @@ static const struct of_device_id dwc2_of - { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, - { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, - { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, -- { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq }, -- { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq }, -+ { .compatible = "lantiq,danube-usb", .data = ¶ms_danube }, -+ { .compatible = "lantiq,ase-usb", .data = ¶ms_ase }, -+ { .compatible = "lantiq,arx100-usb", .data = ¶ms_ase }, -+ { .compatible = "lantiq,xrx200-usb", .data = ¶ms_xrx200 }, -+ { .compatible = "lantiq,xrx300-usb", .data = ¶ms_xrx200 }, - { .compatible = "snps,dwc2", .data = NULL }, - { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, - { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic }, diff --git a/target/linux/lantiq/patches-4.9/0065-MIPS-lantiq-improve-USB-initialization.patch b/target/linux/lantiq/patches-4.9/0065-MIPS-lantiq-improve-USB-initialization.patch deleted file mode 100644 index acc23080f..000000000 --- a/target/linux/lantiq/patches-4.9/0065-MIPS-lantiq-improve-USB-initialization.patch +++ /dev/null @@ -1,202 +0,0 @@ -From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Fri, 6 Jan 2017 17:40:12 +0100 -Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization - -This adds code to initialize the USB controller and PHY also on Danube, -Amazon SE and AR10. This code is based on the Vendor driver from -different UGW versions and compared to the hardware documentation. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/lantiq/xway/reset.c | 120 ++++++++++++++++++++++++++++++---------- - arch/mips/lantiq/xway/sysctrl.c | 20 +++++++ - 2 files changed, 110 insertions(+), 30 deletions(-) - ---- a/arch/mips/lantiq/xway/reset.c -+++ b/arch/mips/lantiq/xway/reset.c -@@ -72,6 +72,8 @@ - #define RCU_USBCFG_HDSEL_BIT BIT(11) - #define RCU_USBCFG_HOST_END_BIT BIT(10) - #define RCU_USBCFG_SLV_END_BIT BIT(9) -+#define RCU_USBCFG_SLV_END_BIT_AR9 BIT(17) -+ - - /* USB reset bits */ - #define RCU_USBRESET 0x0010 -@@ -85,6 +87,8 @@ - - #define RCU_CFG1A 0x0038 - #define RCU_CFG1B 0x003C -+#define RCU_CFG1_TX_PEE BIT(0) -+#define RCU_CFG1_DIS_THR_SHIFT 15 /* Disconnect Threshold */ - - /* USB PMU devices */ - #define PMU_AHBM BIT(15) -@@ -306,38 +310,91 @@ static void ltq_usb_init(void) - /* Power for USB cores 1 & 2 */ - ltq_pmu_enable(PMU_AHBM); - ltq_pmu_enable(PMU_USB0); -- ltq_pmu_enable(PMU_USB1); - -- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A); -- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B); -+ if (of_machine_is_compatible("lantiq,ar10") || -+ of_machine_is_compatible("lantiq,grx390") || -+ of_machine_is_compatible("lantiq,ar9") || -+ of_machine_is_compatible("lantiq,vr9")) -+ ltq_pmu_enable(PMU_USB1); -+ -+ if (of_machine_is_compatible("lantiq,vr9") || -+ of_machine_is_compatible("lantiq,ar10")) { -+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | RCU_CFG1_TX_PEE | -+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1A); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | RCU_CFG1_TX_PEE | -+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1B); -+ } - - /* Enable USB PHY power for cores 1 & 2 */ - ltq_pmu_enable(PMU_USB0_P); -- ltq_pmu_enable(PMU_USB1_P); -+ if (of_machine_is_compatible("lantiq,ar10") || -+ of_machine_is_compatible("lantiq,grx390") || -+ of_machine_is_compatible("lantiq,ar9") || -+ of_machine_is_compatible("lantiq,vr9")) -+ ltq_pmu_enable(PMU_USB1_P); -+ -+ if (of_machine_is_compatible("lantiq,ase") || -+ of_machine_is_compatible("lantiq,danube")) { -+ /* Configure cores to host mode */ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT, -+ RCU_USB1CFG); -+ -+ /* Select DMA endianness (Host-endian: big-endian) */ -+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT) -+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG); -+ } -+ -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ /* Configure cores to host mode */ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT, -+ RCU_USB1CFG); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT, -+ RCU_USB2CFG); -+ -+ /* Select DMA endianness (Host-endian: big-endian) */ -+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9) -+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG); -+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9) -+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG); -+ } -+ -+ if (of_machine_is_compatible("lantiq,vr9") || -+ of_machine_is_compatible("lantiq,ar10")) { -+ /* Configure cores to host mode */ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT, -+ RCU_USB1CFG); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT, -+ RCU_USB2CFG); -+ -+ /* Select DMA endianness (Host-endian: big-endian) */ -+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT) -+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG); -+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT) -+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG); -+ } -+ -+ if (of_machine_is_compatible("lantiq,ar9")) { -+ /* Hard reset USB state machines */ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) -+ | USBRESET_BIT | BIT(28), RCU_USBRESET); -+ udelay(50 * 1000); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) -+ & ~(USBRESET_BIT | BIT(28)), RCU_USBRESET); -+ } else { -+ /* Hard reset USB state machines */ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET); -+ udelay(50 * 1000); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET); -+ } - -- /* Configure cores to host mode */ -- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT, -- RCU_USB1CFG); -- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT, -- RCU_USB2CFG); -- -- /* Select DMA endianness (Host-endian: big-endian) */ -- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT) -- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG); -- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT) -- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG); -- -- /* Hard reset USB state machines */ -- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET); -- udelay(50 * 1000); -- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET); -- -- /* Soft reset USB state machines */ -- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) -- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2); -- udelay(50 * 1000); -- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) -- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2); -+ if (of_machine_is_compatible("lantiq,vr9")) { -+ /* Soft reset USB state machines */ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) -+ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2); -+ udelay(50 * 1000); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2) -+ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2); -+ } - } - - static int __init mips_reboot_setup(void) -@@ -363,8 +420,11 @@ static int __init mips_reboot_setup(void - if (!ltq_rcu_membase) - panic("Failed to remap core memory"); - -- if (of_machine_is_compatible("lantiq,ar9") || -- of_machine_is_compatible("lantiq,vr9")) -+ if (of_machine_is_compatible("lantiq,danube") || -+ of_machine_is_compatible("lantiq,ase") || -+ of_machine_is_compatible("lantiq,ar9") || -+ of_machine_is_compatible("lantiq,vr9") || -+ of_machine_is_compatible("lantiq,ar10")) - ltq_usb_init(); - - if (of_machine_is_compatible("lantiq,vr9")) ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -254,6 +254,25 @@ static void pmu_disable(struct clk *clk) - pr_warn("deactivating PMU module failed!"); - } - -+static void usb_set_clock(void) -+{ -+ unsigned int val = ltq_cgu_r32(ifccr); -+ -+ if (of_machine_is_compatible("lantiq,ar10") || -+ of_machine_is_compatible("lantiq,grx390")) { -+ val &= ~0x03; /* XTAL divided by 3 */ -+ } else if (of_machine_is_compatible("lantiq,ar9") || -+ of_machine_is_compatible("lantiq,vr9")) { -+ /* TODO: this depends on the XTAL frequency */ -+ val |= 0x03; /* XTAL divided by 3 */ -+ } else if (of_machine_is_compatible("lantiq,ase")) { -+ val |= 0x20; /* from XTAL */ -+ } else if (of_machine_is_compatible("lantiq,danube")) { -+ val |= 0x30; /* 12 MHz, generated from 36 MHz */ -+ } -+ ltq_cgu_w32(val, ifccr); -+} -+ - /* the pci enable helper */ - static int pci_enable(struct clk *clk) - { -@@ -608,4 +627,5 @@ void __init ltq_soc_init(void) - - if (of_machine_is_compatible("lantiq,vr9")) - xbar_fpi_burst_disable(); -+ usb_set_clock(); - } diff --git a/target/linux/lantiq/patches-4.9/0090-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-contro.patch b/target/linux/lantiq/patches-4.9/0090-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-contro.patch deleted file mode 100644 index da48ae3a1..000000000 --- a/target/linux/lantiq/patches-4.9/0090-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-contro.patch +++ /dev/null @@ -1,1078 +0,0 @@ -From 941ab0bc001fe24e5f8ce88eed27f2a1b89f3e20 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Tue, 14 Feb 2017 00:31:11 +0100 -Subject: spi: lantiq-ssc: add support for Lantiq SSC SPI controller - -This driver supports the Lantiq SSC SPI controller in master -mode. This controller is found on Intel (former Lantiq) SoCs like -the Danube, Falcon, xRX200, xRX300. - -The hardware uses two hardware FIFOs one for received and one for -transferred bytes. When the driver writes data into the transmit FIFO -the complete word is taken from the FIFO into a shift register. The -data from this shift register is then written to the wire. This driver -uses the interrupts signaling the status of the FIFOs and not the shift -register. It is also possible to use the interrupts for the shift -register, but they will send a signal after every word. When using the -interrupts for the shift register we get a signal when the last word is -written into the shift register and not when it is written to the wire. -After all FIFOs are empty the driver busy waits till the hardware is -not busy any more and returns the transfer status. - -Signed-off-by: Daniel Schwierzeck -Signed-off-by: Hauke Mehrtens -Signed-off-by: Mark Brown ---- - .../devicetree/bindings/spi/spi-lantiq-ssc.txt | 29 + - drivers/spi/Kconfig | 8 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-lantiq-ssc.c | 983 +++++++++++++++++++++ - 4 files changed, 1021 insertions(+) - create mode 100644 Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt - create mode 100644 drivers/spi/spi-lantiq-ssc.c - ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt -@@ -0,0 +1,29 @@ -+Lantiq Synchronous Serial Controller (SSC) SPI master driver -+ -+Required properties: -+- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi" -+- #address-cells: see spi-bus.txt -+- #size-cells: see spi-bus.txt -+- reg: address and length of the spi master registers -+- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt. -+ -+ -+Optional properties: -+- clocks: spi clock phandle -+- num-cs: see spi-bus.txt, set to 8 if unset -+- base-cs: the number of the first chip select, set to 1 if unset. -+ -+Example: -+ -+ -+spi: spi@E100800 { -+ compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi"; -+ reg = <0xE100800 0x100>; -+ interrupt-parent = <&icu0>; -+ interrupts = <22 23 24>; -+ interrupt-names = "spi_rx", "spi_tx", "spi_err"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ num-cs = <6>; -+ base-cs = <1>; -+}; ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -403,6 +403,14 @@ config SPI_NUC900 - help - SPI driver for Nuvoton NUC900 series ARM SoCs - -+config SPI_LANTIQ_SSC -+ tristate "Lantiq SSC SPI controller" -+ depends on LANTIQ -+ help -+ This driver supports the Lantiq SSC SPI controller in master -+ mode. This controller is found on Intel (former Lantiq) SoCs like -+ the Danube, Falcon, xRX200, xRX300. -+ - config SPI_OC_TINY - tristate "OpenCores tiny SPI" - depends on GPIOLIB || COMPILE_TEST ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-sp - obj-$(CONFIG_SPI_GPIO) += spi-gpio.o - obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o - obj-$(CONFIG_SPI_IMX) += spi-imx.o -+obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o - obj-$(CONFIG_SPI_JCORE) += spi-jcore.o - obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o - obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o ---- /dev/null -+++ b/drivers/spi/spi-lantiq-ssc.c -@@ -0,0 +1,983 @@ -+/* -+ * Copyright (C) 2011-2015 Daniel Schwierzeck -+ * Copyright (C) 2016 Hauke Mehrtens -+ * -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_LANTIQ -+#include -+#endif -+ -+#define SPI_RX_IRQ_NAME "spi_rx" -+#define SPI_TX_IRQ_NAME "spi_tx" -+#define SPI_ERR_IRQ_NAME "spi_err" -+#define SPI_FRM_IRQ_NAME "spi_frm" -+ -+#define SPI_CLC 0x00 -+#define SPI_PISEL 0x04 -+#define SPI_ID 0x08 -+#define SPI_CON 0x10 -+#define SPI_STAT 0x14 -+#define SPI_WHBSTATE 0x18 -+#define SPI_TB 0x20 -+#define SPI_RB 0x24 -+#define SPI_RXFCON 0x30 -+#define SPI_TXFCON 0x34 -+#define SPI_FSTAT 0x38 -+#define SPI_BRT 0x40 -+#define SPI_BRSTAT 0x44 -+#define SPI_SFCON 0x60 -+#define SPI_SFSTAT 0x64 -+#define SPI_GPOCON 0x70 -+#define SPI_GPOSTAT 0x74 -+#define SPI_FPGO 0x78 -+#define SPI_RXREQ 0x80 -+#define SPI_RXCNT 0x84 -+#define SPI_DMACON 0xec -+#define SPI_IRNEN 0xf4 -+#define SPI_IRNICR 0xf8 -+#define SPI_IRNCR 0xfc -+ -+#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ -+#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S) -+#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ -+#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S) -+#define SPI_CLC_DISS BIT(1) /* Disable status bit */ -+#define SPI_CLC_DISR BIT(0) /* Disable request bit */ -+ -+#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ -+#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S) -+#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ -+#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S) -+#define SPI_ID_MOD_S 8 /* Module ID */ -+#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S) -+#define SPI_ID_CFG_S 5 /* DMA interface support */ -+#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S) -+#define SPI_ID_REV_M 0x1F /* Hardware revision number */ -+ -+#define SPI_CON_BM_S 16 /* Data width selection */ -+#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S) -+#define SPI_CON_EM BIT(24) /* Echo mode */ -+#define SPI_CON_IDLE BIT(23) /* Idle bit value */ -+#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */ -+#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ -+#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ -+#define SPI_CON_AEN BIT(10) /* Abort error enable */ -+#define SPI_CON_REN BIT(9) /* Receive overflow error enable */ -+#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ -+#define SPI_CON_LB BIT(7) /* Loopback control */ -+#define SPI_CON_PO BIT(6) /* Clock polarity control */ -+#define SPI_CON_PH BIT(5) /* Clock phase control */ -+#define SPI_CON_HB BIT(4) /* Heading control */ -+#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */ -+#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ -+ -+#define SPI_STAT_RXBV_S 28 -+#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S) -+#define SPI_STAT_BSY BIT(13) /* Busy flag */ -+#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ -+#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ -+#define SPI_STAT_AE BIT(10) /* Abort error flag */ -+#define SPI_STAT_RE BIT(9) /* Receive error flag */ -+#define SPI_STAT_TE BIT(8) /* Transmit error flag */ -+#define SPI_STAT_ME BIT(7) /* Mode error flag */ -+#define SPI_STAT_MS BIT(1) /* Master/slave select bit */ -+#define SPI_STAT_EN BIT(0) /* Enable bit */ -+#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \ -+ SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE) -+ -+#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ -+#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ -+#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ -+#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ -+#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ -+#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ -+#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ -+#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ -+#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ -+#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ -+#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ -+#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ -+#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ -+#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ -+#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ -+#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ -+#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \ -+ SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \ -+ SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE) -+ -+#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ -+#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S) -+#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ -+#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ -+ -+#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ -+#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S) -+#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ -+#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ -+ -+#define SPI_FSTAT_RXFFL_S 0 -+#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S) -+#define SPI_FSTAT_TXFFL_S 8 -+#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S) -+ -+#define SPI_GPOCON_ISCSBN_S 8 -+#define SPI_GPOCON_INVOUTN_S 0 -+ -+#define SPI_FGPO_SETOUTN_S 8 -+#define SPI_FGPO_CLROUTN_S 0 -+ -+#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ -+#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ -+ -+#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ -+#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ -+#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */ -+#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ -+#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ -+#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ -+#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ -+#define SPI_IRNEN_ALL 0x1F -+ -+struct lantiq_ssc_hwcfg { -+ unsigned int irnen_r; -+ unsigned int irnen_t; -+}; -+ -+struct lantiq_ssc_spi { -+ struct spi_master *master; -+ struct device *dev; -+ void __iomem *regbase; -+ struct clk *spi_clk; -+ struct clk *fpi_clk; -+ const struct lantiq_ssc_hwcfg *hwcfg; -+ -+ spinlock_t lock; -+ struct workqueue_struct *wq; -+ struct work_struct work; -+ -+ const u8 *tx; -+ u8 *rx; -+ unsigned int tx_todo; -+ unsigned int rx_todo; -+ unsigned int bits_per_word; -+ unsigned int speed_hz; -+ unsigned int tx_fifo_size; -+ unsigned int rx_fifo_size; -+ unsigned int base_cs; -+}; -+ -+static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg) -+{ -+ return __raw_readl(spi->regbase + reg); -+} -+ -+static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val, -+ u32 reg) -+{ -+ __raw_writel(val, spi->regbase + reg); -+} -+ -+static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, -+ u32 set, u32 reg) -+{ -+ u32 val = __raw_readl(spi->regbase + reg); -+ -+ val &= ~clr; -+ val |= set; -+ __raw_writel(val, spi->regbase + reg); -+} -+ -+static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) -+{ -+ u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); -+ -+ return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S; -+} -+ -+static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) -+{ -+ u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); -+ -+ return fstat & SPI_FSTAT_RXFFL_M; -+} -+ -+static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) -+{ -+ return spi->tx_fifo_size - tx_fifo_level(spi); -+} -+ -+static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) -+{ -+ u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S; -+ -+ val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU; -+ lantiq_ssc_writel(spi, val, SPI_RXFCON); -+} -+ -+static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) -+{ -+ u32 val = 1 << SPI_TXFCON_TXFITL_S; -+ -+ val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU; -+ lantiq_ssc_writel(spi, val, SPI_TXFCON); -+} -+ -+static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) -+{ -+ lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON); -+} -+ -+static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) -+{ -+ lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON); -+} -+ -+static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) -+{ -+ lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE); -+} -+ -+static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) -+{ -+ lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE); -+} -+ -+static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, -+ unsigned int max_speed_hz) -+{ -+ u32 spi_clk, brt; -+ -+ /* -+ * SPI module clock is derived from FPI bus clock dependent on -+ * divider value in CLC.RMS which is always set to 1. -+ * -+ * f_SPI -+ * baudrate = -------------- -+ * 2 * (BR + 1) -+ */ -+ spi_clk = clk_get_rate(spi->fpi_clk) / 2; -+ -+ if (max_speed_hz > spi_clk) -+ brt = 0; -+ else -+ brt = spi_clk / max_speed_hz - 1; -+ -+ if (brt > 0xFFFF) -+ brt = 0xFFFF; -+ -+ dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", -+ spi_clk, max_speed_hz, brt); -+ -+ lantiq_ssc_writel(spi, brt, SPI_BRT); -+} -+ -+static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, -+ unsigned int bits_per_word) -+{ -+ u32 bm; -+ -+ /* CON.BM value = bits_per_word - 1 */ -+ bm = (bits_per_word - 1) << SPI_CON_BM_S; -+ -+ lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON); -+} -+ -+static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, -+ unsigned int mode) -+{ -+ u32 con_set = 0, con_clr = 0; -+ -+ /* -+ * SPI mode mapping in CON register: -+ * Mode CPOL CPHA CON.PO CON.PH -+ * 0 0 0 0 1 -+ * 1 0 1 0 0 -+ * 2 1 0 1 1 -+ * 3 1 1 1 0 -+ */ -+ if (mode & SPI_CPHA) -+ con_clr |= SPI_CON_PH; -+ else -+ con_set |= SPI_CON_PH; -+ -+ if (mode & SPI_CPOL) -+ con_set |= SPI_CON_PO | SPI_CON_IDLE; -+ else -+ con_clr |= SPI_CON_PO | SPI_CON_IDLE; -+ -+ /* Set heading control */ -+ if (mode & SPI_LSB_FIRST) -+ con_clr |= SPI_CON_HB; -+ else -+ con_set |= SPI_CON_HB; -+ -+ /* Set loopback mode */ -+ if (mode & SPI_LOOP) -+ con_set |= SPI_CON_LB; -+ else -+ con_clr |= SPI_CON_LB; -+ -+ lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON); -+} -+ -+static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) -+{ -+ const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; -+ -+ /* -+ * Set clock divider for run mode to 1 to -+ * run at same frequency as FPI bus -+ */ -+ lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC); -+ -+ /* Put controller into config mode */ -+ hw_enter_config_mode(spi); -+ -+ /* Clear error flags */ -+ lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); -+ -+ /* Enable error checking, disable TX/RX */ -+ lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN | -+ SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); -+ -+ /* Setup default SPI mode */ -+ hw_setup_bits_per_word(spi, spi->bits_per_word); -+ hw_setup_clock_mode(spi, SPI_MODE_0); -+ -+ /* Enable master mode and clear error flags */ -+ lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS, -+ SPI_WHBSTATE); -+ -+ /* Reset GPIO/CS registers */ -+ lantiq_ssc_writel(spi, 0, SPI_GPOCON); -+ lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO); -+ -+ /* Enable and flush FIFOs */ -+ rx_fifo_reset(spi); -+ tx_fifo_reset(spi); -+ -+ /* Enable interrupts */ -+ lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E, -+ SPI_IRNEN); -+} -+ -+static int lantiq_ssc_setup(struct spi_device *spidev) -+{ -+ struct spi_master *master = spidev->master; -+ struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); -+ unsigned int cs = spidev->chip_select; -+ u32 gpocon; -+ -+ /* GPIOs are used for CS */ -+ if (gpio_is_valid(spidev->cs_gpio)) -+ return 0; -+ -+ dev_dbg(spi->dev, "using internal chipselect %u\n", cs); -+ -+ if (cs < spi->base_cs) { -+ dev_err(spi->dev, -+ "chipselect %i too small (min %i)\n", cs, spi->base_cs); -+ return -EINVAL; -+ } -+ -+ /* set GPO pin to CS mode */ -+ gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S); -+ -+ /* invert GPO pin */ -+ if (spidev->mode & SPI_CS_HIGH) -+ gpocon |= 1 << (cs - spi->base_cs); -+ -+ lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON); -+ -+ return 0; -+} -+ -+static int lantiq_ssc_prepare_message(struct spi_master *master, -+ struct spi_message *message) -+{ -+ struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); -+ -+ hw_enter_config_mode(spi); -+ hw_setup_clock_mode(spi, message->spi->mode); -+ hw_enter_active_mode(spi); -+ -+ return 0; -+} -+ -+static void hw_setup_transfer(struct lantiq_ssc_spi *spi, -+ struct spi_device *spidev, struct spi_transfer *t) -+{ -+ unsigned int speed_hz = t->speed_hz; -+ unsigned int bits_per_word = t->bits_per_word; -+ u32 con; -+ -+ if (bits_per_word != spi->bits_per_word || -+ speed_hz != spi->speed_hz) { -+ hw_enter_config_mode(spi); -+ hw_setup_speed_hz(spi, speed_hz); -+ hw_setup_bits_per_word(spi, bits_per_word); -+ hw_enter_active_mode(spi); -+ -+ spi->speed_hz = speed_hz; -+ spi->bits_per_word = bits_per_word; -+ } -+ -+ /* Configure transmitter and receiver */ -+ con = lantiq_ssc_readl(spi, SPI_CON); -+ if (t->tx_buf) -+ con &= ~SPI_CON_TXOFF; -+ else -+ con |= SPI_CON_TXOFF; -+ -+ if (t->rx_buf) -+ con &= ~SPI_CON_RXOFF; -+ else -+ con |= SPI_CON_RXOFF; -+ -+ lantiq_ssc_writel(spi, con, SPI_CON); -+} -+ -+static int lantiq_ssc_unprepare_message(struct spi_master *master, -+ struct spi_message *message) -+{ -+ struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); -+ -+ flush_workqueue(spi->wq); -+ -+ /* Disable transmitter and receiver while idle */ -+ lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); -+ -+ return 0; -+} -+ -+static void tx_fifo_write(struct lantiq_ssc_spi *spi) -+{ -+ const u8 *tx8; -+ const u16 *tx16; -+ const u32 *tx32; -+ u32 data; -+ unsigned int tx_free = tx_fifo_free(spi); -+ -+ while (spi->tx_todo && tx_free) { -+ switch (spi->bits_per_word) { -+ case 2 ... 8: -+ tx8 = spi->tx; -+ data = *tx8; -+ spi->tx_todo--; -+ spi->tx++; -+ break; -+ case 16: -+ tx16 = (u16 *) spi->tx; -+ data = *tx16; -+ spi->tx_todo -= 2; -+ spi->tx += 2; -+ break; -+ case 32: -+ tx32 = (u32 *) spi->tx; -+ data = *tx32; -+ spi->tx_todo -= 4; -+ spi->tx += 4; -+ break; -+ default: -+ WARN_ON(1); -+ data = 0; -+ break; -+ } -+ -+ lantiq_ssc_writel(spi, data, SPI_TB); -+ tx_free--; -+ } -+} -+ -+static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) -+{ -+ u8 *rx8; -+ u16 *rx16; -+ u32 *rx32; -+ u32 data; -+ unsigned int rx_fill = rx_fifo_level(spi); -+ -+ while (rx_fill) { -+ data = lantiq_ssc_readl(spi, SPI_RB); -+ -+ switch (spi->bits_per_word) { -+ case 2 ... 8: -+ rx8 = spi->rx; -+ *rx8 = data; -+ spi->rx_todo--; -+ spi->rx++; -+ break; -+ case 16: -+ rx16 = (u16 *) spi->rx; -+ *rx16 = data; -+ spi->rx_todo -= 2; -+ spi->rx += 2; -+ break; -+ case 32: -+ rx32 = (u32 *) spi->rx; -+ *rx32 = data; -+ spi->rx_todo -= 4; -+ spi->rx += 4; -+ break; -+ default: -+ WARN_ON(1); -+ break; -+ } -+ -+ rx_fill--; -+ } -+} -+ -+static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) -+{ -+ u32 data, *rx32; -+ u8 *rx8; -+ unsigned int rxbv, shift; -+ unsigned int rx_fill = rx_fifo_level(spi); -+ -+ /* -+ * In RX-only mode the bits per word value is ignored by HW. A value -+ * of 32 is used instead. Thus all 4 bytes per FIFO must be read. -+ * If remaining RX bytes are less than 4, the FIFO must be read -+ * differently. The amount of received and valid bytes is indicated -+ * by STAT.RXBV register value. -+ */ -+ while (rx_fill) { -+ if (spi->rx_todo < 4) { -+ rxbv = (lantiq_ssc_readl(spi, SPI_STAT) & -+ SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S; -+ data = lantiq_ssc_readl(spi, SPI_RB); -+ -+ shift = (rxbv - 1) * 8; -+ rx8 = spi->rx; -+ -+ while (rxbv) { -+ *rx8++ = (data >> shift) & 0xFF; -+ rxbv--; -+ shift -= 8; -+ spi->rx_todo--; -+ spi->rx++; -+ } -+ } else { -+ data = lantiq_ssc_readl(spi, SPI_RB); -+ rx32 = (u32 *) spi->rx; -+ -+ *rx32++ = data; -+ spi->rx_todo -= 4; -+ spi->rx += 4; -+ } -+ rx_fill--; -+ } -+} -+ -+static void rx_request(struct lantiq_ssc_spi *spi) -+{ -+ unsigned int rxreq, rxreq_max; -+ -+ /* -+ * To avoid receive overflows at high clocks it is better to request -+ * only the amount of bytes that fits into all FIFOs. This value -+ * depends on the FIFO size implemented in hardware. -+ */ -+ rxreq = spi->rx_todo; -+ rxreq_max = spi->rx_fifo_size * 4; -+ if (rxreq > rxreq_max) -+ rxreq = rxreq_max; -+ -+ lantiq_ssc_writel(spi, rxreq, SPI_RXREQ); -+} -+ -+static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) -+{ -+ struct lantiq_ssc_spi *spi = data; -+ -+ if (spi->tx) { -+ if (spi->rx && spi->rx_todo) -+ rx_fifo_read_full_duplex(spi); -+ -+ if (spi->tx_todo) -+ tx_fifo_write(spi); -+ else if (!tx_fifo_level(spi)) -+ goto completed; -+ } else if (spi->rx) { -+ if (spi->rx_todo) { -+ rx_fifo_read_half_duplex(spi); -+ -+ if (spi->rx_todo) -+ rx_request(spi); -+ else -+ goto completed; -+ } else { -+ goto completed; -+ } -+ } -+ -+ return IRQ_HANDLED; -+ -+completed: -+ queue_work(spi->wq, &spi->work); -+ -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) -+{ -+ struct lantiq_ssc_spi *spi = data; -+ u32 stat = lantiq_ssc_readl(spi, SPI_STAT); -+ -+ if (!(stat & SPI_STAT_ERRORS)) -+ return IRQ_NONE; -+ -+ if (stat & SPI_STAT_RUE) -+ dev_err(spi->dev, "receive underflow error\n"); -+ if (stat & SPI_STAT_TUE) -+ dev_err(spi->dev, "transmit underflow error\n"); -+ if (stat & SPI_STAT_AE) -+ dev_err(spi->dev, "abort error\n"); -+ if (stat & SPI_STAT_RE) -+ dev_err(spi->dev, "receive overflow error\n"); -+ if (stat & SPI_STAT_TE) -+ dev_err(spi->dev, "transmit overflow error\n"); -+ if (stat & SPI_STAT_ME) -+ dev_err(spi->dev, "mode error\n"); -+ -+ /* Clear error flags */ -+ lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); -+ -+ /* set bad status so it can be retried */ -+ if (spi->master->cur_msg) -+ spi->master->cur_msg->status = -EIO; -+ queue_work(spi->wq, &spi->work); -+ -+ return IRQ_HANDLED; -+} -+ -+static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev, -+ struct spi_transfer *t) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&spi->lock, flags); -+ -+ spi->tx = t->tx_buf; -+ spi->rx = t->rx_buf; -+ -+ if (t->tx_buf) { -+ spi->tx_todo = t->len; -+ -+ /* initially fill TX FIFO */ -+ tx_fifo_write(spi); -+ } -+ -+ if (spi->rx) { -+ spi->rx_todo = t->len; -+ -+ /* start shift clock in RX-only mode */ -+ if (!spi->tx) -+ rx_request(spi); -+ } -+ -+ spin_unlock_irqrestore(&spi->lock, flags); -+ -+ return t->len; -+} -+ -+/* -+ * The driver only gets an interrupt when the FIFO is empty, but there -+ * is an additional shift register from which the data is written to -+ * the wire. We get the last interrupt when the controller starts to -+ * write the last word to the wire, not when it is finished. Do busy -+ * waiting till it finishes. -+ */ -+static void lantiq_ssc_bussy_work(struct work_struct *work) -+{ -+ struct lantiq_ssc_spi *spi; -+ unsigned long long timeout = 8LL * 1000LL; -+ unsigned long end; -+ -+ spi = container_of(work, typeof(*spi), work); -+ -+ do_div(timeout, spi->speed_hz); -+ timeout += timeout + 100; /* some tolerance */ -+ -+ end = jiffies + msecs_to_jiffies(timeout); -+ do { -+ u32 stat = lantiq_ssc_readl(spi, SPI_STAT); -+ -+ if (!(stat & SPI_STAT_BSY)) { -+ spi_finalize_current_transfer(spi->master); -+ return; -+ } -+ -+ cond_resched(); -+ } while (!time_after_eq(jiffies, end)); -+ -+ if (spi->master->cur_msg) -+ spi->master->cur_msg->status = -EIO; -+ spi_finalize_current_transfer(spi->master); -+} -+ -+static void lantiq_ssc_handle_err(struct spi_master *master, -+ struct spi_message *message) -+{ -+ struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); -+ -+ /* flush FIFOs on timeout */ -+ rx_fifo_flush(spi); -+ tx_fifo_flush(spi); -+} -+ -+static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) -+{ -+ struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master); -+ unsigned int cs = spidev->chip_select; -+ u32 fgpo; -+ -+ if (!!(spidev->mode & SPI_CS_HIGH) == enable) -+ fgpo = (1 << (cs - spi->base_cs)); -+ else -+ fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S)); -+ -+ lantiq_ssc_writel(spi, fgpo, SPI_FPGO); -+} -+ -+static int lantiq_ssc_transfer_one(struct spi_master *master, -+ struct spi_device *spidev, -+ struct spi_transfer *t) -+{ -+ struct lantiq_ssc_spi *spi = spi_master_get_devdata(master); -+ -+ hw_setup_transfer(spi, spidev, t); -+ -+ return transfer_start(spi, spidev, t); -+} -+ -+static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { -+ .irnen_r = SPI_IRNEN_R_XWAY, -+ .irnen_t = SPI_IRNEN_T_XWAY, -+}; -+ -+static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { -+ .irnen_r = SPI_IRNEN_R_XRX, -+ .irnen_t = SPI_IRNEN_T_XRX, -+}; -+ -+static const struct of_device_id lantiq_ssc_match[] = { -+ { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, }, -+ { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, }, -+ { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, lantiq_ssc_match); -+ -+static int lantiq_ssc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct spi_master *master; -+ struct resource *res; -+ struct lantiq_ssc_spi *spi; -+ const struct lantiq_ssc_hwcfg *hwcfg; -+ const struct of_device_id *match; -+ int err, rx_irq, tx_irq, err_irq; -+ u32 id, supports_dma, revision; -+ unsigned int num_cs; -+ -+ match = of_match_device(lantiq_ssc_match, dev); -+ if (!match) { -+ dev_err(dev, "no device match\n"); -+ return -EINVAL; -+ } -+ hwcfg = match->data; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(dev, "failed to get resources\n"); -+ return -ENXIO; -+ } -+ -+ rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME); -+ if (rx_irq < 0) { -+ dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME); -+ return -ENXIO; -+ } -+ -+ tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME); -+ if (tx_irq < 0) { -+ dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME); -+ return -ENXIO; -+ } -+ -+ err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME); -+ if (err_irq < 0) { -+ dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME); -+ return -ENXIO; -+ } -+ -+ master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi)); -+ if (!master) -+ return -ENOMEM; -+ -+ spi = spi_master_get_devdata(master); -+ spi->master = master; -+ spi->dev = dev; -+ spi->hwcfg = hwcfg; -+ platform_set_drvdata(pdev, spi); -+ -+ spi->regbase = devm_ioremap_resource(dev, res); -+ if (IS_ERR(spi->regbase)) { -+ err = PTR_ERR(spi->regbase); -+ goto err_master_put; -+ } -+ -+ err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, -+ 0, SPI_RX_IRQ_NAME, spi); -+ if (err) -+ goto err_master_put; -+ -+ err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, -+ 0, SPI_TX_IRQ_NAME, spi); -+ if (err) -+ goto err_master_put; -+ -+ err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, -+ 0, SPI_ERR_IRQ_NAME, spi); -+ if (err) -+ goto err_master_put; -+ -+ spi->spi_clk = devm_clk_get(dev, "gate"); -+ if (IS_ERR(spi->spi_clk)) { -+ err = PTR_ERR(spi->spi_clk); -+ goto err_master_put; -+ } -+ err = clk_prepare_enable(spi->spi_clk); -+ if (err) -+ goto err_master_put; -+ -+ /* -+ * Use the old clk_get_fpi() function on Lantiq platform, till it -+ * supports common clk. -+ */ -+#if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK) -+ spi->fpi_clk = clk_get_fpi(); -+#else -+ spi->fpi_clk = clk_get(dev, "freq"); -+#endif -+ if (IS_ERR(spi->fpi_clk)) { -+ err = PTR_ERR(spi->fpi_clk); -+ goto err_clk_disable; -+ } -+ -+ num_cs = 8; -+ of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); -+ -+ spi->base_cs = 1; -+ of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs); -+ -+ spin_lock_init(&spi->lock); -+ spi->bits_per_word = 8; -+ spi->speed_hz = 0; -+ -+ master->dev.of_node = pdev->dev.of_node; -+ master->num_chipselect = num_cs; -+ master->setup = lantiq_ssc_setup; -+ master->set_cs = lantiq_ssc_set_cs; -+ master->handle_err = lantiq_ssc_handle_err; -+ master->prepare_message = lantiq_ssc_prepare_message; -+ master->unprepare_message = lantiq_ssc_unprepare_message; -+ master->transfer_one = lantiq_ssc_transfer_one; -+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH | -+ SPI_LOOP; -+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) | -+ SPI_BPW_MASK(16) | SPI_BPW_MASK(32); -+ -+ spi->wq = alloc_ordered_workqueue(dev_name(dev), 0); -+ if (!spi->wq) { -+ err = -ENOMEM; -+ goto err_clk_put; -+ } -+ INIT_WORK(&spi->work, lantiq_ssc_bussy_work); -+ -+ id = lantiq_ssc_readl(spi, SPI_ID); -+ spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S; -+ spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S; -+ supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S; -+ revision = id & SPI_ID_REV_M; -+ -+ lantiq_ssc_hw_init(spi); -+ -+ dev_info(dev, -+ "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n", -+ revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma); -+ -+ err = devm_spi_register_master(dev, master); -+ if (err) { -+ dev_err(dev, "failed to register spi_master\n"); -+ goto err_wq_destroy; -+ } -+ -+ return 0; -+ -+err_wq_destroy: -+ destroy_workqueue(spi->wq); -+err_clk_put: -+ clk_put(spi->fpi_clk); -+err_clk_disable: -+ clk_disable_unprepare(spi->spi_clk); -+err_master_put: -+ spi_master_put(master); -+ -+ return err; -+} -+ -+static int lantiq_ssc_remove(struct platform_device *pdev) -+{ -+ struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); -+ -+ lantiq_ssc_writel(spi, 0, SPI_IRNEN); -+ lantiq_ssc_writel(spi, 0, SPI_CLC); -+ rx_fifo_flush(spi); -+ tx_fifo_flush(spi); -+ hw_enter_config_mode(spi); -+ -+ destroy_workqueue(spi->wq); -+ clk_disable_unprepare(spi->spi_clk); -+ clk_put(spi->fpi_clk); -+ -+ return 0; -+} -+ -+static struct platform_driver lantiq_ssc_driver = { -+ .probe = lantiq_ssc_probe, -+ .remove = lantiq_ssc_remove, -+ .driver = { -+ .name = "spi-lantiq-ssc", -+ .owner = THIS_MODULE, -+ .of_match_table = lantiq_ssc_match, -+ }, -+}; -+module_platform_driver(lantiq_ssc_driver); -+ -+MODULE_DESCRIPTION("Lantiq SSC SPI controller driver"); -+MODULE_AUTHOR("Daniel Schwierzeck "); -+MODULE_AUTHOR("Hauke Mehrtens "); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:spi-lantiq-ssc"); diff --git a/target/linux/lantiq/patches-4.9/0091-spi-lantiq-ssc-fix-platform_no_drv_owner.cocci-warni.patch b/target/linux/lantiq/patches-4.9/0091-spi-lantiq-ssc-fix-platform_no_drv_owner.cocci-warni.patch deleted file mode 100644 index e81f97f9d..000000000 --- a/target/linux/lantiq/patches-4.9/0091-spi-lantiq-ssc-fix-platform_no_drv_owner.cocci-warni.patch +++ /dev/null @@ -1,28 +0,0 @@ -From ba6e1e39969fa5435127a632757e2906caca7730 Mon Sep 17 00:00:00 2001 -From: kbuild test robot -Date: Mon, 20 Feb 2017 01:33:10 +0800 -Subject: spi: lantiq-ssc: fix platform_no_drv_owner.cocci warnings - -drivers/spi/spi-lantiq-ssc.c:973:3-8: No need to set .owner here. The core will do it. - - Remove .owner field if calls are used which set it automatically - -Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci - -Signed-off-by: Fengguang Wu -Acked-by: Hauke Mehrtens -Signed-off-by: Mark Brown ---- - drivers/spi/spi-lantiq-ssc.c | 1 - - 1 file changed, 1 deletion(-) - ---- a/drivers/spi/spi-lantiq-ssc.c -+++ b/drivers/spi/spi-lantiq-ssc.c -@@ -970,7 +970,6 @@ static struct platform_driver lantiq_ssc - .remove = lantiq_ssc_remove, - .driver = { - .name = "spi-lantiq-ssc", -- .owner = THIS_MODULE, - .of_match_table = lantiq_ssc_match, - }, - }; diff --git a/target/linux/lantiq/patches-4.9/0092-spi-lantiq-ssc-add-LTQ_-prefix-to-defines.patch b/target/linux/lantiq/patches-4.9/0092-spi-lantiq-ssc-add-LTQ_-prefix-to-defines.patch deleted file mode 100644 index 9bcde3c08..000000000 --- a/target/linux/lantiq/patches-4.9/0092-spi-lantiq-ssc-add-LTQ_-prefix-to-defines.patch +++ /dev/null @@ -1,723 +0,0 @@ -From 1aa83e0a2821cd7f4e8f3ddb367859f52e468bf1 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Mon, 27 Feb 2017 23:21:25 +0100 -Subject: spi: lantiq-ssc: add LTQ_ prefix to defines - -The blackfin architecture has a SPI_STAT define which conflicts with -the define from the spi-lantiq-ssc driver in compile test mode. Fix -this by adding a prefix in front of every define. - -Reported-by: kbuild test robot -Signed-off-by: Hauke Mehrtens -Signed-off-by: Mark Brown ---- - drivers/spi/spi-lantiq-ssc.c | 437 ++++++++++++++++++++++--------------------- - 1 file changed, 222 insertions(+), 215 deletions(-) - ---- a/drivers/spi/spi-lantiq-ssc.c -+++ b/drivers/spi/spi-lantiq-ssc.c -@@ -26,136 +26,140 @@ - #include - #endif - --#define SPI_RX_IRQ_NAME "spi_rx" --#define SPI_TX_IRQ_NAME "spi_tx" --#define SPI_ERR_IRQ_NAME "spi_err" --#define SPI_FRM_IRQ_NAME "spi_frm" -- --#define SPI_CLC 0x00 --#define SPI_PISEL 0x04 --#define SPI_ID 0x08 --#define SPI_CON 0x10 --#define SPI_STAT 0x14 --#define SPI_WHBSTATE 0x18 --#define SPI_TB 0x20 --#define SPI_RB 0x24 --#define SPI_RXFCON 0x30 --#define SPI_TXFCON 0x34 --#define SPI_FSTAT 0x38 --#define SPI_BRT 0x40 --#define SPI_BRSTAT 0x44 --#define SPI_SFCON 0x60 --#define SPI_SFSTAT 0x64 --#define SPI_GPOCON 0x70 --#define SPI_GPOSTAT 0x74 --#define SPI_FPGO 0x78 --#define SPI_RXREQ 0x80 --#define SPI_RXCNT 0x84 --#define SPI_DMACON 0xec --#define SPI_IRNEN 0xf4 --#define SPI_IRNICR 0xf8 --#define SPI_IRNCR 0xfc -- --#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ --#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S) --#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ --#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S) --#define SPI_CLC_DISS BIT(1) /* Disable status bit */ --#define SPI_CLC_DISR BIT(0) /* Disable request bit */ -- --#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ --#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S) --#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ --#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S) --#define SPI_ID_MOD_S 8 /* Module ID */ --#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S) --#define SPI_ID_CFG_S 5 /* DMA interface support */ --#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S) --#define SPI_ID_REV_M 0x1F /* Hardware revision number */ -- --#define SPI_CON_BM_S 16 /* Data width selection */ --#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S) --#define SPI_CON_EM BIT(24) /* Echo mode */ --#define SPI_CON_IDLE BIT(23) /* Idle bit value */ --#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */ --#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ --#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ --#define SPI_CON_AEN BIT(10) /* Abort error enable */ --#define SPI_CON_REN BIT(9) /* Receive overflow error enable */ --#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ --#define SPI_CON_LB BIT(7) /* Loopback control */ --#define SPI_CON_PO BIT(6) /* Clock polarity control */ --#define SPI_CON_PH BIT(5) /* Clock phase control */ --#define SPI_CON_HB BIT(4) /* Heading control */ --#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */ --#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ -- --#define SPI_STAT_RXBV_S 28 --#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S) --#define SPI_STAT_BSY BIT(13) /* Busy flag */ --#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ --#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ --#define SPI_STAT_AE BIT(10) /* Abort error flag */ --#define SPI_STAT_RE BIT(9) /* Receive error flag */ --#define SPI_STAT_TE BIT(8) /* Transmit error flag */ --#define SPI_STAT_ME BIT(7) /* Mode error flag */ --#define SPI_STAT_MS BIT(1) /* Master/slave select bit */ --#define SPI_STAT_EN BIT(0) /* Enable bit */ --#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \ -- SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE) -- --#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ --#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ --#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ --#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ --#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ --#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ --#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ --#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ --#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ --#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ --#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ --#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ --#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ --#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ --#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ --#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ --#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \ -- SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \ -- SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE) -- --#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ --#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S) --#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ --#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ -- --#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ --#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S) --#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ --#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ -- --#define SPI_FSTAT_RXFFL_S 0 --#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S) --#define SPI_FSTAT_TXFFL_S 8 --#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S) -- --#define SPI_GPOCON_ISCSBN_S 8 --#define SPI_GPOCON_INVOUTN_S 0 -- --#define SPI_FGPO_SETOUTN_S 8 --#define SPI_FGPO_CLROUTN_S 0 -- --#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ --#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ -- --#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ --#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ --#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */ --#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ --#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ --#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ --#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ --#define SPI_IRNEN_ALL 0x1F -+#define LTQ_SPI_RX_IRQ_NAME "spi_rx" -+#define LTQ_SPI_TX_IRQ_NAME "spi_tx" -+#define LTQ_SPI_ERR_IRQ_NAME "spi_err" -+#define LTQ_SPI_FRM_IRQ_NAME "spi_frm" -+ -+#define LTQ_SPI_CLC 0x00 -+#define LTQ_SPI_PISEL 0x04 -+#define LTQ_SPI_ID 0x08 -+#define LTQ_SPI_CON 0x10 -+#define LTQ_SPI_STAT 0x14 -+#define LTQ_SPI_WHBSTATE 0x18 -+#define LTQ_SPI_TB 0x20 -+#define LTQ_SPI_RB 0x24 -+#define LTQ_SPI_RXFCON 0x30 -+#define LTQ_SPI_TXFCON 0x34 -+#define LTQ_SPI_FSTAT 0x38 -+#define LTQ_SPI_BRT 0x40 -+#define LTQ_SPI_BRSTAT 0x44 -+#define LTQ_SPI_SFCON 0x60 -+#define LTQ_SPI_SFSTAT 0x64 -+#define LTQ_SPI_GPOCON 0x70 -+#define LTQ_SPI_GPOSTAT 0x74 -+#define LTQ_SPI_FPGO 0x78 -+#define LTQ_SPI_RXREQ 0x80 -+#define LTQ_SPI_RXCNT 0x84 -+#define LTQ_SPI_DMACON 0xec -+#define LTQ_SPI_IRNEN 0xf4 -+#define LTQ_SPI_IRNICR 0xf8 -+#define LTQ_SPI_IRNCR 0xfc -+ -+#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ -+#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S) -+#define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ -+#define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S) -+#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ -+#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ -+ -+#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ -+#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S) -+#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ -+#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S) -+#define LTQ_SPI_ID_MOD_S 8 /* Module ID */ -+#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S) -+#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */ -+#define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S) -+#define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */ -+ -+#define LTQ_SPI_CON_BM_S 16 /* Data width selection */ -+#define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S) -+#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ -+#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ -+#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ -+#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ -+#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ -+#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ -+#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ -+#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ -+#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ -+#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ -+#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ -+#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ -+#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ -+#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ -+ -+#define LTQ_SPI_STAT_RXBV_S 28 -+#define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S) -+#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ -+#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ -+#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ -+#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ -+#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ -+#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ -+#define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */ -+#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ -+#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ -+#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \ -+ LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \ -+ LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE) -+ -+#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ -+#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ -+#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ -+#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ -+#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ -+#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ -+#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ -+#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ -+#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ -+#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ -+#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ -+#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ -+#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ -+#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ -+#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ -+#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ -+#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \ -+ LTQ_SPI_WHBSTATE_CLRME | \ -+ LTQ_SPI_WHBSTATE_CLRTE | \ -+ LTQ_SPI_WHBSTATE_CLRRE | \ -+ LTQ_SPI_WHBSTATE_CLRAE | \ -+ LTQ_SPI_WHBSTATE_CLRTUE) -+ -+#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ -+#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S) -+#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ -+#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ -+ -+#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ -+#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S) -+#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ -+#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ -+ -+#define LTQ_SPI_FSTAT_RXFFL_S 0 -+#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S) -+#define LTQ_SPI_FSTAT_TXFFL_S 8 -+#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S) -+ -+#define LTQ_SPI_GPOCON_ISCSBN_S 8 -+#define LTQ_SPI_GPOCON_INVOUTN_S 0 -+ -+#define LTQ_SPI_FGPO_SETOUTN_S 8 -+#define LTQ_SPI_FGPO_CLROUTN_S 0 -+ -+#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ -+#define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ -+ -+#define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ -+#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ -+#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ -+#define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ -+#define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ -+#define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ -+#define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ -+#define LTQ_SPI_IRNEN_ALL 0x1F - - struct lantiq_ssc_hwcfg { - unsigned int irnen_r; -@@ -208,16 +212,16 @@ static void lantiq_ssc_maskl(const struc - - static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) - { -- u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); -+ u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); - -- return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S; -+ return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S; - } - - static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) - { -- u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); -+ u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); - -- return fstat & SPI_FSTAT_RXFFL_M; -+ return fstat & LTQ_SPI_FSTAT_RXFFL_M; - } - - static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) -@@ -227,38 +231,38 @@ static unsigned int tx_fifo_free(const s - - static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) - { -- u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S; -+ u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; - -- val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU; -- lantiq_ssc_writel(spi, val, SPI_RXFCON); -+ val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; -+ lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); - } - - static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) - { -- u32 val = 1 << SPI_TXFCON_TXFITL_S; -+ u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S; - -- val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU; -- lantiq_ssc_writel(spi, val, SPI_TXFCON); -+ val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; -+ lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); - } - - static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) - { -- lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON); -+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); - } - - static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) - { -- lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON); -+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); - } - - static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) - { -- lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE); -+ lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); - } - - static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) - { -- lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE); -+ lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); - } - - static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, -@@ -287,7 +291,7 @@ static void hw_setup_speed_hz(const stru - dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", - spi_clk, max_speed_hz, brt); - -- lantiq_ssc_writel(spi, brt, SPI_BRT); -+ lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT); - } - - static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, -@@ -296,9 +300,9 @@ static void hw_setup_bits_per_word(const - u32 bm; - - /* CON.BM value = bits_per_word - 1 */ -- bm = (bits_per_word - 1) << SPI_CON_BM_S; -+ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S; - -- lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON); -+ lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON); - } - - static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, -@@ -315,28 +319,28 @@ static void hw_setup_clock_mode(const st - * 3 1 1 1 0 - */ - if (mode & SPI_CPHA) -- con_clr |= SPI_CON_PH; -+ con_clr |= LTQ_SPI_CON_PH; - else -- con_set |= SPI_CON_PH; -+ con_set |= LTQ_SPI_CON_PH; - - if (mode & SPI_CPOL) -- con_set |= SPI_CON_PO | SPI_CON_IDLE; -+ con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; - else -- con_clr |= SPI_CON_PO | SPI_CON_IDLE; -+ con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; - - /* Set heading control */ - if (mode & SPI_LSB_FIRST) -- con_clr |= SPI_CON_HB; -+ con_clr |= LTQ_SPI_CON_HB; - else -- con_set |= SPI_CON_HB; -+ con_set |= LTQ_SPI_CON_HB; - - /* Set loopback mode */ - if (mode & SPI_LOOP) -- con_set |= SPI_CON_LB; -+ con_set |= LTQ_SPI_CON_LB; - else -- con_clr |= SPI_CON_LB; -+ con_clr |= LTQ_SPI_CON_LB; - -- lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON); -+ lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON); - } - - static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) -@@ -347,37 +351,39 @@ static void lantiq_ssc_hw_init(const str - * Set clock divider for run mode to 1 to - * run at same frequency as FPI bus - */ -- lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC); -+ lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC); - - /* Put controller into config mode */ - hw_enter_config_mode(spi); - - /* Clear error flags */ -- lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); -+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); - - /* Enable error checking, disable TX/RX */ -- lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN | -- SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); -+ lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | -+ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF | -+ LTQ_SPI_CON_RXOFF, LTQ_SPI_CON); - - /* Setup default SPI mode */ - hw_setup_bits_per_word(spi, spi->bits_per_word); - hw_setup_clock_mode(spi, SPI_MODE_0); - - /* Enable master mode and clear error flags */ -- lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS, -- SPI_WHBSTATE); -+ lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS | -+ LTQ_SPI_WHBSTATE_CLR_ERRORS, -+ LTQ_SPI_WHBSTATE); - - /* Reset GPIO/CS registers */ -- lantiq_ssc_writel(spi, 0, SPI_GPOCON); -- lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO); -+ lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON); -+ lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO); - - /* Enable and flush FIFOs */ - rx_fifo_reset(spi); - tx_fifo_reset(spi); - - /* Enable interrupts */ -- lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E, -- SPI_IRNEN); -+ lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | -+ LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); - } - - static int lantiq_ssc_setup(struct spi_device *spidev) -@@ -400,13 +406,13 @@ static int lantiq_ssc_setup(struct spi_d - } - - /* set GPO pin to CS mode */ -- gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S); -+ gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); - - /* invert GPO pin */ - if (spidev->mode & SPI_CS_HIGH) - gpocon |= 1 << (cs - spi->base_cs); - -- lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON); -+ lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON); - - return 0; - } -@@ -442,18 +448,18 @@ static void hw_setup_transfer(struct lan - } - - /* Configure transmitter and receiver */ -- con = lantiq_ssc_readl(spi, SPI_CON); -+ con = lantiq_ssc_readl(spi, LTQ_SPI_CON); - if (t->tx_buf) -- con &= ~SPI_CON_TXOFF; -+ con &= ~LTQ_SPI_CON_TXOFF; - else -- con |= SPI_CON_TXOFF; -+ con |= LTQ_SPI_CON_TXOFF; - - if (t->rx_buf) -- con &= ~SPI_CON_RXOFF; -+ con &= ~LTQ_SPI_CON_RXOFF; - else -- con |= SPI_CON_RXOFF; -+ con |= LTQ_SPI_CON_RXOFF; - -- lantiq_ssc_writel(spi, con, SPI_CON); -+ lantiq_ssc_writel(spi, con, LTQ_SPI_CON); - } - - static int lantiq_ssc_unprepare_message(struct spi_master *master, -@@ -464,7 +470,8 @@ static int lantiq_ssc_unprepare_message( - flush_workqueue(spi->wq); - - /* Disable transmitter and receiver while idle */ -- lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); -+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF, -+ LTQ_SPI_CON); - - return 0; - } -@@ -503,7 +510,7 @@ static void tx_fifo_write(struct lantiq_ - break; - } - -- lantiq_ssc_writel(spi, data, SPI_TB); -+ lantiq_ssc_writel(spi, data, LTQ_SPI_TB); - tx_free--; - } - } -@@ -517,7 +524,7 @@ static void rx_fifo_read_full_duplex(str - unsigned int rx_fill = rx_fifo_level(spi); - - while (rx_fill) { -- data = lantiq_ssc_readl(spi, SPI_RB); -+ data = lantiq_ssc_readl(spi, LTQ_SPI_RB); - - switch (spi->bits_per_word) { - case 2 ... 8: -@@ -563,9 +570,9 @@ static void rx_fifo_read_half_duplex(str - */ - while (rx_fill) { - if (spi->rx_todo < 4) { -- rxbv = (lantiq_ssc_readl(spi, SPI_STAT) & -- SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S; -- data = lantiq_ssc_readl(spi, SPI_RB); -+ rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) & -+ LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S; -+ data = lantiq_ssc_readl(spi, LTQ_SPI_RB); - - shift = (rxbv - 1) * 8; - rx8 = spi->rx; -@@ -578,7 +585,7 @@ static void rx_fifo_read_half_duplex(str - spi->rx++; - } - } else { -- data = lantiq_ssc_readl(spi, SPI_RB); -+ data = lantiq_ssc_readl(spi, LTQ_SPI_RB); - rx32 = (u32 *) spi->rx; - - *rx32++ = data; -@@ -603,7 +610,7 @@ static void rx_request(struct lantiq_ssc - if (rxreq > rxreq_max) - rxreq = rxreq_max; - -- lantiq_ssc_writel(spi, rxreq, SPI_RXREQ); -+ lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ); - } - - static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) -@@ -642,26 +649,26 @@ completed: - static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) - { - struct lantiq_ssc_spi *spi = data; -- u32 stat = lantiq_ssc_readl(spi, SPI_STAT); -+ u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); - -- if (!(stat & SPI_STAT_ERRORS)) -+ if (!(stat & LTQ_SPI_STAT_ERRORS)) - return IRQ_NONE; - -- if (stat & SPI_STAT_RUE) -+ if (stat & LTQ_SPI_STAT_RUE) - dev_err(spi->dev, "receive underflow error\n"); -- if (stat & SPI_STAT_TUE) -+ if (stat & LTQ_SPI_STAT_TUE) - dev_err(spi->dev, "transmit underflow error\n"); -- if (stat & SPI_STAT_AE) -+ if (stat & LTQ_SPI_STAT_AE) - dev_err(spi->dev, "abort error\n"); -- if (stat & SPI_STAT_RE) -+ if (stat & LTQ_SPI_STAT_RE) - dev_err(spi->dev, "receive overflow error\n"); -- if (stat & SPI_STAT_TE) -+ if (stat & LTQ_SPI_STAT_TE) - dev_err(spi->dev, "transmit overflow error\n"); -- if (stat & SPI_STAT_ME) -+ if (stat & LTQ_SPI_STAT_ME) - dev_err(spi->dev, "mode error\n"); - - /* Clear error flags */ -- lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); -+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); - - /* set bad status so it can be retried */ - if (spi->master->cur_msg) -@@ -721,9 +728,9 @@ static void lantiq_ssc_bussy_work(struct - - end = jiffies + msecs_to_jiffies(timeout); - do { -- u32 stat = lantiq_ssc_readl(spi, SPI_STAT); -+ u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); - -- if (!(stat & SPI_STAT_BSY)) { -+ if (!(stat & LTQ_SPI_STAT_BSY)) { - spi_finalize_current_transfer(spi->master); - return; - } -@@ -755,9 +762,9 @@ static void lantiq_ssc_set_cs(struct spi - if (!!(spidev->mode & SPI_CS_HIGH) == enable) - fgpo = (1 << (cs - spi->base_cs)); - else -- fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S)); -+ fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); - -- lantiq_ssc_writel(spi, fgpo, SPI_FPGO); -+ lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO); - } - - static int lantiq_ssc_transfer_one(struct spi_master *master, -@@ -772,13 +779,13 @@ static int lantiq_ssc_transfer_one(struc - } - - static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { -- .irnen_r = SPI_IRNEN_R_XWAY, -- .irnen_t = SPI_IRNEN_T_XWAY, -+ .irnen_r = LTQ_SPI_IRNEN_R_XWAY, -+ .irnen_t = LTQ_SPI_IRNEN_T_XWAY, - }; - - static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { -- .irnen_r = SPI_IRNEN_R_XRX, -- .irnen_t = SPI_IRNEN_T_XRX, -+ .irnen_r = LTQ_SPI_IRNEN_R_XRX, -+ .irnen_t = LTQ_SPI_IRNEN_T_XRX, - }; - - static const struct of_device_id lantiq_ssc_match[] = { -@@ -814,21 +821,21 @@ static int lantiq_ssc_probe(struct platf - return -ENXIO; - } - -- rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME); -+ rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME); - if (rx_irq < 0) { -- dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME); -+ dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME); - return -ENXIO; - } - -- tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME); -+ tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME); - if (tx_irq < 0) { -- dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME); -+ dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME); - return -ENXIO; - } - -- err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME); -+ err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME); - if (err_irq < 0) { -- dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME); -+ dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME); - return -ENXIO; - } - -@@ -849,17 +856,17 @@ static int lantiq_ssc_probe(struct platf - } - - err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, -- 0, SPI_RX_IRQ_NAME, spi); -+ 0, LTQ_SPI_RX_IRQ_NAME, spi); - if (err) - goto err_master_put; - - err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, -- 0, SPI_TX_IRQ_NAME, spi); -+ 0, LTQ_SPI_TX_IRQ_NAME, spi); - if (err) - goto err_master_put; - - err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, -- 0, SPI_ERR_IRQ_NAME, spi); -+ 0, LTQ_SPI_ERR_IRQ_NAME, spi); - if (err) - goto err_master_put; - -@@ -916,11 +923,11 @@ static int lantiq_ssc_probe(struct platf - } - INIT_WORK(&spi->work, lantiq_ssc_bussy_work); - -- id = lantiq_ssc_readl(spi, SPI_ID); -- spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S; -- spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S; -- supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S; -- revision = id & SPI_ID_REV_M; -+ id = lantiq_ssc_readl(spi, LTQ_SPI_ID); -+ spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S; -+ spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S; -+ supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S; -+ revision = id & LTQ_SPI_ID_REV_M; - - lantiq_ssc_hw_init(spi); - -@@ -952,8 +959,8 @@ static int lantiq_ssc_remove(struct plat - { - struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); - -- lantiq_ssc_writel(spi, 0, SPI_IRNEN); -- lantiq_ssc_writel(spi, 0, SPI_CLC); -+ lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); -+ lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); - rx_fifo_flush(spi); - tx_fifo_flush(spi); - hw_enter_config_mode(spi); diff --git a/target/linux/lantiq/patches-4.9/0101-find_active_root.patch b/target/linux/lantiq/patches-4.9/0101-find_active_root.patch deleted file mode 100644 index 73361c87f..000000000 --- a/target/linux/lantiq/patches-4.9/0101-find_active_root.patch +++ /dev/null @@ -1,93 +0,0 @@ ---- a/drivers/mtd/ofpart.c -+++ b/drivers/mtd/ofpart.c -@@ -25,6 +25,38 @@ static bool node_has_compatible(struct d - return of_get_property(pp, "compatible", NULL); - } - -+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master, -+ loff_t offset) -+{ -+ static uint8_t root_id; -+ int err, len; -+ -+ err = mtd_read(master, offset, 0x01, &len, &root_id); -+ -+ if (mtd_is_bitflip(err) || !err) -+ return &root_id; -+ -+ return NULL; -+} -+ -+static void brnboot_set_active_root_part(struct mtd_partition *pparts, -+ struct device_node **part_nodes, -+ int nr_parts, -+ uint8_t *root_id) -+{ -+ int i; -+ -+ for (i = 0; i < nr_parts; i++) { -+ int part_root_id; -+ -+ if (!of_property_read_u32(part_nodes[i], "brnboot,root-id", &part_root_id) -+ && part_root_id == *root_id) { -+ pparts[i].name = "firmware"; -+ break; -+ } -+ } -+} -+ - static int parse_fixed_partitions(struct mtd_info *master, - const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) -@@ -36,7 +68,8 @@ static int parse_fixed_partitions(struct - struct device_node *pp; - int nr_parts, i, ret = 0; - bool dedicated = true; -- -+ uint8_t *proot_id = NULL; -+ struct device_node **part_nodes; - - /* Pull of_node from the master device node */ - mtd_node = mtd_get_of_node(master); -@@ -72,7 +105,9 @@ static int parse_fixed_partitions(struct - return 0; - - parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); -- if (!parts) -+ part_nodes = kzalloc(nr_parts * sizeof(*part_nodes), GFP_KERNEL); -+ -+ if (!parts || !part_nodes) - return -ENOMEM; - - i = 0; -@@ -121,12 +156,22 @@ static int parse_fixed_partitions(struct - if (of_get_property(pp, "lock", &len)) - parts[i].mask_flags |= MTD_POWERUP_LOCK; - -+ if (!proot_id && of_device_is_compatible(pp, "brnboot,root-selector")) -+ proot_id = brnboot_get_selected_root_part(master, parts[i].offset); -+ -+ part_nodes[i] = pp; -+ - i++; - } - - if (!nr_parts) - goto ofpart_none; - -+ if (proot_id) -+ brnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id); -+ -+ kfree(part_nodes); -+ - *pparts = parts; - return nr_parts; - -@@ -137,6 +182,7 @@ ofpart_fail: - ofpart_none: - of_node_put(pp); - kfree(parts); -+ kfree(part_nodes); - return ret; - } - diff --git a/target/linux/lantiq/patches-4.9/0151-lantiq-ifxmips_pcie-use-of.patch b/target/linux/lantiq/patches-4.9/0151-lantiq-ifxmips_pcie-use-of.patch deleted file mode 100644 index 03d43c241..000000000 --- a/target/linux/lantiq/patches-4.9/0151-lantiq-ifxmips_pcie-use-of.patch +++ /dev/null @@ -1,166 +0,0 @@ ---- a/arch/mips/pci/ifxmips_pcie.c -+++ b/arch/mips/pci/ifxmips_pcie.c -@@ -18,6 +18,9 @@ - #include - #include - -+#include -+#include -+ - #include "ifxmips_pcie.h" - #include "ifxmips_pcie_reg.h" - -@@ -40,6 +43,7 @@ - static DEFINE_SPINLOCK(ifx_pcie_lock); - - u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+static int pcie_reset_gpio; - - static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { - { -@@ -82,6 +86,22 @@ void ifx_pcie_debug(const char *fmt, ... - printk("%s", buf); - } - -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+ gpio_direction_output(pcie_reset_gpio, 1); -+ gpio_set_value(pcie_reset_gpio, 1); -+} -+ -+static inline void pcie_device_rst_assert(int pcie_port) -+{ -+ gpio_set_value(pcie_reset_gpio, 0); -+} -+ -+static inline void pcie_device_rst_deassert(int pcie_port) -+{ -+ mdelay(100); -+ gpio_direction_output(pcie_reset_gpio, 1); -+} - - static inline int pcie_ltssm_enable(int pcie_port) - { -@@ -1045,8 +1065,9 @@ pcie_rc_initialize(int pcie_port) - return 0; - } - --static int __init ifx_pcie_bios_init(void) -+static int ifx_pcie_bios_probe(struct platform_device *pdev) - { -+ struct device_node *node = pdev->dev.of_node; - void __iomem *io_map_base; - int pcie_port; - int startup_port; -@@ -1055,7 +1076,17 @@ static int __init ifx_pcie_bios_init(voi - pcie_ahb_pmu_setup(); - - startup_port = IFX_PCIE_PORT0; -- -+ -+ pcie_reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); -+ if (gpio_is_valid(pcie_reset_gpio)) { -+ int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, "pcie-reset"); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to request gpio %d\n", pcie_reset_gpio); -+ return ret; -+ } -+ gpio_direction_output(pcie_reset_gpio, 1); -+ } -+ - for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ - if (pcie_rc_initialize(pcie_port) == 0) { - IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s: ifx_pcie_cfg_base 0x%p\n", -@@ -1067,6 +1098,7 @@ static int __init ifx_pcie_bios_init(voi - return -ENOMEM; - } - ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node); - - register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); - /* XXX, clear error status */ -@@ -1083,6 +1115,30 @@ static int __init ifx_pcie_bios_init(voi - - return 0; - } -+ -+static const struct of_device_id ifxmips_pcie_match[] = { -+ { .compatible = "lantiq,pcie-xrx200" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match); -+ -+static struct platform_driver ltq_pci_driver = { -+ .probe = ifx_pcie_bios_probe, -+ .driver = { -+ .name = "pcie-xrx200", -+ .owner = THIS_MODULE, -+ .of_match_table = ifxmips_pcie_match, -+ }, -+}; -+ -+int __init ifx_pcie_bios_init(void) -+{ -+ int ret = platform_driver_register(<q_pci_driver); -+ if (ret) -+ pr_info("pcie-xrx200: Error registering platform driver!"); -+ return ret; -+} -+ - arch_initcall(ifx_pcie_bios_init); - - MODULE_LICENSE("GPL"); ---- a/arch/mips/pci/ifxmips_pcie_vr9.h -+++ b/arch/mips/pci/ifxmips_pcie_vr9.h -@@ -22,8 +22,6 @@ - #include - #include - --#define IFX_PCIE_GPIO_RESET 494 -- - #define IFX_REG_R32 ltq_r32 - #define IFX_REG_W32 ltq_w32 - #define CONFIG_IFX_PCIE_HW_SWAP -@@ -53,21 +51,6 @@ - #define OUT ((volatile u32*)(IFX_GPIO + 0x0070)) - - --static inline void pcie_ep_gpio_rst_init(int pcie_port) --{ -- -- gpio_request(IFX_PCIE_GPIO_RESET, "pcie-reset"); -- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); -- gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -- --/* ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); -- ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/ --} -- - static inline void pcie_ahb_pmu_setup(void) - { - /* Enable AHB bus master/slave */ -@@ -180,20 +163,6 @@ static inline void pcie_phy_rst_deassert - IFX_REG_W32(reg, IFX_RCU_RST_REQ); - } - --static inline void pcie_device_rst_assert(int pcie_port) --{ -- gpio_set_value(IFX_PCIE_GPIO_RESET, 0); --// ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); --} -- --static inline void pcie_device_rst_deassert(int pcie_port) --{ -- mdelay(100); -- gpio_direction_output(IFX_PCIE_GPIO_RESET, 1); --// gpio_set_value(IFX_PCIE_GPIO_RESET, 1); -- //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id); --} -- - static inline void pcie_core_pmu_setup(int pcie_port) - { - struct clk *clk; diff --git a/target/linux/lantiq/patches-4.9/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-4.9/0152-lantiq-VPE.patch deleted file mode 100644 index 7b14d9e5a..000000000 --- a/target/linux/lantiq/patches-4.9/0152-lantiq-VPE.patch +++ /dev/null @@ -1,180 +0,0 @@ ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2320,6 +2320,12 @@ config MIPS_VPE_LOADER - Includes a loader for loading an elf relocatable object - onto another VPE and running it. - -+config IFX_VPE_EXT -+ bool "IFX APRP Extensions" -+ depends on MIPS_VPE_LOADER -+ help -+ IFX included extensions in APRP -+ - config MIPS_VPE_LOADER_CMP - bool - default "y" ---- a/arch/mips/include/asm/vpe.h -+++ b/arch/mips/include/asm/vpe.h -@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc); - - int __init vpe_module_init(void); - void __exit vpe_module_exit(void); -+ -+/* For the explanation of the APIs please refer the section "MT APRP Kernel -+ * Programming" in AR9 SW Architecture Specification -+ */ -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags); -+int32_t vpe1_sw_stop(uint32_t flags); -+uint32_t vpe1_get_load_addr(uint32_t flags); -+uint32_t vpe1_get_max_mem(uint32_t flags); -+ - #endif /* _ASM_VPE_H */ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v) - struct vpe_notifications *notifier; - unsigned int vpeflags; - struct tc *t; -+ unsigned long physical_memsize = 0L; - - /* check we are the Master VPE */ - local_irq_save(flags); -@@ -417,6 +418,8 @@ int __init vpe_module_init(void) - } - - v->ntcs = hw_tcs - aprp_cpu_index(); -+ write_tc_c0_tcbind((read_tc_c0_tcbind() & -+ ~TCBIND_CURVPE) | 1); - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); -@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void) - release_vpe(v); - } - } -+ -+#ifdef CONFIG_IFX_VPE_EXT -+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags) -+{ -+ enum vpe_state state; -+ struct vpe *v = get_vpe(tclimit); -+ struct vpe_notifications *not; -+ -+ if (tcmask || flags) { -+ pr_warn("Currently tcmask and flags should be 0. Other values are not supported\n"); -+ return -1; -+ } -+ -+ state = xchg(&v->state, VPE_STATE_INUSE); -+ if (state != VPE_STATE_UNUSED) { -+ vpe_stop(v); -+ -+ list_for_each_entry(not, &v->notify, list) { -+ not->stop(tclimit); -+ } -+ } -+ -+ v->__start = (unsigned long)sw_start_addr; -+ -+ if (!vpe_run(v)) { -+ pr_debug("VPE loader: VPE1 running successfully\n"); -+ return 0; -+ } -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_start); -+ -+int32_t vpe1_sw_stop(uint32_t flags) -+{ -+ struct vpe *v = get_vpe(tclimit); -+ -+ if (!vpe_free(v)) { -+ pr_debug("RP Stopped\n"); -+ return 0; -+ } else -+ return -1; -+} -+EXPORT_SYMBOL(vpe1_sw_stop); -+#endif ---- a/arch/mips/kernel/vpe.c -+++ b/arch/mips/kernel/vpe.c -@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = { - .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) - }; - -+#ifdef CONFIG_IFX_VPE_EXT -+unsigned int vpe1_load_addr; -+ -+static int __init load_address(char *str) -+{ -+ get_option(&str, &vpe1_load_addr); -+ return 1; -+} -+__setup("vpe1_load_addr=", load_address); -+ -+static unsigned int vpe1_mem; -+static int __init vpe1mem(char *str) -+{ -+ vpe1_mem = memparse(str, &str); -+ return 1; -+} -+__setup("vpe1_mem=", vpe1mem); -+ -+uint32_t vpe1_get_load_addr(uint32_t flags) -+{ -+ return vpe1_load_addr; -+} -+EXPORT_SYMBOL(vpe1_get_load_addr); -+ -+uint32_t vpe1_get_max_mem(uint32_t flags) -+{ -+ if (!vpe1_mem) -+ return P_SIZE; -+ else -+ return vpe1_mem; -+} -+EXPORT_SYMBOL(vpe1_get_max_mem); -+ -+#endif -+ - /* get the vpe associated with this minor */ - struct vpe *get_vpe(int minor) - { ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -31,10 +31,14 @@ EXPORT_SYMBOL_GPL(ebu_lock); - */ - static struct ltq_soc_info soc_info; - -+/* for Multithreading (APRP), vpe.c will use it */ -+unsigned long cp0_memsize; -+ - const char *get_system_type(void) - { - return soc_info.sys_type; - } -+EXPORT_SYMBOL(ltq_soc_type); - - int ltq_soc_type(void) - { ---- a/arch/mips/include/asm/mipsmtregs.h -+++ b/arch/mips/include/asm/mipsmtregs.h -@@ -31,6 +31,9 @@ - #define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) - #define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) - -+#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) -+#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) -+ - #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) - #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) - -@@ -376,6 +379,8 @@ do { \ - #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) - #define read_vpe_c0_vpeconf1() mftc0(1, 3) - #define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) -+#define read_vpe_c0_vpeopt() mftc0(1, 7) -+#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) - #define read_vpe_c0_count() mftc0(9, 0) - #define write_vpe_c0_count(val) mttc0(9, 0, val) - #define read_vpe_c0_status() mftc0(12, 0) diff --git a/target/linux/lantiq/patches-4.9/0154-lantiq-pci-bar11mask-fix.patch b/target/linux/lantiq/patches-4.9/0154-lantiq-pci-bar11mask-fix.patch deleted file mode 100644 index d0acd4bb1..000000000 --- a/target/linux/lantiq/patches-4.9/0154-lantiq-pci-bar11mask-fix.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -61,6 +61,8 @@ - #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) - #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) - -+extern u32 max_low_pfn; -+ - __iomem void *ltq_pci_mapped_cfg; - static __iomem void *ltq_pci_membase; - -@@ -86,8 +88,8 @@ static inline u32 ltq_calc_bar11mask(voi - u32 mem, bar11mask; - - /* BAR11MASK value depends on available memory on system. */ -- mem = get_num_physpages() * PAGE_SIZE; -- bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8; -+ mem = max_low_pfn << PAGE_SHIFT; -+ bar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8; - - return bar11mask; - } diff --git a/target/linux/lantiq/patches-4.9/0155-lantiq-VPE-nosmp.patch b/target/linux/lantiq/patches-4.9/0155-lantiq-VPE-nosmp.patch deleted file mode 100644 index 898c2d482..000000000 --- a/target/linux/lantiq/patches-4.9/0155-lantiq-VPE-nosmp.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/mips/kernel/vpe-mt.c -+++ b/arch/mips/kernel/vpe-mt.c -@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v) - * kernels need to turn it on, even if that wasn't the pre-dvpe() state. - */ - #ifdef CONFIG_SMP -- evpe(vpeflags); -+ if (!setup_max_cpus) /* nosmp is set */ -+ evpe(EVPE_ENABLE); -+ else -+ evpe(vpeflags); - #else - evpe(EVPE_ENABLE); - #endif diff --git a/target/linux/lantiq/patches-4.9/0160-owrt-lantiq-multiple-flash.patch b/target/linux/lantiq/patches-4.9/0160-owrt-lantiq-multiple-flash.patch deleted file mode 100644 index fd8b7b892..000000000 --- a/target/linux/lantiq/patches-4.9/0160-owrt-lantiq-multiple-flash.patch +++ /dev/null @@ -1,221 +0,0 @@ ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -38,13 +39,16 @@ enum { - LTQ_NOR_NORMAL - }; - -+#define MAX_RESOURCES 4 -+ - struct ltq_mtd { -- struct resource *res; -- struct mtd_info *mtd; -- struct map_info *map; -+ struct mtd_info *mtd[MAX_RESOURCES]; -+ struct mtd_info *cmtd; -+ struct map_info map[MAX_RESOURCES]; - }; - - static const char ltq_map_name[] = "ltq_nor"; -+static const char * const ltq_probe_types[] = { "cmdlinepart", "ofpart", NULL }; - - static map_word - ltq_read16(struct map_info *map, unsigned long adr) -@@ -108,11 +112,43 @@ ltq_copy_to(struct map_info *map, unsign - } - - static int -+ltq_mtd_remove(struct platform_device *pdev) -+{ -+ struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -+ int i; -+ -+ if (ltq_mtd == NULL) -+ return 0; -+ -+ if (ltq_mtd->cmtd) { -+ mtd_device_unregister(ltq_mtd->cmtd); -+ if (ltq_mtd->cmtd != ltq_mtd->mtd[0]) -+ mtd_concat_destroy(ltq_mtd->cmtd); -+ } -+ -+ for (i = 0; i < MAX_RESOURCES; i++) { -+ if (ltq_mtd->mtd[i] != NULL) -+ map_destroy(ltq_mtd->mtd[i]); -+ } -+ -+ kfree(ltq_mtd); -+ -+ return 0; -+} -+ -+static int - ltq_mtd_probe(struct platform_device *pdev) - { - struct ltq_mtd *ltq_mtd; - struct cfi_private *cfi; -- int err; -+ int err = 0; -+ int i; -+ int devices_found = 0; -+ -+ static const char *rom_probe_types[] = { -+ "cfi_probe", "jedec_probe", NULL -+ }; -+ const char **type; - - if (of_machine_is_compatible("lantiq,falcon") && - (ltq_boot_select() != BS_FLASH)) { -@@ -126,75 +162,89 @@ ltq_mtd_probe(struct platform_device *pd - - platform_set_drvdata(pdev, ltq_mtd); - -- ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- if (!ltq_mtd->res) { -- dev_err(&pdev->dev, "failed to get memory resource\n"); -- return -ENOENT; -+ for (i = 0; i < pdev->num_resources; i++) { -+ printk(KERN_NOTICE "lantiq nor flash device: %.8llx at %.8llx\n", -+ (unsigned long long)resource_size(&pdev->resource[i]), -+ (unsigned long long)pdev->resource[i].start); -+ -+ if (!devm_request_mem_region(&pdev->dev, -+ pdev->resource[i].start, -+ resource_size(&pdev->resource[i]), -+ dev_name(&pdev->dev))) { -+ dev_err(&pdev->dev, "Could not reserve memory region\n"); -+ return -ENOMEM; -+ } -+ -+ ltq_mtd->map[i].name = ltq_map_name; -+ ltq_mtd->map[i].bankwidth = 2; -+ ltq_mtd->map[i].read = ltq_read16; -+ ltq_mtd->map[i].write = ltq_write16; -+ ltq_mtd->map[i].copy_from = ltq_copy_from; -+ ltq_mtd->map[i].copy_to = ltq_copy_to; -+ -+ if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -+ ltq_mtd->map[i].phys = NO_XIP; -+ else -+ ltq_mtd->map[i].phys = pdev->resource[i].start; -+ ltq_mtd->map[i].size = resource_size(&pdev->resource[i]); -+ ltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start, -+ ltq_mtd->map[i].size); -+ if (IS_ERR(ltq_mtd->map[i].virt)) -+ return PTR_ERR(ltq_mtd->map[i].virt); -+ -+ if (ltq_mtd->map[i].virt == NULL) { -+ dev_err(&pdev->dev, "Failed to ioremap flash region\n"); -+ err = PTR_ERR(ltq_mtd->map[i].virt); -+ goto err_out; -+ } -+ -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING; -+ for (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++) -+ ltq_mtd->mtd[i] = do_map_probe(*type, <q_mtd->map[i]); -+ ltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL; -+ -+ if (!ltq_mtd->mtd[i]) { -+ dev_err(&pdev->dev, "probing failed\n"); -+ return -ENXIO; -+ } else { -+ devices_found++; -+ } -+ -+ ltq_mtd->mtd[i]->owner = THIS_MODULE; -+ ltq_mtd->mtd[i]->dev.parent = &pdev->dev; -+ -+ cfi = ltq_mtd->map[i].fldrv_priv; -+ cfi->addr_unlock1 ^= 1; -+ cfi->addr_unlock2 ^= 1; - } - -- ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), -- GFP_KERNEL); -- if (!ltq_mtd->map) -- return -ENOMEM; -+ if (devices_found == 1) { -+ ltq_mtd->cmtd = ltq_mtd->mtd[0]; -+ } else if (devices_found > 1) { -+ /* -+ * We detected multiple devices. Concatenate them together. -+ */ -+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev)); -+ if (ltq_mtd->cmtd == NULL) -+ err = -ENXIO; -+ } - -- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL)) -- ltq_mtd->map->phys = NO_XIP; -- else -- ltq_mtd->map->phys = ltq_mtd->res->start; -- ltq_mtd->res->start; -- ltq_mtd->map->size = resource_size(ltq_mtd->res); -- ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); -- if (IS_ERR(ltq_mtd->map->virt)) -- return PTR_ERR(ltq_mtd->map->virt); -- -- ltq_mtd->map->name = ltq_map_name; -- ltq_mtd->map->bankwidth = 2; -- ltq_mtd->map->read = ltq_read16; -- ltq_mtd->map->write = ltq_write16; -- ltq_mtd->map->copy_from = ltq_copy_from; -- ltq_mtd->map->copy_to = ltq_copy_to; -- -- ltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING; -- ltq_mtd->mtd = do_map_probe("cfi_probe", ltq_mtd->map); -- ltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL; -- -- if (!ltq_mtd->mtd) { -- dev_err(&pdev->dev, "probing failed\n"); -- return -ENXIO; -- } -- -- ltq_mtd->mtd->dev.parent = &pdev->dev; -- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node); -- -- cfi = ltq_mtd->map->fldrv_priv; -- cfi->addr_unlock1 ^= 1; -- cfi->addr_unlock2 ^= 1; -+ ltq_mtd->cmtd->dev.parent = &pdev->dev; -+ mtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node); - -- err = mtd_device_register(ltq_mtd->mtd, NULL, 0); -+ err = mtd_device_register(ltq_mtd->cmtd, NULL, 0); - if (err) { - dev_err(&pdev->dev, "failed to add partitions\n"); -- goto err_destroy; -+ goto err_out; - } - - return 0; - --err_destroy: -- map_destroy(ltq_mtd->mtd); -+err_out: -+ ltq_mtd_remove(pdev); - return err; - } - --static int --ltq_mtd_remove(struct platform_device *pdev) --{ -- struct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev); -- -- if (ltq_mtd && ltq_mtd->mtd) { -- mtd_device_unregister(ltq_mtd->mtd); -- map_destroy(ltq_mtd->mtd); -- } -- return 0; --} -- - static const struct of_device_id ltq_mtd_match[] = { - { .compatible = "lantiq,nor" }, - {}, diff --git a/target/linux/lantiq/patches-4.9/0170-MIPS-lantiq-lock-DMA-register-accesses-for-SMP.patch b/target/linux/lantiq/patches-4.9/0170-MIPS-lantiq-lock-DMA-register-accesses-for-SMP.patch deleted file mode 100644 index 234a2527f..000000000 --- a/target/linux/lantiq/patches-4.9/0170-MIPS-lantiq-lock-DMA-register-accesses-for-SMP.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 58078a30038b578c26c532545448fe3746648390 Mon Sep 17 00:00:00 2001 -From: Hauke Mehrtens -Date: Thu, 29 Dec 2016 21:02:57 +0100 -Subject: [PATCH] MIPS: lantiq: lock DMA register accesses for SMP - -The DMA controller channel and port configuration is changed by -selecting the port or channel in one register and then update the -configuration in other registers. This has to be done in an atomic -operation. Previously only the local interrupts were deactivated which -works for single CPU systems. If the system supports SMP a better -locking is needed, use spinlocks instead. -On more recent SoCs (at least xrx200 and later) there are two memory -regions to change the configuration, there we could use one area for -each CPU and do not have to synchronize between the CPUs and more. - -Signed-off-by: Hauke Mehrtens ---- - arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++++++------------------ - 1 file changed, 20 insertions(+), 18 deletions(-) - ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -59,16 +60,17 @@ - ltq_dma_membase + (z)) - - static void __iomem *ltq_dma_membase; -+static DEFINE_SPINLOCK(ltq_dma_lock); - - void - ltq_dma_enable_irq(struct ltq_dma_channel *ch) - { - unsigned long flags; - -- local_irq_save(flags); -+ spin_lock_irqsave(<q_dma_lock, flags); - ltq_dma_w32(ch->nr, LTQ_DMA_CS); - ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); -- local_irq_restore(flags); -+ spin_unlock_irqrestore(<q_dma_lock, flags); - } - EXPORT_SYMBOL_GPL(ltq_dma_enable_irq); - -@@ -77,10 +79,10 @@ ltq_dma_disable_irq(struct ltq_dma_chann - { - unsigned long flags; - -- local_irq_save(flags); -+ spin_lock_irqsave(<q_dma_lock, flags); - ltq_dma_w32(ch->nr, LTQ_DMA_CS); - ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); -- local_irq_restore(flags); -+ spin_unlock_irqrestore(<q_dma_lock, flags); - } - EXPORT_SYMBOL_GPL(ltq_dma_disable_irq); - -@@ -89,10 +91,10 @@ ltq_dma_ack_irq(struct ltq_dma_channel * - { - unsigned long flags; - -- local_irq_save(flags); -+ spin_lock_irqsave(<q_dma_lock, flags); - ltq_dma_w32(ch->nr, LTQ_DMA_CS); - ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS); -- local_irq_restore(flags); -+ spin_unlock_irqrestore(<q_dma_lock, flags); - } - EXPORT_SYMBOL_GPL(ltq_dma_ack_irq); - -@@ -101,11 +103,11 @@ ltq_dma_open(struct ltq_dma_channel *ch) - { - unsigned long flag; - -- local_irq_save(flag); -+ spin_lock_irqsave(<q_dma_lock, flag); - ltq_dma_w32(ch->nr, LTQ_DMA_CS); - ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL); -- ltq_dma_enable_irq(ch); -- local_irq_restore(flag); -+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); -+ spin_unlock_irqrestore(<q_dma_lock, flag); - } - EXPORT_SYMBOL_GPL(ltq_dma_open); - -@@ -114,11 +116,11 @@ ltq_dma_close(struct ltq_dma_channel *ch - { - unsigned long flag; - -- local_irq_save(flag); -+ spin_lock_irqsave(<q_dma_lock, flag); - ltq_dma_w32(ch->nr, LTQ_DMA_CS); - ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); -- ltq_dma_disable_irq(ch); -- local_irq_restore(flag); -+ ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN); -+ spin_unlock_irqrestore(<q_dma_lock, flag); - } - EXPORT_SYMBOL_GPL(ltq_dma_close); - -@@ -133,7 +135,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch - &ch->phys, GFP_ATOMIC); - memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE); - -- local_irq_save(flags); -+ spin_lock_irqsave(<q_dma_lock, flags); - ltq_dma_w32(ch->nr, LTQ_DMA_CS); - ltq_dma_w32(ch->phys, LTQ_DMA_CDBA); - ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN); -@@ -142,7 +144,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch - ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL); - while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST) - ; -- local_irq_restore(flags); -+ spin_unlock_irqrestore(<q_dma_lock, flags); - } - - void -@@ -152,11 +154,11 @@ ltq_dma_alloc_tx(struct ltq_dma_channel - - ltq_dma_alloc(ch); - -- local_irq_save(flags); -+ spin_lock_irqsave(<q_dma_lock, flags); - ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); - ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); - ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL); -- local_irq_restore(flags); -+ spin_unlock_irqrestore(<q_dma_lock, flags); - } - EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx); - -@@ -167,11 +169,11 @@ ltq_dma_alloc_rx(struct ltq_dma_channel - - ltq_dma_alloc(ch); - -- local_irq_save(flags); -+ spin_lock_irqsave(<q_dma_lock, flags); - ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE); - ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN); - ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL); -- local_irq_restore(flags); -+ spin_unlock_irqrestore(<q_dma_lock, flags); - } - EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx); - diff --git a/target/linux/lantiq/patches-4.9/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch b/target/linux/lantiq/patches-4.9/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch deleted file mode 100644 index d153c521d..000000000 --- a/target/linux/lantiq/patches-4.9/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/mtd/chips/cfi_cmdset_0001.c -+++ b/drivers/mtd/chips/cfi_cmdset_0001.c -@@ -39,7 +39,7 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - /* Intel chips */ - #define I82802AB 0x00ad diff --git a/target/linux/lantiq/patches-4.9/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch b/target/linux/lantiq/patches-4.9/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch deleted file mode 100644 index e42aaf9c0..000000000 --- a/target/linux/lantiq/patches-4.9/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -442,6 +442,20 @@ static void clkdev_add_clkout(void) - } - } - -+static void set_phy_clock_source(struct device_node *np_cgu) -+{ -+ u32 phy_clk_src, ifcc; -+ -+ if (!np_cgu) -+ return; -+ -+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src)) -+ return; -+ -+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c); -+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr); -+} -+ - /* bring up all register ranges that we need for basic system control */ - void __init ltq_soc_init(void) - { -@@ -628,4 +642,6 @@ void __init ltq_soc_init(void) - if (of_machine_is_compatible("lantiq,vr9")) - xbar_fpi_burst_disable(); - usb_set_clock(); -+ -+ set_phy_clock_source(np_cgu); - } diff --git a/target/linux/lantiq/patches-4.9/0302-xrx200-add-sensors-driver.patch b/target/linux/lantiq/patches-4.9/0302-xrx200-add-sensors-driver.patch deleted file mode 100644 index 7e0051e66..000000000 --- a/target/linux/lantiq/patches-4.9/0302-xrx200-add-sensors-driver.patch +++ /dev/null @@ -1,184 +0,0 @@ ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -109,6 +109,7 @@ obj-$(CONFIG_SENSORS_LTC4222) += ltc4222 - obj-$(CONFIG_SENSORS_LTC4245) += ltc4245.o - obj-$(CONFIG_SENSORS_LTC4260) += ltc4260.o - obj-$(CONFIG_SENSORS_LTC4261) += ltc4261.o -+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o - obj-$(CONFIG_SENSORS_MAX1111) += max1111.o - obj-$(CONFIG_SENSORS_MAX16065) += max16065.o - obj-$(CONFIG_SENSORS_MAX1619) += max1619.o ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -780,6 +780,14 @@ config SENSORS_LTC4261 - This driver can also be built as a module. If so, the module will - be called ltc4261. - -+config SENSORS_LTQ_CPUTEMP -+ bool "Lantiq CPU temperature sensor" -+ depends on LANTIQ -+ default n -+ help -+ If you say yes here you get support for the temperature -+ sensor inside your CPU. -+ - config SENSORS_MAX1111 - tristate "Maxim MAX1111 Serial 8-bit ADC chip and compatibles" - depends on SPI_MASTER ---- /dev/null -+++ b/drivers/hwmon/ltq-cputemp.c -@@ -0,0 +1,154 @@ -+/* Lantiq CPU Temperatur sensor driver for xrx200 -+ * -+ * Copyright (C) 2016 Florian Eckert -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version -+ * -+ * This program is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, see -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* gphy1 configuration register contains cpu temperature */ -+#define CGU_GPHY1_CR 0x0040 -+#define CGU_TEMP_PD BIT(19) -+ -+static void ltq_cputemp_enable(void) -+{ -+ ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR); -+ -+ /* wait a short moment to let the SoC get the first temperatur value */ -+ mdelay(100); -+} -+ -+static void ltq_cputemp_disable(void) -+{ -+ ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR); -+} -+ -+static int ltq_cputemp_read(void) -+{ -+ int value; -+ -+ /* get the temperature including one decimal place */ -+ value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF; -+ value = (value << 2 ) + value; -+ -+ /* range -38 to +154 °C, register value zero is -38.0 °C */ -+ value -= 380; -+ -+ return value; -+} -+ -+static ssize_t show_cputemp(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ int value; -+ -+ value = ltq_cputemp_read(); -+ /* scale temp to millidegree */ -+ value = value * 100; -+ -+ return sprintf(buf, "%d\n", value); -+} -+ -+static DEVICE_ATTR(temp1_input, S_IRUGO, show_cputemp, NULL); -+ -+static struct attribute *ltq_cputemp_attrs[] = { -+ &dev_attr_temp1_input.attr, -+ NULL -+}; -+ -+ATTRIBUTE_GROUPS(ltq_cputemp); -+ -+static int ltq_cputemp_probe(struct platform_device *pdev) -+{ -+ int value = 0; -+ int ret; -+ struct device *hwmon_dev; -+ -+ /* available on vr9 v1.2 SoCs only */ -+ if (ltq_soc_type() != SOC_TYPE_VR9_2) -+ return -ENODEV; -+ -+ hwmon_dev = devm_hwmon_device_register_with_groups(&pdev->dev, -+ "CPU0", -+ NULL, -+ ltq_cputemp_groups); -+ -+ if (IS_ERR(hwmon_dev)) { -+ dev_err(&pdev->dev, "Failed to register as hwmon device"); -+ ret = PTR_ERR(hwmon_dev); -+ goto error_hwmon; -+ } -+ -+ ltq_cputemp_enable(); -+ value = ltq_cputemp_read(); -+ dev_info(&pdev->dev, "Current CPU die temperature: %d.%d °C", value / 10, value % 10); -+ -+ return 0; -+ -+error_hwmon: -+ return ret; -+} -+ -+static int ltq_cputemp_release(struct platform_device *pdev) -+{ -+ hwmon_device_unregister(&pdev->dev); -+ ltq_cputemp_disable(); -+ return 0; -+} -+ -+const struct of_device_id ltq_cputemp_match[] = { -+ { .compatible = "lantiq,cputemp" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ltq_cputemp_match); -+ -+static struct platform_driver ltq_cputemp_driver = { -+ .probe = ltq_cputemp_probe, -+ .remove = ltq_cputemp_release, -+ .driver = { -+ .name = "ltq-cputemp", -+ .owner = THIS_MODULE, -+ .of_match_table = ltq_cputemp_match, -+ }, -+}; -+ -+int __init init_ltq_cputemp(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(<q_cputemp_driver); -+ return ret; -+} -+ -+void clean_ltq_cputemp(void) -+{ -+ platform_driver_unregister(<q_cputemp_driver); -+ return; -+} -+ -+module_init(init_ltq_cputemp); -+module_exit(clean_ltq_cputemp); -+ -+MODULE_AUTHOR("Florian Eckert "); -+ -+MODULE_DESCRIPTION("Lantiq Temperature Sensor"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/xrx200/config-4.9 b/target/linux/lantiq/xrx200/config-4.9 deleted file mode 100644 index 73ccaf34a..000000000 --- a/target/linux/lantiq/xrx200/config-4.9 +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_AT803X_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_RMAP=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_HWMON=y -CONFIG_ICPLUS_PHY=y -CONFIG_IFX_VPE_EXT=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -CONFIG_INTEL_XWAY_PHY=y -# CONFIG_ISDN is not set -CONFIG_LANTIQ_XRX200=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MIPS_MT=y -# CONFIG_MIPS_MT_FPAFF is not set -CONFIG_MIPS_MT_SMP=y -CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y -CONFIG_MIPS_VPE_APSP_API=y -CONFIG_MIPS_VPE_APSP_API_MT=y -CONFIG_MIPS_VPE_LOADER=y -CONFIG_MIPS_VPE_LOADER_MT=y -CONFIG_MIPS_VPE_LOADER_TOM=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_NAND_XWAY=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NLS=y -CONFIG_NR_CPUS=2 -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_PADATA=y -CONFIG_PCI=y -CONFIG_PCIE_LANTIQ=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_SENSORS_LTQ_CPUTEMP=y -CONFIG_SMP=y -CONFIG_SMP_UP=y -CONFIG_SWCONFIG_LEDS=y -CONFIG_SYNC_R4K=y -CONFIG_SYS_SUPPORTS_SCHED_SMT=y -CONFIG_SYS_SUPPORTS_SMP=y -CONFIG_TREE_RCU=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -CONFIG_XPS=y -CONFIG_XRX200_PHY_FW=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/xway/config-4.9 b/target/linux/lantiq/xway/config-4.9 deleted file mode 100644 index 79064ccc0..000000000 --- a/target/linux/lantiq/xway/config-4.9 +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_ISDN is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_NAND_XWAY=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_NLS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_PCI=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/lantiq/xway_legacy/config-4.9 b/target/linux/lantiq/xway_legacy/config-4.9 deleted file mode 100644 index c8aa63178..000000000 --- a/target/linux/lantiq/xway_legacy/config-4.9 +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_ADM6996_PHY=y -CONFIG_AR8216_PHY=y -CONFIG_BLK_MQ_PCI=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_FIRMWARE_IN_KERNEL=y -# CONFIG_GPIO_SYSFS is not set -# CONFIG_HW_RANDOM is not set -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_POLLDEV=y -# CONFIG_ISDN is not set -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MTD_PHYSMAP_OF is not set -CONFIG_NLS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_PCI=y -# CONFIG_PCIE_LANTIQ is not set -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_LANTIQ=y -CONFIG_RTL8306_PHY=y -CONFIG_RTL8366S_PHY=y -CONFIG_RTL8367B_PHY=y -CONFIG_RTL8367_PHY=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -# CONFIG_USB_EHCI_HCD is not set -CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y diff --git a/target/linux/mediatek/32/target.mk b/target/linux/mediatek/32/target.mk deleted file mode 100644 index 0a444c275..000000000 --- a/target/linux/mediatek/32/target.mk +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (C) 2009 OpenWrt.org -# - -SUBTARGET:=32 -BOARDNAME:=32bit -CPU_TYPE:=cortex-a7 -CPU_SUBTYPE:=neon-vfpv4 - -define Target/Description - Build firmware images for MediaTek 32bit ARM based boards. -endef - diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index 6b30f3b19..f61230408 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -5,14 +5,12 @@ include $(TOPDIR)/rules.mk ARCH:=arm BOARD:=mediatek BOARDNAME:=MediaTek Ralink ARM -SUBTARGETS:=32 +SUBTARGETS:=mt7622 mt7623 FEATURES:=squashfs nand ramdisk fpu MAINTAINER:=John Crispin KERNEL_PATCHVER:=4.14 -KERNELNAME:=Image dtbs zImage - include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ kmod-mt76 kmod-leds-gpio kmod-gpio-button-hotplug \ diff --git a/target/linux/mediatek/base-files/etc/inittab b/target/linux/mediatek/base-files/etc/inittab index b169c8274..9820e7144 100644 --- a/target/linux/mediatek/base-files/etc/inittab +++ b/target/linux/mediatek/base-files/etc/inittab @@ -1,3 +1,3 @@ ::sysinit:/etc/init.d/rcS S boot ::shutdown:/etc/init.d/rcS K shutdown -ttyS0::askfirst:/usr/libexec/login.sh +::askconsole:/usr/libexec/login.sh diff --git a/target/linux/mediatek/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/base-files/lib/upgrade/platform.sh index 0429ca8b8..646ce0dc5 100755 --- a/target/linux/mediatek/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/base-files/lib/upgrade/platform.sh @@ -1,49 +1,29 @@ -# -# Copyright (C) 2016 OpenWrt.org -# +platform_do_upgrade() { + default_do_upgrade "$ARGV" +} -platform_do_upgrade() { - local tar_file="$1" - local board="$(board_name)" +PART_NAME=firmware - case "$(board_name)" in - mediatek,mt7623-rfb-nand-ephy |\ - mediatek,mt7623-rfb-nand) - nand_do_upgrade $1 - ;; - *) - echo "flashing kernel" - tar xf $tar_file sysupgrade-$board/kernel -O | mtd write - kernel +platform_check_image() { + local board=$(board_name) + local magic="$(get_magic_long "$1")" - echo "flashing rootfs" - tar xf $tar_file sysupgrade-$board/root -O | mtd write - rootfs + [ "$#" -gt 1 ] && return 1 - return 0 - ;; - esac -} + case "$board" in + bananapi,bpi-r2) + [ "$magic" != "27051956" ] && { + echo "Invalid image type." + return 1 + } + return 0 + ;; -platform_check_image() { - local tar_file="$1" - local board=$(board_name) - - case "$board" in - bananapi,bpi-r2 |\ - mediatek,mt7623a-rfb-emmc) - local kernel_length=`(tar xf $tar_file sysupgrade-$board/kernel -O | wc -c) 2> /dev/null` - local rootfs_length=`(tar xf $tar_file sysupgrade-$board/root -O | wc -c) 2> /dev/null` - ;; - - *) + *) echo "Sysupgrade is not supported on your board yet." - return 1 - ;; - esac + return 1 + ;; + esac - [ "$kernel_length" = 0 -o "$rootfs_length" = 0 ] && { - echo "The upgarde image is corrupt." - return 1 - } - - return 0 -} + return 0 +} diff --git a/target/linux/mediatek/image/32.mk b/target/linux/mediatek/image/32.mk deleted file mode 100644 index 7b7e30312..000000000 --- a/target/linux/mediatek/image/32.mk +++ /dev/null @@ -1,32 +0,0 @@ -define Image/BuilduImage - $(CP) $(KDIR)/zImage$(2) $(KDIR)/zImage-$(1)$(2) - cat $(LINUX_DIR)/arch/arm/boot/dts/$1.dtb >> $(KDIR)/zImage-$(1)$(2) - mkimage -A arm -O linux -T kernel -C none -a 0x80008000 -e 0x80008000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' -d $(KDIR)/zImage-$(1)$(2) $(KDIR)/uImage-$(1)$(2) -endef - -define Image/Build/SysupgradeCombined - $(call Image/BuilduImage,$1) -ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),) - $(call Image/BuilduImage,$1,-initramfs) - $(CP) $(KDIR)/uImage-$(1)-initramfs $(BIN_DIR)/$(IMG_PREFIX)-uImage-$(1)-initramfs -endif - mkdir -p "$(KDIR_TMP)/sysupgrade-$(3)/" - echo "BOARD=$(3)" > "$(KDIR_TMP)/sysupgrade-$(3)/CONTROL" - $(CP) "$(KDIR)/root.$(2)" "$(KDIR_TMP)/sysupgrade-$(3)/root" - $(CP) "$(KDIR)/uImage-$(1)" "$(KDIR_TMP)/sysupgrade-$(3)/kernel" - (cd "$(KDIR_TMP)"; $(TAR) cvf \ - "$(BIN_DIR)/$(IMG_PREFIX)-$(3)-sysupgrade.tar" sysupgrade-$(3) \ - $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") \ - ) -endef - -COMPAT_BPI-R2:=bananapi,bpi-r2 -COMPAT_EMMC:=mediatek,mt7623a-rfb-emmc - -define Image/Build/squashfs - $(call prepare_generic_squashfs,$(KDIR)/root.squashfs) - $(CP) $(KDIR)/root.squashfs $(BIN_DIR)/$(IMG_PREFIX)-root.squashfs - - $(call Image/Build/SysupgradeCombined,mt7623n-bananapi-bpi-r2,squashfs,$$(COMPAT_BPI-R2)) - $(call Image/Build/SysupgradeCombined,mt7623a-rfb-emmc,squashfs,$$(COMPAT_EMMC)) -endef diff --git a/target/linux/mediatek/image/Makefile b/target/linux/mediatek/image/Makefile index 6721259b2..6659d446d 100644 --- a/target/linux/mediatek/image/Makefile +++ b/target/linux/mediatek/image/Makefile @@ -1,10 +1,58 @@ +# +# Copyright (C) 2012-2015 OpenWrt.org +# Copyright (C) 2016-2017 LEDE project +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk -include $(SUBTARGET).mk +# for arm +KERNEL_LOADADDR := 0x80008000 + +# for arm64 +ifeq ($(SUBTARGET),mt7622) +KERNEL_LOADADDR = 0x41080000 +endif + +# build dtb +define Build/dtb + $(call Image/BuildDTB,$(DEVICE_DTS_DIR)/$(DEVICE_DTS).dts,$(DEVICE_DTS_DIR)/$(DEVICE_DTS).dtb) + $(CP) $(DEVICE_DTS_DIR)/$(DEVICE_DTS).dtb $(BIN_DIR)/ +endef + +# default all platform image(fit) build +define Device/Default + PROFILES = Default $$(DEVICE_NAME) + KERNEL_NAME := zImage + FILESYSTEMS := squashfs + DEVICE_DTS_DIR := $(DTS_DIR) + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata +ifeq ($(SUBTARGET),mt7623) + KERNEL_NAME := zImage + KERNEL := dtb | kernel-bin | append-dtb | uImage none + KERNEL_INITRAMFS := dtb | kernel-bin | append-dtb | uImage none +endif +ifeq ($(SUBTARGET),mt7622) + KERNEL_NAME := Image + KERNEL = dtb | kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_INITRAMFS = dtb | kernel-bin | lzma | fit lzma $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb +endif +endef + +ifeq ($(SUBTARGET),mt7622) +include mt7622.mk +endif + +ifeq ($(SUBTARGET),mt7623) +include mt7623.mk +endif define Image/Build $(call Image/Build/$(1),$(1)) endef $(eval $(call BuildImage)) + diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk new file mode 100644 index 000000000..86b25ce33 --- /dev/null +++ b/target/linux/mediatek/image/mt7622.mk @@ -0,0 +1,9 @@ +define Device/MTK-RFB1 + DEVICE_TITLE := MTK7622 rfb1 AP + DEVICE_DTS := mt7622-rfb1 + DEVICE_DTS_DIR := $(DTS_DIR)/mediatek + SUPPORTED_DEVICES := mt7622 + DEVICE_PACKAGES := kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-usb3 \ + kmod-ata-core kmod-ata-ahci-mtk +endef +TARGET_DEVICES += MTK-RFB1 diff --git a/target/linux/mediatek/image/mt7623.mk b/target/linux/mediatek/image/mt7623.mk new file mode 100644 index 000000000..ddb4faa48 --- /dev/null +++ b/target/linux/mediatek/image/mt7623.mk @@ -0,0 +1,6 @@ +define Device/7623n-bananapi-bpi-r2 + DEVICE_TITLE := MTK7623n BananaPi R2 + DEVICE_DTS := mt7623n-bananapi-bpi-r2 +endef + +TARGET_DEVICES += 7623n-bananapi-bpi-r2 diff --git a/target/linux/mediatek/modules.mk b/target/linux/mediatek/modules.mk new file mode 100644 index 000000000..7f8c038ca --- /dev/null +++ b/target/linux/mediatek/modules.mk @@ -0,0 +1,51 @@ +define KernelPackage/ata-ahci-mtk + TITLE:=Mediatek AHCI Serial ATA support + KCONFIG:=CONFIG_AHCI_MTK + FILES:= \ + $(LINUX_DIR)/drivers/ata/ahci_mtk.ko \ + $(LINUX_DIR)/drivers/ata/libahci_platform.ko + AUTOLOAD:=$(call AutoLoad,40,libahci libahci_platform ahci_mtk,1) + $(call AddDepends/ata) + DEPENDS+=@TARGET_mediatek_mt7622 +endef + +define KernelPackage/ata-ahci-mtk/description + Mediatek AHCI Serial ATA host controllers +endef + +$(eval $(call KernelPackage,ata-ahci-mtk)) + +define KernelPackage/sdhci-mtk + SUBMENU:=Other modules + TITLE:=Mediatek SDHCI driver + DEPENDS:=@TARGET_mediatek_mt7622 +kmod-sdhci + KCONFIG:=CONFIG_MMC_MTK + FILES:= \ + $(LINUX_DIR)/drivers/mmc/host/mtk-sd.ko + AUTOLOAD:=$(call AutoProbe,mtk-sd,1) +endef + +$(eval $(call KernelPackage,sdhci-mtk)) + +define KernelPackage/crypto-hw-mtk + TITLE:= MediaTek's Crypto Engine module + DEPENDS:=@TARGET_mediatek + KCONFIG:= \ + CONFIG_CRYPTO_HW=y \ + CONFIG_CRYPTO_AES=y \ + CONFIG_CRYPTO_AEAD=y \ + CONFIG_CRYPTO_SHA1=y \ + CONFIG_CRYPTO_SHA256=y \ + CONFIG_CRYPTO_SHA512=y \ + CONFIG_CRYPTO_HMAC=y \ + CONFIG_CRYPTO_DEV_MEDIATEK + FILES:=$(LINUX_DIR)/drivers/crypto/mediatek/mtk-crypto.ko + AUTOLOAD:=$(call AutoLoad,90,mtk-crypto) + $(call AddDepends/crypto) +endef + +define KernelPackage/crypto-hw-mtk/description + MediaTek's EIP97 Cryptographic Engine driver. +endef + +$(eval $(call KernelPackage,crypto-hw-mtk)) diff --git a/target/linux/mediatek/mt7622/config-4.14 b/target/linux/mediatek/mt7622/config-4.14 new file mode 100644 index 000000000..5d43b224f --- /dev/null +++ b/target/linux/mediatek/mt7622/config-4.14 @@ -0,0 +1,461 @@ +CONFIG_64BIT=y +# CONFIG_ACPI is not set +CONFIG_AHCI_MTK=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +CONFIG_ARCH_HAS_KCOV=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARM64=y +# CONFIG_ARM64_16K_PAGES is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_CONT_SHIFT=4 +# CONFIG_ARM64_CRYPTO is not set +CONFIG_ARM64_HW_AFDBM=y +# CONFIG_ARM64_LSE_ATOMICS is not set +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_PTDUMP_CORE is not set +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_UAO=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VHE=y +# CONFIG_ARMV8_DEPRECATED is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_BLK_DEV is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLOCK_COMPAT=y +# CONFIG_BOUNCE is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BT=y +CONFIG_BT_DEBUGFS=y +CONFIG_BT_HCIUART=y +# CONFIG_BT_HCIUART_BCM is not set +# CONFIG_BT_HCIUART_INTEL is not set +# CONFIG_BT_HCIUART_NOKIA is not set +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIVHCI=y +CONFIG_BUILD_BIN2C=y +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLOCK_THERMAL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MT2712=y +# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set +# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set +# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set +# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set +# CONFIG_COMMON_CLK_MT2712_MMSYS is not set +# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set +# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set +# CONFIG_COMMON_CLK_MT6797 is not set +CONFIG_COMMON_CLK_MT7622=y +CONFIG_COMMON_CLK_MT7622_AUDSYS=y +CONFIG_COMMON_CLK_MT7622_ETHSYS=y +CONFIG_COMMON_CLK_MT7622_HIFSYS=y +# CONFIG_COMMON_CLK_MT8173 is not set +CONFIG_COMPAT=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +# CONFIG_CPUFREQ_DT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THERMAL=y +CONFIG_CRC16=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMADEVICES=y +CONFIG_DMATEST=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ENGINE_RAID=y +CONFIG_DMA_OF=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DTC=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_ENABLE_WARN_DEPRECATED is not set +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GLOB=y +CONFIG_GPIOLIB=y +# CONFIG_GRO_CELLS is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_GENERIC_GUP=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HUGETLBFS is not set +# CONFIG_HW_RANDOM_MTK is not set +# CONFIG_I2C_MT65XX is not set +CONFIG_ICPLUS_PHY=y +CONFIG_IIO=y +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IOMMU_HELPER=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JUMP_LABEL=y +CONFIG_LEDS_MT6323=y +CONFIG_LIBFDT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEDIATEK_MT6577_AUXADC=y +CONFIG_MEDIATEK_WATCHDOG=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +CONFIG_MFD_CORE=y +CONFIG_MFD_MT6397=y +CONFIG_MFD_SYSCON=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MMC=y +CONFIG_MMC_MTK=y +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_MT81xx_NOR=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_MTK=y +# CONFIG_MTD_OF_PARTS is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTK_EFUSE is not set +CONFIG_MTK_HSDMA=y +CONFIG_MTK_INFRACFG=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_SCPSYS=y +CONFIG_MTK_THERMAL=y +CONFIG_MTK_TIMER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +# CONFIG_NET_CADENCE is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_VENDOR_MEDIATEK=y +CONFIG_NLS=y +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +# CONFIG_NUMA is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_MDIO=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PCIE_PME=y +CONFIG_PCI_BUS_ADDR_T_64BIT=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PERF_EVENTS=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_MT6397 is not set +CONFIG_PINCTRL_MT7622=y +# CONFIG_PINCTRL_MT8173 is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_OPP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_SUPPLY=y +CONFIG_PRINTK_TIME=y +CONFIG_PWM=y +CONFIG_PWM_MEDIATEK=y +# CONFIG_PWM_MTK_DISP is not set +CONFIG_PWM_SYSFS=y +# CONFIG_RANDOMIZE_BASE is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_SPI=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MT6323=y +CONFIG_REGULATOR_MT6380=y +# CONFIG_REGULATOR_MT6397 is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_MT6397 is not set +CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +# CONFIG_SCHED_INFO is not set +CONFIG_SCHED_MC=y +CONFIG_SCSI=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MT65XX=y +CONFIG_SRCU=y +CONFIG_SWAP=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_EMULATION=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_USB=y +CONFIG_USB_COMMON=y +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_MTU3 is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_VMAP_STACK=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y diff --git a/target/linux/mediatek/32/profiles/default.mk b/target/linux/mediatek/mt7622/profiles/default.mk similarity index 100% rename from target/linux/mediatek/32/profiles/default.mk rename to target/linux/mediatek/mt7622/profiles/default.mk diff --git a/target/linux/mediatek/mt7622/target.mk b/target/linux/mediatek/mt7622/target.mk new file mode 100644 index 000000000..1fc33b8af --- /dev/null +++ b/target/linux/mediatek/mt7622/target.mk @@ -0,0 +1,11 @@ +ARCH:=aarch64 +SUBTARGET:=mt7622 +BOARDNAME:=MT7622 +CPU_TYPE:=cortex-a53 +CPU_SUBTYPE:=neon-vfpv4 + +KERNELNAME:=Image dtbs + +define Target/Description + Build firmware images for MediaTek MT7622 ARM based boards. +endef diff --git a/target/linux/mediatek/config-4.14 b/target/linux/mediatek/mt7623/config-4.14 similarity index 97% rename from target/linux/mediatek/config-4.14 rename to target/linux/mediatek/mt7623/config-4.14 index 88165045c..9f7098941 100644 --- a/target/linux/mediatek/config-4.14 +++ b/target/linux/mediatek/mt7623/config-4.14 @@ -1,4 +1,3 @@ -# CONFIG_AHCI_MTK is not set # CONFIG_AIO is not set CONFIG_ALIGNMENT_TRAP=y CONFIG_ARCH_CLOCKSOURCE_DATA=y @@ -28,7 +27,6 @@ CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -# CONFIG_ARCH_WANTS_THP_SWAP is not set CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_ARM=y @@ -64,7 +62,7 @@ CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FORCE=y +CONFIG_CMDLINE_FROM_BOOTLOADER=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y CONFIG_COMMON_CLK_MT2701=y @@ -74,6 +72,7 @@ CONFIG_COMMON_CLK_MT2701_HIFSYS=y CONFIG_COMMON_CLK_MT2701_IMGSYS=y CONFIG_COMMON_CLK_MT2701_MMSYS=y CONFIG_COMMON_CLK_MT2701_VDECSYS=y +# CONFIG_COMMON_CLK_MT7622 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8173 is not set CONFIG_COMPACTION=y @@ -160,20 +159,15 @@ CONFIG_DEBUG_UNCOMPRESS=y # CONFIG_DEBUG_USER is not set CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y -# CONFIG_DMA_NOOP_OPS is not set CONFIG_DMA_OF=y -# CONFIG_DMA_VIRT_OPS is not set -# CONFIG_DRM_LIB_RANDOM is not set CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_ELF_CORE=y -CONFIG_EXPORTFS=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FREEZER=y -CONFIG_FUTEX_PI=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y @@ -263,7 +257,6 @@ CONFIG_IIO=y # CONFIG_IIO_BUFFER is not set # CONFIG_IIO_TRIGGER is not set CONFIG_INITRAMFS_COMPRESSION="" -# CONFIG_INITRAMFS_FORCE is not set CONFIG_INITRAMFS_ROOT_GID=1000 CONFIG_INITRAMFS_ROOT_UID=1000 CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt" @@ -282,11 +275,11 @@ CONFIG_LIBFDT=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_MT2701=y +# CONFIG_MACH_MT2701 is not set # CONFIG_MACH_MT6589 is not set # CONFIG_MACH_MT6592 is not set CONFIG_MACH_MT7623=y -CONFIG_MACH_MT8127=y +# CONFIG_MACH_MT8127 is not set # CONFIG_MACH_MT8135 is not set CONFIG_MAGIC_SYSRQ=y CONFIG_MDIO_BITBANG=y @@ -317,6 +310,8 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_MTK=y CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_UIMAGE_FW=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_BLOCK=y @@ -324,6 +319,7 @@ CONFIG_MTD_UBI_BLOCK=y # CONFIG_MTD_UBI_GLUEBI is not set CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTK_EFUSE=y +# CONFIG_MTK_HSDMA is not set CONFIG_MTK_INFRACFG=y # CONFIG_MTK_IOMMU is not set # CONFIG_MTK_IOMMU_V1 is not set @@ -383,7 +379,6 @@ CONFIG_PHY_MTK_TPHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MT2701=y CONFIG_PINCTRL_MT6397=y -CONFIG_PINCTRL_MT8127=y CONFIG_PINCTRL_MTK=y CONFIG_PM=y CONFIG_PM_CLK=y @@ -428,6 +423,7 @@ CONFIG_RPS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_DRV_CMOS is not set # CONFIG_RTC_DRV_MT6397 is not set +# CONFIG_RTC_DRV_MT7622 is not set CONFIG_RTC_I2C_AND_SPI=y CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y @@ -461,7 +457,6 @@ CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_OF=y -CONFIG_THIN_ARCHIVES=y # CONFIG_THUMB2_KERNEL is not set CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y diff --git a/target/linux/mediatek/mt7623/profiles/default.mk b/target/linux/mediatek/mt7623/profiles/default.mk new file mode 100644 index 000000000..2ef570ba6 --- /dev/null +++ b/target/linux/mediatek/mt7623/profiles/default.mk @@ -0,0 +1,15 @@ +# +# Copyright (C) 2015 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# + +define Profile/Default + NAME:=Default Profile (minimum package set) +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef +$(eval $(call Profile,Default)) diff --git a/target/linux/mediatek/mt7623/target.mk b/target/linux/mediatek/mt7623/target.mk new file mode 100644 index 000000000..9f995f995 --- /dev/null +++ b/target/linux/mediatek/mt7623/target.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2009 OpenWrt.org +# + +ARCH:=arm +SUBTARGET:=mt7623 +BOARDNAME:=MT7623 +CPU_TYPE:=cortex-a7 +CPU_SUBTYPE:=neon-vfpv4 + +KERNELNAME:=Image dtbs zImage + +define Target/Description + Build firmware images for MediaTek mt7623 ARM based boards. +endef + diff --git a/target/linux/mediatek/patches-4.14/0045-net-dsa-mediatek-turn-into-platform-driver.patch b/target/linux/mediatek/patches-4.14/0045-net-dsa-mediatek-turn-into-platform-driver.patch index 87e3e8822..55f101577 100644 --- a/target/linux/mediatek/patches-4.14/0045-net-dsa-mediatek-turn-into-platform-driver.patch +++ b/target/linux/mediatek/patches-4.14/0045-net-dsa-mediatek-turn-into-platform-driver.patch @@ -57,9 +57,9 @@ Signed-off-by: John Crispin } static const struct of_device_id mt7530_of_match[] = { -@@ -1135,16 +1142,16 @@ static const struct of_device_id mt7530_ - { /* sentinel */ }, +@@ -1136,16 +1143,16 @@ static const struct of_device_id mt7530_ }; + MODULE_DEVICE_TABLE(of, mt7530_of_match); -static struct mdio_driver mt7530_mdio_driver = { +static struct platform_driver mtk_mt7530_driver = { diff --git a/target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch b/target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch new file mode 100644 index 000000000..123af6011 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0101-reset-mediatek-add-reset-controller-dt-bindings-requ.patch @@ -0,0 +1,114 @@ +From 5d6a82632eb7258c8ca49cc96c18b8b4071b6639 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 20 Sep 2017 17:40:16 +0800 +Subject: [PATCH 101/224] reset: mediatek: add reset controller dt-bindings + required header for MT7622 SoC + +Add the reset controller dt-bindings exported from infracfg, pericfg, +hifsys and ethsys which could be found on MT7622 SoC. So that we can +reference them from within a device-tree file. + +Signed-off-by: Sean Wang +Signed-off-by: Philipp Zabel +--- + include/dt-bindings/reset/mt7622-reset.h | 94 ++++++++++++++++++++++++++++++++ + 1 file changed, 94 insertions(+) + create mode 100644 include/dt-bindings/reset/mt7622-reset.h + +--- /dev/null ++++ b/include/dt-bindings/reset/mt7622-reset.h +@@ -0,0 +1,94 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 ++#define _DT_BINDINGS_RESET_CONTROLLER_MT7622 ++ ++/* INFRACFG resets */ ++#define MT7622_INFRA_EMI_REG_RST 0 ++#define MT7622_INFRA_DRAMC0_A0_RST 1 ++#define MT7622_INFRA_APCIRQ_EINT_RST 3 ++#define MT7622_INFRA_APXGPT_RST 4 ++#define MT7622_INFRA_SCPSYS_RST 5 ++#define MT7622_INFRA_PMIC_WRAP_RST 7 ++#define MT7622_INFRA_IRRX_RST 9 ++#define MT7622_INFRA_EMI_RST 16 ++#define MT7622_INFRA_WED0_RST 17 ++#define MT7622_INFRA_DRAMC_RST 18 ++#define MT7622_INFRA_CCI_INTF_RST 19 ++#define MT7622_INFRA_TRNG_RST 21 ++#define MT7622_INFRA_SYSIRQ_RST 22 ++#define MT7622_INFRA_WED1_RST 25 ++ ++/* PERICFG Subsystem resets */ ++#define MT7622_PERI_UART0_SW_RST 0 ++#define MT7622_PERI_UART1_SW_RST 1 ++#define MT7622_PERI_UART2_SW_RST 2 ++#define MT7622_PERI_UART3_SW_RST 3 ++#define MT7622_PERI_UART4_SW_RST 4 ++#define MT7622_PERI_BTIF_SW_RST 6 ++#define MT7622_PERI_PWM_SW_RST 8 ++#define MT7622_PERI_AUXADC_SW_RST 10 ++#define MT7622_PERI_DMA_SW_RST 11 ++#define MT7622_PERI_IRTX_SW_RST 13 ++#define MT7622_PERI_NFI_SW_RST 14 ++#define MT7622_PERI_THERM_SW_RST 16 ++#define MT7622_PERI_MSDC0_SW_RST 19 ++#define MT7622_PERI_MSDC1_SW_RST 20 ++#define MT7622_PERI_I2C0_SW_RST 22 ++#define MT7622_PERI_I2C1_SW_RST 23 ++#define MT7622_PERI_I2C2_SW_RST 24 ++#define MT7622_PERI_SPI0_SW_RST 33 ++#define MT7622_PERI_SPI1_SW_RST 34 ++#define MT7622_PERI_FLASHIF_SW_RST 36 ++ ++/* TOPRGU resets */ ++#define MT7622_TOPRGU_INFRA_RST 0 ++#define MT7622_TOPRGU_ETHDMA_RST 1 ++#define MT7622_TOPRGU_DDRPHY_RST 6 ++#define MT7622_TOPRGU_INFRA_AO_RST 8 ++#define MT7622_TOPRGU_CONN_RST 9 ++#define MT7622_TOPRGU_APMIXED_RST 10 ++#define MT7622_TOPRGU_CONN_MCU_RST 12 ++ ++/* PCIe/SATA Subsystem resets */ ++#define MT7622_SATA_PHY_REG_RST 12 ++#define MT7622_SATA_PHY_SW_RST 13 ++#define MT7622_SATA_AXI_BUS_RST 15 ++#define MT7622_PCIE1_CORE_RST 19 ++#define MT7622_PCIE1_MMIO_RST 20 ++#define MT7622_PCIE1_HRST 21 ++#define MT7622_PCIE1_USER_RST 22 ++#define MT7622_PCIE1_PIPE_RST 23 ++#define MT7622_PCIE0_CORE_RST 27 ++#define MT7622_PCIE0_MMIO_RST 28 ++#define MT7622_PCIE0_HRST 29 ++#define MT7622_PCIE0_USER_RST 30 ++#define MT7622_PCIE0_PIPE_RST 31 ++ ++/* SSUSB Subsystem resets */ ++#define MT7622_SSUSB_PHY_PWR_RST 3 ++#define MT7622_SSUSB_MAC_PWR_RST 4 ++ ++/* ETHSYS Subsystem resets */ ++#define MT7622_ETHSYS_SYS_RST 0 ++#define MT7622_ETHSYS_MCM_RST 2 ++#define MT7622_ETHSYS_HSDMA_RST 5 ++#define MT7622_ETHSYS_FE_RST 6 ++#define MT7622_ETHSYS_GMAC_RST 23 ++#define MT7622_ETHSYS_EPHY_RST 24 ++#define MT7622_ETHSYS_CRYPTO_RST 29 ++#define MT7622_ETHSYS_PPE_RST 31 ++ ++#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ diff --git a/target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch b/target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch new file mode 100644 index 000000000..a66fa3493 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0102-soc-mediatek-pwrap-fixup-warnings-from-coding-style.patch @@ -0,0 +1,71 @@ +From c7cb4b7e750fc9a23cd80ef34ad4ef8a47f895d5 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 21 Sep 2017 16:26:57 +0800 +Subject: [PATCH 102/224] soc: mediatek: pwrap: fixup warnings from coding + style + +fixup those warnings such as lines over 80 words and parenthesis +alignment which would be complained by checkpatch.pl. + +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 20 +++++++++++++------- + 1 file changed, 13 insertions(+), 7 deletions(-) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -827,7 +827,8 @@ static int pwrap_init_cipher(struct pmic + /* wait for cipher data ready@PMIC */ + ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready); + if (ret) { +- dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n"); ++ dev_err(wrp->dev, ++ "timeout waiting for cipher data ready@PMIC\n"); + return ret; + } + +@@ -1159,23 +1160,27 @@ static int pwrap_probe(struct platform_d + if (IS_ERR(wrp->bridge_base)) + return PTR_ERR(wrp->bridge_base); + +- wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge"); ++ wrp->rstc_bridge = devm_reset_control_get(wrp->dev, ++ "pwrap-bridge"); + if (IS_ERR(wrp->rstc_bridge)) { + ret = PTR_ERR(wrp->rstc_bridge); +- dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret); ++ dev_dbg(wrp->dev, ++ "cannot get pwrap-bridge reset: %d\n", ret); + return ret; + } + } + + wrp->clk_spi = devm_clk_get(wrp->dev, "spi"); + if (IS_ERR(wrp->clk_spi)) { +- dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi)); ++ dev_dbg(wrp->dev, "failed to get clock: %ld\n", ++ PTR_ERR(wrp->clk_spi)); + return PTR_ERR(wrp->clk_spi); + } + + wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap"); + if (IS_ERR(wrp->clk_wrap)) { +- dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap)); ++ dev_dbg(wrp->dev, "failed to get clock: %ld\n", ++ PTR_ERR(wrp->clk_wrap)); + return PTR_ERR(wrp->clk_wrap); + } + +@@ -1220,8 +1225,9 @@ static int pwrap_probe(struct platform_d + pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN); + + irq = platform_get_irq(pdev, 0); +- ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH, +- "mt-pmic-pwrap", wrp); ++ ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, ++ IRQF_TRIGGER_HIGH, ++ "mt-pmic-pwrap", wrp); + if (ret) + goto err_out2; + diff --git a/target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch b/target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch new file mode 100644 index 000000000..4b72094fc --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0104-usb-mtu3-support-option-to-disable-usb3-ports.patch @@ -0,0 +1,108 @@ +From 7a46c3488c48a0fbe313ed25c12af3fb3af48a01 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:38 +0800 +Subject: [PATCH 104/224] usb: mtu3: support option to disable usb3 ports + +Add support to disable specific usb3 ports, it's useful when +usb3 phy is shared with PCIe or SATA, because we should disable +the corresponding usb3 port if the phy is used by PCIe or SATA. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3.h | 3 +++ + drivers/usb/mtu3/mtu3_host.c | 16 +++++++++++++--- + drivers/usb/mtu3/mtu3_plat.c | 8 ++++++-- + 3 files changed, 22 insertions(+), 5 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -210,6 +210,8 @@ struct otg_switch_mtk { + * host only, device only or dual-role mode + * @u2_ports: number of usb2.0 host ports + * @u3_ports: number of usb3.0 host ports ++ * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to ++ * disable u3port0, bit1==1 to disable u3port1,... etc + * @dbgfs_root: only used when supports manual dual-role switch via debugfs + * @wakeup_en: it's true when supports remote wakeup in host mode + * @wk_deb_p0: port0's wakeup debounce clock +@@ -232,6 +234,7 @@ struct ssusb_mtk { + bool is_host; + int u2_ports; + int u3_ports; ++ int u3p_dis_msk; + struct dentry *dbgfs_root; + /* usb wakeup for host mode */ + bool wakeup_en; +--- a/drivers/usb/mtu3/mtu3_host.c ++++ b/drivers/usb/mtu3/mtu3_host.c +@@ -151,6 +151,7 @@ int ssusb_host_enable(struct ssusb_mtk * + void __iomem *ibase = ssusb->ippc_base; + int num_u3p = ssusb->u3_ports; + int num_u2p = ssusb->u2_ports; ++ int u3_ports_disabed; + u32 check_clk; + u32 value; + int i; +@@ -158,8 +159,14 @@ int ssusb_host_enable(struct ssusb_mtk * + /* power on host ip */ + mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN); + +- /* power on and enable all u3 ports */ ++ /* power on and enable u3 ports except skipped ones */ ++ u3_ports_disabed = 0; + for (i = 0; i < num_u3p; i++) { ++ if ((0x1 << i) & ssusb->u3p_dis_msk) { ++ u3_ports_disabed++; ++ continue; ++ } ++ + value = mtu3_readl(ibase, SSUSB_U3_CTRL(i)); + value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS); + value |= SSUSB_U3_PORT_HOST_SEL; +@@ -175,7 +182,7 @@ int ssusb_host_enable(struct ssusb_mtk * + } + + check_clk = SSUSB_XHCI_RST_B_STS; +- if (num_u3p) ++ if (num_u3p > u3_ports_disabed) + check_clk = SSUSB_U3_MAC_RST_B_STS; + + return ssusb_check_clocks(ssusb, check_clk); +@@ -190,8 +197,11 @@ int ssusb_host_disable(struct ssusb_mtk + int ret; + int i; + +- /* power down and disable all u3 ports */ ++ /* power down and disable u3 ports except skipped ones */ + for (i = 0; i < num_u3p; i++) { ++ if ((0x1 << i) & ssusb->u3p_dis_msk) ++ continue; ++ + value = mtu3_readl(ibase, SSUSB_U3_CTRL(i)); + value |= SSUSB_U3_PORT_PDN; + value |= suspend ? 0 : SSUSB_U3_PORT_DIS; +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -276,6 +276,10 @@ static int get_ssusb_rscs(struct platfor + if (ret) + return ret; + ++ /* optional property, ignore the error if it does not exist */ ++ of_property_read_u32(node, "mediatek,u3p-dis-msk", ++ &ssusb->u3p_dis_msk); ++ + if (ssusb->dr_mode != USB_DR_MODE_OTG) + return 0; + +@@ -304,8 +308,8 @@ static int get_ssusb_rscs(struct platfor + } + } + +- dev_info(dev, "dr_mode: %d, is_u3_dr: %d\n", +- ssusb->dr_mode, otg_sx->is_u3_drd); ++ dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n", ++ ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk); + + return 0; + } diff --git a/target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch b/target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch new file mode 100644 index 000000000..aaefc0e6e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0105-usb-mtu3-remove-dummy-wakeup-debounce-clocks.patch @@ -0,0 +1,119 @@ +From 50005796f146351dc9c34bbf8898b305c562e964 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:39 +0800 +Subject: [PATCH 105/224] usb: mtu3: remove dummy wakeup debounce clocks + +The wakeup debounce clocks for each ports in fact are not +needed, so remove them. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3.h | 4 ---- + drivers/usb/mtu3/mtu3_host.c | 57 ++++---------------------------------------- + 2 files changed, 4 insertions(+), 57 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -214,8 +214,6 @@ struct otg_switch_mtk { + * disable u3port0, bit1==1 to disable u3port1,... etc + * @dbgfs_root: only used when supports manual dual-role switch via debugfs + * @wakeup_en: it's true when supports remote wakeup in host mode +- * @wk_deb_p0: port0's wakeup debounce clock +- * @wk_deb_p1: it's optional, and depends on port1 is supported or not + */ + struct ssusb_mtk { + struct device *dev; +@@ -238,8 +236,6 @@ struct ssusb_mtk { + struct dentry *dbgfs_root; + /* usb wakeup for host mode */ + bool wakeup_en; +- struct clk *wk_deb_p0; +- struct clk *wk_deb_p1; + struct regmap *pericfg; + }; + +--- a/drivers/usb/mtu3/mtu3_host.c ++++ b/drivers/usb/mtu3/mtu3_host.c +@@ -79,20 +79,6 @@ int ssusb_wakeup_of_property_parse(struc + if (!ssusb->wakeup_en) + return 0; + +- ssusb->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0"); +- if (IS_ERR(ssusb->wk_deb_p0)) { +- dev_err(dev, "fail to get wakeup_deb_p0\n"); +- return PTR_ERR(ssusb->wk_deb_p0); +- } +- +- if (of_property_read_bool(dn, "wakeup_deb_p1")) { +- ssusb->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1"); +- if (IS_ERR(ssusb->wk_deb_p1)) { +- dev_err(dev, "fail to get wakeup_deb_p1\n"); +- return PTR_ERR(ssusb->wk_deb_p1); +- } +- } +- + ssusb->pericfg = syscon_regmap_lookup_by_phandle(dn, + "mediatek,syscon-wakeup"); + if (IS_ERR(ssusb->pericfg)) { +@@ -103,36 +89,6 @@ int ssusb_wakeup_of_property_parse(struc + return 0; + } + +-static int ssusb_wakeup_clks_enable(struct ssusb_mtk *ssusb) +-{ +- int ret; +- +- ret = clk_prepare_enable(ssusb->wk_deb_p0); +- if (ret) { +- dev_err(ssusb->dev, "failed to enable wk_deb_p0\n"); +- goto usb_p0_err; +- } +- +- ret = clk_prepare_enable(ssusb->wk_deb_p1); +- if (ret) { +- dev_err(ssusb->dev, "failed to enable wk_deb_p1\n"); +- goto usb_p1_err; +- } +- +- return 0; +- +-usb_p1_err: +- clk_disable_unprepare(ssusb->wk_deb_p0); +-usb_p0_err: +- return -EINVAL; +-} +- +-static void ssusb_wakeup_clks_disable(struct ssusb_mtk *ssusb) +-{ +- clk_disable_unprepare(ssusb->wk_deb_p1); +- clk_disable_unprepare(ssusb->wk_deb_p0); +-} +- + static void host_ports_num_get(struct ssusb_mtk *ssusb) + { + u32 xhci_cap; +@@ -286,19 +242,14 @@ void ssusb_host_exit(struct ssusb_mtk *s + + int ssusb_wakeup_enable(struct ssusb_mtk *ssusb) + { +- int ret = 0; +- +- if (ssusb->wakeup_en) { +- ret = ssusb_wakeup_clks_enable(ssusb); ++ if (ssusb->wakeup_en) + ssusb_wakeup_ip_sleep_en(ssusb); +- } +- return ret; ++ ++ return 0; + } + + void ssusb_wakeup_disable(struct ssusb_mtk *ssusb) + { +- if (ssusb->wakeup_en) { ++ if (ssusb->wakeup_en) + ssusb_wakeup_ip_sleep_dis(ssusb); +- ssusb_wakeup_clks_disable(ssusb); +- } + } diff --git a/target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch b/target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch new file mode 100644 index 000000000..9b68caa36 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0106-usb-mtu3-add-optional-mcu-and-dma-bus-clocks.patch @@ -0,0 +1,227 @@ +From 677805f6d83524717b46b3cde74aa455dbf6299f Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:40 +0800 +Subject: [PATCH 106/224] usb: mtu3: add optional mcu and dma bus clocks + +There are mcu_bus and dma_bus clocks needed to be turned on/off by +driver on some SoCs, so add them as optional ones + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3.h | 5 ++ + drivers/usb/mtu3/mtu3_plat.c | 121 +++++++++++++++++++++++++++++-------------- + 2 files changed, 86 insertions(+), 40 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -206,6 +206,9 @@ struct otg_switch_mtk { + * @ippc_base: register base address of IP Power and Clock interface (IPPC) + * @vusb33: usb3.3V shared by device/host IP + * @sys_clk: system clock of mtu3, shared by device/host IP ++ * @ref_clk: reference clock ++ * @mcu_clk: mcu_bus_ck clock for AHB bus etc ++ * @dma_clk: dma_bus_ck clock for AXI bus etc + * @dr_mode: works in which mode: + * host only, device only or dual-role mode + * @u2_ports: number of usb2.0 host ports +@@ -226,6 +229,8 @@ struct ssusb_mtk { + struct regulator *vusb33; + struct clk *sys_clk; + struct clk *ref_clk; ++ struct clk *mcu_clk; ++ struct clk *dma_clk; + /* otg */ + struct otg_switch_mtk otg_switch; + enum usb_dr_mode dr_mode; +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -110,15 +110,9 @@ static void ssusb_phy_power_off(struct s + phy_power_off(ssusb->phys[i]); + } + +-static int ssusb_rscs_init(struct ssusb_mtk *ssusb) ++static int ssusb_clks_enable(struct ssusb_mtk *ssusb) + { +- int ret = 0; +- +- ret = regulator_enable(ssusb->vusb33); +- if (ret) { +- dev_err(ssusb->dev, "failed to enable vusb33\n"); +- goto vusb33_err; +- } ++ int ret; + + ret = clk_prepare_enable(ssusb->sys_clk); + if (ret) { +@@ -132,6 +126,52 @@ static int ssusb_rscs_init(struct ssusb_ + goto ref_clk_err; + } + ++ ret = clk_prepare_enable(ssusb->mcu_clk); ++ if (ret) { ++ dev_err(ssusb->dev, "failed to enable mcu_clk\n"); ++ goto mcu_clk_err; ++ } ++ ++ ret = clk_prepare_enable(ssusb->dma_clk); ++ if (ret) { ++ dev_err(ssusb->dev, "failed to enable dma_clk\n"); ++ goto dma_clk_err; ++ } ++ ++ return 0; ++ ++dma_clk_err: ++ clk_disable_unprepare(ssusb->mcu_clk); ++mcu_clk_err: ++ clk_disable_unprepare(ssusb->ref_clk); ++ref_clk_err: ++ clk_disable_unprepare(ssusb->sys_clk); ++sys_clk_err: ++ return ret; ++} ++ ++static void ssusb_clks_disable(struct ssusb_mtk *ssusb) ++{ ++ clk_disable_unprepare(ssusb->dma_clk); ++ clk_disable_unprepare(ssusb->mcu_clk); ++ clk_disable_unprepare(ssusb->ref_clk); ++ clk_disable_unprepare(ssusb->sys_clk); ++} ++ ++static int ssusb_rscs_init(struct ssusb_mtk *ssusb) ++{ ++ int ret = 0; ++ ++ ret = regulator_enable(ssusb->vusb33); ++ if (ret) { ++ dev_err(ssusb->dev, "failed to enable vusb33\n"); ++ goto vusb33_err; ++ } ++ ++ ret = ssusb_clks_enable(ssusb); ++ if (ret) ++ goto clks_err; ++ + ret = ssusb_phy_init(ssusb); + if (ret) { + dev_err(ssusb->dev, "failed to init phy\n"); +@@ -149,20 +189,16 @@ static int ssusb_rscs_init(struct ssusb_ + phy_err: + ssusb_phy_exit(ssusb); + phy_init_err: +- clk_disable_unprepare(ssusb->ref_clk); +-ref_clk_err: +- clk_disable_unprepare(ssusb->sys_clk); +-sys_clk_err: ++ ssusb_clks_disable(ssusb); ++clks_err: + regulator_disable(ssusb->vusb33); + vusb33_err: +- + return ret; + } + + static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) + { +- clk_disable_unprepare(ssusb->sys_clk); +- clk_disable_unprepare(ssusb->ref_clk); ++ ssusb_clks_disable(ssusb); + regulator_disable(ssusb->vusb33); + ssusb_phy_power_off(ssusb); + ssusb_phy_exit(ssusb); +@@ -203,6 +239,19 @@ static int get_iddig_pinctrl(struct ssus + return 0; + } + ++/* ignore the error if the clock does not exist */ ++static struct clk *get_optional_clk(struct device *dev, const char *id) ++{ ++ struct clk *opt_clk; ++ ++ opt_clk = devm_clk_get(dev, id); ++ /* ignore error number except EPROBE_DEFER */ ++ if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER)) ++ opt_clk = NULL; ++ ++ return opt_clk; ++} ++ + static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb) + { + struct device_node *node = pdev->dev.of_node; +@@ -225,18 +274,17 @@ static int get_ssusb_rscs(struct platfor + return PTR_ERR(ssusb->sys_clk); + } + +- /* +- * reference clock is usually a "fixed-clock", make it optional +- * for backward compatibility and ignore the error if it does +- * not exist. +- */ +- ssusb->ref_clk = devm_clk_get(dev, "ref_ck"); +- if (IS_ERR(ssusb->ref_clk)) { +- if (PTR_ERR(ssusb->ref_clk) == -EPROBE_DEFER) +- return -EPROBE_DEFER; +- +- ssusb->ref_clk = NULL; +- } ++ ssusb->ref_clk = get_optional_clk(dev, "ref_ck"); ++ if (IS_ERR(ssusb->ref_clk)) ++ return PTR_ERR(ssusb->ref_clk); ++ ++ ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck"); ++ if (IS_ERR(ssusb->mcu_clk)) ++ return PTR_ERR(ssusb->mcu_clk); ++ ++ ssusb->dma_clk = get_optional_clk(dev, "dma_ck"); ++ if (IS_ERR(ssusb->dma_clk)) ++ return PTR_ERR(ssusb->dma_clk); + + ssusb->num_phys = of_count_phandle_with_args(node, + "phys", "#phy-cells"); +@@ -451,8 +499,7 @@ static int __maybe_unused mtu3_suspend(s + + ssusb_host_disable(ssusb, true); + ssusb_phy_power_off(ssusb); +- clk_disable_unprepare(ssusb->sys_clk); +- clk_disable_unprepare(ssusb->ref_clk); ++ ssusb_clks_disable(ssusb); + ssusb_wakeup_enable(ssusb); + + return 0; +@@ -470,27 +517,21 @@ static int __maybe_unused mtu3_resume(st + return 0; + + ssusb_wakeup_disable(ssusb); +- ret = clk_prepare_enable(ssusb->sys_clk); +- if (ret) +- goto err_sys_clk; +- +- ret = clk_prepare_enable(ssusb->ref_clk); ++ ret = ssusb_clks_enable(ssusb); + if (ret) +- goto err_ref_clk; ++ goto clks_err; + + ret = ssusb_phy_power_on(ssusb); + if (ret) +- goto err_power_on; ++ goto phy_err; + + ssusb_host_enable(ssusb); + + return 0; + +-err_power_on: +- clk_disable_unprepare(ssusb->ref_clk); +-err_ref_clk: +- clk_disable_unprepare(ssusb->sys_clk); +-err_sys_clk: ++phy_err: ++ ssusb_clks_disable(ssusb); ++clks_err: + return ret; + } + diff --git a/target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch b/target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch new file mode 100644 index 000000000..d2633c1ca --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0107-usb-mtu3-support-36-bit-DMA-address.patch @@ -0,0 +1,362 @@ +From d366bf086a61b7a895d8819a3c1349b9c6b8e40f Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:41 +0800 +Subject: [PATCH 107/224] usb: mtu3: support 36-bit DMA address + +add support for 36-bit DMA address + +[ Felipe Balbi: fix printk format for dma_addr_t ] + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3.h | 17 ++++++- + drivers/usb/mtu3/mtu3_core.c | 34 +++++++++++++- + drivers/usb/mtu3/mtu3_hw_regs.h | 10 ++++ + drivers/usb/mtu3/mtu3_qmu.c | 102 +++++++++++++++++++++++++++++++++------- + 4 files changed, 142 insertions(+), 21 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -46,6 +46,9 @@ struct mtu3_request; + #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10)) + #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10)) + ++#define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4)) ++#define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4)) ++ + #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10)) + #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10)) + #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10)) +@@ -138,23 +141,33 @@ struct mtu3_fifo_info { + * Checksum value is calculated over the 16 bytes of the GPD by default; + * @data_buf_len (RX ONLY): This value indicates the length of + * the assigned data buffer ++ * @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer, ++ * [7:4] are 4 extension bits of @next_gpd + * @next_gpd: Physical address of the next GPD + * @buffer: Physical address of the data buffer + * @buf_len: + * (TX): This value indicates the length of the assigned data buffer + * (RX): The total length of data received + * @ext_len: reserved ++ * @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer, ++ * [7:4] are 4 extension bits of @next_gpd + * @ext_flag: + * bit5 (TX ONLY): Zero Length Packet (ZLP), + */ + struct qmu_gpd { + __u8 flag; + __u8 chksum; +- __le16 data_buf_len; ++ union { ++ __le16 data_buf_len; ++ __le16 tx_ext_addr; ++ }; + __le32 next_gpd; + __le32 buffer; + __le16 buf_len; +- __u8 ext_len; ++ union { ++ __u8 ext_len; ++ __u8 rx_ext_addr; ++ }; + __u8 ext_flag; + } __packed; + +--- a/drivers/usb/mtu3/mtu3_core.c ++++ b/drivers/usb/mtu3/mtu3_core.c +@@ -17,6 +17,7 @@ + * + */ + ++#include + #include + #include + #include +@@ -759,7 +760,31 @@ static void mtu3_hw_exit(struct mtu3 *mt + mtu3_mem_free(mtu); + } + +-/*-------------------------------------------------------------------------*/ ++/** ++ * we set 32-bit DMA mask by default, here check whether the controller ++ * supports 36-bit DMA or not, if it does, set 36-bit DMA mask. ++ */ ++static int mtu3_set_dma_mask(struct mtu3 *mtu) ++{ ++ struct device *dev = mtu->dev; ++ bool is_36bit = false; ++ int ret = 0; ++ u32 value; ++ ++ value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL); ++ if (value & DMA_ADDR_36BIT) { ++ is_36bit = true; ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); ++ /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */ ++ if (ret) { ++ is_36bit = false; ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); ++ } ++ } ++ dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32"); ++ ++ return ret; ++} + + int ssusb_gadget_init(struct ssusb_mtk *ssusb) + { +@@ -820,6 +845,12 @@ int ssusb_gadget_init(struct ssusb_mtk * + return ret; + } + ++ ret = mtu3_set_dma_mask(mtu); ++ if (ret) { ++ dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret); ++ goto dma_mask_err; ++ } ++ + ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu); + if (ret) { + dev_err(dev, "request irq %d failed!\n", mtu->irq); +@@ -845,6 +876,7 @@ int ssusb_gadget_init(struct ssusb_mtk * + gadget_err: + device_init_wakeup(dev, false); + ++dma_mask_err: + irq_err: + mtu3_hw_exit(mtu); + ssusb->u3d = NULL; +--- a/drivers/usb/mtu3/mtu3_hw_regs.h ++++ b/drivers/usb/mtu3/mtu3_hw_regs.h +@@ -58,6 +58,8 @@ + #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404) + #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408) + #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C) ++#define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484) ++#define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4) + + #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510) + #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514) +@@ -189,6 +191,13 @@ + #define QMU_RX_COZ(x) (BIT(16) << (x)) + #define QMU_RX_ZLP(x) (BIT(0) << (x)) + ++/* U3D_TXQHIAR1 */ ++/* U3D_RXQHIAR1 */ ++#define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf) ++#define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf) ++#define QMU_START_ADDR_HI_MSK GENMASK(3, 0) ++#define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0) ++ + /* U3D_TXQCSR1 */ + /* U3D_RXQCSR1 */ + #define QMU_Q_ACTIVE BIT(15) +@@ -225,6 +234,7 @@ + #define CAP_TX_EP_NUM(x) ((x) & 0x1f) + + /* U3D_MISC_CTRL */ ++#define DMA_ADDR_36BIT BIT(31) + #define VBUS_ON BIT(1) + #define VBUS_FRC_EN BIT(0) + +--- a/drivers/usb/mtu3/mtu3_qmu.c ++++ b/drivers/usb/mtu3/mtu3_qmu.c +@@ -40,7 +40,58 @@ + #define GPD_FLAGS_IOC BIT(7) + + #define GPD_EXT_FLAG_ZLP BIT(5) ++#define GPD_EXT_NGP(x) (((x) & 0xf) << 4) ++#define GPD_EXT_BUF(x) (((x) & 0xf) << 0) + ++#define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo)) ++#define HILO_DMA(hi, lo) \ ++ ((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo)))) ++ ++static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum) ++{ ++ u32 txcpr; ++ u32 txhiar; ++ ++ txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum)); ++ txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum)); ++ ++ return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr); ++} ++ ++static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum) ++{ ++ u32 rxcpr; ++ u32 rxhiar; ++ ++ rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum)); ++ rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum)); ++ ++ return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr); ++} ++ ++static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma) ++{ ++ u32 tqhiar; ++ ++ mtu3_writel(mbase, USB_QMU_TQSAR(epnum), ++ cpu_to_le32(lower_32_bits(dma))); ++ tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum)); ++ tqhiar &= ~QMU_START_ADDR_HI_MSK; ++ tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma)); ++ mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar); ++} ++ ++static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma) ++{ ++ u32 rqhiar; ++ ++ mtu3_writel(mbase, USB_QMU_RQSAR(epnum), ++ cpu_to_le32(lower_32_bits(dma))); ++ rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum)); ++ rqhiar &= ~QMU_START_ADDR_HI_MSK; ++ rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma)); ++ mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar); ++} + + static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring, + dma_addr_t dma_addr) +@@ -193,21 +244,27 @@ static int mtu3_prepare_tx_gpd(struct mt + struct mtu3_gpd_ring *ring = &mep->gpd_ring; + struct qmu_gpd *gpd = ring->enqueue; + struct usb_request *req = &mreq->request; ++ dma_addr_t enq_dma; ++ u16 ext_addr; + + /* set all fields to zero as default value */ + memset(gpd, 0, sizeof(*gpd)); + +- gpd->buffer = cpu_to_le32((u32)req->dma); ++ gpd->buffer = cpu_to_le32(lower_32_bits(req->dma)); ++ ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma)); + gpd->buf_len = cpu_to_le16(req->length); + gpd->flag |= GPD_FLAGS_IOC; + + /* get the next GPD */ + enq = advance_enq_gpd(ring); +- dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n", +- mep->epnum, gpd, enq); ++ enq_dma = gpd_virt_to_dma(ring, enq); ++ dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n", ++ mep->epnum, gpd, enq, enq_dma); + + enq->flag &= ~GPD_FLAGS_HWO; +- gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq)); ++ gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma)); ++ ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma)); ++ gpd->tx_ext_addr = cpu_to_le16(ext_addr); + + if (req->zero) + gpd->ext_flag |= GPD_EXT_FLAG_ZLP; +@@ -226,21 +283,27 @@ static int mtu3_prepare_rx_gpd(struct mt + struct mtu3_gpd_ring *ring = &mep->gpd_ring; + struct qmu_gpd *gpd = ring->enqueue; + struct usb_request *req = &mreq->request; ++ dma_addr_t enq_dma; ++ u16 ext_addr; + + /* set all fields to zero as default value */ + memset(gpd, 0, sizeof(*gpd)); + +- gpd->buffer = cpu_to_le32((u32)req->dma); ++ gpd->buffer = cpu_to_le32(lower_32_bits(req->dma)); ++ ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma)); + gpd->data_buf_len = cpu_to_le16(req->length); + gpd->flag |= GPD_FLAGS_IOC; + + /* get the next GPD */ + enq = advance_enq_gpd(ring); +- dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n", +- mep->epnum, gpd, enq); ++ enq_dma = gpd_virt_to_dma(ring, enq); ++ dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n", ++ mep->epnum, gpd, enq, enq_dma); + + enq->flag &= ~GPD_FLAGS_HWO; +- gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq)); ++ gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma)); ++ ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma)); ++ gpd->rx_ext_addr = cpu_to_le16(ext_addr); + gpd->chksum = qmu_calc_checksum((u8 *)gpd); + gpd->flag |= GPD_FLAGS_HWO; + +@@ -267,8 +330,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep) + + if (mep->is_in) { + /* set QMU start address */ +- mtu3_writel(mbase, USB_QMU_TQSAR(mep->epnum), ring->dma); +- mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN); ++ write_txq_start_addr(mbase, epnum, ring->dma); ++ mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN); + mtu3_setbits(mbase, U3D_QCR0, QMU_TX_CS_EN(epnum)); + /* send zero length packet according to ZLP flag in GPD */ + mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum)); +@@ -282,8 +345,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep) + mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START); + + } else { +- mtu3_writel(mbase, USB_QMU_RQSAR(mep->epnum), ring->dma); +- mtu3_setbits(mbase, MU3D_EP_RXCR0(mep->epnum), RX_DMAREQEN); ++ write_rxq_start_addr(mbase, epnum, ring->dma); ++ mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN); + mtu3_setbits(mbase, U3D_QCR0, QMU_RX_CS_EN(epnum)); + /* don't expect ZLP */ + mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum)); +@@ -353,9 +416,9 @@ static void qmu_tx_zlp_error_handler(str + struct mtu3_gpd_ring *ring = &mep->gpd_ring; + void __iomem *mbase = mtu->mac_base; + struct qmu_gpd *gpd_current = NULL; +- dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum)); + struct usb_request *req = NULL; + struct mtu3_request *mreq; ++ dma_addr_t cur_gpd_dma; + u32 txcsr = 0; + int ret; + +@@ -365,7 +428,8 @@ static void qmu_tx_zlp_error_handler(str + else + return; + +- gpd_current = gpd_dma_to_virt(ring, gpd_dma); ++ cur_gpd_dma = read_txq_cur_addr(mbase, epnum); ++ gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); + + if (le16_to_cpu(gpd_current->buf_len) != 0) { + dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum); +@@ -408,12 +472,13 @@ static void qmu_done_tx(struct mtu3 *mtu + void __iomem *mbase = mtu->mac_base; + struct qmu_gpd *gpd = ring->dequeue; + struct qmu_gpd *gpd_current = NULL; +- dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum)); + struct usb_request *request = NULL; + struct mtu3_request *mreq; ++ dma_addr_t cur_gpd_dma; + + /*transfer phy address got from QMU register to virtual address */ +- gpd_current = gpd_dma_to_virt(ring, gpd_dma); ++ cur_gpd_dma = read_txq_cur_addr(mbase, epnum); ++ gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); + + dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n", + __func__, epnum, gpd, gpd_current, ring->enqueue); +@@ -446,11 +511,12 @@ static void qmu_done_rx(struct mtu3 *mtu + void __iomem *mbase = mtu->mac_base; + struct qmu_gpd *gpd = ring->dequeue; + struct qmu_gpd *gpd_current = NULL; +- dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum)); + struct usb_request *req = NULL; + struct mtu3_request *mreq; ++ dma_addr_t cur_gpd_dma; + +- gpd_current = gpd_dma_to_virt(ring, gpd_dma); ++ cur_gpd_dma = read_rxq_cur_addr(mbase, epnum); ++ gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); + + dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n", + __func__, epnum, gpd, gpd_current, ring->enqueue); diff --git a/target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch b/target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch new file mode 100644 index 000000000..6ff80e446 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0108-usb-mtu3-use-FORCE-RG_IDDIG-to-implement-manual-DRD-.patch @@ -0,0 +1,274 @@ +From 6c4995c9a8ba8841ba640201636954c84f494587 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:42 +0800 +Subject: [PATCH 108/224] usb: mtu3: use FORCE/RG_IDDIG to implement manual DRD + switch + +In order to keep manual DRD switch independent on IDDIG interrupt, +make use of FORCE/RG_IDDIG instead of IDDIG EINT interrupt to +implement manual DRD switch function. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3.h | 18 ++++++++---- + drivers/usb/mtu3/mtu3_dr.c | 61 ++++++++++++++++++++++++++++++----------- + drivers/usb/mtu3/mtu3_dr.h | 6 ++++ + drivers/usb/mtu3/mtu3_host.c | 5 ++++ + drivers/usb/mtu3/mtu3_hw_regs.h | 2 ++ + drivers/usb/mtu3/mtu3_plat.c | 38 ++----------------------- + 6 files changed, 74 insertions(+), 56 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -115,6 +115,19 @@ enum mtu3_g_ep0_state { + }; + + /** ++ * MTU3_DR_FORCE_NONE: automatically switch host and periperal mode ++ * by IDPIN signal. ++ * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG ++ * IDPIN signal. ++ * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode. ++ */ ++enum mtu3_dr_force_mode { ++ MTU3_DR_FORCE_NONE = 0, ++ MTU3_DR_FORCE_HOST, ++ MTU3_DR_FORCE_DEVICE, ++}; ++ ++/** + * @base: the base address of fifo + * @limit: the bitmap size in bits + * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT +@@ -196,7 +209,6 @@ struct mtu3_gpd_ring { + * xHCI driver initialization, it's necessary for system bootup + * as device. + * @is_u3_drd: whether port0 supports usb3.0 dual-role device or not +-* @id_*: used to maually switch between host and device modes by idpin + * @manual_drd_enabled: it's true when supports dual-role device by debugfs + * to switch host/device modes depending on user input. + */ +@@ -207,10 +219,6 @@ struct otg_switch_mtk { + struct notifier_block id_nb; + struct delayed_work extcon_reg_dwork; + bool is_u3_drd; +- /* dual-role switch by debugfs */ +- struct pinctrl *id_pinctrl; +- struct pinctrl_state *id_float; +- struct pinctrl_state *id_ground; + bool manual_drd_enabled; + }; + +--- a/drivers/usb/mtu3/mtu3_dr.c ++++ b/drivers/usb/mtu3/mtu3_dr.c +@@ -261,21 +261,22 @@ static void extcon_register_dwork(struct + * depending on user input. + * This is useful in special cases, such as uses TYPE-A receptacle but also + * wants to support dual-role mode. +- * It generates cable state changes by pulling up/down IDPIN and +- * notifies driver to switch mode by "extcon-usb-gpio". +- * NOTE: when use MICRO receptacle, should not enable this interface. + */ + static void ssusb_mode_manual_switch(struct ssusb_mtk *ssusb, int to_host) + { + struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; + +- if (to_host) +- pinctrl_select_state(otg_sx->id_pinctrl, otg_sx->id_ground); +- else +- pinctrl_select_state(otg_sx->id_pinctrl, otg_sx->id_float); ++ if (to_host) { ++ ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST); ++ ssusb_set_mailbox(otg_sx, MTU3_VBUS_OFF); ++ ssusb_set_mailbox(otg_sx, MTU3_ID_GROUND); ++ } else { ++ ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_DEVICE); ++ ssusb_set_mailbox(otg_sx, MTU3_ID_FLOAT); ++ ssusb_set_mailbox(otg_sx, MTU3_VBUS_VALID); ++ } + } + +- + static int ssusb_mode_show(struct seq_file *sf, void *unused) + { + struct ssusb_mtk *ssusb = sf->private; +@@ -388,17 +389,45 @@ static void ssusb_debugfs_exit(struct ss + debugfs_remove_recursive(ssusb->dbgfs_root); + } + ++void ssusb_set_force_mode(struct ssusb_mtk *ssusb, ++ enum mtu3_dr_force_mode mode) ++{ ++ u32 value; ++ ++ value = mtu3_readl(ssusb->ippc_base, SSUSB_U2_CTRL(0)); ++ switch (mode) { ++ case MTU3_DR_FORCE_DEVICE: ++ value |= SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG; ++ break; ++ case MTU3_DR_FORCE_HOST: ++ value |= SSUSB_U2_PORT_FORCE_IDDIG; ++ value &= ~SSUSB_U2_PORT_RG_IDDIG; ++ break; ++ case MTU3_DR_FORCE_NONE: ++ value &= ~(SSUSB_U2_PORT_FORCE_IDDIG | SSUSB_U2_PORT_RG_IDDIG); ++ break; ++ default: ++ return; ++ } ++ mtu3_writel(ssusb->ippc_base, SSUSB_U2_CTRL(0), value); ++} ++ + int ssusb_otg_switch_init(struct ssusb_mtk *ssusb) + { + struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; + +- INIT_DELAYED_WORK(&otg_sx->extcon_reg_dwork, extcon_register_dwork); +- +- if (otg_sx->manual_drd_enabled) ++ if (otg_sx->manual_drd_enabled) { + ssusb_debugfs_init(ssusb); ++ } else { ++ INIT_DELAYED_WORK(&otg_sx->extcon_reg_dwork, ++ extcon_register_dwork); + +- /* It is enough to delay 1s for waiting for host initialization */ +- schedule_delayed_work(&otg_sx->extcon_reg_dwork, HZ); ++ /* ++ * It is enough to delay 1s for waiting for ++ * host initialization ++ */ ++ schedule_delayed_work(&otg_sx->extcon_reg_dwork, HZ); ++ } + + return 0; + } +@@ -407,8 +436,8 @@ void ssusb_otg_switch_exit(struct ssusb_ + { + struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; + +- cancel_delayed_work(&otg_sx->extcon_reg_dwork); +- + if (otg_sx->manual_drd_enabled) + ssusb_debugfs_exit(ssusb); ++ else ++ cancel_delayed_work(&otg_sx->extcon_reg_dwork); + } +--- a/drivers/usb/mtu3/mtu3_dr.h ++++ b/drivers/usb/mtu3/mtu3_dr.h +@@ -87,6 +87,8 @@ static inline void ssusb_gadget_exit(str + int ssusb_otg_switch_init(struct ssusb_mtk *ssusb); + void ssusb_otg_switch_exit(struct ssusb_mtk *ssusb); + int ssusb_set_vbus(struct otg_switch_mtk *otg_sx, int is_on); ++void ssusb_set_force_mode(struct ssusb_mtk *ssusb, ++ enum mtu3_dr_force_mode mode); + + #else + +@@ -103,6 +105,10 @@ static inline int ssusb_set_vbus(struct + return 0; + } + ++static inline void ++ssusb_set_force_mode(struct ssusb_mtk *ssusb, enum mtu3_dr_force_mode mode) ++{} ++ + #endif + + #endif /* _MTU3_DR_H_ */ +--- a/drivers/usb/mtu3/mtu3_host.c ++++ b/drivers/usb/mtu3/mtu3_host.c +@@ -189,6 +189,8 @@ int ssusb_host_disable(struct ssusb_mtk + + static void ssusb_host_setup(struct ssusb_mtk *ssusb) + { ++ struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; ++ + host_ports_num_get(ssusb); + + /* +@@ -197,6 +199,9 @@ static void ssusb_host_setup(struct ssus + */ + ssusb_host_enable(ssusb); + ++ if (otg_sx->manual_drd_enabled) ++ ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST); ++ + /* if port0 supports dual-role, works as host mode by default */ + ssusb_set_vbus(&ssusb->otg_switch, 1); + } +--- a/drivers/usb/mtu3/mtu3_hw_regs.h ++++ b/drivers/usb/mtu3/mtu3_hw_regs.h +@@ -472,6 +472,8 @@ + #define SSUSB_U3_PORT_DIS BIT(0) + + /* U3D_SSUSB_U2_CTRL_0P */ ++#define SSUSB_U2_PORT_RG_IDDIG BIT(12) ++#define SSUSB_U2_PORT_FORCE_IDDIG BIT(11) + #define SSUSB_U2_PORT_VBUSVALID BIT(9) + #define SSUSB_U2_PORT_OTG_SEL BIT(7) + #define SSUSB_U2_PORT_HOST BIT(2) +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -21,7 +21,6 @@ + #include + #include + #include +-#include + #include + + #include "mtu3.h" +@@ -212,33 +211,6 @@ static void ssusb_ip_sw_reset(struct ssu + mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); + } + +-static int get_iddig_pinctrl(struct ssusb_mtk *ssusb) +-{ +- struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; +- +- otg_sx->id_pinctrl = devm_pinctrl_get(ssusb->dev); +- if (IS_ERR(otg_sx->id_pinctrl)) { +- dev_err(ssusb->dev, "Cannot find id pinctrl!\n"); +- return PTR_ERR(otg_sx->id_pinctrl); +- } +- +- otg_sx->id_float = +- pinctrl_lookup_state(otg_sx->id_pinctrl, "id_float"); +- if (IS_ERR(otg_sx->id_float)) { +- dev_err(ssusb->dev, "Cannot find pinctrl id_float!\n"); +- return PTR_ERR(otg_sx->id_float); +- } +- +- otg_sx->id_ground = +- pinctrl_lookup_state(otg_sx->id_pinctrl, "id_ground"); +- if (IS_ERR(otg_sx->id_ground)) { +- dev_err(ssusb->dev, "Cannot find pinctrl id_ground!\n"); +- return PTR_ERR(otg_sx->id_ground); +- } +- +- return 0; +-} +- + /* ignore the error if the clock does not exist */ + static struct clk *get_optional_clk(struct device *dev, const char *id) + { +@@ -349,15 +321,11 @@ static int get_ssusb_rscs(struct platfor + dev_err(ssusb->dev, "couldn't get extcon device\n"); + return -EPROBE_DEFER; + } +- if (otg_sx->manual_drd_enabled) { +- ret = get_iddig_pinctrl(ssusb); +- if (ret) +- return ret; +- } + } + +- dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk:%x\n", +- ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk); ++ dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n", ++ ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk, ++ otg_sx->manual_drd_enabled ? "manual" : "auto"); + + return 0; + } diff --git a/target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch b/target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch new file mode 100644 index 000000000..c17a77be5 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0109-usb-mtu3-add-support-for-usb3.1-IP.patch @@ -0,0 +1,152 @@ +From 8f444887e23b9f0ea31aaae74fbc18171714d8d2 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:43 +0800 +Subject: [PATCH 109/224] usb: mtu3: add support for usb3.1 IP + +Support SuperSpeedPlus for usb3.1 device IP + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3.h | 1 + + drivers/usb/mtu3/mtu3_core.c | 14 +++++++++++--- + drivers/usb/mtu3/mtu3_gadget.c | 3 ++- + drivers/usb/mtu3/mtu3_gadget_ep0.c | 16 ++++++++-------- + drivers/usb/mtu3/mtu3_hw_regs.h | 1 + + 5 files changed, 23 insertions(+), 12 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -94,6 +94,7 @@ enum mtu3_speed { + MTU3_SPEED_FULL = 1, + MTU3_SPEED_HIGH = 3, + MTU3_SPEED_SUPER = 4, ++ MTU3_SPEED_SUPER_PLUS = 5, + }; + + /** +--- a/drivers/usb/mtu3/mtu3_core.c ++++ b/drivers/usb/mtu3/mtu3_core.c +@@ -237,7 +237,7 @@ void mtu3_ep_stall_set(struct mtu3_ep *m + + void mtu3_dev_on_off(struct mtu3 *mtu, int is_on) + { +- if (mtu->is_u3_ip && (mtu->max_speed == USB_SPEED_SUPER)) ++ if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER) + mtu3_ss_func_set(mtu, is_on); + else + mtu3_hs_softconn_set(mtu, is_on); +@@ -547,6 +547,9 @@ static void mtu3_set_speed(struct mtu3 * + mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN); + /* HS/FS detected by HW */ + mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE); ++ } else if (mtu->max_speed == USB_SPEED_SUPER) { ++ mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), ++ SSUSB_U3_PORT_SSP_SPEED); + } + + dev_info(mtu->dev, "max_speed: %s\n", +@@ -624,6 +627,10 @@ static irqreturn_t mtu3_link_isr(struct + udev_speed = USB_SPEED_SUPER; + maxpkt = 512; + break; ++ case MTU3_SPEED_SUPER_PLUS: ++ udev_speed = USB_SPEED_SUPER_PLUS; ++ maxpkt = 512; ++ break; + default: + udev_speed = USB_SPEED_UNKNOWN; + break; +@@ -825,14 +832,15 @@ int ssusb_gadget_init(struct ssusb_mtk * + case USB_SPEED_FULL: + case USB_SPEED_HIGH: + case USB_SPEED_SUPER: ++ case USB_SPEED_SUPER_PLUS: + break; + default: + dev_err(dev, "invalid max_speed: %s\n", + usb_speed_string(mtu->max_speed)); + /* fall through */ + case USB_SPEED_UNKNOWN: +- /* default as SS */ +- mtu->max_speed = USB_SPEED_SUPER; ++ /* default as SSP */ ++ mtu->max_speed = USB_SPEED_SUPER_PLUS; + break; + } + +--- a/drivers/usb/mtu3/mtu3_gadget.c ++++ b/drivers/usb/mtu3/mtu3_gadget.c +@@ -89,6 +89,7 @@ static int mtu3_ep_enable(struct mtu3_ep + + switch (mtu->g.speed) { + case USB_SPEED_SUPER: ++ case USB_SPEED_SUPER_PLUS: + if (usb_endpoint_xfer_int(desc) || + usb_endpoint_xfer_isoc(desc)) { + interval = desc->bInterval; +@@ -456,7 +457,7 @@ static int mtu3_gadget_wakeup(struct usb + return -EOPNOTSUPP; + + spin_lock_irqsave(&mtu->lock, flags); +- if (mtu->g.speed == USB_SPEED_SUPER) { ++ if (mtu->g.speed >= USB_SPEED_SUPER) { + mtu3_setbits(mtu->mac_base, U3D_LINK_POWER_CONTROL, UX_EXIT); + } else { + mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT, RESUME); +--- a/drivers/usb/mtu3/mtu3_gadget_ep0.c ++++ b/drivers/usb/mtu3/mtu3_gadget_ep0.c +@@ -212,8 +212,8 @@ ep0_get_status(struct mtu3 *mtu, const s + case USB_RECIP_DEVICE: + result[0] = mtu->is_self_powered << USB_DEVICE_SELF_POWERED; + result[0] |= mtu->may_wakeup << USB_DEVICE_REMOTE_WAKEUP; +- /* superspeed only */ +- if (mtu->g.speed == USB_SPEED_SUPER) { ++ ++ if (mtu->g.speed >= USB_SPEED_SUPER) { + result[0] |= mtu->u1_enable << USB_DEV_STAT_U1_ENABLED; + result[0] |= mtu->u2_enable << USB_DEV_STAT_U2_ENABLED; + } +@@ -329,8 +329,8 @@ static int ep0_handle_feature_dev(struct + handled = handle_test_mode(mtu, setup); + break; + case USB_DEVICE_U1_ENABLE: +- if (mtu->g.speed != USB_SPEED_SUPER || +- mtu->g.state != USB_STATE_CONFIGURED) ++ if (mtu->g.speed < USB_SPEED_SUPER || ++ mtu->g.state != USB_STATE_CONFIGURED) + break; + + lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL); +@@ -344,8 +344,8 @@ static int ep0_handle_feature_dev(struct + handled = 1; + break; + case USB_DEVICE_U2_ENABLE: +- if (mtu->g.speed != USB_SPEED_SUPER || +- mtu->g.state != USB_STATE_CONFIGURED) ++ if (mtu->g.speed < USB_SPEED_SUPER || ++ mtu->g.state != USB_STATE_CONFIGURED) + break; + + lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL); +@@ -384,8 +384,8 @@ static int ep0_handle_feature(struct mtu + break; + case USB_RECIP_INTERFACE: + /* superspeed only */ +- if ((value == USB_INTRF_FUNC_SUSPEND) +- && (mtu->g.speed == USB_SPEED_SUPER)) { ++ if (value == USB_INTRF_FUNC_SUSPEND && ++ mtu->g.speed >= USB_SPEED_SUPER) { + /* + * forward the request because function drivers + * should handle it +--- a/drivers/usb/mtu3/mtu3_hw_regs.h ++++ b/drivers/usb/mtu3/mtu3_hw_regs.h +@@ -467,6 +467,7 @@ + #define SSUSB_VBUS_CHG_INT_B_EN BIT(6) + + /* U3D_SSUSB_U3_CTRL_0P */ ++#define SSUSB_U3_PORT_SSP_SPEED BIT(9) + #define SSUSB_U3_PORT_HOST_SEL BIT(2) + #define SSUSB_U3_PORT_PDN BIT(1) + #define SSUSB_U3_PORT_DIS BIT(0) diff --git a/target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch b/target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch new file mode 100644 index 000000000..4bd367d80 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0110-usb-mtu3-get-optional-vbus-for-host-only-mode.patch @@ -0,0 +1,40 @@ +From b6712b72d1273e792ee8a533048ba731a3709163 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:44 +0800 +Subject: [PATCH 110/224] usb: mtu3: get optional vbus for host only mode + +When dr_mode is set as USB_DR_MODE_HOST, it's better to try to +get optional vbus, this can increase flexibility, although we +can set vbus as always on for regulator or put it in host driver +to turn it on. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3_plat.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -300,10 +300,6 @@ static int get_ssusb_rscs(struct platfor + of_property_read_u32(node, "mediatek,u3p-dis-msk", + &ssusb->u3p_dis_msk); + +- if (ssusb->dr_mode != USB_DR_MODE_OTG) +- return 0; +- +- /* if dual-role mode is supported */ + vbus = devm_regulator_get(&pdev->dev, "vbus"); + if (IS_ERR(vbus)) { + dev_err(dev, "failed to get vbus\n"); +@@ -311,6 +307,10 @@ static int get_ssusb_rscs(struct platfor + } + otg_sx->vbus = vbus; + ++ if (ssusb->dr_mode == USB_DR_MODE_HOST) ++ return 0; ++ ++ /* if dual-role mode is supported */ + otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd"); + otg_sx->manual_drd_enabled = + of_property_read_bool(node, "enable-manual-drd"); diff --git a/target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch b/target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch new file mode 100644 index 000000000..c7d94aa7f --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0111-usb-mtu3-set-invalid-dr_mode-as-dual-role-mode.patch @@ -0,0 +1,29 @@ +From e315036cdbf8dad7cff4df9dfe8bcff2eddf2277 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:45 +0800 +Subject: [PATCH 111/224] usb: mtu3: set invalid dr_mode as dual-role mode + +Treat dr_mode of USB_DR_MODE_UNKNOWN as USB_DR_MODE_OTG to +enhance functional robustness. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3_plat.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -283,10 +283,8 @@ static int get_ssusb_rscs(struct platfor + return PTR_ERR(ssusb->ippc_base); + + ssusb->dr_mode = usb_get_dr_mode(dev); +- if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) { +- dev_err(dev, "dr_mode is error\n"); +- return -EINVAL; +- } ++ if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) ++ ssusb->dr_mode = USB_DR_MODE_OTG; + + if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) + return 0; diff --git a/target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch b/target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch new file mode 100644 index 000000000..a1be0e20f --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch @@ -0,0 +1,44 @@ +From 36f70702b66cd3453b65d46b5c26ea87d8897363 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:46 +0800 +Subject: [PATCH 112/224] usb: mtu3: set otg_sel for u2port only if works as + dual-role mode + +When set otg_sel(SSUSB_U2_PORT_OTG_SEL) for u2port which supports +dual-role mode, the controller will automatically switch mode +between host and device according to IDDIG signal. But if the +u2port only supports device mode, and no IDDIG pin is provided, +setting otg_sel may cause failure of detection by host. +So set it only for dual-role mode. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + drivers/usb/mtu3/mtu3_core.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +--- a/drivers/usb/mtu3/mtu3_core.c ++++ b/drivers/usb/mtu3/mtu3_core.c +@@ -115,7 +115,9 @@ static int mtu3_device_enable(struct mtu + mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), + (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN | + SSUSB_U2_PORT_HOST_SEL)); +- mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); ++ ++ if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) ++ mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); + + return ssusb_check_clocks(mtu->ssusb, check_clk); + } +@@ -130,7 +132,10 @@ static void mtu3_device_disable(struct m + + mtu3_setbits(ibase, SSUSB_U2_CTRL(0), + SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN); +- mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); ++ ++ if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) ++ mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL); ++ + mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN); + } + diff --git a/target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch b/target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch new file mode 100644 index 000000000..21d65e565 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0113-dt-bindings-usb-mtu3-add-a-optional-property-to-disa.patch @@ -0,0 +1,25 @@ +From 6b6f2c178ee2cd57713993e3cf0afbe4effb2578 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:47 +0800 +Subject: [PATCH 113/224] dt-bindings: usb: mtu3: add a optional property to + disable u3ports + +Add a new optional property to disable u3ports + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +@@ -44,6 +44,8 @@ Optional properties: + - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode + - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup + control register, it depends on "mediatek,enable-wakeup". ++ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, ++ bit1 for u3port1, ... etc; + + Sub-nodes: + The xhci should be added as subnode to mtu3 as shown in the following example diff --git a/target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch b/target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch new file mode 100644 index 000000000..c52de97c1 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0114-dt-bindings-usb-mtu3-remove-dummy-clocks-and-add-opt.patch @@ -0,0 +1,41 @@ +From 2c90367440a0dbf9962e7a7f701b0e7a320d325a Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:48 +0800 +Subject: [PATCH 114/224] dt-bindings: usb: mtu3: remove dummy clocks and add + optional ones + +Remove dummy clocks for usb wakeup and add optional ones for +mcu_bus and dma_bus bus. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +@@ -14,9 +14,9 @@ Required properties: + - vusb33-supply : regulator of USB avdd3.3v + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- - clock-names : must contain "sys_ck" and "ref_ck" for clock of controller; +- "wakeup_deb_p0" and "wakeup_deb_p1" are optional, they are +- depends on "mediatek,enable-wakeup" ++ - clock-names : must contain "sys_ck" for clock of controller, ++ the following clocks are optional: ++ "ref_ck", "mcu_ck" and "dam_ck"; + - phys : a list of phandle + phy specifier pairs + - dr_mode : should be one of "host", "peripheral" or "otg", + refer to usb/generic.txt +@@ -65,9 +65,7 @@ ssusb: usb@11271000 { + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, + <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB1>; +- clock-names = "sys_ck", "ref_ck", +- "wakeup_deb_p0", +- "wakeup_deb_p1"; ++ clock-names = "sys_ck", "ref_ck"; + vusb33-supply = <&mt6397_vusb_reg>; + vbus-supply = <&usb_p0_vbus>; + extcon = <&extcon_usb>; diff --git a/target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch b/target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch new file mode 100644 index 000000000..f1f083ddb --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0115-dt-bindings-usb-mtu3-remove-optional-pinctrls.patch @@ -0,0 +1,30 @@ +From df2f0d10213798a806c90bc06db6bed501e7bf7d Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 17:10:49 +0800 +Subject: [PATCH 115/224] dt-bindings: usb: mtu3: remove optional pinctrls + +Remove optional pinctrls due to using FORCE/RG_IDDIG to implement +manual switch function. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Felipe Balbi +--- + Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +@@ -30,9 +30,10 @@ Optional properties: + when supports dual-role mode. + - vbus-supply : reference to the VBUS regulator, needed when supports + dual-role mode. +- - pinctl-names : a pinctrl state named "default" must be defined, +- "id_float" and "id_ground" are optinal which depends on +- "mediatek,enable-manual-drd" ++ - pinctrl-names : a pinctrl state named "default" is optional, and need be ++ defined if auto drd switch is enabled, that means the property dr_mode ++ is set as "otg", and meanwhile the property "mediatek,enable-manual-drd" ++ is not set. + - pinctrl-0 : pin control group + See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + diff --git a/target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch b/target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch new file mode 100644 index 000000000..919e6af8c --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0116-dt-bindings-arm-mediatek-add-MT7622-string-to-the-PM.patch @@ -0,0 +1,38 @@ +From 1567cde49a0f2304e18c08e2ccd830e0686fc0a7 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 18 Oct 2017 16:28:42 +0800 +Subject: [PATCH 116/224] dt-bindings: arm: mediatek: add MT7622 string to the + PMIC wrapper doc + +Signed-off-by: Chenglin Xu +Signed-off-by: Sean Wang +Acked-by: Rob Herring +Signed-off-by: Matthias Brugger +--- + Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt ++++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +@@ -19,6 +19,7 @@ IP Pairing + Required properties in pwrap device node. + - compatible: + "mediatek,mt2701-pwrap" for MT2701/7623 SoCs ++ "mediatek,mt7622-pwrap" for MT7622 SoCs + "mediatek,mt8135-pwrap" for MT8135 SoCs + "mediatek,mt8173-pwrap" for MT8173 SoCs + - interrupts: IRQ for pwrap in SOC +@@ -36,9 +37,12 @@ Required properties in pwrap device node + - clocks: Must contain an entry for each entry in clock-names. + + Optional properities: +-- pmic: Mediatek PMIC MFD is the child device of pwrap ++- pmic: Using either MediaTek PMIC MFD as the child device of pwrap + See the following for child node definitions: + Documentation/devicetree/bindings/mfd/mt6397.txt ++ or the regulator-only device as the child device of pwrap, such as MT6380. ++ See the following definitions for such kinds of devices. ++ Documentation/devicetree/bindings/regulator/mt6380-regulator.txt + + Example: + pwrap: pwrap@1000f000 { diff --git a/target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch b/target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch new file mode 100644 index 000000000..ce0b0fe47 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0117-soc-mediatek-pwrap-add-pwrap_read32-for-reading-in-3.patch @@ -0,0 +1,134 @@ +From 9c37953bd08daa3ca227098d763e980d1898add3 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 18 Oct 2017 16:28:43 +0800 +Subject: [PATCH 117/224] soc: mediatek: pwrap: add pwrap_read32 for reading in + 32-bit mode + +Some regulators such as MediaTek MT6380 has to be read in 32-bit mode. +So the patch adds pwrap_read32, rename old pwrap_read into pwrap_read16 +and one function pointer is introduced for increasing flexibility allowing +the determination which mode is used by the pwrap slave detection through +device tree. + +Signed-off-by: Chenglin Xu +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 55 +++++++++++++++++++++++++++++++++++- + 1 file changed, 54 insertions(+), 1 deletion(-) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -487,6 +487,7 @@ static int mt8135_regs[] = { + + enum pmic_type { + PMIC_MT6323, ++ PMIC_MT6380, + PMIC_MT6397, + }; + +@@ -496,9 +497,16 @@ enum pwrap_type { + PWRAP_MT8173, + }; + ++struct pmic_wrapper; + struct pwrap_slv_type { + const u32 *dew_regs; + enum pmic_type type; ++ /* ++ * pwrap operations are highly associated with the PMIC types, ++ * so the pointers added increases flexibility allowing determination ++ * which type is used by the detection through device tree. ++ */ ++ int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); + }; + + struct pmic_wrapper { +@@ -609,7 +617,7 @@ static int pwrap_write(struct pmic_wrapp + return 0; + } + +-static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) ++static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) + { + int ret; + +@@ -632,6 +640,39 @@ static int pwrap_read(struct pmic_wrappe + return 0; + } + ++static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) ++{ ++ int ret, msb; ++ ++ *rdata = 0; ++ for (msb = 0; msb < 2; msb++) { ++ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); ++ if (ret) { ++ pwrap_leave_fsm_vldclr(wrp); ++ return ret; ++ } ++ ++ pwrap_writel(wrp, ((msb << 30) | (adr << 16)), ++ PWRAP_WACS2_CMD); ++ ++ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr); ++ if (ret) ++ return ret; ++ ++ *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, ++ PWRAP_WACS2_RDATA)) << (16 * msb)); ++ ++ pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR); ++ } ++ ++ return 0; ++} ++ ++static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) ++{ ++ return wrp->slave->pwrap_read(wrp, adr, rdata); ++} ++ + static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) + { + return pwrap_read(context, adr, rdata); +@@ -752,6 +793,8 @@ static int pwrap_mt2701_init_reg_clock(s + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START); + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END); + break; ++ default: ++ break; + } + + return 0; +@@ -815,6 +858,8 @@ static int pwrap_init_cipher(struct pmic + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN], + 0x1); + break; ++ default: ++ break; + } + + /* wait for cipher data ready@AP */ +@@ -1036,11 +1081,19 @@ static const struct regmap_config pwrap_ + static const struct pwrap_slv_type pmic_mt6323 = { + .dew_regs = mt6323_regs, + .type = PMIC_MT6323, ++ .pwrap_read = pwrap_read16, ++}; ++ ++static const struct pwrap_slv_type pmic_mt6380 = { ++ .dew_regs = NULL, ++ .type = PMIC_MT6380, ++ .pwrap_read = pwrap_read32, + }; + + static const struct pwrap_slv_type pmic_mt6397 = { + .dew_regs = mt6397_regs, + .type = PMIC_MT6397, ++ .pwrap_read = pwrap_read16, + }; + + static const struct of_device_id of_slave_match_tbl[] = { diff --git a/target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch b/target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch new file mode 100644 index 000000000..0fb60f37b --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0118-soc-mediatek-pwrap-add-pwrap_write32-for-writing-in-.patch @@ -0,0 +1,132 @@ +From 635f800995e4ea2a18ce7520d816dab018ce091f Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 18 Oct 2017 16:28:44 +0800 +Subject: [PATCH 118/224] soc: mediatek: pwrap: add pwrap_write32 for writing + in 32-bit mode + +Some regulators such as MediaTek MT6380 also has to be written in +32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write +into pwrap_write16 and one additional function pointer is introduced +for increasing flexibility allowing the determination which mode is +used by the pwrap slave detection through device tree. + +Signed-off-by: Chenglin Xu +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 70 +++++++++++++++++++++++++++--------- + 1 file changed, 54 insertions(+), 16 deletions(-) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -507,6 +507,7 @@ struct pwrap_slv_type { + * which type is used by the detection through device tree. + */ + int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata); ++ int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); + }; + + struct pmic_wrapper { +@@ -601,22 +602,6 @@ static int pwrap_wait_for_state(struct p + } while (1); + } + +-static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) +-{ +- int ret; +- +- ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); +- if (ret) { +- pwrap_leave_fsm_vldclr(wrp); +- return ret; +- } +- +- pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, +- PWRAP_WACS2_CMD); +- +- return 0; +-} +- + static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) + { + int ret; +@@ -673,6 +658,56 @@ static int pwrap_read(struct pmic_wrappe + return wrp->slave->pwrap_read(wrp, adr, rdata); + } + ++static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata) ++{ ++ int ret; ++ ++ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); ++ if (ret) { ++ pwrap_leave_fsm_vldclr(wrp); ++ return ret; ++ } ++ ++ pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata, ++ PWRAP_WACS2_CMD); ++ ++ return 0; ++} ++ ++static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata) ++{ ++ int ret, msb, rdata; ++ ++ for (msb = 0; msb < 2; msb++) { ++ ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); ++ if (ret) { ++ pwrap_leave_fsm_vldclr(wrp); ++ return ret; ++ } ++ ++ pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) | ++ ((wdata >> (msb * 16)) & 0xffff), ++ PWRAP_WACS2_CMD); ++ ++ /* ++ * The pwrap_read operation is the requirement of hardware used ++ * for the synchronization between two successive 16-bit ++ * pwrap_writel operations composing one 32-bit bus writing. ++ * Otherwise, we'll find the result fails on the lower 16-bit ++ * pwrap writing. ++ */ ++ if (!msb) ++ pwrap_read(wrp, adr, &rdata); ++ } ++ ++ return 0; ++} ++ ++static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) ++{ ++ return wrp->slave->pwrap_write(wrp, adr, wdata); ++} ++ + static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata) + { + return pwrap_read(context, adr, rdata); +@@ -1082,18 +1117,21 @@ static const struct pwrap_slv_type pmic_ + .dew_regs = mt6323_regs, + .type = PMIC_MT6323, + .pwrap_read = pwrap_read16, ++ .pwrap_write = pwrap_write16, + }; + + static const struct pwrap_slv_type pmic_mt6380 = { + .dew_regs = NULL, + .type = PMIC_MT6380, + .pwrap_read = pwrap_read32, ++ .pwrap_write = pwrap_write32, + }; + + static const struct pwrap_slv_type pmic_mt6397 = { + .dew_regs = mt6397_regs, + .type = PMIC_MT6397, + .pwrap_read = pwrap_read16, ++ .pwrap_write = pwrap_write16, + }; + + static const struct of_device_id of_slave_match_tbl[] = { diff --git a/target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch b/target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch new file mode 100644 index 000000000..a9f720c90 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0119-soc-mediatek-pwrap-refactor-pwrap_init-for-the-vario.patch @@ -0,0 +1,227 @@ +From 16bebe4ad52083316907fb7149c797cd331f5948 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 18 Oct 2017 16:28:45 +0800 +Subject: [PATCH 119/224] soc: mediatek: pwrap: refactor pwrap_init for the + various PMIC types + +pwrap initialization is highly associated with the base SoC and the +target PMICs, so slight refactorization is made here for allowing +pwrap_init to run on those PMICs with different capability from the +previous MediaTek PMICs and the determination for the enablement of the +pwrap capability depending on PMIC type. Apart from this, the patch +makes the driver more extensible especially when more PMICs join into +the pwrap driver. + +Signed-off-by: Chenglin Xu +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 130 ++++++++++++++++++++++++----------- + 1 file changed, 90 insertions(+), 40 deletions(-) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -70,6 +70,12 @@ + PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ + PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) + ++/* Group of bits used for shown slave capability */ ++#define PWRAP_SLV_CAP_SPI BIT(0) ++#define PWRAP_SLV_CAP_DUALIO BIT(1) ++#define PWRAP_SLV_CAP_SECURITY BIT(2) ++#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x)) ++ + /* defines for slave device wrapper registers */ + enum dew_regs { + PWRAP_DEW_BASE, +@@ -501,6 +507,8 @@ struct pmic_wrapper; + struct pwrap_slv_type { + const u32 *dew_regs; + enum pmic_type type; ++ /* Flags indicating the capability for the target slave */ ++ u32 caps; + /* + * pwrap operations are highly associated with the PMIC types, + * so the pointers added increases flexibility allowing determination +@@ -787,6 +795,37 @@ static int pwrap_init_sidly(struct pmic_ + return 0; + } + ++static int pwrap_init_dual_io(struct pmic_wrapper *wrp) ++{ ++ int ret; ++ u32 rdata; ++ ++ /* Enable dual IO mode */ ++ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); ++ ++ /* Check IDLE & INIT_DONE in advance */ ++ ret = pwrap_wait_for_state(wrp, ++ pwrap_is_fsm_idle_and_sync_idle); ++ if (ret) { ++ dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); ++ return ret; ++ } ++ ++ pwrap_writel(wrp, 1, PWRAP_DIO_EN); ++ ++ /* Read Test */ ++ pwrap_read(wrp, ++ wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); ++ if (rdata != PWRAP_DEW_READ_TEST_VAL) { ++ dev_err(wrp->dev, ++ "Read failed on DIO mode: 0x%04x!=0x%04x\n", ++ PWRAP_DEW_READ_TEST_VAL, rdata); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ + static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp) + { + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); +@@ -935,6 +974,30 @@ static int pwrap_init_cipher(struct pmic + return 0; + } + ++static int pwrap_init_security(struct pmic_wrapper *wrp) ++{ ++ int ret; ++ ++ /* Enable encryption */ ++ ret = pwrap_init_cipher(wrp); ++ if (ret) ++ return ret; ++ ++ /* Signature checking - using CRC */ ++ if (pwrap_write(wrp, ++ wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) ++ return -EFAULT; ++ ++ pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); ++ pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); ++ pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], ++ PWRAP_SIG_ADR); ++ pwrap_writel(wrp, ++ wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); ++ ++ return 0; ++} ++ + static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) + { + /* enable pwrap events and pwrap bridge in AP side */ +@@ -995,7 +1058,6 @@ static int pwrap_mt2701_init_soc_specifi + static int pwrap_init(struct pmic_wrapper *wrp) + { + int ret; +- u32 rdata; + + reset_control_reset(wrp->rstc); + if (wrp->rstc_bridge) +@@ -1007,10 +1069,12 @@ static int pwrap_init(struct pmic_wrappe + pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); + } + +- /* Reset SPI slave */ +- ret = pwrap_reset_spislave(wrp); +- if (ret) +- return ret; ++ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { ++ /* Reset SPI slave */ ++ ret = pwrap_reset_spislave(wrp); ++ if (ret) ++ return ret; ++ } + + pwrap_writel(wrp, 1, PWRAP_WRAP_EN); + +@@ -1022,45 +1086,26 @@ static int pwrap_init(struct pmic_wrappe + if (ret) + return ret; + +- /* Setup serial input delay */ +- ret = pwrap_init_sidly(wrp); +- if (ret) +- return ret; +- +- /* Enable dual IO mode */ +- pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); +- +- /* Check IDLE & INIT_DONE in advance */ +- ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle); +- if (ret) { +- dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret); +- return ret; ++ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) { ++ /* Setup serial input delay */ ++ ret = pwrap_init_sidly(wrp); ++ if (ret) ++ return ret; + } + +- pwrap_writel(wrp, 1, PWRAP_DIO_EN); +- +- /* Read Test */ +- pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); +- if (rdata != PWRAP_DEW_READ_TEST_VAL) { +- dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n", +- PWRAP_DEW_READ_TEST_VAL, rdata); +- return -EFAULT; ++ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) { ++ /* Enable dual I/O mode */ ++ ret = pwrap_init_dual_io(wrp); ++ if (ret) ++ return ret; + } + +- /* Enable encryption */ +- ret = pwrap_init_cipher(wrp); +- if (ret) +- return ret; +- +- /* Signature checking - using CRC */ +- if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) +- return -EFAULT; +- +- pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); +- pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); +- pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], +- PWRAP_SIG_ADR); +- pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); ++ if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) { ++ /* Enable security on bus */ ++ ret = pwrap_init_security(wrp); ++ if (ret) ++ return ret; ++ } + + if (wrp->master->type == PWRAP_MT8135) + pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); +@@ -1116,6 +1161,8 @@ static const struct regmap_config pwrap_ + static const struct pwrap_slv_type pmic_mt6323 = { + .dew_regs = mt6323_regs, + .type = PMIC_MT6323, ++ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | ++ PWRAP_SLV_CAP_SECURITY, + .pwrap_read = pwrap_read16, + .pwrap_write = pwrap_write16, + }; +@@ -1123,6 +1170,7 @@ static const struct pwrap_slv_type pmic_ + static const struct pwrap_slv_type pmic_mt6380 = { + .dew_regs = NULL, + .type = PMIC_MT6380, ++ .caps = 0, + .pwrap_read = pwrap_read32, + .pwrap_write = pwrap_write32, + }; +@@ -1130,6 +1178,8 @@ static const struct pwrap_slv_type pmic_ + static const struct pwrap_slv_type pmic_mt6397 = { + .dew_regs = mt6397_regs, + .type = PMIC_MT6397, ++ .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | ++ PWRAP_SLV_CAP_SECURITY, + .pwrap_read = pwrap_read16, + .pwrap_write = pwrap_write16, + }; diff --git a/target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch b/target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch new file mode 100644 index 000000000..8ace9150a --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0120-soc-mediatek-pwrap-add-MediaTek-MT6380-as-one-slave-.patch @@ -0,0 +1,98 @@ +From 81c54afc5bc918ea3ed65cc356236b302b1f21ca Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 18 Oct 2017 16:28:46 +0800 +Subject: [PATCH 120/224] soc: mediatek: pwrap: add MediaTek MT6380 as one + slave of pwrap + +Add MediaTek MT6380 regulator becoming one of PMIC wrapper slave +and also add extra new regmap_config of 32-bit mode for MT6380 +since old regmap_config of 16-bit mode can't be fit into the need. + +Signed-off-by: Chenglin Xu +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 24 +++++++++++++++++++++--- + 1 file changed, 21 insertions(+), 3 deletions(-) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -507,6 +507,7 @@ struct pmic_wrapper; + struct pwrap_slv_type { + const u32 *dew_regs; + enum pmic_type type; ++ const struct regmap_config *regmap; + /* Flags indicating the capability for the target slave */ + u32 caps; + /* +@@ -1149,7 +1150,7 @@ static irqreturn_t pwrap_interrupt(int i + return IRQ_HANDLED; + } + +-static const struct regmap_config pwrap_regmap_config = { ++static const struct regmap_config pwrap_regmap_config16 = { + .reg_bits = 16, + .val_bits = 16, + .reg_stride = 2, +@@ -1158,9 +1159,19 @@ static const struct regmap_config pwrap_ + .max_register = 0xffff, + }; + ++static const struct regmap_config pwrap_regmap_config32 = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ .reg_read = pwrap_regmap_read, ++ .reg_write = pwrap_regmap_write, ++ .max_register = 0xffff, ++}; ++ + static const struct pwrap_slv_type pmic_mt6323 = { + .dew_regs = mt6323_regs, + .type = PMIC_MT6323, ++ .regmap = &pwrap_regmap_config16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, + .pwrap_read = pwrap_read16, +@@ -1170,6 +1181,7 @@ static const struct pwrap_slv_type pmic_ + static const struct pwrap_slv_type pmic_mt6380 = { + .dew_regs = NULL, + .type = PMIC_MT6380, ++ .regmap = &pwrap_regmap_config32, + .caps = 0, + .pwrap_read = pwrap_read32, + .pwrap_write = pwrap_write32, +@@ -1178,6 +1190,7 @@ static const struct pwrap_slv_type pmic_ + static const struct pwrap_slv_type pmic_mt6397 = { + .dew_regs = mt6397_regs, + .type = PMIC_MT6397, ++ .regmap = &pwrap_regmap_config16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, + .pwrap_read = pwrap_read16, +@@ -1189,9 +1202,14 @@ static const struct of_device_id of_slav + .compatible = "mediatek,mt6323", + .data = &pmic_mt6323, + }, { ++ /* The MT6380 PMIC only implements a regulator, so we bind it ++ * directly instead of using a MFD. ++ */ ++ .compatible = "mediatek,mt6380-regulator", ++ .data = &pmic_mt6380, ++ }, { + .compatible = "mediatek,mt6397", + .data = &pmic_mt6397, +- }, { + /* sentinel */ + } + }; +@@ -1372,7 +1390,7 @@ static int pwrap_probe(struct platform_d + if (ret) + goto err_out2; + +- wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config); ++ wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap); + if (IS_ERR(wrp->regmap)) { + ret = PTR_ERR(wrp->regmap); + goto err_out2; diff --git a/target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch b/target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch new file mode 100644 index 000000000..7b60c68e4 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0121-soc-mediatek-pwrap-add-common-way-for-setup-CS-timin.patch @@ -0,0 +1,121 @@ +From 442c890727e0f585154662b0908fbe3a7986052a Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 18 Oct 2017 16:28:47 +0800 +Subject: [PATCH 121/224] soc: mediatek: pwrap: add common way for setup CS + timing extenstion + +Multiple platforms would always use their own way handling CS timing +extension on the bus which leads to a little bit code duplication. +Therefore, the patch groups the similar logic to handle CS timing +extension into the common function which allows the following SoCs +have more reusability for configing CS timing. + +Signed-off-by: Chenglin Xu +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 59 ++++++++++++++++++++++-------------- + 1 file changed, 37 insertions(+), 22 deletions(-) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -827,23 +827,44 @@ static int pwrap_init_dual_io(struct pmi + return 0; + } + +-static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp) +-{ +- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); +- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE); +- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); +- pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START); +- pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END); +- +- return 0; ++/* ++ * pwrap_init_chip_select_ext is used to configure CS extension time for each ++ * phase during data transactions on the pwrap bus. ++ */ ++static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write, ++ u8 hext_read, u8 lext_start, ++ u8 lext_end) ++{ ++ /* ++ * After finishing a write and read transaction, extends CS high time ++ * to be at least xT of BUS CLK as hext_write and hext_read specifies ++ * respectively. ++ */ ++ pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE); ++ pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ); ++ ++ /* ++ * Extends CS low time after CSL and before CSH command to be at ++ * least xT of BUS CLK as lext_start and lext_end specifies ++ * respectively. ++ */ ++ pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START); ++ pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END); + } + +-static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp) ++static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) + { +- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE); +- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); +- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START); +- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END); ++ switch (wrp->master->type) { ++ case PWRAP_MT8173: ++ pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); ++ break; ++ case PWRAP_MT8135: ++ pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); ++ pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); ++ break; ++ default: ++ break; ++ } + + return 0; + } +@@ -853,20 +874,14 @@ static int pwrap_mt2701_init_reg_clock(s + switch (wrp->slave->type) { + case PMIC_MT6397: + pwrap_writel(wrp, 0xc, PWRAP_RDDMY); +- pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE); +- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ); +- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START); +- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END); ++ pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2); + break; + + case PMIC_MT6323: + pwrap_writel(wrp, 0x8, PWRAP_RDDMY); + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO], + 0x8); +- pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE); +- pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ); +- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START); +- pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END); ++ pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2); + break; + default: + break; +@@ -1235,7 +1250,7 @@ static const struct pmic_wrapper_type pw + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .has_bridge = 1, +- .init_reg_clock = pwrap_mt8135_init_reg_clock, ++ .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt8135_init_soc_specific, + }; + +@@ -1247,7 +1262,7 @@ static const struct pmic_wrapper_type pw + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD, + .has_bridge = 0, +- .init_reg_clock = pwrap_mt8173_init_reg_clock, ++ .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt8173_init_soc_specific, + }; + diff --git a/target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch new file mode 100644 index 000000000..b0ec04afc --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0122-soc-mediatek-pwrap-add-support-for-MT7622-SoC.patch @@ -0,0 +1,237 @@ +From 87996dabef0d83bbd2ed5264b83b01224bc42968 Mon Sep 17 00:00:00 2001 +From: Chenglin Xu +Date: Wed, 18 Oct 2017 16:28:48 +0800 +Subject: [PATCH 122/224] soc: mediatek: pwrap: add support for MT7622 SoC + +Add the registers, callbacks and data structures required to make the +PMIC wrapper work on MT7622. + +Signed-off-by: Chenglin Xu +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/mtk-pmic-wrap.c | 170 +++++++++++++++++++++++++++++++++++ + 1 file changed, 170 insertions(+) + +--- a/drivers/soc/mediatek/mtk-pmic-wrap.c ++++ b/drivers/soc/mediatek/mtk-pmic-wrap.c +@@ -214,6 +214,36 @@ enum pwrap_regs { + PWRAP_ADC_RDATA_ADDR1, + PWRAP_ADC_RDATA_ADDR2, + ++ /* MT7622 only regs */ ++ PWRAP_EINT_STA0_ADR, ++ PWRAP_EINT_STA1_ADR, ++ PWRAP_STA, ++ PWRAP_CLR, ++ PWRAP_DVFS_ADR8, ++ PWRAP_DVFS_WDATA8, ++ PWRAP_DVFS_ADR9, ++ PWRAP_DVFS_WDATA9, ++ PWRAP_DVFS_ADR10, ++ PWRAP_DVFS_WDATA10, ++ PWRAP_DVFS_ADR11, ++ PWRAP_DVFS_WDATA11, ++ PWRAP_DVFS_ADR12, ++ PWRAP_DVFS_WDATA12, ++ PWRAP_DVFS_ADR13, ++ PWRAP_DVFS_WDATA13, ++ PWRAP_DVFS_ADR14, ++ PWRAP_DVFS_WDATA14, ++ PWRAP_DVFS_ADR15, ++ PWRAP_DVFS_WDATA15, ++ PWRAP_EXT_CK, ++ PWRAP_ADC_RDATA_ADDR, ++ PWRAP_GPS_STA, ++ PWRAP_SW_RST, ++ PWRAP_DVFS_STEP_CTRL0, ++ PWRAP_DVFS_STEP_CTRL1, ++ PWRAP_DVFS_STEP_CTRL2, ++ PWRAP_SPI2_CTRL, ++ + /* MT8135 only regs */ + PWRAP_CSHEXT, + PWRAP_EVENT_IN_EN, +@@ -336,6 +366,118 @@ static int mt2701_regs[] = { + [PWRAP_ADC_RDATA_ADDR2] = 0x154, + }; + ++static int mt7622_regs[] = { ++ [PWRAP_MUX_SEL] = 0x0, ++ [PWRAP_WRAP_EN] = 0x4, ++ [PWRAP_DIO_EN] = 0x8, ++ [PWRAP_SIDLY] = 0xC, ++ [PWRAP_RDDMY] = 0x10, ++ [PWRAP_SI_CK_CON] = 0x14, ++ [PWRAP_CSHEXT_WRITE] = 0x18, ++ [PWRAP_CSHEXT_READ] = 0x1C, ++ [PWRAP_CSLEXT_START] = 0x20, ++ [PWRAP_CSLEXT_END] = 0x24, ++ [PWRAP_STAUPD_PRD] = 0x28, ++ [PWRAP_STAUPD_GRPEN] = 0x2C, ++ [PWRAP_EINT_STA0_ADR] = 0x30, ++ [PWRAP_EINT_STA1_ADR] = 0x34, ++ [PWRAP_STA] = 0x38, ++ [PWRAP_CLR] = 0x3C, ++ [PWRAP_STAUPD_MAN_TRIG] = 0x40, ++ [PWRAP_STAUPD_STA] = 0x44, ++ [PWRAP_WRAP_STA] = 0x48, ++ [PWRAP_HARB_INIT] = 0x4C, ++ [PWRAP_HARB_HPRIO] = 0x50, ++ [PWRAP_HIPRIO_ARB_EN] = 0x54, ++ [PWRAP_HARB_STA0] = 0x58, ++ [PWRAP_HARB_STA1] = 0x5C, ++ [PWRAP_MAN_EN] = 0x60, ++ [PWRAP_MAN_CMD] = 0x64, ++ [PWRAP_MAN_RDATA] = 0x68, ++ [PWRAP_MAN_VLDCLR] = 0x6C, ++ [PWRAP_WACS0_EN] = 0x70, ++ [PWRAP_INIT_DONE0] = 0x74, ++ [PWRAP_WACS0_CMD] = 0x78, ++ [PWRAP_WACS0_RDATA] = 0x7C, ++ [PWRAP_WACS0_VLDCLR] = 0x80, ++ [PWRAP_WACS1_EN] = 0x84, ++ [PWRAP_INIT_DONE1] = 0x88, ++ [PWRAP_WACS1_CMD] = 0x8C, ++ [PWRAP_WACS1_RDATA] = 0x90, ++ [PWRAP_WACS1_VLDCLR] = 0x94, ++ [PWRAP_WACS2_EN] = 0x98, ++ [PWRAP_INIT_DONE2] = 0x9C, ++ [PWRAP_WACS2_CMD] = 0xA0, ++ [PWRAP_WACS2_RDATA] = 0xA4, ++ [PWRAP_WACS2_VLDCLR] = 0xA8, ++ [PWRAP_INT_EN] = 0xAC, ++ [PWRAP_INT_FLG_RAW] = 0xB0, ++ [PWRAP_INT_FLG] = 0xB4, ++ [PWRAP_INT_CLR] = 0xB8, ++ [PWRAP_SIG_ADR] = 0xBC, ++ [PWRAP_SIG_MODE] = 0xC0, ++ [PWRAP_SIG_VALUE] = 0xC4, ++ [PWRAP_SIG_ERRVAL] = 0xC8, ++ [PWRAP_CRC_EN] = 0xCC, ++ [PWRAP_TIMER_EN] = 0xD0, ++ [PWRAP_TIMER_STA] = 0xD4, ++ [PWRAP_WDT_UNIT] = 0xD8, ++ [PWRAP_WDT_SRC_EN] = 0xDC, ++ [PWRAP_WDT_FLG] = 0xE0, ++ [PWRAP_DEBUG_INT_SEL] = 0xE4, ++ [PWRAP_DVFS_ADR0] = 0xE8, ++ [PWRAP_DVFS_WDATA0] = 0xEC, ++ [PWRAP_DVFS_ADR1] = 0xF0, ++ [PWRAP_DVFS_WDATA1] = 0xF4, ++ [PWRAP_DVFS_ADR2] = 0xF8, ++ [PWRAP_DVFS_WDATA2] = 0xFC, ++ [PWRAP_DVFS_ADR3] = 0x100, ++ [PWRAP_DVFS_WDATA3] = 0x104, ++ [PWRAP_DVFS_ADR4] = 0x108, ++ [PWRAP_DVFS_WDATA4] = 0x10C, ++ [PWRAP_DVFS_ADR5] = 0x110, ++ [PWRAP_DVFS_WDATA5] = 0x114, ++ [PWRAP_DVFS_ADR6] = 0x118, ++ [PWRAP_DVFS_WDATA6] = 0x11C, ++ [PWRAP_DVFS_ADR7] = 0x120, ++ [PWRAP_DVFS_WDATA7] = 0x124, ++ [PWRAP_DVFS_ADR8] = 0x128, ++ [PWRAP_DVFS_WDATA8] = 0x12C, ++ [PWRAP_DVFS_ADR9] = 0x130, ++ [PWRAP_DVFS_WDATA9] = 0x134, ++ [PWRAP_DVFS_ADR10] = 0x138, ++ [PWRAP_DVFS_WDATA10] = 0x13C, ++ [PWRAP_DVFS_ADR11] = 0x140, ++ [PWRAP_DVFS_WDATA11] = 0x144, ++ [PWRAP_DVFS_ADR12] = 0x148, ++ [PWRAP_DVFS_WDATA12] = 0x14C, ++ [PWRAP_DVFS_ADR13] = 0x150, ++ [PWRAP_DVFS_WDATA13] = 0x154, ++ [PWRAP_DVFS_ADR14] = 0x158, ++ [PWRAP_DVFS_WDATA14] = 0x15C, ++ [PWRAP_DVFS_ADR15] = 0x160, ++ [PWRAP_DVFS_WDATA15] = 0x164, ++ [PWRAP_SPMINF_STA] = 0x168, ++ [PWRAP_CIPHER_KEY_SEL] = 0x16C, ++ [PWRAP_CIPHER_IV_SEL] = 0x170, ++ [PWRAP_CIPHER_EN] = 0x174, ++ [PWRAP_CIPHER_RDY] = 0x178, ++ [PWRAP_CIPHER_MODE] = 0x17C, ++ [PWRAP_CIPHER_SWRST] = 0x180, ++ [PWRAP_DCM_EN] = 0x184, ++ [PWRAP_DCM_DBC_PRD] = 0x188, ++ [PWRAP_EXT_CK] = 0x18C, ++ [PWRAP_ADC_CMD_ADDR] = 0x190, ++ [PWRAP_PWRAP_ADC_CMD] = 0x194, ++ [PWRAP_ADC_RDATA_ADDR] = 0x198, ++ [PWRAP_GPS_STA] = 0x19C, ++ [PWRAP_SW_RST] = 0x1A0, ++ [PWRAP_DVFS_STEP_CTRL0] = 0x238, ++ [PWRAP_DVFS_STEP_CTRL1] = 0x23C, ++ [PWRAP_DVFS_STEP_CTRL2] = 0x240, ++ [PWRAP_SPI2_CTRL] = 0x244, ++}; ++ + static int mt8173_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, +@@ -499,6 +641,7 @@ enum pmic_type { + + enum pwrap_type { + PWRAP_MT2701, ++ PWRAP_MT7622, + PWRAP_MT8135, + PWRAP_MT8173, + }; +@@ -927,6 +1070,9 @@ static int pwrap_init_cipher(struct pmic + case PWRAP_MT8173: + pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); + break; ++ case PWRAP_MT7622: ++ pwrap_writel(wrp, 0, PWRAP_CIPHER_EN); ++ break; + } + + /* Config cipher mode @PMIC */ +@@ -1071,6 +1217,15 @@ static int pwrap_mt2701_init_soc_specifi + return 0; + } + ++static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) ++{ ++ pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); ++ /* enable 2wire SPI master */ ++ pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL); ++ ++ return 0; ++} ++ + static int pwrap_init(struct pmic_wrapper *wrp) + { + int ret; +@@ -1242,6 +1397,18 @@ static const struct pmic_wrapper_type pw + .init_soc_specific = pwrap_mt2701_init_soc_specific, + }; + ++static const struct pmic_wrapper_type pwrap_mt7622 = { ++ .regs = mt7622_regs, ++ .type = PWRAP_MT7622, ++ .arb_en_all = 0xff, ++ .int_en_all = ~(u32)BIT(31), ++ .spi_w = PWRAP_MAN_CMD_SPI_WRITE, ++ .wdt_src = PWRAP_WDT_SRC_MASK_ALL, ++ .has_bridge = 0, ++ .init_reg_clock = pwrap_common_init_reg_clock, ++ .init_soc_specific = pwrap_mt7622_init_soc_specific, ++}; ++ + static const struct pmic_wrapper_type pwrap_mt8135 = { + .regs = mt8135_regs, + .type = PWRAP_MT8135, +@@ -1271,6 +1438,9 @@ static const struct of_device_id of_pwra + .compatible = "mediatek,mt2701-pwrap", + .data = &pwrap_mt2701, + }, { ++ .compatible = "mediatek,mt7622-pwrap", ++ .data = &pwrap_mt7622, ++ }, { + .compatible = "mediatek,mt8135-pwrap", + .data = &pwrap_mt8135, + }, { diff --git a/target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch b/target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch new file mode 100644 index 000000000..26a9eceab --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0123-soc-mediatek-place-Kconfig-for-all-SoC-drivers-under.patch @@ -0,0 +1,57 @@ +From 21501b17e017cb10f1a64a73e62e3e2e91a52efa Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 5 Oct 2017 11:17:49 +0800 +Subject: [PATCH 123/224] soc: mediatek: place Kconfig for all SoC drivers + under menu + +Add cleanup for placing all Kconfig for all MediaTek SoC drivers under +the independent menu as other SoCs vendor usually did. Since the menu +would be shown depending on "ARCH_MEDIATEK || COMPILE_TEST" selected and +MTK_PMIC_WRAP is still safe compiling with the case of "COMPILE_TEST" +only, the superfluous dependency for those items under the menu also is +also being removed for the sake of simplicity. + +Signed-off-by: Sean Wang +Reviewed-by: Jean Delvare +Signed-off-by: Matthias Brugger +--- + drivers/soc/mediatek/Kconfig | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +--- a/drivers/soc/mediatek/Kconfig ++++ b/drivers/soc/mediatek/Kconfig +@@ -1,9 +1,11 @@ + # + # MediaTek SoC drivers + # ++menu "MediaTek SoC drivers" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ + config MTK_INFRACFG + bool "MediaTek INFRACFG Support" +- depends on ARCH_MEDIATEK || COMPILE_TEST + select REGMAP + help + Say yes here to add support for the MediaTek INFRACFG controller. The +@@ -12,7 +14,6 @@ config MTK_INFRACFG + + config MTK_PMIC_WRAP + tristate "MediaTek PMIC Wrapper Support" +- depends on ARCH_MEDIATEK + depends on RESET_CONTROLLER + select REGMAP + help +@@ -22,7 +23,6 @@ config MTK_PMIC_WRAP + + config MTK_SCPSYS + bool "MediaTek SCPSYS Support" +- depends on ARCH_MEDIATEK || COMPILE_TEST + default ARCH_MEDIATEK + select REGMAP + select MTK_INFRACFG +@@ -30,3 +30,5 @@ config MTK_SCPSYS + help + Say yes here to add support for the MediaTek SCPSYS power domain + driver. ++ ++endmenu diff --git a/target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch b/target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch new file mode 100644 index 000000000..6af0ae831 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0124-arm64-mediatek-cleanup-message-for-platform-selectio.patch @@ -0,0 +1,34 @@ +From f9bea440dd8dbf1eda8644e4b1d76503053f17b6 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 19 Oct 2017 17:52:54 +0800 +Subject: [PATCH 124/224] arm64: mediatek: cleanup message for platform + selection + +The latest kernel tree already can support more MediaTek platforms such as +MT2712 and MT7622, so additional descriptions for those platforms are added +and certain cleanups are also being made here. + +Signed-off-by: Sean Wang +Signed-off-by: Matthias Brugger +--- + arch/arm64/Kconfig.platforms | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -91,12 +91,13 @@ config ARCH_HISI + This enables support for Hisilicon ARMv8 SoC family + + config ARCH_MEDIATEK +- bool "Mediatek MT65xx & MT81xx ARMv8 SoC" ++ bool "MediaTek SoC Family" + select ARM_GIC + select PINCTRL + select MTK_TIMER + help +- Support for Mediatek MT65xx & MT81xx ARMv8 SoCs ++ This enables support for MediaTek MT27xx, MT65xx, MT76xx ++ & MT81xx ARMv8 SoCs + + config ARCH_MESON + bool "Amlogic Platforms" diff --git a/target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch b/target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch new file mode 100644 index 000000000..a9481f3d6 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0125-phy-phy-mtk-tphy-add-set_mode-callback.patch @@ -0,0 +1,86 @@ +From d42ebed1aa669c5a897ec0aa5e1ede8d9069894a Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Thu, 21 Sep 2017 18:31:49 +0800 +Subject: [PATCH 125/224] phy: phy-mtk-tphy: add set_mode callback + +This is used to force PHY with USB OTG function to enter a specific +mode, and override OTG IDPIN(or IDDIG) signal. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Kishon Vijay Abraham I +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 39 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -96,9 +96,11 @@ + + #define U3P_U2PHYDTM1 0x06C + #define P2C_RG_UART_EN BIT(16) ++#define P2C_FORCE_IDDIG BIT(9) + #define P2C_RG_VBUSVALID BIT(5) + #define P2C_RG_SESSEND BIT(4) + #define P2C_RG_AVALID BIT(2) ++#define P2C_RG_IDDIG BIT(1) + + #define U3P_U3_CHIP_GPIO_CTLD 0x0c + #define P3C_REG_IP_SW_RST BIT(31) +@@ -585,6 +587,31 @@ static void u2_phy_instance_exit(struct + } + } + ++static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, ++ struct mtk_phy_instance *instance, ++ enum phy_mode mode) ++{ ++ struct u2phy_banks *u2_banks = &instance->u2_banks; ++ u32 tmp; ++ ++ tmp = readl(u2_banks->com + U3P_U2PHYDTM1); ++ switch (mode) { ++ case PHY_MODE_USB_DEVICE: ++ tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; ++ break; ++ case PHY_MODE_USB_HOST: ++ tmp |= P2C_FORCE_IDDIG; ++ tmp &= ~P2C_RG_IDDIG; ++ break; ++ case PHY_MODE_USB_OTG: ++ tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); ++ break; ++ default: ++ return; ++ } ++ writel(tmp, u2_banks->com + U3P_U2PHYDTM1); ++} ++ + static void pcie_phy_instance_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) + { +@@ -881,6 +908,17 @@ static int mtk_phy_exit(struct phy *phy) + return 0; + } + ++static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode) ++{ ++ struct mtk_phy_instance *instance = phy_get_drvdata(phy); ++ struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); ++ ++ if (instance->type == PHY_TYPE_USB2) ++ u2_phy_instance_set_mode(tphy, instance, mode); ++ ++ return 0; ++} ++ + static struct phy *mtk_phy_xlate(struct device *dev, + struct of_phandle_args *args) + { +@@ -931,6 +969,7 @@ static const struct phy_ops mtk_tphy_ops + .exit = mtk_phy_exit, + .power_on = mtk_phy_power_on, + .power_off = mtk_phy_power_off, ++ .set_mode = mtk_phy_set_mode, + .owner = THIS_MODULE, + }; + diff --git a/target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch b/target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch new file mode 100644 index 000000000..26c751594 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0126-usb-xhci-mtk-use-dma_set_mask_and_coherent-in-probe-.patch @@ -0,0 +1,35 @@ +From 9f617ce19c5dab429a539d411204ae220b5b8cd6 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:33 +0800 +Subject: [PATCH 126/224] usb: xhci-mtk: use dma_set_mask_and_coherent() in + probe function + +This patch uses the simpler dma_set_mask_and_coherent() instead of +doing these as separate steps + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk.c | 7 +------ + 1 file changed, 1 insertion(+), 6 deletions(-) + +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -606,15 +606,10 @@ static int xhci_mtk_probe(struct platfor + } + + /* Initialize dma_mask and coherent_dma_mask to 32-bits */ +- ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) + goto disable_clk; + +- if (!dev->dma_mask) +- dev->dma_mask = &dev->coherent_dma_mask; +- else +- dma_set_mask(dev, DMA_BIT_MASK(32)); +- + hcd = usb_create_hcd(driver, dev, dev_name(dev)); + if (!hcd) { + ret = -ENOMEM; diff --git a/target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch b/target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch new file mode 100644 index 000000000..15c1b29dc --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0127-usb-xhci-mtk-use-ports-count-from-xhci-in-xhci_mtk_s.patch @@ -0,0 +1,53 @@ +From f97aa71fe34135e7fc8da6231e61ee06f79d739d Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:34 +0800 +Subject: [PATCH 127/224] usb: xhci-mtk: use ports count from xhci in + xhci_mtk_sch_init() + +Make use of ports count from xhci but not from ippc in +xhci_mtk_sch_init() + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk-sch.c | 3 ++- + drivers/usb/host/xhci-mtk.c | 3 --- + 2 files changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/usb/host/xhci-mtk-sch.c ++++ b/drivers/usb/host/xhci-mtk-sch.c +@@ -287,12 +287,13 @@ static bool need_bw_sch(struct usb_host_ + + int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk) + { ++ struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd); + struct mu3h_sch_bw_info *sch_array; + int num_usb_bus; + int i; + + /* ss IN and OUT are separated */ +- num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports; ++ num_usb_bus = xhci->num_usb3_ports * 2 + xhci->num_usb2_ports; + + sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL); + if (sch_array == NULL) +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -492,7 +492,6 @@ static void xhci_mtk_quirks(struct devic + /* called during probe() after chip reset completes */ + static int xhci_mtk_setup(struct usb_hcd *hcd) + { +- struct xhci_hcd *xhci = hcd_to_xhci(hcd); + struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); + int ret; + +@@ -507,8 +506,6 @@ static int xhci_mtk_setup(struct usb_hcd + return ret; + + if (usb_hcd_is_primary_hcd(hcd)) { +- mtk->num_u3_ports = xhci->num_usb3_ports; +- mtk->num_u2_ports = xhci->num_usb2_ports; + ret = xhci_mtk_sch_init(mtk); + if (ret) + return ret; diff --git a/target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch b/target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch new file mode 100644 index 000000000..ebd0ea10d --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0128-usb-xhci-mtk-check-clock-stability-of-U3_MAC.patch @@ -0,0 +1,36 @@ +From 4422c4efeed2a8b9fa745c6e529623d89c0be75e Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:35 +0800 +Subject: [PATCH 128/224] usb: xhci-mtk: check clock stability of U3_MAC + +This is useful to find out the root cause when the Super Speed doesn't +work. Such as when the T-PHY is switched to PCIe or SATA, and affects +Super Speed function, the check will fail. + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -43,6 +43,7 @@ + + /* ip_pw_sts1 register */ + #define STS1_IP_SLEEP_STS BIT(30) ++#define STS1_U3_MAC_RST BIT(16) + #define STS1_XHCI_RST BIT(11) + #define STS1_SYS125_RST BIT(10) + #define STS1_REF_RST BIT(8) +@@ -125,6 +126,9 @@ static int xhci_mtk_host_enable(struct x + check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | + STS1_SYS125_RST | STS1_XHCI_RST; + ++ if (mtk->num_u3_ports) ++ check_val |= STS1_U3_MAC_RST; ++ + ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, + (check_val == (value & check_val)), 100, 20000); + if (ret) { diff --git a/target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch b/target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch new file mode 100644 index 000000000..d5e48c7d0 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0129-usb-xhci-mtk-support-option-to-disable-usb3-ports.patch @@ -0,0 +1,85 @@ +From 13a1b2e927893cbb046a1ec5a55ec3516873a3f6 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:36 +0800 +Subject: [PATCH 129/224] usb: xhci-mtk: support option to disable usb3 ports + +Add support to disable specific usb3 ports, it's useful when +usb3 phy is shared with PCIe or SATA, because we should disable +the corresponding usb3 port if the phy is used by PCIe or SATA. +Sometimes it's helpful to analyse and solve problems. + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk.c | 18 +++++++++++++++--- + drivers/usb/host/xhci-mtk.h | 1 + + 2 files changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -92,6 +92,7 @@ static int xhci_mtk_host_enable(struct x + { + struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; + u32 value, check_val; ++ int u3_ports_disabed = 0; + int ret; + int i; + +@@ -103,8 +104,13 @@ static int xhci_mtk_host_enable(struct x + value &= ~CTRL1_IP_HOST_PDN; + writel(value, &ippc->ip_pw_ctr1); + +- /* power on and enable all u3 ports */ ++ /* power on and enable u3 ports except skipped ones */ + for (i = 0; i < mtk->num_u3_ports; i++) { ++ if ((0x1 << i) & mtk->u3p_dis_msk) { ++ u3_ports_disabed++; ++ continue; ++ } ++ + value = readl(&ippc->u3_ctrl_p[i]); + value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); + value |= CTRL_U3_PORT_HOST_SEL; +@@ -126,7 +132,7 @@ static int xhci_mtk_host_enable(struct x + check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | + STS1_SYS125_RST | STS1_XHCI_RST; + +- if (mtk->num_u3_ports) ++ if (mtk->num_u3_ports > u3_ports_disabed) + check_val |= STS1_U3_MAC_RST; + + ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, +@@ -149,8 +155,11 @@ static int xhci_mtk_host_disable(struct + if (!mtk->has_ippc) + return 0; + +- /* power down all u3 ports */ ++ /* power down u3 ports except skipped ones */ + for (i = 0; i < mtk->num_u3_ports; i++) { ++ if ((0x1 << i) & mtk->u3p_dis_msk) ++ continue; ++ + value = readl(&ippc->u3_ctrl_p[i]); + value |= CTRL_U3_PORT_PDN; + writel(value, &ippc->u3_ctrl_p[i]); +@@ -573,6 +582,9 @@ static int xhci_mtk_probe(struct platfor + } + + mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); ++ /* optional property, ignore the error if it does not exist */ ++ of_property_read_u32(node, "mediatek,u3p-dis-msk", ++ &mtk->u3p_dis_msk); + + ret = usb_wakeup_of_property_parse(mtk, node); + if (ret) +--- a/drivers/usb/host/xhci-mtk.h ++++ b/drivers/usb/host/xhci-mtk.h +@@ -121,6 +121,7 @@ struct xhci_hcd_mtk { + bool has_ippc; + int num_u2_ports; + int num_u3_ports; ++ int u3p_dis_msk; + struct regulator *vusb33; + struct regulator *vbus; + struct clk *sys_clk; /* sys and mac clock */ diff --git a/target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch b/target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch new file mode 100644 index 000000000..85ee07baa --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0130-usb-xhci-mtk-remove-dummy-wakeup-debounce-clocks.patch @@ -0,0 +1,86 @@ +From 25adaf94e0fcbf6c1b47cb610edb7f5c23c53139 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:37 +0800 +Subject: [PATCH 130/224] usb: xhci-mtk: remove dummy wakeup debounce clocks + +The wakeup debounce clocks for each ports in fact are not +needed, so remove them. + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Reviewed-by: Matthias Brugger +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk.c | 33 --------------------------------- + drivers/usb/host/xhci-mtk.h | 2 -- + 2 files changed, 35 deletions(-) + +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -237,25 +237,8 @@ static int xhci_mtk_clks_enable(struct x + goto sys_clk_err; + } + +- if (mtk->wakeup_src) { +- ret = clk_prepare_enable(mtk->wk_deb_p0); +- if (ret) { +- dev_err(mtk->dev, "failed to enable wk_deb_p0\n"); +- goto usb_p0_err; +- } +- +- ret = clk_prepare_enable(mtk->wk_deb_p1); +- if (ret) { +- dev_err(mtk->dev, "failed to enable wk_deb_p1\n"); +- goto usb_p1_err; +- } +- } + return 0; + +-usb_p1_err: +- clk_disable_unprepare(mtk->wk_deb_p0); +-usb_p0_err: +- clk_disable_unprepare(mtk->sys_clk); + sys_clk_err: + clk_disable_unprepare(mtk->ref_clk); + ref_clk_err: +@@ -264,10 +247,6 @@ ref_clk_err: + + static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) + { +- if (mtk->wakeup_src) { +- clk_disable_unprepare(mtk->wk_deb_p1); +- clk_disable_unprepare(mtk->wk_deb_p0); +- } + clk_disable_unprepare(mtk->sys_clk); + clk_disable_unprepare(mtk->ref_clk); + } +@@ -371,18 +350,6 @@ static int usb_wakeup_of_property_parse( + if (!mtk->wakeup_src) + return 0; + +- mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0"); +- if (IS_ERR(mtk->wk_deb_p0)) { +- dev_err(dev, "fail to get wakeup_deb_p0\n"); +- return PTR_ERR(mtk->wk_deb_p0); +- } +- +- mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1"); +- if (IS_ERR(mtk->wk_deb_p1)) { +- dev_err(dev, "fail to get wakeup_deb_p1\n"); +- return PTR_ERR(mtk->wk_deb_p1); +- } +- + mtk->pericfg = syscon_regmap_lookup_by_phandle(dn, + "mediatek,syscon-wakeup"); + if (IS_ERR(mtk->pericfg)) { +--- a/drivers/usb/host/xhci-mtk.h ++++ b/drivers/usb/host/xhci-mtk.h +@@ -126,8 +126,6 @@ struct xhci_hcd_mtk { + struct regulator *vbus; + struct clk *sys_clk; /* sys and mac clock */ + struct clk *ref_clk; +- struct clk *wk_deb_p0; /* port0's wakeup debounce clock */ +- struct clk *wk_deb_p1; + struct regmap *pericfg; + struct phy **phys; + int num_phys; diff --git a/target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch b/target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch new file mode 100644 index 000000000..264cd25e7 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0131-usb-xhci-mtk-add-optional-mcu-and-dma-bus-clocks.patch @@ -0,0 +1,139 @@ +From 9dce908d64ffb8b0ab71cb3a4b79db398d2e6dc3 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:38 +0800 +Subject: [PATCH 131/224] usb: xhci-mtk: add optional mcu and dma bus clocks + +There are mcu_bus and dma_bus clocks needed to be controlled by +driver on some SoCs, so add them as optional ones + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Reviewed-by: Matthias Brugger +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk.c | 79 ++++++++++++++++++++++++++++++++++----------- + drivers/usb/host/xhci-mtk.h | 2 ++ + 2 files changed, 62 insertions(+), 19 deletions(-) + +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -221,6 +221,44 @@ static int xhci_mtk_ssusb_config(struct + return xhci_mtk_host_enable(mtk); + } + ++/* ignore the error if the clock does not exist */ ++static struct clk *optional_clk_get(struct device *dev, const char *id) ++{ ++ struct clk *opt_clk; ++ ++ opt_clk = devm_clk_get(dev, id); ++ /* ignore error number except EPROBE_DEFER */ ++ if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER)) ++ opt_clk = NULL; ++ ++ return opt_clk; ++} ++ ++static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) ++{ ++ struct device *dev = mtk->dev; ++ ++ mtk->sys_clk = devm_clk_get(dev, "sys_ck"); ++ if (IS_ERR(mtk->sys_clk)) { ++ dev_err(dev, "fail to get sys_ck\n"); ++ return PTR_ERR(mtk->sys_clk); ++ } ++ ++ mtk->ref_clk = optional_clk_get(dev, "ref_ck"); ++ if (IS_ERR(mtk->ref_clk)) ++ return PTR_ERR(mtk->ref_clk); ++ ++ mtk->mcu_clk = optional_clk_get(dev, "mcu_ck"); ++ if (IS_ERR(mtk->mcu_clk)) ++ return PTR_ERR(mtk->mcu_clk); ++ ++ mtk->dma_clk = optional_clk_get(dev, "dma_ck"); ++ if (IS_ERR(mtk->dma_clk)) ++ return PTR_ERR(mtk->dma_clk); ++ ++ return 0; ++} ++ + static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk) + { + int ret; +@@ -237,16 +275,34 @@ static int xhci_mtk_clks_enable(struct x + goto sys_clk_err; + } + ++ ret = clk_prepare_enable(mtk->mcu_clk); ++ if (ret) { ++ dev_err(mtk->dev, "failed to enable mcu_clk\n"); ++ goto mcu_clk_err; ++ } ++ ++ ret = clk_prepare_enable(mtk->dma_clk); ++ if (ret) { ++ dev_err(mtk->dev, "failed to enable dma_clk\n"); ++ goto dma_clk_err; ++ } ++ + return 0; + ++dma_clk_err: ++ clk_disable_unprepare(mtk->mcu_clk); ++mcu_clk_err: ++ clk_disable_unprepare(mtk->sys_clk); + sys_clk_err: + clk_disable_unprepare(mtk->ref_clk); + ref_clk_err: +- return -EINVAL; ++ return ret; + } + + static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) + { ++ clk_disable_unprepare(mtk->dma_clk); ++ clk_disable_unprepare(mtk->mcu_clk); + clk_disable_unprepare(mtk->sys_clk); + clk_disable_unprepare(mtk->ref_clk); + } +@@ -529,24 +585,9 @@ static int xhci_mtk_probe(struct platfor + return PTR_ERR(mtk->vusb33); + } + +- mtk->sys_clk = devm_clk_get(dev, "sys_ck"); +- if (IS_ERR(mtk->sys_clk)) { +- dev_err(dev, "fail to get sys_ck\n"); +- return PTR_ERR(mtk->sys_clk); +- } +- +- /* +- * reference clock is usually a "fixed-clock", make it optional +- * for backward compatibility and ignore the error if it does +- * not exist. +- */ +- mtk->ref_clk = devm_clk_get(dev, "ref_ck"); +- if (IS_ERR(mtk->ref_clk)) { +- if (PTR_ERR(mtk->ref_clk) == -EPROBE_DEFER) +- return -EPROBE_DEFER; +- +- mtk->ref_clk = NULL; +- } ++ ret = xhci_mtk_clks_get(mtk); ++ if (ret) ++ return ret; + + mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); + /* optional property, ignore the error if it does not exist */ +--- a/drivers/usb/host/xhci-mtk.h ++++ b/drivers/usb/host/xhci-mtk.h +@@ -126,6 +126,8 @@ struct xhci_hcd_mtk { + struct regulator *vbus; + struct clk *sys_clk; /* sys and mac clock */ + struct clk *ref_clk; ++ struct clk *mcu_clk; ++ struct clk *dma_clk; + struct regmap *pericfg; + struct phy **phys; + int num_phys; diff --git a/target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch b/target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch new file mode 100644 index 000000000..e62a3e39d --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0132-usb-host-modify-description-for-MTK-xHCI-config.patch @@ -0,0 +1,32 @@ +From d975bd8976c4d19fbfbaafe269dd466e281a2e3e Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:39 +0800 +Subject: [PATCH 132/224] usb: host: modify description for MTK xHCI config + +Due to all MediaTek SoCs with xHCI host controller use this +driver, remove limitation for specific SoCs + +Signed-off-by: Chunfeng Yun +Acked-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -45,12 +45,12 @@ config USB_XHCI_PLATFORM + If unsure, say N. + + config USB_XHCI_MTK +- tristate "xHCI support for Mediatek MT65xx/MT7621" ++ tristate "xHCI support for MediaTek SoCs" + select MFD_SYSCON + depends on (MIPS && SOC_MT7621) || ARCH_MEDIATEK || COMPILE_TEST + ---help--- + Say 'Y' to enable the support for the xHCI host controller +- found in Mediatek MT65xx SoCs. ++ found in MediaTek SoCs. + If unsure, say N. + + config USB_XHCI_MVEBU diff --git a/target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch b/target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch new file mode 100644 index 000000000..5124bbaa4 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0133-dt-bindings-usb-mtk-xhci-add-a-optional-property-to-.patch @@ -0,0 +1,25 @@ +From 3a2dce7d84793ec60cff173e17e3669acaade8c9 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:40 +0800 +Subject: [PATCH 133/224] dt-bindings: usb: mtk-xhci: add a optional property + to disable u3ports + +Add a new optional property to disable u3ports + +Signed-off-by: Chunfeng Yun +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +@@ -38,6 +38,8 @@ Optional properties: + mode; + - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup + control register, it depends on "mediatek,wakeup-src". ++ - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, ++ bit1 for u3port1, ... etc; + - vbus-supply : reference to the VBUS regulator; + - usb3-lpm-capable : supports USB3.0 LPM + - pinctrl-names : a pinctrl state named "default" must be defined diff --git a/target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch b/target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch new file mode 100644 index 000000000..24fd1260e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0134-dt-bindings-usb-mtk-xhci-remove-dummy-clocks-and-add.patch @@ -0,0 +1,58 @@ +From a96468412cac8abd66667c322fbcda756cc3abc9 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 13 Oct 2017 16:26:41 +0800 +Subject: [PATCH 134/224] dt-bindings: usb: mtk-xhci: remove dummy clocks and + add optional ones + +Remove dummy clocks for usb wakeup and add optional ones for +MCU_BUS_CK and DMA_BUS_CK. + +Signed-off-by: Chunfeng Yun +Acked-by: Rob Herring +Reviewed-by: Matthias Brugger +Signed-off-by: Greg Kroah-Hartman +--- + .../devicetree/bindings/usb/mediatek,mtk-xhci.txt | 18 ++++++++---------- + 1 file changed, 8 insertions(+), 10 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +@@ -26,10 +26,11 @@ Required properties: + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names + - clock-names : must contain +- "sys_ck": for clock of xHCI MAC +- "ref_ck": for reference clock of xHCI MAC +- "wakeup_deb_p0": for USB wakeup debounce clock of port0 +- "wakeup_deb_p1": for USB wakeup debounce clock of port1 ++ "sys_ck": controller clock used by normal mode, ++ the following ones are optional: ++ "ref_ck": reference clock used by low power mode etc, ++ "mcu_ck": mcu_bus clock for register access, ++ "dma_ck": dma_bus clock for data transfer by DMA + + - phys : a list of phandle + phy specifier pairs + +@@ -57,9 +58,7 @@ usb30: usb@11270000 { + clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>, + <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB1>; +- clock-names = "sys_ck", "ref_ck", +- "wakeup_deb_p0", +- "wakeup_deb_p1"; ++ clock-names = "sys_ck", "ref_ck"; + phys = <&phy_port0 PHY_TYPE_USB3>, + <&phy_port1 PHY_TYPE_USB2>; + vusb33-supply = <&mt6397_vusb_reg>; +@@ -91,9 +90,8 @@ Required properties: + + - clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- - clock-names : must be +- "sys_ck": for clock of xHCI MAC +- "ref_ck": for reference clock of xHCI MAC ++ - clock-names : must contain "sys_ck", and the following ones are optional: ++ "ref_ck", "mcu_ck" and "dma_ck" + + Optional properties: + - vbus-supply : reference to the VBUS regulator; diff --git a/target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch b/target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch new file mode 100644 index 000000000..53b33fa5a --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0135-dt-bindings-mtd-add-new-compatible-strings-and-impro.patch @@ -0,0 +1,42 @@ +From 2af9a8582cb28e786a8cbd913f41e6db9adcf3dc Mon Sep 17 00:00:00 2001 +From: Guochun Mao +Date: Thu, 21 Sep 2017 20:45:05 +0800 +Subject: [PATCH 135/224] dt-bindings: mtd: add new compatible strings and + improve description + +Add "mediatak,mt2712-nor" and "mediatek,mt7622-nor" +for nor flash node's compatible strings. +Explicate the fallback compatible. + +Acked-by: Rob Herring +Signed-off-by: Guochun Mao +Signed-off-by: Cyrille Pitchen +--- + Documentation/devicetree/bindings/mtd/mtk-quadspi.txt | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +--- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt ++++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt +@@ -1,13 +1,16 @@ + * Serial NOR flash controller for MTK MT81xx (and similar) + + Required properties: +-- compatible: The possible values are: +- "mediatek,mt2701-nor" +- "mediatek,mt7623-nor" ++- compatible: For mt8173, compatible should be "mediatek,mt8173-nor", ++ and it's the fallback compatible for other Soc. ++ For every other SoC, should contain both the SoC-specific compatible ++ string and "mediatek,mt8173-nor". ++ The possible values are: ++ "mediatek,mt2701-nor", "mediatek,mt8173-nor" ++ "mediatek,mt2712-nor", "mediatek,mt8173-nor" ++ "mediatek,mt7622-nor", "mediatek,mt8173-nor" ++ "mediatek,mt7623-nor", "mediatek,mt8173-nor" + "mediatek,mt8173-nor" +- For mt8173, compatible should be "mediatek,mt8173-nor". +- For every other SoC, should contain both the SoC-specific compatible string +- and "mediatek,mt8173-nor". + - reg: physical base address and length of the controller's register + - clocks: the phandle of the clocks needed by the nor controller + - clock-names: the names of the clocks diff --git a/target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch b/target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch new file mode 100644 index 000000000..8bfba8953 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0136-mtd-mtk-nor-add-suspend-resume-support.patch @@ -0,0 +1,128 @@ +From 8947f8cd407a55db816cd03fc03b59096210978e Mon Sep 17 00:00:00 2001 +From: Guochun Mao +Date: Thu, 21 Sep 2017 20:45:06 +0800 +Subject: [PATCH 136/224] mtd: mtk-nor: add suspend/resume support + +Abstract functions of clock setting, to avoid duplicated code, +these functions been used in new feature. +Implement suspend/resume functions. + +Signed-off-by: Guochun Mao +Signed-off-by: Cyrille Pitchen +--- + drivers/mtd/spi-nor/mtk-quadspi.c | 70 ++++++++++++++++++++++++++++++++------- + 1 file changed, 58 insertions(+), 12 deletions(-) + +--- a/drivers/mtd/spi-nor/mtk-quadspi.c ++++ b/drivers/mtd/spi-nor/mtk-quadspi.c +@@ -404,6 +404,29 @@ static int mt8173_nor_write_reg(struct s + return ret; + } + ++static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor) ++{ ++ clk_disable_unprepare(mt8173_nor->spi_clk); ++ clk_disable_unprepare(mt8173_nor->nor_clk); ++} ++ ++static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(mt8173_nor->spi_clk); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(mt8173_nor->nor_clk); ++ if (ret) { ++ clk_disable_unprepare(mt8173_nor->spi_clk); ++ return ret; ++ } ++ ++ return 0; ++} ++ + static int mtk_nor_init(struct mt8173_nor *mt8173_nor, + struct device_node *flash_node) + { +@@ -468,15 +491,11 @@ static int mtk_nor_drv_probe(struct plat + return PTR_ERR(mt8173_nor->nor_clk); + + mt8173_nor->dev = &pdev->dev; +- ret = clk_prepare_enable(mt8173_nor->spi_clk); ++ ++ ret = mt8173_nor_enable_clk(mt8173_nor); + if (ret) + return ret; + +- ret = clk_prepare_enable(mt8173_nor->nor_clk); +- if (ret) { +- clk_disable_unprepare(mt8173_nor->spi_clk); +- return ret; +- } + /* only support one attached flash */ + flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); + if (!flash_np) { +@@ -487,10 +506,9 @@ static int mtk_nor_drv_probe(struct plat + ret = mtk_nor_init(mt8173_nor, flash_np); + + nor_free: +- if (ret) { +- clk_disable_unprepare(mt8173_nor->spi_clk); +- clk_disable_unprepare(mt8173_nor->nor_clk); +- } ++ if (ret) ++ mt8173_nor_disable_clk(mt8173_nor); ++ + return ret; + } + +@@ -498,11 +516,38 @@ static int mtk_nor_drv_remove(struct pla + { + struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); + +- clk_disable_unprepare(mt8173_nor->spi_clk); +- clk_disable_unprepare(mt8173_nor->nor_clk); ++ mt8173_nor_disable_clk(mt8173_nor); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mtk_nor_suspend(struct device *dev) ++{ ++ struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); ++ ++ mt8173_nor_disable_clk(mt8173_nor); ++ + return 0; + } + ++static int mtk_nor_resume(struct device *dev) ++{ ++ struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); ++ ++ return mt8173_nor_enable_clk(mt8173_nor); ++} ++ ++static const struct dev_pm_ops mtk_nor_dev_pm_ops = { ++ .suspend = mtk_nor_suspend, ++ .resume = mtk_nor_resume, ++}; ++ ++#define MTK_NOR_DEV_PM_OPS (&mtk_nor_dev_pm_ops) ++#else ++#define MTK_NOR_DEV_PM_OPS NULL ++#endif ++ + static const struct of_device_id mtk_nor_of_ids[] = { + { .compatible = "mediatek,mt8173-nor"}, + { /* sentinel */ } +@@ -514,6 +559,7 @@ static struct platform_driver mtk_nor_dr + .remove = mtk_nor_drv_remove, + .driver = { + .name = "mtk-nor", ++ .pm = MTK_NOR_DEV_PM_OPS, + .of_match_table = mtk_nor_of_ids, + }, + }; diff --git a/target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch b/target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch new file mode 100644 index 000000000..a003bd78a --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0137-dt-bindings-rtc-mediatek-add-bindings-for-MediaTek-S.patch @@ -0,0 +1,41 @@ +From 3254edde244fcbcce3bf4da1ade9db2db558ae28 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 23 Oct 2017 15:16:44 +0800 +Subject: [PATCH 137/224] dt-bindings: rtc: mediatek: add bindings for MediaTek + SoC based RTC + +Add device-tree binding for MediaTek SoC based RTC + +Cc: devicetree@vger.kernel.org +Signed-off-by: Sean Wang +Acked-by: Rob Herring +Signed-off-by: Alexandre Belloni +--- + .../devicetree/bindings/rtc/rtc-mt7622.txt | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mt7622.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/rtc/rtc-mt7622.txt +@@ -0,0 +1,21 @@ ++Device-Tree bindings for MediaTek SoC based RTC ++ ++Required properties: ++- compatible : Should be ++ "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC ++- reg : Specifies base physical address and size of the registers; ++- interrupts : Should contain the interrupt for RTC alarm; ++- clocks : Specifies list of clock specifiers, corresponding to ++ entries in clock-names property; ++- clock-names : Should contain "rtc" entries ++ ++Example: ++ ++rtc: rtc@10212800 { ++ compatible = "mediatek,mt7622-rtc", ++ "mediatek,soc-rtc"; ++ reg = <0 0x10212800 0 0x200>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_RTC>; ++ clock-names = "rtc"; ++}; diff --git a/target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch new file mode 100644 index 000000000..8cf900d14 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0138-rtc-mediatek-add-driver-for-RTC-on-MT7622-SoC.patch @@ -0,0 +1,471 @@ +From 4cf0b74c175cb5cb751e449223c0baafc2f98499 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 23 Oct 2017 15:16:45 +0800 +Subject: [PATCH 138/224] rtc: mediatek: add driver for RTC on MT7622 SoC + +This patch introduces the driver for the RTC on MT7622 SoC. + +Signed-off-by: Sean Wang +Reviewed-by: Yingjoe Chen +Signed-off-by: Alexandre Belloni +--- + drivers/rtc/Kconfig | 10 ++ + drivers/rtc/Makefile | 1 + + drivers/rtc/rtc-mt7622.c | 422 +++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 433 insertions(+) + create mode 100644 drivers/rtc/rtc-mt7622.c + +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1715,6 +1715,16 @@ config RTC_DRV_MT6397 + + If you want to use Mediatek(R) RTC interface, select Y or M here. + ++config RTC_DRV_MT7622 ++ tristate "MediaTek SoC based RTC" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ help ++ This enables support for the real time clock built in the MediaTek ++ SoCs. ++ ++ This drive can also be built as a module. If so, the module ++ will be called rtc-mt7622. ++ + config RTC_DRV_XGENE + tristate "APM X-Gene RTC" + depends on HAS_IOMEM +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -103,6 +103,7 @@ obj-$(CONFIG_RTC_DRV_MPC5121) += rtc-mpc + obj-$(CONFIG_RTC_DRV_VRTC) += rtc-mrst.o + obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o + obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o ++obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o + obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o + obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o + obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o +--- /dev/null ++++ b/drivers/rtc/rtc-mt7622.c +@@ -0,0 +1,422 @@ ++/* ++ * Driver for MediaTek SoC based RTC ++ * ++ * Copyright (C) 2017 Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MTK_RTC_DEV KBUILD_MODNAME ++ ++#define MTK_RTC_PWRCHK1 0x4 ++#define RTC_PWRCHK1_MAGIC 0xc6 ++ ++#define MTK_RTC_PWRCHK2 0x8 ++#define RTC_PWRCHK2_MAGIC 0x9a ++ ++#define MTK_RTC_KEY 0xc ++#define RTC_KEY_MAGIC 0x59 ++ ++#define MTK_RTC_PROT1 0x10 ++#define RTC_PROT1_MAGIC 0xa3 ++ ++#define MTK_RTC_PROT2 0x14 ++#define RTC_PROT2_MAGIC 0x57 ++ ++#define MTK_RTC_PROT3 0x18 ++#define RTC_PROT3_MAGIC 0x67 ++ ++#define MTK_RTC_PROT4 0x1c ++#define RTC_PROT4_MAGIC 0xd2 ++ ++#define MTK_RTC_CTL 0x20 ++#define RTC_RC_STOP BIT(0) ++ ++#define MTK_RTC_DEBNCE 0x2c ++#define RTC_DEBNCE_MASK GENMASK(2, 0) ++ ++#define MTK_RTC_INT 0x30 ++#define RTC_INT_AL_STA BIT(4) ++ ++/* ++ * Ranges from 0x40 to 0x78 provide RTC time setup for year, month, ++ * day of month, day of week, hour, minute and second. ++ */ ++#define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20)) ++ ++#define MTK_RTC_AL_CTL 0x7c ++#define RTC_AL_EN BIT(0) ++#define RTC_AL_ALL GENMASK(7, 0) ++ ++/* ++ * The offset is used in the translation for the year between in struct ++ * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA) ++ */ ++#define MTK_RTC_TM_YR_OFFSET 100 ++ ++/* ++ * The lowest value for the valid tm_year. RTC hardware would take incorrectly ++ * tm_year 100 as not a leap year and thus it is also required being excluded ++ * from the valid options. ++ */ ++#define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1) ++ ++/* ++ * The most year the RTC can hold is 99 and the next to 99 in year register ++ * would be wraparound to 0, for MT7622. ++ */ ++#define MTK_RTC_HW_YR_LIMIT 99 ++ ++/* The highest value for the valid tm_year */ ++#define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT) ++ ++/* Simple macro helps to check whether the hardware supports the tm_year */ ++#define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \ ++ (_y) <= MTK_RTC_TM_YR_H) ++ ++/* Types of the function the RTC provides are time counter and alarm. */ ++enum { ++ MTK_TC, ++ MTK_AL, ++}; ++ ++/* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */ ++enum { ++ MTK_YEA, ++ MTK_MON, ++ MTK_DOM, ++ MTK_DOW, ++ MTK_HOU, ++ MTK_MIN, ++ MTK_SEC ++}; ++ ++struct mtk_rtc { ++ struct rtc_device *rtc; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++}; ++ ++static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val) ++{ ++ writel_relaxed(val, rtc->base + reg); ++} ++ ++static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg) ++{ ++ return readl_relaxed(rtc->base + reg); ++} ++ ++static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set) ++{ ++ u32 val; ++ ++ val = mtk_r32(rtc, reg); ++ val &= ~mask; ++ val |= set; ++ mtk_w32(rtc, reg, val); ++} ++ ++static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val) ++{ ++ mtk_rmw(rtc, reg, 0, val); ++} ++ ++static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val) ++{ ++ mtk_rmw(rtc, reg, val, 0); ++} ++ ++static void mtk_rtc_hw_init(struct mtk_rtc *hw) ++{ ++ /* The setup of the init sequence is for allowing RTC got to work */ ++ mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC); ++ mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC); ++ mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC); ++ mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC); ++ mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC); ++ mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC); ++ mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC); ++ mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0); ++ mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP); ++} ++ ++static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm, ++ int time_alarm) ++{ ++ u32 year, mon, mday, wday, hour, min, sec; ++ ++ /* ++ * Read again until the field of the second is not changed which ++ * ensures all fields in the consistent state. Note that MTK_SEC must ++ * be read first. In this way, it guarantees the others remain not ++ * changed when the results for two MTK_SEC consecutive reads are same. ++ */ ++ do { ++ sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)); ++ min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN)); ++ hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU)); ++ wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW)); ++ mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM)); ++ mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON)); ++ year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA)); ++ } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC))); ++ ++ tm->tm_sec = sec; ++ tm->tm_min = min; ++ tm->tm_hour = hour; ++ tm->tm_wday = wday; ++ tm->tm_mday = mday; ++ tm->tm_mon = mon - 1; ++ ++ /* Rebase to the absolute year which userspace queries */ ++ tm->tm_year = year + MTK_RTC_TM_YR_OFFSET; ++} ++ ++static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm, ++ int time_alarm) ++{ ++ u32 year; ++ ++ /* Rebase to the relative year which RTC hardware requires */ ++ year = tm->tm_year - MTK_RTC_TM_YR_OFFSET; ++ ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year); ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1); ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday); ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday); ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour); ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min); ++ mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec); ++} ++ ++static irqreturn_t mtk_rtc_alarmirq(int irq, void *id) ++{ ++ struct mtk_rtc *hw = (struct mtk_rtc *)id; ++ u32 irq_sta; ++ ++ irq_sta = mtk_r32(hw, MTK_RTC_INT); ++ if (irq_sta & RTC_INT_AL_STA) { ++ /* Stop alarm also implicitly disables the alarm interrupt */ ++ mtk_w32(hw, MTK_RTC_AL_CTL, 0); ++ rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF); ++ ++ /* Ack alarm interrupt status */ ++ mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA); ++ return IRQ_HANDLED; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm) ++{ ++ struct mtk_rtc *hw = dev_get_drvdata(dev); ++ ++ mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC); ++ ++ return rtc_valid_tm(tm); ++} ++ ++static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm) ++{ ++ struct mtk_rtc *hw = dev_get_drvdata(dev); ++ ++ if (!MTK_RTC_TM_YR_VALID(tm->tm_year)) ++ return -EINVAL; ++ ++ /* Stop time counter before setting a new one*/ ++ mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP); ++ ++ mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC); ++ ++ /* Restart the time counter */ ++ mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP); ++ ++ return 0; ++} ++ ++static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) ++{ ++ struct mtk_rtc *hw = dev_get_drvdata(dev); ++ struct rtc_time *alrm_tm = &wkalrm->time; ++ ++ mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL); ++ ++ wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN); ++ wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA); ++ ++ return 0; ++} ++ ++static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) ++{ ++ struct mtk_rtc *hw = dev_get_drvdata(dev); ++ struct rtc_time *alrm_tm = &wkalrm->time; ++ ++ if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year)) ++ return -EINVAL; ++ ++ /* ++ * Stop the alarm also implicitly including disables interrupt before ++ * setting a new one. ++ */ ++ mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN); ++ ++ /* ++ * Avoid contention between mtk_rtc_setalarm and IRQ handler so that ++ * disabling the interrupt and awaiting for pending IRQ handler to ++ * complete. ++ */ ++ synchronize_irq(hw->irq); ++ ++ mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL); ++ ++ /* Restart the alarm with the new setup */ ++ mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops mtk_rtc_ops = { ++ .read_time = mtk_rtc_gettime, ++ .set_time = mtk_rtc_settime, ++ .read_alarm = mtk_rtc_getalarm, ++ .set_alarm = mtk_rtc_setalarm, ++}; ++ ++static const struct of_device_id mtk_rtc_match[] = { ++ { .compatible = "mediatek,mt7622-rtc" }, ++ { .compatible = "mediatek,soc-rtc" }, ++ {}, ++}; ++ ++static int mtk_rtc_probe(struct platform_device *pdev) ++{ ++ struct mtk_rtc *hw; ++ struct resource *res; ++ int ret; ++ ++ hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); ++ if (!hw) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, hw); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ hw->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hw->base)) ++ return PTR_ERR(hw->base); ++ ++ hw->clk = devm_clk_get(&pdev->dev, "rtc"); ++ if (IS_ERR(hw->clk)) { ++ dev_err(&pdev->dev, "No clock\n"); ++ return PTR_ERR(hw->clk); ++ } ++ ++ ret = clk_prepare_enable(hw->clk); ++ if (ret) ++ return ret; ++ ++ hw->irq = platform_get_irq(pdev, 0); ++ if (hw->irq < 0) { ++ dev_err(&pdev->dev, "No IRQ resource\n"); ++ ret = hw->irq; ++ goto err; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq, ++ 0, dev_name(&pdev->dev), hw); ++ if (ret) { ++ dev_err(&pdev->dev, "Can't request IRQ\n"); ++ goto err; ++ } ++ ++ mtk_rtc_hw_init(hw); ++ ++ device_init_wakeup(&pdev->dev, true); ++ ++ hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, ++ &mtk_rtc_ops, THIS_MODULE); ++ if (IS_ERR(hw->rtc)) { ++ ret = PTR_ERR(hw->rtc); ++ dev_err(&pdev->dev, "Unable to register device\n"); ++ goto err; ++ } ++ ++ return 0; ++err: ++ clk_disable_unprepare(hw->clk); ++ ++ return ret; ++} ++ ++static int mtk_rtc_remove(struct platform_device *pdev) ++{ ++ struct mtk_rtc *hw = platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(hw->clk); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mtk_rtc_suspend(struct device *dev) ++{ ++ struct mtk_rtc *hw = dev_get_drvdata(dev); ++ ++ if (device_may_wakeup(dev)) ++ enable_irq_wake(hw->irq); ++ ++ return 0; ++} ++ ++static int mtk_rtc_resume(struct device *dev) ++{ ++ struct mtk_rtc *hw = dev_get_drvdata(dev); ++ ++ if (device_may_wakeup(dev)) ++ disable_irq_wake(hw->irq); ++ ++ return 0; ++} ++ ++static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume); ++ ++#define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops) ++#else /* CONFIG_PM */ ++#define MTK_RTC_PM_OPS NULL ++#endif /* CONFIG_PM */ ++ ++static struct platform_driver mtk_rtc_driver = { ++ .probe = mtk_rtc_probe, ++ .remove = mtk_rtc_remove, ++ .driver = { ++ .name = MTK_RTC_DEV, ++ .of_match_table = mtk_rtc_match, ++ .pm = MTK_RTC_PM_OPS, ++ }, ++}; ++ ++module_platform_driver(mtk_rtc_driver); ++ ++MODULE_DESCRIPTION("MediaTek SoC based RTC Driver"); ++MODULE_AUTHOR("Sean Wang "); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch b/target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch new file mode 100644 index 000000000..0513a085a --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0139-rtc-mediatek-enhance-the-description-for-MediaTek-PM.patch @@ -0,0 +1,39 @@ +From ff4f8c2c894f1e6b5b5551571e22b2f947545bff Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 23 Oct 2017 15:16:46 +0800 +Subject: [PATCH 139/224] rtc: mediatek: enhance the description for MediaTek + PMIC based RTC + +Give a better description for original MediaTek RTC driver as PMIC based +RTC in order to distinguish SoC based RTC. Also turning all words with +Mediatek to MediaTek here. + +Cc: Eddie Huang +Signed-off-by: Sean Wang +Acked-by: Eddie Huang +Signed-off-by: Alexandre Belloni +--- + drivers/rtc/Kconfig | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1706,14 +1706,14 @@ config RTC_DRV_MOXART + will be called rtc-moxart + + config RTC_DRV_MT6397 +- tristate "Mediatek Real Time Clock driver" ++ tristate "MediaTek PMIC based RTC" + depends on MFD_MT6397 || (COMPILE_TEST && IRQ_DOMAIN) + help +- This selects the Mediatek(R) RTC driver. RTC is part of Mediatek ++ This selects the MediaTek(R) RTC driver. RTC is part of MediaTek + MT6397 PMIC. You should enable MT6397 PMIC MFD before select +- Mediatek(R) RTC driver. ++ MediaTek(R) RTC driver. + +- If you want to use Mediatek(R) RTC interface, select Y or M here. ++ If you want to use MediaTek(R) RTC interface, select Y or M here. + + config RTC_DRV_MT7622 + tristate "MediaTek SoC based RTC" diff --git a/target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch b/target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch new file mode 100644 index 000000000..2afb956ef --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0140-mtd-nand-mtk-change-the-compile-sequence-of-mtk_nand.patch @@ -0,0 +1,31 @@ +From 71f568692a6d0a746d72c32d46a1bc09486b9dbb Mon Sep 17 00:00:00 2001 +From: Xiaolei Li +Date: Sat, 28 Oct 2017 14:52:23 +0800 +Subject: [PATCH 140/224] mtd: nand: mtk: change the compile sequence of + mtk_nand.o and mtk_ecc.o + +There will get mtk ecc handler during mtk nand probe now. +If mtk ecc module is not initialized, then mtk nand probe will return +-EPROBE_DEFER, and retry later. + +Change the compile sequence of mtk_nand.o and mtk_ecc.o, initialize mtk +ecc module before mtk nand module. This makes mtk nand module initialized +as soon as possible. + +Signed-off-by: Xiaolei Li +Signed-off-by: Boris Brezillon +--- + drivers/mtd/nand/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -59,7 +59,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o + obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ + obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o +-obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o mtk_ecc.o ++obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o + + nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o + nand-objs += nand_amd.o diff --git a/target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch b/target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch new file mode 100644 index 000000000..2750a2cc2 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0142-mmc-dt-bindings-Add-reg-source_cg-latch-ck-for-Media.patch @@ -0,0 +1,60 @@ +From 9ff279fef1a47a152993bf23f8d75fd233c27015 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:28 +0800 +Subject: [PATCH 142/224] mmc: dt-bindings: Add reg/source_cg/latch-ck for + Mediatek MMC bindings + +Change the comptiable for support of multi-platform +Make compatible explicit, as MMC host of mt8173 has difference with +mt8135(mt8173 supports hs400 and hs400_tune),so that need separate +mt8173/mt8135 compatible name. +Add description for reg +Add description for source_cg +Add description for mediatek,latch-ck +Note that source_cg and mediatek,latch-ck are optional for some projects, +eg, MT2701 do not have source_cg, and MT2712 do not need +mediatek,latch-ck + +Signed-off-by: Chaotian Jing +Acked-by: Rob Herring +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + Documentation/devicetree/bindings/mmc/mtk-sd.txt | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt ++++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt +@@ -7,10 +7,18 @@ This file documents differences between + and the properties used by the msdc driver. + + Required properties: +-- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc" ++- compatible: value should be either of the following. ++ "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135 ++ "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 ++ "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 ++ "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 ++- reg: physical base address of the controller and length + - interrupts: Should contain MSDC interrupt number +-- clocks: MSDC source clock, HCLK +-- clock-names: "source", "hclk" ++- clocks: Should contain phandle for the clock feeding the MMC controller ++- clock-names: Should contain the following: ++ "source" - source clock (required) ++ "hclk" - HCLK which used for host (required) ++ "source_cg" - independent source clock gate (required for MT2712) + - pinctrl-names: should be "default", "state_uhs" + - pinctrl-0: should contain default/high speed pin ctrl + - pinctrl-1: should contain uhs mode pin ctrl +@@ -30,6 +38,10 @@ Optional properties: + - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection + If present,HS400 command responses are sampled on rising edges. + If not present,HS400 command responses are sampled on falling edges. ++- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc ++ error caused by stop clock(fifo full) ++ Valid range = [0:0x7]. if not present, default value is 0. ++ applied to compatible "mediatek,mt2701-mmc". + + Examples: + mmc0: mmc@11230000 { diff --git a/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch b/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch new file mode 100644 index 000000000..9b43df80e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0143-mmc-mediatek-add-support-of-mt2701-mt2712.patch @@ -0,0 +1,187 @@ +From 8119f3e147deaf97a66e953fecf3d2b0edbb07fd Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:29 +0800 +Subject: [PATCH 143/224] mmc: mediatek: add support of mt2701/mt2712 + +mt2701/mt2712 has 12bit clock div, which is not compatible with +mt8135/mt8173. and, some additional features will be added in +mt2701/mt2712, so that need distinguish it by comatibale name. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 82 +++++++++++++++++++++++++++++++++++++++-------- + 1 file changed, 69 insertions(+), 13 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -95,6 +95,9 @@ + #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ + #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ + #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ ++#define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ ++#define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ ++#define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ + + /* MSDC_IOCON mask */ + #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ +@@ -295,6 +298,10 @@ struct msdc_save_para { + u32 emmc50_cfg0; + }; + ++struct mtk_mmc_compatible { ++ u8 clk_div_bits; ++}; ++ + struct msdc_tune_para { + u32 iocon; + u32 pad_tune; +@@ -309,6 +316,7 @@ struct msdc_delay_phase { + + struct msdc_host { + struct device *dev; ++ const struct mtk_mmc_compatible *dev_comp; + struct mmc_host *mmc; /* mmc structure */ + int cmd_rsp; + +@@ -350,6 +358,31 @@ struct msdc_host { + struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + }; + ++static const struct mtk_mmc_compatible mt8135_compat = { ++ .clk_div_bits = 8, ++}; ++ ++static const struct mtk_mmc_compatible mt8173_compat = { ++ .clk_div_bits = 8, ++}; ++ ++static const struct mtk_mmc_compatible mt2701_compat = { ++ .clk_div_bits = 12, ++}; ++ ++static const struct mtk_mmc_compatible mt2712_compat = { ++ .clk_div_bits = 12, ++}; ++ ++static const struct of_device_id msdc_of_ids[] = { ++ { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, ++ { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, ++ { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, ++ { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, msdc_of_ids); ++ + static void sdr_set_bits(void __iomem *reg, u32 bs) + { + u32 val = readl(reg); +@@ -509,7 +542,12 @@ static void msdc_set_timeout(struct msdc + timeout = (ns + clk_ns - 1) / clk_ns + clks; + /* in 1048576 sclk cycle unit */ + timeout = (timeout + (0x1 << 20) - 1) >> 20; +- sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); ++ if (host->dev_comp->clk_div_bits == 8) ++ sdr_get_field(host->base + MSDC_CFG, ++ MSDC_CFG_CKMOD, &mode); ++ else ++ sdr_get_field(host->base + MSDC_CFG, ++ MSDC_CFG_CKMOD_EXTRA, &mode); + /*DDR mode will double the clk cycles for data timeout */ + timeout = mode >= 2 ? timeout * 2 : timeout; + timeout = timeout > 1 ? timeout - 1 : 0; +@@ -548,7 +586,11 @@ static void msdc_set_mclk(struct msdc_ho + + flags = readl(host->base + MSDC_INTEN); + sdr_clr_bits(host->base + MSDC_INTEN, flags); +- sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); ++ if (host->dev_comp->clk_div_bits == 8) ++ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); ++ else ++ sdr_clr_bits(host->base + MSDC_CFG, ++ MSDC_CFG_HS400_CK_MODE_EXTRA); + if (timing == MMC_TIMING_UHS_DDR50 || + timing == MMC_TIMING_MMC_DDR52 || + timing == MMC_TIMING_MMC_HS400) { +@@ -568,8 +610,12 @@ static void msdc_set_mclk(struct msdc_ho + + if (timing == MMC_TIMING_MMC_HS400 && + hz >= (host->src_clk_freq >> 1)) { +- sdr_set_bits(host->base + MSDC_CFG, +- MSDC_CFG_HS400_CK_MODE); ++ if (host->dev_comp->clk_div_bits == 8) ++ sdr_set_bits(host->base + MSDC_CFG, ++ MSDC_CFG_HS400_CK_MODE); ++ else ++ sdr_set_bits(host->base + MSDC_CFG, ++ MSDC_CFG_HS400_CK_MODE_EXTRA); + sclk = host->src_clk_freq >> 1; + div = 0; /* div is ignore when bit18 is set */ + } +@@ -587,8 +633,15 @@ static void msdc_set_mclk(struct msdc_ho + sclk = (host->src_clk_freq >> 2) / div; + } + } +- sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, +- (mode << 8) | div); ++ if (host->dev_comp->clk_div_bits == 8) ++ sdr_set_field(host->base + MSDC_CFG, ++ MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, ++ (mode << 8) | div); ++ else ++ sdr_set_field(host->base + MSDC_CFG, ++ MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, ++ (mode << 12) | div); ++ + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) + cpu_relax(); +@@ -1617,12 +1670,17 @@ static int msdc_drv_probe(struct platfor + struct mmc_host *mmc; + struct msdc_host *host; + struct resource *res; ++ const struct of_device_id *of_id; + int ret; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } ++ ++ of_id = of_match_node(msdc_of_ids, pdev->dev.of_node); ++ if (!of_id) ++ return -EINVAL; + /* Allocate MMC host for this device */ + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); + if (!mmc) +@@ -1686,11 +1744,15 @@ static int msdc_drv_probe(struct platfor + msdc_of_property_parse(pdev, host); + + host->dev = &pdev->dev; ++ host->dev_comp = of_id->data; + host->mmc = mmc; + host->src_clk_freq = clk_get_rate(host->src_clk); + /* Set host parameters to mmc */ + mmc->ops = &mt_msdc_ops; +- mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); ++ if (host->dev_comp->clk_div_bits == 8) ++ mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); ++ else ++ mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); + + mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; + /* MMC core transfer sizes tunable parameters */ +@@ -1839,12 +1901,6 @@ static const struct dev_pm_ops msdc_dev_ + SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) + }; + +-static const struct of_device_id msdc_of_ids[] = { +- { .compatible = "mediatek,mt8135-mmc", }, +- {} +-}; +-MODULE_DEVICE_TABLE(of, msdc_of_ids); +- + static struct platform_driver mt_msdc_driver = { + .probe = msdc_drv_probe, + .remove = msdc_drv_remove, diff --git a/target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch b/target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch new file mode 100644 index 000000000..132ae8f4f --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0144-dt-bindings-ARM-Mediatek-Document-bindings-for-MT271.patch @@ -0,0 +1,196 @@ +From 815d90faddd22e05f05623086a9c42187fbfb1d8 Mon Sep 17 00:00:00 2001 +From: "weiyi.lu@mediatek.com" +Date: Mon, 23 Oct 2017 12:10:32 +0800 +Subject: [PATCH 144/224] dt-bindings: ARM: Mediatek: Document bindings for + MT2712 + +This patch adds the binding documentation for apmixedsys, bdpsys, +imgsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, pericfg, topckgen, +vdecsys and vencsys for Mediatek MT2712. + +Acked-by: Rob Herring +Signed-off-by: Weiyi Lu +Signed-off-by: Stephen Boyd +--- + .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,bdpsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + + .../bindings/arm/mediatek/mediatek,jpgdecsys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,mcucfg.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,mfgcfg.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 + + .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + + .../bindings/arm/mediatek/mediatek,vdecsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,vencsys.txt | 1 + + 12 files changed, 75 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-apmixedsys" ++ - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6797-apmixedsys" + - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8173-apmixedsys" +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be: + - "mediatek,mt2701-bdpsys", "syscon" ++ - "mediatek,mt2712-bdpsys", "syscon" + - #clock-cells: Must be 1 + + The bdpsys controller uses the common clk binding from +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-imgsys", "syscon" ++ - "mediatek,mt2712-imgsys", "syscon" + - "mediatek,mt6797-imgsys", "syscon" + - "mediatek,mt8173-imgsys", "syscon" + - #clock-cells: Must be 1 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +@@ -8,6 +8,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-infracfg", "syscon" ++ - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6797-infracfg", "syscon" + - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8173-infracfg", "syscon" +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt +@@ -0,0 +1,22 @@ ++Mediatek jpgdecsys controller ++============================ ++ ++The Mediatek jpgdecsys controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt2712-jpgdecsys", "syscon" ++- #clock-cells: Must be 1 ++ ++The jpgdecsys controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++jpgdecsys: syscon@19000000 { ++ compatible = "mediatek,mt2712-jpgdecsys", "syscon"; ++ reg = <0 0x19000000 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt +@@ -0,0 +1,22 @@ ++Mediatek mcucfg controller ++============================ ++ ++The Mediatek mcucfg controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be one of: ++ - "mediatek,mt2712-mcucfg", "syscon" ++- #clock-cells: Must be 1 ++ ++The mcucfg controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++mcucfg: syscon@10220000 { ++ compatible = "mediatek,mt2712-mcucfg", "syscon"; ++ reg = <0 0x10220000 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt +@@ -0,0 +1,22 @@ ++Mediatek mfgcfg controller ++============================ ++ ++The Mediatek mfgcfg controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be one of: ++ - "mediatek,mt2712-mfgcfg", "syscon" ++- #clock-cells: Must be 1 ++ ++The mfgcfg controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++mfgcfg: syscon@13000000 { ++ compatible = "mediatek,mt2712-mfgcfg", "syscon"; ++ reg = <0 0x13000000 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-mmsys", "syscon" ++ - "mediatek,mt2712-mmsys", "syscon" + - "mediatek,mt6797-mmsys", "syscon" + - "mediatek,mt8173-mmsys", "syscon" + - #clock-cells: Must be 1 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +@@ -8,6 +8,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-pericfg", "syscon" ++ - "mediatek,mt2712-pericfg", "syscon" + - "mediatek,mt8135-pericfg", "syscon" + - "mediatek,mt8173-pericfg", "syscon" + - #clock-cells: Must be 1 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-topckgen" ++ - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6797-topckgen" + - "mediatek,mt8135-topckgen" + - "mediatek,mt8173-topckgen" +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be one of: + - "mediatek,mt2701-vdecsys", "syscon" ++ - "mediatek,mt2712-vdecsys", "syscon" + - "mediatek,mt6797-vdecsys", "syscon" + - "mediatek,mt8173-vdecsys", "syscon" + - #clock-cells: Must be 1 +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides + Required Properties: + + - compatible: Should be one of: ++ - "mediatek,mt2712-vencsys", "syscon" + - "mediatek,mt6797-vencsys", "syscon" + - "mediatek,mt8173-vencsys", "syscon" + - #clock-cells: Must be 1 diff --git a/target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch b/target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch new file mode 100644 index 000000000..fb86c81bc --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0145-clk-mediatek-Add-dt-bindings-for-MT2712-clocks.patch @@ -0,0 +1,446 @@ +From 8a64bf0c04a4b7670cf56be5b0ae63fe9d6ecd56 Mon Sep 17 00:00:00 2001 +From: "weiyi.lu@mediatek.com" +Date: Mon, 23 Oct 2017 12:10:33 +0800 +Subject: [PATCH 145/224] clk: mediatek: Add dt-bindings for MT2712 clocks + +Add MT2712 clock dt-bindings, include topckgen, apmixedsys, +infracfg, pericfg, mcucfg and subsystem clocks. + +Signed-off-by: Weiyi Lu +Acked-by: Rob Herring +Signed-off-by: Stephen Boyd +--- + include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++ + 1 file changed, 427 insertions(+) + create mode 100644 include/dt-bindings/clock/mt2712-clk.h + +--- /dev/null ++++ b/include/dt-bindings/clock/mt2712-clk.h +@@ -0,0 +1,427 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT2712_H ++#define _DT_BINDINGS_CLK_MT2712_H ++ ++/* APMIXEDSYS */ ++ ++#define CLK_APMIXED_MAINPLL 0 ++#define CLK_APMIXED_UNIVPLL 1 ++#define CLK_APMIXED_VCODECPLL 2 ++#define CLK_APMIXED_VENCPLL 3 ++#define CLK_APMIXED_APLL1 4 ++#define CLK_APMIXED_APLL2 5 ++#define CLK_APMIXED_LVDSPLL 6 ++#define CLK_APMIXED_LVDSPLL2 7 ++#define CLK_APMIXED_MSDCPLL 8 ++#define CLK_APMIXED_MSDCPLL2 9 ++#define CLK_APMIXED_TVDPLL 10 ++#define CLK_APMIXED_MMPLL 11 ++#define CLK_APMIXED_ARMCA35PLL 12 ++#define CLK_APMIXED_ARMCA72PLL 13 ++#define CLK_APMIXED_ETHERPLL 14 ++#define CLK_APMIXED_NR_CLK 15 ++ ++/* TOPCKGEN */ ++ ++#define CLK_TOP_ARMCA35PLL 0 ++#define CLK_TOP_ARMCA35PLL_600M 1 ++#define CLK_TOP_ARMCA35PLL_400M 2 ++#define CLK_TOP_ARMCA72PLL 3 ++#define CLK_TOP_SYSPLL 4 ++#define CLK_TOP_SYSPLL_D2 5 ++#define CLK_TOP_SYSPLL1_D2 6 ++#define CLK_TOP_SYSPLL1_D4 7 ++#define CLK_TOP_SYSPLL1_D8 8 ++#define CLK_TOP_SYSPLL1_D16 9 ++#define CLK_TOP_SYSPLL_D3 10 ++#define CLK_TOP_SYSPLL2_D2 11 ++#define CLK_TOP_SYSPLL2_D4 12 ++#define CLK_TOP_SYSPLL_D5 13 ++#define CLK_TOP_SYSPLL3_D2 14 ++#define CLK_TOP_SYSPLL3_D4 15 ++#define CLK_TOP_SYSPLL_D7 16 ++#define CLK_TOP_SYSPLL4_D2 17 ++#define CLK_TOP_SYSPLL4_D4 18 ++#define CLK_TOP_UNIVPLL 19 ++#define CLK_TOP_UNIVPLL_D7 20 ++#define CLK_TOP_UNIVPLL_D26 21 ++#define CLK_TOP_UNIVPLL_D52 22 ++#define CLK_TOP_UNIVPLL_D104 23 ++#define CLK_TOP_UNIVPLL_D208 24 ++#define CLK_TOP_UNIVPLL_D2 25 ++#define CLK_TOP_UNIVPLL1_D2 26 ++#define CLK_TOP_UNIVPLL1_D4 27 ++#define CLK_TOP_UNIVPLL1_D8 28 ++#define CLK_TOP_UNIVPLL_D3 29 ++#define CLK_TOP_UNIVPLL2_D2 30 ++#define CLK_TOP_UNIVPLL2_D4 31 ++#define CLK_TOP_UNIVPLL2_D8 32 ++#define CLK_TOP_UNIVPLL_D5 33 ++#define CLK_TOP_UNIVPLL3_D2 34 ++#define CLK_TOP_UNIVPLL3_D4 35 ++#define CLK_TOP_UNIVPLL3_D8 36 ++#define CLK_TOP_F_MP0_PLL1 37 ++#define CLK_TOP_F_MP0_PLL2 38 ++#define CLK_TOP_F_BIG_PLL1 39 ++#define CLK_TOP_F_BIG_PLL2 40 ++#define CLK_TOP_F_BUS_PLL1 41 ++#define CLK_TOP_F_BUS_PLL2 42 ++#define CLK_TOP_APLL1 43 ++#define CLK_TOP_APLL1_D2 44 ++#define CLK_TOP_APLL1_D4 45 ++#define CLK_TOP_APLL1_D8 46 ++#define CLK_TOP_APLL1_D16 47 ++#define CLK_TOP_APLL2 48 ++#define CLK_TOP_APLL2_D2 49 ++#define CLK_TOP_APLL2_D4 50 ++#define CLK_TOP_APLL2_D8 51 ++#define CLK_TOP_APLL2_D16 52 ++#define CLK_TOP_LVDSPLL 53 ++#define CLK_TOP_LVDSPLL_D2 54 ++#define CLK_TOP_LVDSPLL_D4 55 ++#define CLK_TOP_LVDSPLL_D8 56 ++#define CLK_TOP_LVDSPLL2 57 ++#define CLK_TOP_LVDSPLL2_D2 58 ++#define CLK_TOP_LVDSPLL2_D4 59 ++#define CLK_TOP_LVDSPLL2_D8 60 ++#define CLK_TOP_ETHERPLL_125M 61 ++#define CLK_TOP_ETHERPLL_50M 62 ++#define CLK_TOP_CVBS 63 ++#define CLK_TOP_CVBS_D2 64 ++#define CLK_TOP_SYS_26M 65 ++#define CLK_TOP_MMPLL 66 ++#define CLK_TOP_MMPLL_D2 67 ++#define CLK_TOP_VENCPLL 68 ++#define CLK_TOP_VENCPLL_D2 69 ++#define CLK_TOP_VCODECPLL 70 ++#define CLK_TOP_VCODECPLL_D2 71 ++#define CLK_TOP_TVDPLL 72 ++#define CLK_TOP_TVDPLL_D2 73 ++#define CLK_TOP_TVDPLL_D4 74 ++#define CLK_TOP_TVDPLL_D8 75 ++#define CLK_TOP_TVDPLL_429M 76 ++#define CLK_TOP_TVDPLL_429M_D2 77 ++#define CLK_TOP_TVDPLL_429M_D4 78 ++#define CLK_TOP_MSDCPLL 79 ++#define CLK_TOP_MSDCPLL_D2 80 ++#define CLK_TOP_MSDCPLL_D4 81 ++#define CLK_TOP_MSDCPLL2 82 ++#define CLK_TOP_MSDCPLL2_D2 83 ++#define CLK_TOP_MSDCPLL2_D4 84 ++#define CLK_TOP_CLK26M_D2 85 ++#define CLK_TOP_D2A_ULCLK_6P5M 86 ++#define CLK_TOP_VPLL3_DPIX 87 ++#define CLK_TOP_VPLL_DPIX 88 ++#define CLK_TOP_LTEPLL_FS26M 89 ++#define CLK_TOP_DMPLL 90 ++#define CLK_TOP_DSI0_LNTC 91 ++#define CLK_TOP_DSI1_LNTC 92 ++#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 ++#define CLK_TOP_LVDSTX_CLKDIG_CTS 94 ++#define CLK_TOP_CLKRTC_EXT 95 ++#define CLK_TOP_CLKRTC_INT 96 ++#define CLK_TOP_CSI0 97 ++#define CLK_TOP_CVBSPLL 98 ++#define CLK_TOP_AXI_SEL 99 ++#define CLK_TOP_MEM_SEL 100 ++#define CLK_TOP_MM_SEL 101 ++#define CLK_TOP_PWM_SEL 102 ++#define CLK_TOP_VDEC_SEL 103 ++#define CLK_TOP_VENC_SEL 104 ++#define CLK_TOP_MFG_SEL 105 ++#define CLK_TOP_CAMTG_SEL 106 ++#define CLK_TOP_UART_SEL 107 ++#define CLK_TOP_SPI_SEL 108 ++#define CLK_TOP_USB20_SEL 109 ++#define CLK_TOP_USB30_SEL 110 ++#define CLK_TOP_MSDC50_0_HCLK_SEL 111 ++#define CLK_TOP_MSDC50_0_SEL 112 ++#define CLK_TOP_MSDC30_1_SEL 113 ++#define CLK_TOP_MSDC30_2_SEL 114 ++#define CLK_TOP_MSDC30_3_SEL 115 ++#define CLK_TOP_AUDIO_SEL 116 ++#define CLK_TOP_AUD_INTBUS_SEL 117 ++#define CLK_TOP_PMICSPI_SEL 118 ++#define CLK_TOP_DPILVDS1_SEL 119 ++#define CLK_TOP_ATB_SEL 120 ++#define CLK_TOP_NR_SEL 121 ++#define CLK_TOP_NFI2X_SEL 122 ++#define CLK_TOP_IRDA_SEL 123 ++#define CLK_TOP_CCI400_SEL 124 ++#define CLK_TOP_AUD_1_SEL 125 ++#define CLK_TOP_AUD_2_SEL 126 ++#define CLK_TOP_MEM_MFG_IN_AS_SEL 127 ++#define CLK_TOP_AXI_MFG_IN_AS_SEL 128 ++#define CLK_TOP_SCAM_SEL 129 ++#define CLK_TOP_NFIECC_SEL 130 ++#define CLK_TOP_PE2_MAC_P0_SEL 131 ++#define CLK_TOP_PE2_MAC_P1_SEL 132 ++#define CLK_TOP_DPILVDS_SEL 133 ++#define CLK_TOP_MSDC50_3_HCLK_SEL 134 ++#define CLK_TOP_HDCP_SEL 135 ++#define CLK_TOP_HDCP_24M_SEL 136 ++#define CLK_TOP_RTC_SEL 137 ++#define CLK_TOP_SPINOR_SEL 138 ++#define CLK_TOP_APLL_SEL 139 ++#define CLK_TOP_APLL2_SEL 140 ++#define CLK_TOP_A1SYS_HP_SEL 141 ++#define CLK_TOP_A2SYS_HP_SEL 142 ++#define CLK_TOP_ASM_L_SEL 143 ++#define CLK_TOP_ASM_M_SEL 144 ++#define CLK_TOP_ASM_H_SEL 145 ++#define CLK_TOP_I2SO1_SEL 146 ++#define CLK_TOP_I2SO2_SEL 147 ++#define CLK_TOP_I2SO3_SEL 148 ++#define CLK_TOP_TDMO0_SEL 149 ++#define CLK_TOP_TDMO1_SEL 150 ++#define CLK_TOP_I2SI1_SEL 151 ++#define CLK_TOP_I2SI2_SEL 152 ++#define CLK_TOP_I2SI3_SEL 153 ++#define CLK_TOP_ETHER_125M_SEL 154 ++#define CLK_TOP_ETHER_50M_SEL 155 ++#define CLK_TOP_JPGDEC_SEL 156 ++#define CLK_TOP_SPISLV_SEL 157 ++#define CLK_TOP_ETHER_50M_RMII_SEL 158 ++#define CLK_TOP_CAM2TG_SEL 159 ++#define CLK_TOP_DI_SEL 160 ++#define CLK_TOP_TVD_SEL 161 ++#define CLK_TOP_I2C_SEL 162 ++#define CLK_TOP_PWM_INFRA_SEL 163 ++#define CLK_TOP_MSDC0P_AES_SEL 164 ++#define CLK_TOP_CMSYS_SEL 165 ++#define CLK_TOP_GCPU_SEL 166 ++#define CLK_TOP_AUD_APLL1_SEL 167 ++#define CLK_TOP_AUD_APLL2_SEL 168 ++#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 ++#define CLK_TOP_APLL_DIV0 170 ++#define CLK_TOP_APLL_DIV1 171 ++#define CLK_TOP_APLL_DIV2 172 ++#define CLK_TOP_APLL_DIV3 173 ++#define CLK_TOP_APLL_DIV4 174 ++#define CLK_TOP_APLL_DIV5 175 ++#define CLK_TOP_APLL_DIV6 176 ++#define CLK_TOP_APLL_DIV7 177 ++#define CLK_TOP_APLL_DIV_PDN0 178 ++#define CLK_TOP_APLL_DIV_PDN1 179 ++#define CLK_TOP_APLL_DIV_PDN2 180 ++#define CLK_TOP_APLL_DIV_PDN3 181 ++#define CLK_TOP_APLL_DIV_PDN4 182 ++#define CLK_TOP_APLL_DIV_PDN5 183 ++#define CLK_TOP_APLL_DIV_PDN6 184 ++#define CLK_TOP_APLL_DIV_PDN7 185 ++#define CLK_TOP_NR_CLK 186 ++ ++/* INFRACFG */ ++ ++#define CLK_INFRA_DBGCLK 0 ++#define CLK_INFRA_GCE 1 ++#define CLK_INFRA_M4U 2 ++#define CLK_INFRA_KP 3 ++#define CLK_INFRA_AO_SPI0 4 ++#define CLK_INFRA_AO_SPI1 5 ++#define CLK_INFRA_AO_UART5 6 ++#define CLK_INFRA_NR_CLK 7 ++ ++/* PERICFG */ ++ ++#define CLK_PERI_NFI 0 ++#define CLK_PERI_THERM 1 ++#define CLK_PERI_PWM0 2 ++#define CLK_PERI_PWM1 3 ++#define CLK_PERI_PWM2 4 ++#define CLK_PERI_PWM3 5 ++#define CLK_PERI_PWM4 6 ++#define CLK_PERI_PWM5 7 ++#define CLK_PERI_PWM6 8 ++#define CLK_PERI_PWM7 9 ++#define CLK_PERI_PWM 10 ++#define CLK_PERI_AP_DMA 11 ++#define CLK_PERI_MSDC30_0 12 ++#define CLK_PERI_MSDC30_1 13 ++#define CLK_PERI_MSDC30_2 14 ++#define CLK_PERI_MSDC30_3 15 ++#define CLK_PERI_UART0 16 ++#define CLK_PERI_UART1 17 ++#define CLK_PERI_UART2 18 ++#define CLK_PERI_UART3 19 ++#define CLK_PERI_I2C0 20 ++#define CLK_PERI_I2C1 21 ++#define CLK_PERI_I2C2 22 ++#define CLK_PERI_I2C3 23 ++#define CLK_PERI_I2C4 24 ++#define CLK_PERI_AUXADC 25 ++#define CLK_PERI_SPI0 26 ++#define CLK_PERI_SPI 27 ++#define CLK_PERI_I2C5 28 ++#define CLK_PERI_SPI2 29 ++#define CLK_PERI_SPI3 30 ++#define CLK_PERI_SPI5 31 ++#define CLK_PERI_UART4 32 ++#define CLK_PERI_SFLASH 33 ++#define CLK_PERI_GMAC 34 ++#define CLK_PERI_PCIE0 35 ++#define CLK_PERI_PCIE1 36 ++#define CLK_PERI_GMAC_PCLK 37 ++#define CLK_PERI_MSDC50_0_EN 38 ++#define CLK_PERI_MSDC30_1_EN 39 ++#define CLK_PERI_MSDC30_2_EN 40 ++#define CLK_PERI_MSDC30_3_EN 41 ++#define CLK_PERI_MSDC50_0_HCLK_EN 42 ++#define CLK_PERI_MSDC50_3_HCLK_EN 43 ++#define CLK_PERI_NR_CLK 44 ++ ++/* MCUCFG */ ++ ++#define CLK_MCU_MP0_SEL 0 ++#define CLK_MCU_MP2_SEL 1 ++#define CLK_MCU_BUS_SEL 2 ++#define CLK_MCU_NR_CLK 3 ++ ++/* MFGCFG */ ++ ++#define CLK_MFG_BG3D 0 ++#define CLK_MFG_NR_CLK 1 ++ ++/* MMSYS */ ++ ++#define CLK_MM_SMI_COMMON 0 ++#define CLK_MM_SMI_LARB0 1 ++#define CLK_MM_CAM_MDP 2 ++#define CLK_MM_MDP_RDMA0 3 ++#define CLK_MM_MDP_RDMA1 4 ++#define CLK_MM_MDP_RSZ0 5 ++#define CLK_MM_MDP_RSZ1 6 ++#define CLK_MM_MDP_RSZ2 7 ++#define CLK_MM_MDP_TDSHP0 8 ++#define CLK_MM_MDP_TDSHP1 9 ++#define CLK_MM_MDP_CROP 10 ++#define CLK_MM_MDP_WDMA 11 ++#define CLK_MM_MDP_WROT0 12 ++#define CLK_MM_MDP_WROT1 13 ++#define CLK_MM_FAKE_ENG 14 ++#define CLK_MM_MUTEX_32K 15 ++#define CLK_MM_DISP_OVL0 16 ++#define CLK_MM_DISP_OVL1 17 ++#define CLK_MM_DISP_RDMA0 18 ++#define CLK_MM_DISP_RDMA1 19 ++#define CLK_MM_DISP_RDMA2 20 ++#define CLK_MM_DISP_WDMA0 21 ++#define CLK_MM_DISP_WDMA1 22 ++#define CLK_MM_DISP_COLOR0 23 ++#define CLK_MM_DISP_COLOR1 24 ++#define CLK_MM_DISP_AAL 25 ++#define CLK_MM_DISP_GAMMA 26 ++#define CLK_MM_DISP_UFOE 27 ++#define CLK_MM_DISP_SPLIT0 28 ++#define CLK_MM_DISP_OD 29 ++#define CLK_MM_DISP_PWM0_MM 30 ++#define CLK_MM_DISP_PWM0_26M 31 ++#define CLK_MM_DISP_PWM1_MM 32 ++#define CLK_MM_DISP_PWM1_26M 33 ++#define CLK_MM_DSI0_ENGINE 34 ++#define CLK_MM_DSI0_DIGITAL 35 ++#define CLK_MM_DSI1_ENGINE 36 ++#define CLK_MM_DSI1_DIGITAL 37 ++#define CLK_MM_DPI_PIXEL 38 ++#define CLK_MM_DPI_ENGINE 39 ++#define CLK_MM_DPI1_PIXEL 40 ++#define CLK_MM_DPI1_ENGINE 41 ++#define CLK_MM_LVDS_PIXEL 42 ++#define CLK_MM_LVDS_CTS 43 ++#define CLK_MM_SMI_LARB4 44 ++#define CLK_MM_SMI_COMMON1 45 ++#define CLK_MM_SMI_LARB5 46 ++#define CLK_MM_MDP_RDMA2 47 ++#define CLK_MM_MDP_TDSHP2 48 ++#define CLK_MM_DISP_OVL2 49 ++#define CLK_MM_DISP_WDMA2 50 ++#define CLK_MM_DISP_COLOR2 51 ++#define CLK_MM_DISP_AAL1 52 ++#define CLK_MM_DISP_OD1 53 ++#define CLK_MM_LVDS1_PIXEL 54 ++#define CLK_MM_LVDS1_CTS 55 ++#define CLK_MM_SMI_LARB7 56 ++#define CLK_MM_MDP_RDMA3 57 ++#define CLK_MM_MDP_WROT2 58 ++#define CLK_MM_DSI2 59 ++#define CLK_MM_DSI2_DIGITAL 60 ++#define CLK_MM_DSI3 61 ++#define CLK_MM_DSI3_DIGITAL 62 ++#define CLK_MM_NR_CLK 63 ++ ++/* IMGSYS */ ++ ++#define CLK_IMG_SMI_LARB2 0 ++#define CLK_IMG_SENINF_SCAM_EN 1 ++#define CLK_IMG_SENINF_CAM_EN 2 ++#define CLK_IMG_CAM_SV_EN 3 ++#define CLK_IMG_CAM_SV1_EN 4 ++#define CLK_IMG_CAM_SV2_EN 5 ++#define CLK_IMG_NR_CLK 6 ++ ++/* BDPSYS */ ++ ++#define CLK_BDP_BRIDGE_B 0 ++#define CLK_BDP_BRIDGE_DRAM 1 ++#define CLK_BDP_LARB_DRAM 2 ++#define CLK_BDP_WR_CHANNEL_VDI_PXL 3 ++#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 ++#define CLK_BDP_WR_CHANNEL_VDI_B 5 ++#define CLK_BDP_MT_B 6 ++#define CLK_BDP_DISPFMT_27M 7 ++#define CLK_BDP_DISPFMT_27M_VDOUT 8 ++#define CLK_BDP_DISPFMT_27_74_74 9 ++#define CLK_BDP_DISPFMT_2FS 10 ++#define CLK_BDP_DISPFMT_2FS_2FS74_148 11 ++#define CLK_BDP_DISPFMT_B 12 ++#define CLK_BDP_VDO_DRAM 13 ++#define CLK_BDP_VDO_2FS 14 ++#define CLK_BDP_VDO_B 15 ++#define CLK_BDP_WR_CHANNEL_DI_PXL 16 ++#define CLK_BDP_WR_CHANNEL_DI_DRAM 17 ++#define CLK_BDP_WR_CHANNEL_DI_B 18 ++#define CLK_BDP_NR_AGENT 19 ++#define CLK_BDP_NR_DRAM 20 ++#define CLK_BDP_NR_B 21 ++#define CLK_BDP_BRIDGE_RT_B 22 ++#define CLK_BDP_BRIDGE_RT_DRAM 23 ++#define CLK_BDP_LARB_RT_DRAM 24 ++#define CLK_BDP_TVD_TDC 25 ++#define CLK_BDP_TVD_54 26 ++#define CLK_BDP_TVD_CBUS 27 ++#define CLK_BDP_NR_CLK 28 ++ ++/* VDECSYS */ ++ ++#define CLK_VDEC_CKEN 0 ++#define CLK_VDEC_LARB1_CKEN 1 ++#define CLK_VDEC_IMGRZ_CKEN 2 ++#define CLK_VDEC_NR_CLK 3 ++ ++/* VENCSYS */ ++ ++#define CLK_VENC_SMI_COMMON_CON 0 ++#define CLK_VENC_VENC 1 ++#define CLK_VENC_SMI_LARB6 2 ++#define CLK_VENC_NR_CLK 3 ++ ++/* JPGDECSYS */ ++ ++#define CLK_JPGDEC_JPGDEC1 0 ++#define CLK_JPGDEC_JPGDEC 1 ++#define CLK_JPGDEC_NR_CLK 2 ++ ++#endif /* _DT_BINDINGS_CLK_MT2712_H */ diff --git a/target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch b/target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch new file mode 100644 index 000000000..98ddbd6af --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0146-clk-mediatek-Add-MT2712-clock-support.patch @@ -0,0 +1,2296 @@ +From ec5192303a3938d0972fde3b1f2526d8d6dd02d7 Mon Sep 17 00:00:00 2001 +From: "weiyi.lu@mediatek.com" +Date: Mon, 23 Oct 2017 12:10:34 +0800 +Subject: [PATCH 146/224] clk: mediatek: Add MT2712 clock support + +Add MT2712 clock support, include topckgen, apmixedsys, +infracfg, pericfg, mcucfg and subsystem clocks. + +Signed-off-by: Weiyi Lu +[sboyd@codeaurora.org: Static on top_clk_data] +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/Kconfig | 50 ++ + drivers/clk/mediatek/Makefile | 8 + + drivers/clk/mediatek/clk-mt2712-bdp.c | 102 +++ + drivers/clk/mediatek/clk-mt2712-img.c | 80 ++ + drivers/clk/mediatek/clk-mt2712-jpgdec.c | 76 ++ + drivers/clk/mediatek/clk-mt2712-mfg.c | 75 ++ + drivers/clk/mediatek/clk-mt2712-mm.c | 170 ++++ + drivers/clk/mediatek/clk-mt2712-vdec.c | 94 ++ + drivers/clk/mediatek/clk-mt2712-venc.c | 77 ++ + drivers/clk/mediatek/clk-mt2712.c | 1435 ++++++++++++++++++++++++++++++ + drivers/clk/mediatek/clk-mtk.h | 2 + + drivers/clk/mediatek/clk-pll.c | 13 +- + 12 files changed, 2180 insertions(+), 2 deletions(-) + create mode 100644 drivers/clk/mediatek/clk-mt2712-bdp.c + create mode 100644 drivers/clk/mediatek/clk-mt2712-img.c + create mode 100644 drivers/clk/mediatek/clk-mt2712-jpgdec.c + create mode 100644 drivers/clk/mediatek/clk-mt2712-mfg.c + create mode 100644 drivers/clk/mediatek/clk-mt2712-mm.c + create mode 100644 drivers/clk/mediatek/clk-mt2712-vdec.c + create mode 100644 drivers/clk/mediatek/clk-mt2712-venc.c + create mode 100644 drivers/clk/mediatek/clk-mt2712.c + +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS + ---help--- + This driver supports Mediatek MT2701 bdpsys clocks. + ++config COMMON_CLK_MT2712 ++ bool "Clock driver for Mediatek MT2712" ++ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK && ARM64 ++ ---help--- ++ This driver supports Mediatek MT2712 basic clocks. ++ ++config COMMON_CLK_MT2712_BDPSYS ++ bool "Clock driver for Mediatek MT2712 bdpsys" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 bdpsys clocks. ++ ++config COMMON_CLK_MT2712_IMGSYS ++ bool "Clock driver for Mediatek MT2712 imgsys" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 imgsys clocks. ++ ++config COMMON_CLK_MT2712_JPGDECSYS ++ bool "Clock driver for Mediatek MT2712 jpgdecsys" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 jpgdecsys clocks. ++ ++config COMMON_CLK_MT2712_MFGCFG ++ bool "Clock driver for Mediatek MT2712 mfgcfg" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 mfgcfg clocks. ++ ++config COMMON_CLK_MT2712_MMSYS ++ bool "Clock driver for Mediatek MT2712 mmsys" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 mmsys clocks. ++ ++config COMMON_CLK_MT2712_VDECSYS ++ bool "Clock driver for Mediatek MT2712 vdecsys" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 vdecsys clocks. ++ ++config COMMON_CLK_MT2712_VENCSYS ++ bool "Clock driver for Mediatek MT2712 vencsys" ++ depends on COMMON_CLK_MT2712 ++ ---help--- ++ This driver supports Mediatek MT2712 vencsys clocks. ++ + config COMMON_CLK_MT6797 + bool "Clock driver for Mediatek MT6797" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -13,5 +13,13 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) + + obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o + obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o + obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o ++obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o ++obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o ++obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o ++obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o ++obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o ++obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o ++obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o ++obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-bdp.c +@@ -0,0 +1,102 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs bdp_cg_regs = { ++ .set_ofs = 0x100, ++ .clr_ofs = 0x100, ++ .sta_ofs = 0x100, ++}; ++ ++#define GATE_BDP(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &bdp_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++static const struct mtk_gate bdp_clks[] = { ++ GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0), ++ GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1), ++ GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2), ++ GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3), ++ GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4), ++ GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5), ++ GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9), ++ GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10), ++ GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11), ++ GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12), ++ GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13), ++ GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14), ++ GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15), ++ GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16), ++ GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17), ++ GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18), ++ GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19), ++ GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20), ++ GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21), ++ GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22), ++ GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23), ++ GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24), ++ GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25), ++ GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26), ++ GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27), ++ GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28), ++ GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29), ++ GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30), ++}; ++ ++static int clk_mt2712_bdp_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK); ++ ++ mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_bdp[] = { ++ { .compatible = "mediatek,mt2712-bdpsys", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_bdp_drv = { ++ .probe = clk_mt2712_bdp_probe, ++ .driver = { ++ .name = "clk-mt2712-bdp", ++ .of_match_table = of_match_clk_mt2712_bdp, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_bdp_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-img.c +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs img_cg_regs = { ++ .set_ofs = 0x0, ++ .clr_ofs = 0x0, ++ .sta_ofs = 0x0, ++}; ++ ++#define GATE_IMG(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &img_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++static const struct mtk_gate img_clks[] = { ++ GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0), ++ GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3), ++ GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8), ++ GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9), ++ GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10), ++ GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11), ++}; ++ ++static int clk_mt2712_img_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); ++ ++ mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_img[] = { ++ { .compatible = "mediatek,mt2712-imgsys", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_img_drv = { ++ .probe = clk_mt2712_img_probe, ++ .driver = { ++ .name = "clk-mt2712-img", ++ .of_match_table = of_match_clk_mt2712_img, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_img_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c +@@ -0,0 +1,76 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs jpgdec_cg_regs = { ++ .set_ofs = 0x4, ++ .clr_ofs = 0x8, ++ .sta_ofs = 0x0, ++}; ++ ++#define GATE_JPGDEC(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &jpgdec_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr_inv, \ ++ } ++ ++static const struct mtk_gate jpgdec_clks[] = { ++ GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0), ++ GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4), ++}; ++ ++static int clk_mt2712_jpgdec_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK); ++ ++ mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_jpgdec[] = { ++ { .compatible = "mediatek,mt2712-jpgdecsys", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_jpgdec_drv = { ++ .probe = clk_mt2712_jpgdec_probe, ++ .driver = { ++ .name = "clk-mt2712-jpgdec", ++ .of_match_table = of_match_clk_mt2712_jpgdec, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_jpgdec_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-mfg.c +@@ -0,0 +1,75 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs mfg_cg_regs = { ++ .set_ofs = 0x4, ++ .clr_ofs = 0x8, ++ .sta_ofs = 0x0, ++}; ++ ++#define GATE_MFG(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &mfg_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate mfg_clks[] = { ++ GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), ++}; ++ ++static int clk_mt2712_mfg_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); ++ ++ mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_mfg[] = { ++ { .compatible = "mediatek,mt2712-mfgcfg", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_mfg_drv = { ++ .probe = clk_mt2712_mfg_probe, ++ .driver = { ++ .name = "clk-mt2712-mfg", ++ .of_match_table = of_match_clk_mt2712_mfg, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_mfg_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-mm.c +@@ -0,0 +1,170 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs mm0_cg_regs = { ++ .set_ofs = 0x104, ++ .clr_ofs = 0x108, ++ .sta_ofs = 0x100, ++}; ++ ++static const struct mtk_gate_regs mm1_cg_regs = { ++ .set_ofs = 0x114, ++ .clr_ofs = 0x118, ++ .sta_ofs = 0x110, ++}; ++ ++static const struct mtk_gate_regs mm2_cg_regs = { ++ .set_ofs = 0x224, ++ .clr_ofs = 0x228, ++ .sta_ofs = 0x220, ++}; ++ ++#define GATE_MM0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &mm0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_MM1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &mm1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_MM2(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &mm2_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate mm_clks[] = { ++ /* MM0 */ ++ GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0), ++ GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), ++ GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2), ++ GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3), ++ GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4), ++ GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5), ++ GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6), ++ GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7), ++ GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8), ++ GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9), ++ GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10), ++ GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11), ++ GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12), ++ GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13), ++ GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14), ++ GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15), ++ GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16), ++ GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17), ++ GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18), ++ GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19), ++ GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20), ++ GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21), ++ GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22), ++ GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23), ++ GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24), ++ GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25), ++ GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26), ++ GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27), ++ GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28), ++ GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31), ++ /* MM1 */ ++ GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0), ++ GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1), ++ GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2), ++ GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3), ++ GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4), ++ GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5), ++ GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6), ++ GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7), ++ GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8), ++ GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9), ++ GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10), ++ GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11), ++ GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16), ++ GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17), ++ GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18), ++ GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21), ++ GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22), ++ GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23), ++ GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24), ++ GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25), ++ GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26), ++ GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27), ++ GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28), ++ GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29), ++ GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30), ++ GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31), ++ /* MM2 */ ++ GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0), ++ GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1), ++ GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2), ++ GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3), ++ GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4), ++ GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5), ++ GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6), ++}; ++ ++static int clk_mt2712_mm_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); ++ ++ mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_mm[] = { ++ { .compatible = "mediatek,mt2712-mmsys", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_mm_drv = { ++ .probe = clk_mt2712_mm_probe, ++ .driver = { ++ .name = "clk-mt2712-mm", ++ .of_match_table = of_match_clk_mt2712_mm, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_mm_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-vdec.c +@@ -0,0 +1,94 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs vdec0_cg_regs = { ++ .set_ofs = 0x0, ++ .clr_ofs = 0x4, ++ .sta_ofs = 0x0, ++}; ++ ++static const struct mtk_gate_regs vdec1_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0xc, ++ .sta_ofs = 0x8, ++}; ++ ++#define GATE_VDEC0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &vdec0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr_inv, \ ++ } ++ ++#define GATE_VDEC1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &vdec1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr_inv, \ ++ } ++ ++static const struct mtk_gate vdec_clks[] = { ++ /* VDEC0 */ ++ GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), ++ /* VDEC1 */ ++ GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0), ++ GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1), ++}; ++ ++static int clk_mt2712_vdec_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); ++ ++ mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_vdec[] = { ++ { .compatible = "mediatek,mt2712-vdecsys", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_vdec_drv = { ++ .probe = clk_mt2712_vdec_probe, ++ .driver = { ++ .name = "clk-mt2712-vdec", ++ .of_match_table = of_match_clk_mt2712_vdec, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_vdec_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712-venc.c +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static const struct mtk_gate_regs venc_cg_regs = { ++ .set_ofs = 0x4, ++ .clr_ofs = 0x8, ++ .sta_ofs = 0x0, ++}; ++ ++#define GATE_VENC(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &venc_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr_inv, \ ++ } ++ ++static const struct mtk_gate venc_clks[] = { ++ GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0), ++ GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4), ++ GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12), ++}; ++ ++static int clk_mt2712_venc_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); ++ ++ mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712_venc[] = { ++ { .compatible = "mediatek,mt2712-vencsys", }, ++ {} ++}; ++ ++static struct platform_driver clk_mt2712_venc_drv = { ++ .probe = clk_mt2712_venc_probe, ++ .driver = { ++ .name = "clk-mt2712-venc", ++ .of_match_table = of_match_clk_mt2712_venc, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt2712_venc_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt2712.c +@@ -0,0 +1,1435 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Weiyi Lu ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++static DEFINE_SPINLOCK(mt2712_clk_lock); ++ ++static const struct mtk_fixed_clk top_fixed_clks[] = { ++ FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000), ++ FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000), ++ FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000), ++ FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000), ++ FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000), ++ FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000), ++ FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000), ++ FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000), ++ FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768), ++ FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747), ++ FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000), ++ FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), ++}; ++ ++static const struct mtk_fixed_factor top_early_divs[] = { ++ FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, ++ 1), ++ FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, ++ 2), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] = { ++ FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, ++ 1), ++ FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, ++ 3), ++ FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, ++ 1), ++ FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, ++ 1), ++ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, ++ 2), ++ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, ++ 4), ++ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, ++ 8), ++ FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, ++ 16), ++ FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, ++ 3), ++ FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, ++ 2), ++ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, ++ 4), ++ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, ++ 5), ++ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, ++ 2), ++ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, ++ 4), ++ FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, ++ 7), ++ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, ++ 2), ++ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, ++ 4), ++ FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, ++ 1), ++ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, ++ 7), ++ FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, ++ 26), ++ FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, ++ 52), ++ FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, ++ 104), ++ FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, ++ 208), ++ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, ++ 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, ++ 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, ++ 8), ++ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, ++ 3), ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, ++ 2), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, ++ 4), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, ++ 8), ++ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, ++ 5), ++ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, ++ 2), ++ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, ++ 4), ++ FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, ++ 8), ++ FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, ++ 1), ++ FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, ++ 1), ++ FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, ++ 1), ++ FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, ++ 1), ++ FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, ++ 1), ++ FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, ++ 1), ++ FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, ++ 1), ++ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, ++ 8), ++ FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, ++ 16), ++ FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, ++ 1), ++ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, ++ 8), ++ FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, ++ 16), ++ FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, ++ 1), ++ FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, ++ 8), ++ FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, ++ 1), ++ FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, ++ 8), ++ FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, ++ 1), ++ FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, ++ 1), ++ FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, ++ 1), ++ FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, ++ 2), ++ FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, ++ 1), ++ FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, ++ 1), ++ FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, ++ 1), ++ FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, ++ 1), ++ FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, ++ 8), ++ FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, ++ 1), ++ FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, ++ 2), ++ FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, ++ 4), ++ FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, ++ 1), ++ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, ++ 1), ++ FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, ++ 2), ++ FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, ++ 4), ++ FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, ++ 4), ++}; ++ ++static const char * const axi_parents[] = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "msdcpll2_ck" ++}; ++ ++static const char * const mem_parents[] = { ++ "clk26m", ++ "dmpll_ck" ++}; ++ ++static const char * const mm_parents[] = { ++ "clk26m", ++ "vencpll_ck", ++ "syspll_d3", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll1_d2", ++ "univpll2_d2" ++}; ++ ++static const char * const pwm_parents[] = { ++ "clk26m", ++ "univpll2_d4", ++ "univpll3_d2", ++ "univpll1_d4" ++}; ++ ++static const char * const vdec_parents[] = { ++ "clk26m", ++ "vcodecpll_ck", ++ "tvdpll_429m", ++ "univpll_d3", ++ "vencpll_ck", ++ "syspll_d3", ++ "univpll1_d2", ++ "mmpll_d2", ++ "syspll3_d2", ++ "tvdpll_ck" ++}; ++ ++static const char * const venc_parents[] = { ++ "clk26m", ++ "univpll1_d2", ++ "mmpll_d2", ++ "tvdpll_d2", ++ "syspll1_d2", ++ "univpll_d5", ++ "vcodecpll_d2", ++ "univpll2_d2", ++ "syspll3_d2" ++}; ++ ++static const char * const mfg_parents[] = { ++ "clk26m", ++ "mmpll_ck", ++ "univpll_d3", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "clk26m", ++ "syspll_d3", ++ "syspll1_d2", ++ "syspll_d5", ++ "univpll_d3", ++ "univpll1_d2", ++ "univpll_d5", ++ "univpll2_d2" ++}; ++ ++static const char * const camtg_parents[] = { ++ "clk26m", ++ "univpll_d52", ++ "univpll_d208", ++ "univpll_d104", ++ "clk26m_d2", ++ "univpll_d26", ++ "univpll2_d8", ++ "syspll3_d4", ++ "syspll3_d2", ++ "univpll1_d4", ++ "univpll2_d2" ++}; ++ ++static const char * const uart_parents[] = { ++ "clk26m", ++ "univpll2_d8" ++}; ++ ++static const char * const spi_parents[] = { ++ "clk26m", ++ "univpll2_d4", ++ "univpll1_d4", ++ "univpll2_d2", ++ "univpll3_d2", ++ "univpll1_d8" ++}; ++ ++static const char * const usb20_parents[] = { ++ "clk26m", ++ "univpll1_d8", ++ "univpll3_d4" ++}; ++ ++static const char * const usb30_parents[] = { ++ "clk26m", ++ "univpll3_d2", ++ "univpll3_d4", ++ "univpll2_d4" ++}; ++ ++static const char * const msdc50_0_h_parents[] = { ++ "clk26m", ++ "syspll1_d2", ++ "syspll2_d2", ++ "syspll4_d2", ++ "univpll_d5", ++ "univpll1_d4" ++}; ++ ++static const char * const msdc50_0_parents[] = { ++ "clk26m", ++ "msdcpll_ck", ++ "msdcpll_d2", ++ "univpll1_d4", ++ "syspll2_d2", ++ "msdcpll_d4", ++ "vencpll_d2", ++ "univpll1_d2", ++ "msdcpll2_ck", ++ "msdcpll2_d2", ++ "msdcpll2_d4" ++}; ++ ++static const char * const msdc30_1_parents[] = { ++ "clk26m", ++ "univpll2_d2", ++ "msdcpll_d2", ++ "univpll1_d4", ++ "syspll2_d2", ++ "univpll_d7", ++ "vencpll_d2" ++}; ++ ++static const char * const msdc30_3_parents[] = { ++ "clk26m", ++ "msdcpll2_ck", ++ "msdcpll2_d2", ++ "univpll2_d2", ++ "msdcpll2_d4", ++ "univpll1_d4", ++ "syspll2_d2", ++ "syspll_d7", ++ "univpll_d7", ++ "vencpll_d2", ++ "msdcpll_ck", ++ "msdcpll_d2", ++ "msdcpll_d4" ++}; ++ ++static const char * const audio_parents[] = { ++ "clk26m", ++ "syspll3_d4", ++ "syspll4_d4", ++ "syspll1_d16" ++}; ++ ++static const char * const aud_intbus_parents[] = { ++ "clk26m", ++ "syspll1_d4", ++ "syspll4_d2", ++ "univpll3_d2", ++ "univpll2_d8", ++ "syspll3_d2", ++ "syspll3_d4" ++}; ++ ++static const char * const pmicspi_parents[] = { ++ "clk26m", ++ "syspll1_d8", ++ "syspll3_d4", ++ "syspll1_d16", ++ "univpll3_d4", ++ "univpll_d26", ++ "syspll3_d4" ++}; ++ ++static const char * const dpilvds1_parents[] = { ++ "clk26m", ++ "lvdspll2_ck", ++ "lvdspll2_d2", ++ "lvdspll2_d4", ++ "lvdspll2_d8", ++ "clkfpc" ++}; ++ ++static const char * const atb_parents[] = { ++ "clk26m", ++ "syspll1_d2", ++ "univpll_d5", ++ "syspll_d5" ++}; ++ ++static const char * const nr_parents[] = { ++ "clk26m", ++ "univpll1_d4", ++ "syspll2_d2", ++ "syspll1_d4", ++ "univpll1_d8", ++ "univpll3_d2", ++ "univpll2_d2", ++ "syspll_d5" ++}; ++ ++static const char * const nfi2x_parents[] = { ++ "clk26m", ++ "syspll4_d4", ++ "univpll3_d4", ++ "univpll1_d8", ++ "syspll2_d4", ++ "univpll3_d2", ++ "syspll_d7", ++ "syspll2_d2", ++ "univpll2_d2", ++ "syspll_d5", ++ "syspll1_d2" ++}; ++ ++static const char * const irda_parents[] = { ++ "clk26m", ++ "univpll2_d4", ++ "syspll2_d4", ++ "univpll2_d8" ++}; ++ ++static const char * const cci400_parents[] = { ++ "clk26m", ++ "vencpll_ck", ++ "armca35pll_600m", ++ "armca35pll_400m", ++ "univpll_d2", ++ "syspll_d2", ++ "msdcpll_ck", ++ "univpll_d3" ++}; ++ ++static const char * const aud_1_parents[] = { ++ "clk26m", ++ "apll1_ck", ++ "univpll2_d4", ++ "univpll2_d8" ++}; ++ ++static const char * const aud_2_parents[] = { ++ "clk26m", ++ "apll2_ck", ++ "univpll2_d4", ++ "univpll2_d8" ++}; ++ ++static const char * const mem_mfg_parents[] = { ++ "clk26m", ++ "mmpll_ck", ++ "univpll_d3" ++}; ++ ++static const char * const axi_mfg_parents[] = { ++ "clk26m", ++ "axi_sel", ++ "univpll_d5" ++}; ++ ++static const char * const scam_parents[] = { ++ "clk26m", ++ "syspll3_d2", ++ "univpll2_d4", ++ "syspll2_d4" ++}; ++ ++static const char * const nfiecc_parents[] = { ++ "clk26m", ++ "nfi2x_sel", ++ "syspll_d7", ++ "syspll2_d2", ++ "univpll2_d2", ++ "univpll_d5", ++ "syspll1_d2" ++}; ++ ++static const char * const pe2_mac_p0_parents[] = { ++ "clk26m", ++ "syspll1_d8", ++ "syspll4_d2", ++ "syspll2_d4", ++ "univpll2_d4", ++ "syspll3_d2" ++}; ++ ++static const char * const dpilvds_parents[] = { ++ "clk26m", ++ "lvdspll_ck", ++ "lvdspll_d2", ++ "lvdspll_d4", ++ "lvdspll_d8", ++ "clkfpc" ++}; ++ ++static const char * const hdcp_parents[] = { ++ "clk26m", ++ "syspll4_d2", ++ "syspll3_d4", ++ "univpll2_d4" ++}; ++ ++static const char * const hdcp_24m_parents[] = { ++ "clk26m", ++ "univpll_d26", ++ "univpll_d52", ++ "univpll2_d8" ++}; ++ ++static const char * const rtc_parents[] = { ++ "clkrtc_int", ++ "clkrtc_ext", ++ "clk26m", ++ "univpll3_d8" ++}; ++ ++static const char * const spinor_parents[] = { ++ "clk26m", ++ "clk26m_d2", ++ "syspll4_d4", ++ "univpll2_d8", ++ "univpll3_d4", ++ "syspll4_d2", ++ "syspll2_d4", ++ "univpll2_d4", ++ "etherpll_125m", ++ "syspll1_d4" ++}; ++ ++static const char * const apll_parents[] = { ++ "clk26m", ++ "apll1_ck", ++ "apll1_d2", ++ "apll1_d4", ++ "apll1_d8", ++ "apll1_d16", ++ "apll2_ck", ++ "apll2_d2", ++ "apll2_d4", ++ "apll2_d8", ++ "apll2_d16", ++ "clk26m", ++ "clk26m" ++}; ++ ++static const char * const a1sys_hp_parents[] = { ++ "clk26m", ++ "apll1_ck", ++ "apll1_d2", ++ "apll1_d4", ++ "apll1_d8" ++}; ++ ++static const char * const a2sys_hp_parents[] = { ++ "clk26m", ++ "apll2_ck", ++ "apll2_d2", ++ "apll2_d4", ++ "apll2_d8" ++}; ++ ++static const char * const asm_l_parents[] = { ++ "clk26m", ++ "univpll2_d4", ++ "univpll2_d2", ++ "syspll_d5" ++}; ++ ++static const char * const i2so1_parents[] = { ++ "clk26m", ++ "apll1_ck", ++ "apll2_ck" ++}; ++ ++static const char * const ether_125m_parents[] = { ++ "clk26m", ++ "etherpll_125m", ++ "univpll3_d2" ++}; ++ ++static const char * const ether_50m_parents[] = { ++ "clk26m", ++ "etherpll_50m", ++ "univpll_d26", ++ "univpll3_d4" ++}; ++ ++static const char * const jpgdec_parents[] = { ++ "clk26m", ++ "univpll_d3", ++ "tvdpll_429m", ++ "vencpll_ck", ++ "syspll_d3", ++ "vcodecpll_ck", ++ "univpll1_d2", ++ "armca35pll_400m", ++ "tvdpll_429m_d2", ++ "tvdpll_429m_d4" ++}; ++ ++static const char * const spislv_parents[] = { ++ "clk26m", ++ "univpll2_d4", ++ "univpll1_d4", ++ "univpll2_d2", ++ "univpll3_d2", ++ "univpll1_d8", ++ "univpll1_d2", ++ "univpll_d5" ++}; ++ ++static const char * const ether_parents[] = { ++ "clk26m", ++ "etherpll_50m", ++ "univpll_d26" ++}; ++ ++static const char * const di_parents[] = { ++ "clk26m", ++ "tvdpll_d2", ++ "tvdpll_d4", ++ "tvdpll_d8", ++ "vencpll_ck", ++ "vencpll_d2", ++ "cvbs", ++ "cvbs_d2" ++}; ++ ++static const char * const tvd_parents[] = { ++ "clk26m", ++ "cvbs_d2", ++ "univpll2_d8" ++}; ++ ++static const char * const i2c_parents[] = { ++ "clk26m", ++ "univpll_d26", ++ "univpll2_d4", ++ "univpll3_d2", ++ "univpll1_d4" ++}; ++ ++static const char * const msdc0p_aes_parents[] = { ++ "clk26m", ++ "msdcpll_ck", ++ "univpll_d3", ++ "vcodecpll_ck" ++}; ++ ++static const char * const cmsys_parents[] = { ++ "clk26m", ++ "univpll_d3", ++ "syspll_d3", ++ "syspll1_d2", ++ "syspll2_d2" ++}; ++ ++static const char * const gcpu_parents[] = { ++ "clk26m", ++ "syspll_d3", ++ "syspll1_d2", ++ "univpll1_d2", ++ "univpll_d5", ++ "univpll3_d2", ++ "univpll_d3" ++}; ++ ++static const char * const aud_apll1_parents[] = { ++ "apll1", ++ "clkaud_ext_i_1" ++}; ++ ++static const char * const aud_apll2_parents[] = { ++ "apll2", ++ "clkaud_ext_i_2" ++}; ++ ++static const char * const audull_vtx_parents[] = { ++ "d2a_ulclk_6p5m", ++ "clkaud_ext_i_0" ++}; ++ ++static struct mtk_composite top_muxes[] = { ++ /* CLK_CFG_0 */ ++ MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, ++ 7, CLK_IS_CRITICAL), ++ MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, ++ 15, CLK_IS_CRITICAL), ++ MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", ++ mm_parents, 0x040, 24, 3, 31), ++ /* CLK_CFG_1 */ ++ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", ++ pwm_parents, 0x050, 0, 2, 7), ++ MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", ++ vdec_parents, 0x050, 8, 4, 15), ++ MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", ++ venc_parents, 0x050, 16, 4, 23), ++ MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", ++ mfg_parents, 0x050, 24, 4, 31), ++ /* CLK_CFG_2 */ ++ MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", ++ camtg_parents, 0x060, 0, 4, 7), ++ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", ++ uart_parents, 0x060, 8, 1, 15), ++ MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", ++ spi_parents, 0x060, 16, 3, 23), ++ MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", ++ usb20_parents, 0x060, 24, 2, 31), ++ /* CLK_CFG_3 */ ++ MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", ++ usb30_parents, 0x070, 0, 2, 7), ++ MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", ++ msdc50_0_h_parents, 0x070, 8, 3, 15), ++ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", ++ msdc50_0_parents, 0x070, 16, 4, 23), ++ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", ++ msdc30_1_parents, 0x070, 24, 3, 31), ++ /* CLK_CFG_4 */ ++ MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", ++ msdc30_1_parents, 0x080, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", ++ msdc30_3_parents, 0x080, 8, 4, 15), ++ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", ++ audio_parents, 0x080, 16, 2, 23), ++ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", ++ aud_intbus_parents, 0x080, 24, 3, 31), ++ /* CLK_CFG_5 */ ++ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", ++ pmicspi_parents, 0x090, 0, 3, 7), ++ MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", ++ dpilvds1_parents, 0x090, 8, 3, 15), ++ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", ++ atb_parents, 0x090, 16, 2, 23), ++ MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", ++ nr_parents, 0x090, 24, 3, 31), ++ /* CLK_CFG_6 */ ++ MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", ++ nfi2x_parents, 0x0a0, 0, 4, 7), ++ MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", ++ irda_parents, 0x0a0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", ++ cci400_parents, 0x0a0, 16, 3, 23), ++ MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", ++ aud_1_parents, 0x0a0, 24, 2, 31), ++ /* CLK_CFG_7 */ ++ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", ++ aud_2_parents, 0x0b0, 0, 2, 7), ++ MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", ++ mem_mfg_parents, 0x0b0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", ++ axi_mfg_parents, 0x0b0, 16, 2, 23), ++ MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", ++ scam_parents, 0x0b0, 24, 2, 31), ++ /* CLK_CFG_8 */ ++ MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", ++ nfiecc_parents, 0x0c0, 0, 3, 7), ++ MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", ++ pe2_mac_p0_parents, 0x0c0, 8, 3, 15), ++ MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", ++ pe2_mac_p0_parents, 0x0c0, 16, 3, 23), ++ MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", ++ dpilvds_parents, 0x0c0, 24, 3, 31), ++ /* CLK_CFG_9 */ ++ MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", ++ msdc50_0_h_parents, 0x0d0, 0, 3, 7), ++ MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", ++ hdcp_parents, 0x0d0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", ++ hdcp_24m_parents, 0x0d0, 16, 2, 23), ++ MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2, ++ 31, CLK_IS_CRITICAL), ++ /* CLK_CFG_10 */ ++ MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", ++ spinor_parents, 0x500, 0, 4, 7), ++ MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", ++ apll_parents, 0x500, 8, 4, 15), ++ MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", ++ apll_parents, 0x500, 16, 4, 23), ++ MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", ++ a1sys_hp_parents, 0x500, 24, 3, 31), ++ /* CLK_CFG_11 */ ++ MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", ++ a2sys_hp_parents, 0x510, 0, 3, 7), ++ MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", ++ asm_l_parents, 0x510, 8, 2, 15), ++ MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", ++ asm_l_parents, 0x510, 16, 2, 23), ++ MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", ++ asm_l_parents, 0x510, 24, 2, 31), ++ /* CLK_CFG_12 */ ++ MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", ++ i2so1_parents, 0x520, 0, 2, 7), ++ MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", ++ i2so1_parents, 0x520, 8, 2, 15), ++ MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", ++ i2so1_parents, 0x520, 16, 2, 23), ++ MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", ++ i2so1_parents, 0x520, 24, 2, 31), ++ /* CLK_CFG_13 */ ++ MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", ++ i2so1_parents, 0x530, 0, 2, 7), ++ MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", ++ i2so1_parents, 0x530, 8, 2, 15), ++ MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", ++ i2so1_parents, 0x530, 16, 2, 23), ++ MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", ++ i2so1_parents, 0x530, 24, 2, 31), ++ /* CLK_CFG_14 */ ++ MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", ++ ether_125m_parents, 0x540, 0, 2, 7), ++ MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", ++ ether_50m_parents, 0x540, 8, 2, 15), ++ MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", ++ jpgdec_parents, 0x540, 16, 4, 23), ++ MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", ++ spislv_parents, 0x540, 24, 3, 31), ++ /* CLK_CFG_15 */ ++ MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ++ ether_parents, 0x550, 0, 2, 7), ++ MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", ++ camtg_parents, 0x550, 8, 4, 15), ++ MUX_GATE(CLK_TOP_DI_SEL, "di_sel", ++ di_parents, 0x550, 16, 3, 23), ++ MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", ++ tvd_parents, 0x550, 24, 2, 31), ++ /* CLK_CFG_16 */ ++ MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", ++ i2c_parents, 0x560, 0, 3, 7), ++ MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", ++ pwm_parents, 0x560, 8, 2, 15), ++ MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", ++ msdc0p_aes_parents, 0x560, 16, 2, 23), ++ MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", ++ cmsys_parents, 0x560, 24, 3, 31), ++ /* CLK_CFG_17 */ ++ MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", ++ gcpu_parents, 0x570, 0, 3, 7), ++ /* CLK_AUDDIV_4 */ ++ MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", ++ aud_apll1_parents, 0x134, 0, 1), ++ MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", ++ aud_apll2_parents, 0x134, 1, 1), ++ MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", ++ audull_vtx_parents, 0x134, 31, 1), ++}; ++ ++static const char * const mcu_mp0_parents[] = { ++ "clk26m", ++ "armca35pll_ck", ++ "f_mp0_pll1_ck", ++ "f_mp0_pll2_ck" ++}; ++ ++static const char * const mcu_mp2_parents[] = { ++ "clk26m", ++ "armca72pll_ck", ++ "f_big_pll1_ck", ++ "f_big_pll2_ck" ++}; ++ ++static const char * const mcu_bus_parents[] = { ++ "clk26m", ++ "cci400_sel", ++ "f_bus_pll1_ck", ++ "f_bus_pll2_ck" ++}; ++ ++static struct mtk_composite mcu_muxes[] = { ++ /* mp0_pll_divider_cfg */ ++ MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, ++ 9, 2, -1, CLK_IS_CRITICAL), ++ /* mp2_pll_divider_cfg */ ++ MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, ++ 9, 2, -1, CLK_IS_CRITICAL), ++ /* bus_pll_divider_cfg */ ++ MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, ++ 9, 2, -1, CLK_IS_CRITICAL), ++}; ++ ++static const struct mtk_clk_divider top_adj_divs[] = { ++ DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8), ++ DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8), ++}; ++ ++static const struct mtk_gate_regs top_cg_regs = { ++ .set_ofs = 0x120, ++ .clr_ofs = 0x120, ++ .sta_ofs = 0x120, ++}; ++ ++#define GATE_TOP(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &top_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++static const struct mtk_gate top_clks[] = { ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6), ++ GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7), ++}; ++ ++static const struct mtk_gate_regs infra_cg_regs = { ++ .set_ofs = 0x40, ++ .clr_ofs = 0x44, ++ .sta_ofs = 0x40, ++}; ++ ++#define GATE_INFRA(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &infra_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static const struct mtk_gate infra_clks[] = { ++ GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), ++ GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), ++ GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), ++ GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), ++ GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24), ++ GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25), ++ GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26), ++}; ++ ++static const struct mtk_gate_regs peri0_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0x10, ++ .sta_ofs = 0x18, ++}; ++ ++static const struct mtk_gate_regs peri1_cg_regs = { ++ .set_ofs = 0xc, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x1c, ++}; ++ ++static const struct mtk_gate_regs peri2_cg_regs = { ++ .set_ofs = 0x42c, ++ .clr_ofs = 0x42c, ++ .sta_ofs = 0x42c, ++}; ++ ++#define GATE_PERI0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI2(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri2_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate peri_clks[] = { ++ /* PERI0 */ ++ GATE_PERI0(CLK_PERI_NFI, "per_nfi", ++ "axi_sel", 0), ++ GATE_PERI0(CLK_PERI_THERM, "per_therm", ++ "axi_sel", 1), ++ GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", ++ "pwm_sel", 2), ++ GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", ++ "pwm_sel", 3), ++ GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", ++ "pwm_sel", 4), ++ GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", ++ "pwm_sel", 5), ++ GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", ++ "pwm_sel", 6), ++ GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", ++ "pwm_sel", 7), ++ GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", ++ "pwm_sel", 8), ++ GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", ++ "pwm_sel", 9), ++ GATE_PERI0(CLK_PERI_PWM, "per_pwm", ++ "pwm_sel", 10), ++ GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", ++ "axi_sel", 13), ++ GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", ++ "msdc50_0_sel", 14), ++ GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", ++ "msdc30_1_sel", 15), ++ GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", ++ "msdc30_2_sel", 16), ++ GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", ++ "msdc30_3_sel", 17), ++ GATE_PERI0(CLK_PERI_UART0, "per_uart0", ++ "uart_sel", 20), ++ GATE_PERI0(CLK_PERI_UART1, "per_uart1", ++ "uart_sel", 21), ++ GATE_PERI0(CLK_PERI_UART2, "per_uart2", ++ "uart_sel", 22), ++ GATE_PERI0(CLK_PERI_UART3, "per_uart3", ++ "uart_sel", 23), ++ GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", ++ "axi_sel", 24), ++ GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", ++ "axi_sel", 25), ++ GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", ++ "axi_sel", 26), ++ GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", ++ "axi_sel", 27), ++ GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", ++ "axi_sel", 28), ++ GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", ++ "ltepll_fs26m", 29), ++ GATE_PERI0(CLK_PERI_SPI0, "per_spi0", ++ "spi_sel", 30), ++ /* PERI1 */ ++ GATE_PERI1(CLK_PERI_SPI, "per_spi", ++ "spinor_sel", 1), ++ GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", ++ "axi_sel", 3), ++ GATE_PERI1(CLK_PERI_SPI2, "per_spi2", ++ "spi_sel", 5), ++ GATE_PERI1(CLK_PERI_SPI3, "per_spi3", ++ "spi_sel", 6), ++ GATE_PERI1(CLK_PERI_SPI5, "per_spi5", ++ "spi_sel", 8), ++ GATE_PERI1(CLK_PERI_UART4, "per_uart4", ++ "uart_sel", 9), ++ GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", ++ "uart_sel", 11), ++ GATE_PERI1(CLK_PERI_GMAC, "per_gmac", ++ "uart_sel", 12), ++ GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", ++ "uart_sel", 14), ++ GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", ++ "uart_sel", 15), ++ GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", ++ "uart_sel", 16), ++ /* PERI2 */ ++ GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", ++ "msdc50_0_sel", 0), ++ GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", ++ "msdc30_1_sel", 1), ++ GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", ++ "msdc30_2_sel", 2), ++ GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", ++ "msdc30_3_sel", 3), ++ GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", ++ "msdc50_0_h_sel", 4), ++ GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", ++ "msdc50_3_h_sel", 5), ++}; ++ ++#define MT2712_PLL_FMAX (3000UL * MHZ) ++ ++#define CON0_MT2712_RST_BAR BIT(24) ++ ++#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ ++ _tuner_en_bit, _pcw_reg, _pcw_shift, \ ++ _div_table) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = CON0_MT2712_RST_BAR, \ ++ .fmax = MT2712_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .tuner_en_reg = _tuner_en_reg, \ ++ .tuner_en_bit = _tuner_en_bit, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ .div_table = _div_table, \ ++ } ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ ++ _tuner_en_bit, _pcw_reg, _pcw_shift) \ ++ PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ ++ _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ ++ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ ++ _pcw_shift, NULL) ++ ++static const struct mtk_pll_div_table armca35pll_div_table[] = { ++ { .div = 0, .freq = MT2712_PLL_FMAX }, ++ { .div = 1, .freq = 1202500000 }, ++ { .div = 2, .freq = 500500000 }, ++ { .div = 3, .freq = 315250000 }, ++ { .div = 4, .freq = 157625000 }, ++ { } /* sentinel */ ++}; ++ ++static const struct mtk_pll_div_table armca72pll_div_table[] = { ++ { .div = 0, .freq = MT2712_PLL_FMAX }, ++ { .div = 1, .freq = 994500000 }, ++ { .div = 2, .freq = 520000000 }, ++ { .div = 3, .freq = 315250000 }, ++ { .div = 4, .freq = 157625000 }, ++ { } /* sentinel */ ++}; ++ ++static const struct mtk_pll_div_table mmpll_div_table[] = { ++ { .div = 0, .freq = MT2712_PLL_FMAX }, ++ { .div = 1, .freq = 1001000000 }, ++ { .div = 2, .freq = 601250000 }, ++ { .div = 3, .freq = 250250000 }, ++ { .div = 4, .freq = 125125000 }, ++ { } /* sentinel */ ++}; ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101, ++ HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), ++ PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101, ++ HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), ++ PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101, ++ 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), ++ PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101, ++ 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), ++ PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101, ++ 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), ++ PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101, ++ 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), ++ PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101, ++ 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), ++ PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101, ++ 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), ++ PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101, ++ 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), ++ PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101, ++ 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), ++ PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101, ++ 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), ++ PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101, ++ 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, ++ mmpll_div_table), ++ PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101, ++ HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, ++ armca35pll_div_table), ++ PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101, ++ 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, ++ armca72pll_div_table), ++ PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101, ++ 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), ++}; ++ ++static int clk_mt2712_apmixed_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static struct clk_onecell_data *top_clk_data; ++ ++static void clk_mt2712_top_init_early(struct device_node *node) ++{ ++ int r, i; ++ ++ if (!top_clk_data) { ++ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ ++ for (i = 0; i < CLK_TOP_NR_CLK; i++) ++ top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), ++ top_clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); ++ if (r) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++} ++ ++CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen", ++ clk_mt2712_top_init_early); ++ ++static int clk_mt2712_top_probe(struct platform_device *pdev) ++{ ++ int r, i; ++ struct device_node *node = pdev->dev.of_node; ++ void __iomem *base; ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return PTR_ERR(base); ++ } ++ ++ if (!top_clk_data) { ++ top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ } else { ++ for (i = 0; i < CLK_TOP_NR_CLK; i++) { ++ if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) ++ top_clk_data->clks[i] = ERR_PTR(-ENOENT); ++ } ++ } ++ ++ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), ++ top_clk_data); ++ mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), ++ top_clk_data); ++ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); ++ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, ++ &mt2712_clk_lock, top_clk_data); ++ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, ++ &mt2712_clk_lock, top_clk_data); ++ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), ++ top_clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static int clk_mt2712_infra_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ ++ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0x30); ++ ++ return r; ++} ++ ++static int clk_mt2712_peri_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ ++ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ mtk_register_reset_controller(node, 2, 0); ++ ++ return r; ++} ++ ++static int clk_mt2712_mcu_probe(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ void __iomem *base; ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) { ++ pr_err("%s(): ioremap failed\n", __func__); ++ return PTR_ERR(base); ++ } ++ ++ clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); ++ ++ mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, ++ &mt2712_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ ++ if (r != 0) ++ pr_err("%s(): could not register clock provider: %d\n", ++ __func__, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt2712[] = { ++ { ++ .compatible = "mediatek,mt2712-apmixedsys", ++ .data = clk_mt2712_apmixed_probe, ++ }, { ++ .compatible = "mediatek,mt2712-topckgen", ++ .data = clk_mt2712_top_probe, ++ }, { ++ .compatible = "mediatek,mt2712-infracfg", ++ .data = clk_mt2712_infra_probe, ++ }, { ++ .compatible = "mediatek,mt2712-pericfg", ++ .data = clk_mt2712_peri_probe, ++ }, { ++ .compatible = "mediatek,mt2712-mcucfg", ++ .data = clk_mt2712_mcu_probe, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt2712_probe(struct platform_device *pdev) ++{ ++ int (*clk_probe)(struct platform_device *); ++ int r; ++ ++ clk_probe = of_device_get_match_data(&pdev->dev); ++ if (!clk_probe) ++ return -EINVAL; ++ ++ r = clk_probe(pdev); ++ if (r != 0) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt2712_drv = { ++ .probe = clk_mt2712_probe, ++ .driver = { ++ .name = "clk-mt2712", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_clk_mt2712, ++ }, ++}; ++ ++static int __init clk_mt2712_init(void) ++{ ++ return platform_driver_register(&clk_mt2712_drv); ++} ++ ++arch_initcall(clk_mt2712_init); +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -207,6 +207,8 @@ struct mtk_pll_data { + uint32_t en_mask; + uint32_t pd_reg; + uint32_t tuner_reg; ++ uint32_t tuner_en_reg; ++ uint8_t tuner_en_bit; + int pd_shift; + unsigned int flags; + const struct clk_ops *ops; +--- a/drivers/clk/mediatek/clk-pll.c ++++ b/drivers/clk/mediatek/clk-pll.c +@@ -47,6 +47,7 @@ struct mtk_clk_pll { + void __iomem *pd_addr; + void __iomem *pwr_addr; + void __iomem *tuner_addr; ++ void __iomem *tuner_en_addr; + void __iomem *pcw_addr; + const struct mtk_pll_data *data; + }; +@@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw + r |= pll->data->en_mask; + writel(r, pll->base_addr + REG_CON0); + +- if (pll->tuner_addr) { ++ if (pll->tuner_en_addr) { ++ r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); ++ writel(r, pll->tuner_en_addr); ++ } else if (pll->tuner_addr) { + r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; + writel(r, pll->tuner_addr); + } +@@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk + writel(r, pll->base_addr + REG_CON0); + } + +- if (pll->tuner_addr) { ++ if (pll->tuner_en_addr) { ++ r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); ++ writel(r, pll->tuner_en_addr); ++ } else if (pll->tuner_addr) { + r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; + writel(r, pll->tuner_addr); + } +@@ -297,6 +304,8 @@ static struct clk *mtk_clk_register_pll( + pll->pcw_addr = base + data->pcw_reg; + if (data->tuner_reg) + pll->tuner_addr = base + data->tuner_reg; ++ if (data->tuner_en_reg) ++ pll->tuner_en_addr = base + data->tuner_en_reg; + pll->hw.init = &init; + pll->data = data; + diff --git a/target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch b/target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch new file mode 100644 index 000000000..7b2401f52 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0147-dt-bindings-clock-mediatek-document-clk-bindings-for.patch @@ -0,0 +1,190 @@ +From acfa4eba7a4391d443b33a3d90a07eae0ef2ebca Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 5 Oct 2017 11:50:22 +0800 +Subject: [PATCH 147/224] dt-bindings: clock: mediatek: document clk bindings + for MediaTek MT7622 SoC + +This patch adds the binding documentation for apmixedsys, ethsys, hifsys, +infracfg, pericfg, topckgen and audsys for MT7622. + +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Acked-by: Rob Herring +Signed-off-by: Stephen Boyd +--- + .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,audsys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,ethsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,hifsys.txt | 1 + + .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + + .../bindings/arm/mediatek/mediatek,pciesys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 + + .../bindings/arm/mediatek/mediatek,sgmiisys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,ssusbsys.txt | 22 ++++++++++++++++++++++ + .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + + 10 files changed, 94 insertions(+) + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt + create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +@@ -9,6 +9,7 @@ Required Properties: + - "mediatek,mt2701-apmixedsys" + - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6797-apmixedsys" ++ - "mediatek,mt7622-apmixedsys" + - "mediatek,mt8135-apmixedsys" + - "mediatek,mt8173-apmixedsys" + - #clock-cells: Must be 1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +@@ -0,0 +1,22 @@ ++MediaTek AUDSYS controller ++============================ ++ ++The MediaTek AUDSYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be one of: ++ - "mediatek,mt7622-audsys", "syscon" ++- #clock-cells: Must be 1 ++ ++The AUDSYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++audsys: audsys@11220000 { ++ compatible = "mediatek,mt7622-audsys", "syscon"; ++ reg = <0 0x11220000 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +@@ -7,6 +7,7 @@ Required Properties: + + - compatible: Should be: + - "mediatek,mt2701-ethsys", "syscon" ++ - "mediatek,mt7622-ethsys", "syscon" + - #clock-cells: Must be 1 + + The ethsys controller uses the common clk binding from +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt +@@ -8,6 +8,7 @@ Required Properties: + + - compatible: Should be: + - "mediatek,mt2701-hifsys", "syscon" ++ - "mediatek,mt7622-hifsys", "syscon" + - #clock-cells: Must be 1 + + The hifsys controller uses the common clk binding from +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +@@ -10,6 +10,7 @@ Required Properties: + - "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6797-infracfg", "syscon" ++ - "mediatek,mt7622-infracfg", "syscon" + - "mediatek,mt8135-infracfg", "syscon" + - "mediatek,mt8173-infracfg", "syscon" + - #clock-cells: Must be 1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +@@ -0,0 +1,22 @@ ++MediaTek PCIESYS controller ++============================ ++ ++The MediaTek PCIESYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt7622-pciesys", "syscon" ++- #clock-cells: Must be 1 ++ ++The PCIESYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++pciesys: pciesys@1a100800 { ++ compatible = "mediatek,mt7622-pciesys", "syscon"; ++ reg = <0 0x1a100800 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +@@ -9,6 +9,7 @@ Required Properties: + - compatible: Should be one of: + - "mediatek,mt2701-pericfg", "syscon" + - "mediatek,mt2712-pericfg", "syscon" ++ - "mediatek,mt7622-pericfg", "syscon" + - "mediatek,mt8135-pericfg", "syscon" + - "mediatek,mt8173-pericfg", "syscon" + - #clock-cells: Must be 1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt +@@ -0,0 +1,22 @@ ++MediaTek SGMIISYS controller ++============================ ++ ++The MediaTek SGMIISYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt7622-sgmiisys", "syscon" ++- #clock-cells: Must be 1 ++ ++The SGMIISYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++sgmiisys: sgmiisys@1b128000 { ++ compatible = "mediatek,mt7622-sgmiisys", "syscon"; ++ reg = <0 0x1b128000 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- /dev/null ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +@@ -0,0 +1,22 @@ ++MediaTek SSUSBSYS controller ++============================ ++ ++The MediaTek SSUSBSYS controller provides various clocks to the system. ++ ++Required Properties: ++ ++- compatible: Should be: ++ - "mediatek,mt7622-ssusbsys", "syscon" ++- #clock-cells: Must be 1 ++ ++The SSUSBSYS controller uses the common clk binding from ++Documentation/devicetree/bindings/clock/clock-bindings.txt ++The available clocks are defined in dt-bindings/clock/mt*-clk.h. ++ ++Example: ++ ++ssusbsys: ssusbsys@1a000000 { ++ compatible = "mediatek,mt7622-ssusbsys", "syscon"; ++ reg = <0 0x1a000000 0 0x1000>; ++ #clock-cells = <1>; ++}; +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +@@ -9,6 +9,7 @@ Required Properties: + - "mediatek,mt2701-topckgen" + - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6797-topckgen" ++ - "mediatek,mt7622-topckgen" + - "mediatek,mt8135-topckgen" + - "mediatek,mt8173-topckgen" + - #clock-cells: Must be 1 diff --git a/target/linux/mediatek/patches-4.14/0149-clk-mediatek-add-clocks-dt-bindings-required-header-.patch b/target/linux/mediatek/patches-4.14/0149-clk-mediatek-add-clocks-dt-bindings-required-header-.patch new file mode 100644 index 000000000..d82baa758 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0149-clk-mediatek-add-clocks-dt-bindings-required-header-.patch @@ -0,0 +1,310 @@ +From ea009d063f7a3d70831788046c7285a4af4ab82d Mon Sep 17 00:00:00 2001 +From: Chen Zhong +Date: Thu, 5 Oct 2017 11:50:25 +0800 +Subject: [PATCH 149/224] clk: mediatek: add clocks dt-bindings required header + for MT7622 SoC + +Add the required header for the entire clocks dt-bindings exported +from topckgen, apmixedsys, infracfg, pericfg, ethsys, pciesys, ssusbsys +and audsys which could be found on MT7622 SoC. + +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Signed-off-by: Stephen Boyd +--- + include/dt-bindings/clock/mt7622-clk.h | 289 +++++++++++++++++++++++++++++++++ + 1 file changed, 289 insertions(+) + create mode 100644 include/dt-bindings/clock/mt7622-clk.h + +--- /dev/null ++++ b/include/dt-bindings/clock/mt7622-clk.h +@@ -0,0 +1,289 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Chen Zhong ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef _DT_BINDINGS_CLK_MT7622_H ++#define _DT_BINDINGS_CLK_MT7622_H ++ ++/* TOPCKGEN */ ++ ++#define CLK_TOP_TO_U2_PHY 0 ++#define CLK_TOP_TO_U2_PHY_1P 1 ++#define CLK_TOP_PCIE0_PIPE_EN 2 ++#define CLK_TOP_PCIE1_PIPE_EN 3 ++#define CLK_TOP_SSUSB_TX250M 4 ++#define CLK_TOP_SSUSB_EQ_RX250M 5 ++#define CLK_TOP_SSUSB_CDR_REF 6 ++#define CLK_TOP_SSUSB_CDR_FB 7 ++#define CLK_TOP_SATA_ASIC 8 ++#define CLK_TOP_SATA_RBC 9 ++#define CLK_TOP_TO_USB3_SYS 10 ++#define CLK_TOP_P1_1MHZ 11 ++#define CLK_TOP_4MHZ 12 ++#define CLK_TOP_P0_1MHZ 13 ++#define CLK_TOP_TXCLK_SRC_PRE 14 ++#define CLK_TOP_RTC 15 ++#define CLK_TOP_MEMPLL 16 ++#define CLK_TOP_DMPLL 17 ++#define CLK_TOP_SYSPLL_D2 18 ++#define CLK_TOP_SYSPLL1_D2 19 ++#define CLK_TOP_SYSPLL1_D4 20 ++#define CLK_TOP_SYSPLL1_D8 21 ++#define CLK_TOP_SYSPLL2_D4 22 ++#define CLK_TOP_SYSPLL2_D8 23 ++#define CLK_TOP_SYSPLL_D5 24 ++#define CLK_TOP_SYSPLL3_D2 25 ++#define CLK_TOP_SYSPLL3_D4 26 ++#define CLK_TOP_SYSPLL4_D2 27 ++#define CLK_TOP_SYSPLL4_D4 28 ++#define CLK_TOP_SYSPLL4_D16 29 ++#define CLK_TOP_UNIVPLL 30 ++#define CLK_TOP_UNIVPLL_D2 31 ++#define CLK_TOP_UNIVPLL1_D2 32 ++#define CLK_TOP_UNIVPLL1_D4 33 ++#define CLK_TOP_UNIVPLL1_D8 34 ++#define CLK_TOP_UNIVPLL1_D16 35 ++#define CLK_TOP_UNIVPLL2_D2 36 ++#define CLK_TOP_UNIVPLL2_D4 37 ++#define CLK_TOP_UNIVPLL2_D8 38 ++#define CLK_TOP_UNIVPLL2_D16 39 ++#define CLK_TOP_UNIVPLL_D5 40 ++#define CLK_TOP_UNIVPLL3_D2 41 ++#define CLK_TOP_UNIVPLL3_D4 42 ++#define CLK_TOP_UNIVPLL3_D16 43 ++#define CLK_TOP_UNIVPLL_D7 44 ++#define CLK_TOP_UNIVPLL_D80_D4 45 ++#define CLK_TOP_UNIV48M 46 ++#define CLK_TOP_SGMIIPLL 47 ++#define CLK_TOP_SGMIIPLL_D2 48 ++#define CLK_TOP_AUD1PLL 49 ++#define CLK_TOP_AUD2PLL 50 ++#define CLK_TOP_AUD_I2S2_MCK 51 ++#define CLK_TOP_TO_USB3_REF 52 ++#define CLK_TOP_PCIE1_MAC_EN 53 ++#define CLK_TOP_PCIE0_MAC_EN 54 ++#define CLK_TOP_ETH_500M 55 ++#define CLK_TOP_AXI_SEL 56 ++#define CLK_TOP_MEM_SEL 57 ++#define CLK_TOP_DDRPHYCFG_SEL 58 ++#define CLK_TOP_ETH_SEL 59 ++#define CLK_TOP_PWM_SEL 60 ++#define CLK_TOP_F10M_REF_SEL 61 ++#define CLK_TOP_NFI_INFRA_SEL 62 ++#define CLK_TOP_FLASH_SEL 63 ++#define CLK_TOP_UART_SEL 64 ++#define CLK_TOP_SPI0_SEL 65 ++#define CLK_TOP_SPI1_SEL 66 ++#define CLK_TOP_MSDC50_0_SEL 67 ++#define CLK_TOP_MSDC30_0_SEL 68 ++#define CLK_TOP_MSDC30_1_SEL 69 ++#define CLK_TOP_A1SYS_HP_SEL 70 ++#define CLK_TOP_A2SYS_HP_SEL 71 ++#define CLK_TOP_INTDIR_SEL 72 ++#define CLK_TOP_AUD_INTBUS_SEL 73 ++#define CLK_TOP_PMICSPI_SEL 74 ++#define CLK_TOP_SCP_SEL 75 ++#define CLK_TOP_ATB_SEL 76 ++#define CLK_TOP_HIF_SEL 77 ++#define CLK_TOP_AUDIO_SEL 78 ++#define CLK_TOP_U2_SEL 79 ++#define CLK_TOP_AUD1_SEL 80 ++#define CLK_TOP_AUD2_SEL 81 ++#define CLK_TOP_IRRX_SEL 82 ++#define CLK_TOP_IRTX_SEL 83 ++#define CLK_TOP_ASM_L_SEL 84 ++#define CLK_TOP_ASM_M_SEL 85 ++#define CLK_TOP_ASM_H_SEL 86 ++#define CLK_TOP_APLL1_SEL 87 ++#define CLK_TOP_APLL2_SEL 88 ++#define CLK_TOP_I2S0_MCK_SEL 89 ++#define CLK_TOP_I2S1_MCK_SEL 90 ++#define CLK_TOP_I2S2_MCK_SEL 91 ++#define CLK_TOP_I2S3_MCK_SEL 92 ++#define CLK_TOP_APLL1_DIV 93 ++#define CLK_TOP_APLL2_DIV 94 ++#define CLK_TOP_I2S0_MCK_DIV 95 ++#define CLK_TOP_I2S1_MCK_DIV 96 ++#define CLK_TOP_I2S2_MCK_DIV 97 ++#define CLK_TOP_I2S3_MCK_DIV 98 ++#define CLK_TOP_A1SYS_HP_DIV 99 ++#define CLK_TOP_A2SYS_HP_DIV 100 ++#define CLK_TOP_APLL1_DIV_PD 101 ++#define CLK_TOP_APLL2_DIV_PD 102 ++#define CLK_TOP_I2S0_MCK_DIV_PD 103 ++#define CLK_TOP_I2S1_MCK_DIV_PD 104 ++#define CLK_TOP_I2S2_MCK_DIV_PD 105 ++#define CLK_TOP_I2S3_MCK_DIV_PD 106 ++#define CLK_TOP_A1SYS_HP_DIV_PD 107 ++#define CLK_TOP_A2SYS_HP_DIV_PD 108 ++#define CLK_TOP_NR_CLK 109 ++ ++/* INFRACFG */ ++ ++#define CLK_INFRA_MUX1_SEL 0 ++#define CLK_INFRA_DBGCLK_PD 1 ++#define CLK_INFRA_AUDIO_PD 2 ++#define CLK_INFRA_IRRX_PD 3 ++#define CLK_INFRA_APXGPT_PD 4 ++#define CLK_INFRA_PMIC_PD 5 ++#define CLK_INFRA_TRNG 6 ++#define CLK_INFRA_NR_CLK 7 ++ ++/* PERICFG */ ++ ++#define CLK_PERIBUS_SEL 0 ++#define CLK_PERI_THERM_PD 1 ++#define CLK_PERI_PWM1_PD 2 ++#define CLK_PERI_PWM2_PD 3 ++#define CLK_PERI_PWM3_PD 4 ++#define CLK_PERI_PWM4_PD 5 ++#define CLK_PERI_PWM5_PD 6 ++#define CLK_PERI_PWM6_PD 7 ++#define CLK_PERI_PWM7_PD 8 ++#define CLK_PERI_PWM_PD 9 ++#define CLK_PERI_AP_DMA_PD 10 ++#define CLK_PERI_MSDC30_0_PD 11 ++#define CLK_PERI_MSDC30_1_PD 12 ++#define CLK_PERI_UART0_PD 13 ++#define CLK_PERI_UART1_PD 14 ++#define CLK_PERI_UART2_PD 15 ++#define CLK_PERI_UART3_PD 16 ++#define CLK_PERI_UART4_PD 17 ++#define CLK_PERI_BTIF_PD 18 ++#define CLK_PERI_I2C0_PD 19 ++#define CLK_PERI_I2C1_PD 20 ++#define CLK_PERI_I2C2_PD 21 ++#define CLK_PERI_SPI1_PD 22 ++#define CLK_PERI_AUXADC_PD 23 ++#define CLK_PERI_SPI0_PD 24 ++#define CLK_PERI_SNFI_PD 25 ++#define CLK_PERI_NFI_PD 26 ++#define CLK_PERI_NFIECC_PD 27 ++#define CLK_PERI_FLASH_PD 28 ++#define CLK_PERI_IRTX_PD 29 ++#define CLK_PERI_NR_CLK 30 ++ ++/* APMIXEDSYS */ ++ ++#define CLK_APMIXED_ARMPLL 0 ++#define CLK_APMIXED_MAINPLL 1 ++#define CLK_APMIXED_UNIV2PLL 2 ++#define CLK_APMIXED_ETH1PLL 3 ++#define CLK_APMIXED_ETH2PLL 4 ++#define CLK_APMIXED_AUD1PLL 5 ++#define CLK_APMIXED_AUD2PLL 6 ++#define CLK_APMIXED_TRGPLL 7 ++#define CLK_APMIXED_SGMIPLL 8 ++#define CLK_APMIXED_MAIN_CORE_EN 9 ++#define CLK_APMIXED_NR_CLK 10 ++ ++/* AUDIOSYS */ ++ ++#define CLK_AUDIO_AFE 0 ++#define CLK_AUDIO_HDMI 1 ++#define CLK_AUDIO_SPDF 2 ++#define CLK_AUDIO_APLL 3 ++#define CLK_AUDIO_I2SIN1 4 ++#define CLK_AUDIO_I2SIN2 5 ++#define CLK_AUDIO_I2SIN3 6 ++#define CLK_AUDIO_I2SIN4 7 ++#define CLK_AUDIO_I2SO1 8 ++#define CLK_AUDIO_I2SO2 9 ++#define CLK_AUDIO_I2SO3 10 ++#define CLK_AUDIO_I2SO4 11 ++#define CLK_AUDIO_ASRCI1 12 ++#define CLK_AUDIO_ASRCI2 13 ++#define CLK_AUDIO_ASRCO1 14 ++#define CLK_AUDIO_ASRCO2 15 ++#define CLK_AUDIO_INTDIR 16 ++#define CLK_AUDIO_A1SYS 17 ++#define CLK_AUDIO_A2SYS 18 ++#define CLK_AUDIO_UL1 19 ++#define CLK_AUDIO_UL2 20 ++#define CLK_AUDIO_UL3 21 ++#define CLK_AUDIO_UL4 22 ++#define CLK_AUDIO_UL5 23 ++#define CLK_AUDIO_UL6 24 ++#define CLK_AUDIO_DL1 25 ++#define CLK_AUDIO_DL2 26 ++#define CLK_AUDIO_DL3 27 ++#define CLK_AUDIO_DL4 28 ++#define CLK_AUDIO_DL5 29 ++#define CLK_AUDIO_DL6 30 ++#define CLK_AUDIO_DLMCH 31 ++#define CLK_AUDIO_ARB1 32 ++#define CLK_AUDIO_AWB 33 ++#define CLK_AUDIO_AWB2 34 ++#define CLK_AUDIO_DAI 35 ++#define CLK_AUDIO_MOD 36 ++#define CLK_AUDIO_ASRCI3 37 ++#define CLK_AUDIO_ASRCI4 38 ++#define CLK_AUDIO_ASRCO3 39 ++#define CLK_AUDIO_ASRCO4 40 ++#define CLK_AUDIO_MEM_ASRC1 41 ++#define CLK_AUDIO_MEM_ASRC2 42 ++#define CLK_AUDIO_MEM_ASRC3 43 ++#define CLK_AUDIO_MEM_ASRC4 44 ++#define CLK_AUDIO_MEM_ASRC5 45 ++#define CLK_AUDIO_NR_CLK 46 ++ ++/* SSUSBSYS */ ++ ++#define CLK_SSUSB_U2_PHY_1P_EN 0 ++#define CLK_SSUSB_U2_PHY_EN 1 ++#define CLK_SSUSB_REF_EN 2 ++#define CLK_SSUSB_SYS_EN 3 ++#define CLK_SSUSB_MCU_EN 4 ++#define CLK_SSUSB_DMA_EN 5 ++#define CLK_SSUSB_NR_CLK 6 ++ ++/* PCIESYS */ ++ ++#define CLK_PCIE_P1_AUX_EN 0 ++#define CLK_PCIE_P1_OBFF_EN 1 ++#define CLK_PCIE_P1_AHB_EN 2 ++#define CLK_PCIE_P1_AXI_EN 3 ++#define CLK_PCIE_P1_MAC_EN 4 ++#define CLK_PCIE_P1_PIPE_EN 5 ++#define CLK_PCIE_P0_AUX_EN 6 ++#define CLK_PCIE_P0_OBFF_EN 7 ++#define CLK_PCIE_P0_AHB_EN 8 ++#define CLK_PCIE_P0_AXI_EN 9 ++#define CLK_PCIE_P0_MAC_EN 10 ++#define CLK_PCIE_P0_PIPE_EN 11 ++#define CLK_SATA_AHB_EN 12 ++#define CLK_SATA_AXI_EN 13 ++#define CLK_SATA_ASIC_EN 14 ++#define CLK_SATA_RBC_EN 15 ++#define CLK_SATA_PM_EN 16 ++#define CLK_PCIE_NR_CLK 17 ++ ++/* ETHSYS */ ++ ++#define CLK_ETH_HSDMA_EN 0 ++#define CLK_ETH_ESW_EN 1 ++#define CLK_ETH_GP2_EN 2 ++#define CLK_ETH_GP1_EN 3 ++#define CLK_ETH_GP0_EN 4 ++#define CLK_ETH_NR_CLK 5 ++ ++/* SGMIISYS */ ++ ++#define CLK_SGMII_TX250M_EN 0 ++#define CLK_SGMII_RX250M_EN 1 ++#define CLK_SGMII_CDR_REF 2 ++#define CLK_SGMII_CDR_FB 3 ++#define CLK_SGMII_NR_CLK 4 ++ ++#endif /* _DT_BINDINGS_CLK_MT7622_H */ ++ diff --git a/target/linux/mediatek/patches-4.14/0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch new file mode 100644 index 000000000..e993106fe --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0150-clk-mediatek-add-clock-support-for-MT7622-SoC.patch @@ -0,0 +1,1388 @@ +From b24e830d69f1fa637284c093410645a059b60028 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 5 Oct 2017 11:50:24 +0800 +Subject: [PATCH 150/224] clk: mediatek: add clock support for MT7622 SoC + +Add all supported clocks exported from every susbystem found on MT7622 SoC +such as topckgen, apmixedsys, infracfg, pericfg , pciessys, ssusbsys, +ethsys and audsys. + +Signed-off-by: Chen Zhong +Signed-off-by: Sean Wang +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/Kconfig | 30 ++ + drivers/clk/mediatek/Makefile | 4 + + drivers/clk/mediatek/clk-mt7622-aud.c | 195 +++++++++ + drivers/clk/mediatek/clk-mt7622-eth.c | 156 +++++++ + drivers/clk/mediatek/clk-mt7622-hif.c | 169 ++++++++ + drivers/clk/mediatek/clk-mt7622.c | 780 ++++++++++++++++++++++++++++++++++ + 6 files changed, 1334 insertions(+) + create mode 100644 drivers/clk/mediatek/clk-mt7622-aud.c + create mode 100644 drivers/clk/mediatek/clk-mt7622-eth.c + create mode 100644 drivers/clk/mediatek/clk-mt7622-hif.c + create mode 100644 drivers/clk/mediatek/clk-mt7622.c + +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -132,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS + ---help--- + This driver supports Mediatek MT6797 vencsys clocks. + ++config COMMON_CLK_MT7622 ++ bool "Clock driver for MediaTek MT7622" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ ---help--- ++ This driver supports MediaTek MT7622 basic clocks and clocks ++ required for various periperals found on MediaTek. ++ ++config COMMON_CLK_MT7622_ETHSYS ++ bool "Clock driver for MediaTek MT7622 ETHSYS" ++ depends on COMMON_CLK_MT7622 ++ ---help--- ++ This driver add support for clocks for Ethernet and SGMII ++ required on MediaTek MT7622 SoC. ++ ++config COMMON_CLK_MT7622_HIFSYS ++ bool "Clock driver for MediaTek MT7622 HIFSYS" ++ depends on COMMON_CLK_MT7622 ++ ---help--- ++ This driver supports MediaTek MT7622 HIFSYS clocks providing ++ to PCI-E and USB. ++ ++config COMMON_CLK_MT7622_AUDSYS ++ bool "Clock driver for MediaTek MT7622 AUDSYS" ++ depends on COMMON_CLK_MT7622 ++ ---help--- ++ This driver supports MediaTek MT7622 AUDSYS clocks providing ++ to audio consumers such as I2S and TDM. ++ + config COMMON_CLK_MT8135 + bool "Clock driver for Mediatek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -21,5 +21,9 @@ obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) + + obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o + obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o + obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o ++obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o ++obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o ++obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7622-aud.c +@@ -0,0 +1,195 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Chen Zhong ++ * Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &audio0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &audio1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++#define GATE_AUDIO2(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &audio2_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++#define GATE_AUDIO3(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &audio3_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++static const struct mtk_gate_regs audio0_cg_regs = { ++ .set_ofs = 0x0, ++ .clr_ofs = 0x0, ++ .sta_ofs = 0x0, ++}; ++ ++static const struct mtk_gate_regs audio1_cg_regs = { ++ .set_ofs = 0x10, ++ .clr_ofs = 0x10, ++ .sta_ofs = 0x10, ++}; ++ ++static const struct mtk_gate_regs audio2_cg_regs = { ++ .set_ofs = 0x14, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x14, ++}; ++ ++static const struct mtk_gate_regs audio3_cg_regs = { ++ .set_ofs = 0x634, ++ .clr_ofs = 0x634, ++ .sta_ofs = 0x634, ++}; ++ ++static const struct mtk_gate audio_clks[] = { ++ /* AUDIO0 */ ++ GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2), ++ GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20), ++ GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21), ++ GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23), ++ /* AUDIO1 */ ++ GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0), ++ GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1), ++ GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2), ++ GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3), ++ GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6), ++ GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7), ++ GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8), ++ GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9), ++ GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12), ++ GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13), ++ GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14), ++ GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15), ++ GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20), ++ GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21), ++ GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22), ++ /* AUDIO2 */ ++ GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0), ++ GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1), ++ GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2), ++ GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3), ++ GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4), ++ GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5), ++ GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6), ++ GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7), ++ GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8), ++ GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9), ++ GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10), ++ GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11), ++ GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12), ++ GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13), ++ GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14), ++ GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15), ++ GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16), ++ GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17), ++ /* AUDIO3 */ ++ GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2), ++ GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3), ++ GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6), ++ GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7), ++ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10), ++ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11), ++ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12), ++ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13), ++ GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), ++}; ++ ++static int clk_mt7622_audiosys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); ++ ++ mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt7622_aud[] = { ++ { ++ .compatible = "mediatek,mt7622-audsys", ++ .data = clk_mt7622_audiosys_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7622_aud_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7622_aud_drv = { ++ .probe = clk_mt7622_aud_probe, ++ .driver = { ++ .name = "clk-mt7622-aud", ++ .of_match_table = of_match_clk_mt7622_aud, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt7622_aud_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7622-eth.c +@@ -0,0 +1,156 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Chen Zhong ++ * Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++#define GATE_ETH(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = ð_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate_regs eth_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++static const struct mtk_gate eth_clks[] = { ++ GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), ++ GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), ++ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), ++ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), ++ GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), ++}; ++ ++static const struct mtk_gate_regs sgmii_cg_regs = { ++ .set_ofs = 0xE4, ++ .clr_ofs = 0xE4, ++ .sta_ofs = 0xE4, ++}; ++ ++#define GATE_SGMII(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &sgmii_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate sgmii_clks[] = { ++ GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", ++ "ssusb_tx250m", 2), ++ GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", ++ "ssusb_eq_rx250m", 3), ++ GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", ++ "ssusb_cdr_ref", 4), ++ GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", ++ "ssusb_cdr_fb", 5), ++}; ++ ++static int clk_mt7622_ethsys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); ++ ++ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++ ++ return r; ++} ++ ++static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); ++ ++ mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt7622_eth[] = { ++ { ++ .compatible = "mediatek,mt7622-ethsys", ++ .data = clk_mt7622_ethsys_init, ++ }, { ++ .compatible = "mediatek,mt7622-sgmiisys", ++ .data = clk_mt7622_sgmiisys_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7622_eth_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7622_eth_drv = { ++ .probe = clk_mt7622_eth_probe, ++ .driver = { ++ .name = "clk-mt7622-eth", ++ .of_match_table = of_match_clk_mt7622_eth, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt7622_eth_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7622-hif.c +@@ -0,0 +1,169 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Chen Zhong ++ * Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++ ++#include ++ ++#define GATE_PCIE(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &pcie_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++#define GATE_SSUSB(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &ssusb_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++static const struct mtk_gate_regs pcie_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++static const struct mtk_gate_regs ssusb_cg_regs = { ++ .set_ofs = 0x30, ++ .clr_ofs = 0x30, ++ .sta_ofs = 0x30, ++}; ++ ++static const struct mtk_gate ssusb_clks[] = { ++ GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p", ++ "to_u2_phy_1p", 0), ++ GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1), ++ GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5), ++ GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6), ++ GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7), ++ GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8), ++}; ++ ++static const struct mtk_gate pcie_clks[] = { ++ GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12), ++ GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13), ++ GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14), ++ GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15), ++ GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16), ++ GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17), ++ GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18), ++ GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19), ++ GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20), ++ GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21), ++ GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22), ++ GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), ++ GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26), ++ GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27), ++ GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28), ++ GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29), ++ GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), ++}; ++ ++static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); ++ ++ mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++ ++ return r; ++} ++ ++static int clk_mt7622_pciesys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); ++ ++ mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ mtk_register_reset_controller(node, 1, 0x34); ++ ++ return r; ++} ++ ++static const struct of_device_id of_match_clk_mt7622_hif[] = { ++ { ++ .compatible = "mediatek,mt7622-pciesys", ++ .data = clk_mt7622_pciesys_init, ++ }, { ++ .compatible = "mediatek,mt7622-ssusbsys", ++ .data = clk_mt7622_ssusbsys_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7622_hif_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7622_hif_drv = { ++ .probe = clk_mt7622_hif_probe, ++ .driver = { ++ .name = "clk-mt7622-hif", ++ .of_match_table = of_match_clk_mt7622_hif, ++ }, ++}; ++ ++builtin_platform_driver(clk_mt7622_hif_drv); +--- /dev/null ++++ b/drivers/clk/mediatek/clk-mt7622.c +@@ -0,0 +1,780 @@ ++/* ++ * Copyright (c) 2017 MediaTek Inc. ++ * Author: Chen Zhong ++ * Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk-mtk.h" ++#include "clk-gate.h" ++#include "clk-cpumux.h" ++ ++#include ++#include /* for consumer */ ++ ++#define MT7622_PLL_FMAX (2500UL * MHZ) ++#define CON0_MT7622_RST_BAR BIT(27) ++ ++#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ ++ _pcw_shift, _div_table, _parent_name) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .reg = _reg, \ ++ .pwr_reg = _pwr_reg, \ ++ .en_mask = _en_mask, \ ++ .flags = _flags, \ ++ .rst_bar_mask = CON0_MT7622_RST_BAR, \ ++ .fmax = MT7622_PLL_FMAX, \ ++ .pcwbits = _pcwbits, \ ++ .pd_reg = _pd_reg, \ ++ .pd_shift = _pd_shift, \ ++ .tuner_reg = _tuner_reg, \ ++ .pcw_reg = _pcw_reg, \ ++ .pcw_shift = _pcw_shift, \ ++ .div_table = _div_table, \ ++ .parent_name = _parent_name, \ ++ } ++ ++#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ ++ _pcw_shift) \ ++ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ ++ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ ++ NULL, "clkxtal") ++ ++#define GATE_APMIXED(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &apmixed_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ ++ } ++ ++#define GATE_INFRA(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &infra_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_TOP0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &top0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++#define GATE_TOP1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &top1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_no_setclr, \ ++ } ++ ++#define GATE_PERI0(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri0_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++#define GATE_PERI1(_id, _name, _parent, _shift) { \ ++ .id = _id, \ ++ .name = _name, \ ++ .parent_name = _parent, \ ++ .regs = &peri1_cg_regs, \ ++ .shift = _shift, \ ++ .ops = &mtk_clk_gate_ops_setclr, \ ++ } ++ ++static DEFINE_SPINLOCK(mt7622_clk_lock); ++ ++static const char * const infra_mux1_parents[] = { ++ "clkxtal", ++ "armpll", ++ "main_core_en", ++ "armpll" ++}; ++ ++static const char * const axi_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "syspll_d5", ++ "syspll1_d4", ++ "univpll_d5", ++ "univpll2_d2", ++ "univpll_d7" ++}; ++ ++static const char * const mem_parents[] = { ++ "clkxtal", ++ "dmpll_ck" ++}; ++ ++static const char * const ddrphycfg_parents[] = { ++ "clkxtal", ++ "syspll1_d8" ++}; ++ ++static const char * const eth_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "univpll1_d2", ++ "syspll1_d4", ++ "univpll_d5", ++ "clk_null", ++ "univpll_d7" ++}; ++ ++static const char * const pwm_parents[] = { ++ "clkxtal", ++ "univpll2_d4" ++}; ++ ++static const char * const f10m_ref_parents[] = { ++ "clkxtal", ++ "syspll4_d16" ++}; ++ ++static const char * const nfi_infra_parents[] = { ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "clkxtal", ++ "univpll2_d8", ++ "syspll1_d8", ++ "univpll1_d8", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll3_d2", ++ "syspll1_d4" ++}; ++ ++static const char * const flash_parents[] = { ++ "clkxtal", ++ "univpll_d80_d4", ++ "syspll2_d8", ++ "syspll3_d4", ++ "univpll3_d4", ++ "univpll1_d8", ++ "syspll2_d4", ++ "univpll2_d4" ++}; ++ ++static const char * const uart_parents[] = { ++ "clkxtal", ++ "univpll2_d8" ++}; ++ ++static const char * const spi0_parents[] = { ++ "clkxtal", ++ "syspll3_d2", ++ "clkxtal", ++ "syspll2_d4", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll1_d8", ++ "clkxtal" ++}; ++ ++static const char * const spi1_parents[] = { ++ "clkxtal", ++ "syspll3_d2", ++ "clkxtal", ++ "syspll4_d4", ++ "syspll4_d2", ++ "univpll2_d4", ++ "univpll1_d8", ++ "clkxtal" ++}; ++ ++static const char * const msdc30_0_parents[] = { ++ "clkxtal", ++ "univpll2_d16", ++ "univ48m" ++}; ++ ++static const char * const a1sys_hp_parents[] = { ++ "clkxtal", ++ "aud1pll_ck", ++ "aud2pll_ck", ++ "clkxtal" ++}; ++ ++static const char * const intdir_parents[] = { ++ "clkxtal", ++ "syspll_d2", ++ "univpll_d2", ++ "sgmiipll_ck" ++}; ++ ++static const char * const aud_intbus_parents[] = { ++ "clkxtal", ++ "syspll1_d4", ++ "syspll4_d2", ++ "syspll3_d2" ++}; ++ ++static const char * const pmicspi_parents[] = { ++ "clkxtal", ++ "clk_null", ++ "clk_null", ++ "clk_null", ++ "clk_null", ++ "univpll2_d16" ++}; ++ ++static const char * const atb_parents[] = { ++ "clkxtal", ++ "syspll1_d2", ++ "syspll_d5" ++}; ++ ++static const char * const audio_parents[] = { ++ "clkxtal", ++ "syspll3_d4", ++ "syspll4_d4", ++ "univpll1_d16" ++}; ++ ++static const char * const usb20_parents[] = { ++ "clkxtal", ++ "univpll3_d4", ++ "syspll1_d8", ++ "clkxtal" ++}; ++ ++static const char * const aud1_parents[] = { ++ "clkxtal", ++ "aud1pll_ck" ++}; ++ ++static const char * const aud2_parents[] = { ++ "clkxtal", ++ "aud2pll_ck" ++}; ++ ++static const char * const asm_l_parents[] = { ++ "clkxtal", ++ "syspll_d5", ++ "univpll2_d2", ++ "univpll2_d4" ++}; ++ ++static const char * const apll1_ck_parents[] = { ++ "aud1_sel", ++ "aud2_sel" ++}; ++ ++static const char * const peribus_ck_parents[] = { ++ "syspll1_d8", ++ "syspll1_d4" ++}; ++ ++static const struct mtk_gate_regs apmixed_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0x8, ++ .sta_ofs = 0x8, ++}; ++ ++static const struct mtk_gate_regs infra_cg_regs = { ++ .set_ofs = 0x40, ++ .clr_ofs = 0x44, ++ .sta_ofs = 0x48, ++}; ++ ++static const struct mtk_gate_regs top0_cg_regs = { ++ .set_ofs = 0x120, ++ .clr_ofs = 0x120, ++ .sta_ofs = 0x120, ++}; ++ ++static const struct mtk_gate_regs top1_cg_regs = { ++ .set_ofs = 0x128, ++ .clr_ofs = 0x128, ++ .sta_ofs = 0x128, ++}; ++ ++static const struct mtk_gate_regs peri0_cg_regs = { ++ .set_ofs = 0x8, ++ .clr_ofs = 0x10, ++ .sta_ofs = 0x18, ++}; ++ ++static const struct mtk_gate_regs peri1_cg_regs = { ++ .set_ofs = 0xC, ++ .clr_ofs = 0x14, ++ .sta_ofs = 0x1C, ++}; ++ ++static const struct mtk_pll_data plls[] = { ++ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, ++ PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0), ++ PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001, ++ HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0), ++ PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001, ++ HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14), ++ PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001, ++ 0, 21, 0x0300, 1, 0, 0x0304, 0), ++ PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001, ++ 0, 21, 0x0314, 1, 0, 0x0318, 0), ++ PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001, ++ 0, 31, 0x0324, 1, 0, 0x0328, 0), ++ PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001, ++ 0, 31, 0x0334, 1, 0, 0x0338, 0), ++ PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001, ++ 0, 21, 0x0344, 1, 0, 0x0348, 0), ++ PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001, ++ 0, 21, 0x0358, 1, 0, 0x035C, 0), ++}; ++ ++static const struct mtk_gate apmixed_clks[] = { ++ GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5), ++}; ++ ++static const struct mtk_gate infra_clks[] = { ++ GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0), ++ GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2), ++ GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5), ++ GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16), ++ GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18), ++ GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22), ++}; ++ ++static const struct mtk_fixed_clk top_fixed_clks[] = { ++ FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal", ++ 31250000), ++ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal", ++ 31250000), ++ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal", ++ 125000000), ++ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal", ++ 125000000), ++ FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal", ++ 250000000), ++ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal", ++ 250000000), ++ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal", ++ 33333333), ++ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal", ++ 50000000), ++ FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal", ++ 50000000), ++ FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal", ++ 50000000), ++}; ++ ++static const struct mtk_fixed_factor top_divs[] = { ++ FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4), ++ FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500), ++ FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125), ++ FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500), ++ FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1), ++ FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024), ++ FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1), ++ FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1), ++ FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), ++ FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), ++ FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), ++ FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), ++ FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), ++ FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), ++ FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), ++ FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), ++ FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), ++ FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), ++ FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), ++ FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112), ++ FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), ++ FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), ++ FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), ++ FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16), ++ FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32), ++ FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), ++ FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), ++ FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), ++ FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48), ++ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), ++ FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), ++ FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), ++ FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80), ++ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), ++ FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320), ++ FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25), ++ FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1), ++ FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2), ++ FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1), ++ FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1), ++ FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2), ++ FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4), ++ FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1), ++ FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1), ++ FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1), ++}; ++ ++static const struct mtk_gate top_clks[] = { ++ /* TOP0 */ ++ GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0), ++ GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1), ++ GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div", ++ 2), ++ GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div", ++ 3), ++ GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div", ++ 4), ++ GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div", ++ 5), ++ ++ /* TOP1 */ ++ GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0), ++ GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16), ++}; ++ ++static const struct mtk_clk_divider top_adj_divs[] = { ++ DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel", ++ 0x120, 24, 3), ++ DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel", ++ 0x120, 28, 3), ++ DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel", ++ 0x124, 0, 7), ++ DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel", ++ 0x124, 8, 7), ++ DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck", ++ 0x124, 16, 7), ++ DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel", ++ 0x124, 24, 7), ++ DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel", ++ 0x128, 8, 7), ++ DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel", ++ 0x128, 24, 7), ++}; ++ ++static const struct mtk_gate peri_clks[] = { ++ /* PERI0 */ ++ GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1), ++ GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2), ++ GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3), ++ GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4), ++ GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5), ++ GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6), ++ GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7), ++ GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8), ++ GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9), ++ GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12), ++ GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13), ++ GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14), ++ GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17), ++ GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18), ++ GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19), ++ GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20), ++ GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21), ++ GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22), ++ GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23), ++ GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24), ++ GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25), ++ GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26), ++ GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27), ++ GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28), ++ GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29), ++ GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30), ++ GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31), ++ ++ /* PERI1 */ ++ GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1), ++ GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2), ++}; ++ ++static struct mtk_composite infra_muxes[] __initdata = { ++ MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, ++ 0x000, 2, 2), ++}; ++ ++static struct mtk_composite top_muxes[] = { ++ /* CLK_CFG_0 */ ++ MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, ++ 0x040, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, ++ 0x040, 8, 1, 15), ++ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, ++ 0x040, 16, 1, 23), ++ MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, ++ 0x040, 24, 3, 31), ++ ++ /* CLK_CFG_1 */ ++ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, ++ 0x050, 0, 2, 7), ++ MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents, ++ 0x050, 8, 1, 15), ++ MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents, ++ 0x050, 16, 4, 23), ++ MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, ++ 0x050, 24, 3, 31), ++ ++ /* CLK_CFG_2 */ ++ MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, ++ 0x060, 0, 1, 7), ++ MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents, ++ 0x060, 8, 3, 15), ++ MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents, ++ 0x060, 16, 3, 23), ++ MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents, ++ 0x060, 24, 3, 31), ++ ++ /* CLK_CFG_3 */ ++ MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents, ++ 0x070, 0, 3, 7), ++ MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents, ++ 0x070, 8, 3, 15), ++ MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, ++ 0x070, 16, 2, 23), ++ MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents, ++ 0x070, 24, 2, 31), ++ ++ /* CLK_CFG_4 */ ++ MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, ++ 0x080, 0, 2, 7), ++ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, ++ 0x080, 8, 2, 15), ++ MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, ++ 0x080, 16, 3, 23), ++ MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents, ++ 0x080, 24, 2, 31), ++ ++ /* CLK_CFG_5 */ ++ MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, ++ 0x090, 0, 2, 7), ++ MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents, ++ 0x090, 8, 3, 15), ++ MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, ++ 0x090, 16, 2, 23), ++ MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents, ++ 0x090, 24, 2, 31), ++ ++ /* CLK_CFG_6 */ ++ MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents, ++ 0x0A0, 0, 1, 7), ++ MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents, ++ 0x0A0, 8, 1, 15), ++ MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents, ++ 0x0A0, 16, 1, 23), ++ MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents, ++ 0x0A0, 24, 1, 31), ++ ++ /* CLK_CFG_7 */ ++ MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, ++ 0x0B0, 0, 2, 7), ++ MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, ++ 0x0B0, 8, 2, 15), ++ MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, ++ 0x0B0, 16, 2, 23), ++ ++ /* CLK_AUDDIV_0 */ ++ MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents, ++ 0x120, 6, 1), ++ MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents, ++ 0x120, 7, 1), ++ MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents, ++ 0x120, 8, 1), ++ MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents, ++ 0x120, 9, 1), ++ MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents, ++ 0x120, 10, 1), ++ MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents, ++ 0x120, 11, 1), ++}; ++ ++static struct mtk_composite peri_muxes[] = { ++ /* PERI_GLOBALCON_CKSEL */ ++ MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), ++}; ++ ++static int mtk_topckgen_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ struct device_node *node = pdev->dev.of_node; ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); ++ ++ mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), ++ clk_data); ++ ++ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), ++ clk_data); ++ ++ mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), ++ base, &mt7622_clk_lock, clk_data); ++ ++ mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), ++ base, &mt7622_clk_lock, clk_data); ++ ++ mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), ++ clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); ++ clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); ++ clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); ++ ++ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++} ++ ++static int __init mtk_infrasys_init(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct clk_onecell_data *clk_data; ++ int r; ++ ++ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); ++ ++ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), ++ clk_data); ++ ++ mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), ++ clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, ++ clk_data); ++ if (r) ++ return r; ++ ++ mtk_register_reset_controller(node, 1, 0x30); ++ ++ return 0; ++} ++ ++static int mtk_apmixedsys_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ struct device_node *node = pdev->dev.of_node; ++ ++ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); ++ if (!clk_data) ++ return -ENOMEM; ++ ++ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), ++ clk_data); ++ ++ mtk_clk_register_gates(node, apmixed_clks, ++ ARRAY_SIZE(apmixed_clks), clk_data); ++ ++ clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); ++ clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); ++ ++ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++} ++ ++static int mtk_pericfg_init(struct platform_device *pdev) ++{ ++ struct clk_onecell_data *clk_data; ++ void __iomem *base; ++ int r; ++ struct device_node *node = pdev->dev.of_node; ++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); ++ ++ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), ++ clk_data); ++ ++ mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, ++ &mt7622_clk_lock, clk_data); ++ ++ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); ++ if (r) ++ return r; ++ ++ clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); ++ ++ mtk_register_reset_controller(node, 2, 0x0); ++ ++ return 0; ++} ++ ++static const struct of_device_id of_match_clk_mt7622[] = { ++ { ++ .compatible = "mediatek,mt7622-apmixedsys", ++ .data = mtk_apmixedsys_init, ++ }, { ++ .compatible = "mediatek,mt7622-infracfg", ++ .data = mtk_infrasys_init, ++ }, { ++ .compatible = "mediatek,mt7622-topckgen", ++ .data = mtk_topckgen_init, ++ }, { ++ .compatible = "mediatek,mt7622-pericfg", ++ .data = mtk_pericfg_init, ++ }, { ++ /* sentinel */ ++ } ++}; ++ ++static int clk_mt7622_probe(struct platform_device *pdev) ++{ ++ int (*clk_init)(struct platform_device *); ++ int r; ++ ++ clk_init = of_device_get_match_data(&pdev->dev); ++ if (!clk_init) ++ return -EINVAL; ++ ++ r = clk_init(pdev); ++ if (r) ++ dev_err(&pdev->dev, ++ "could not register clock provider: %s: %d\n", ++ pdev->name, r); ++ ++ return r; ++} ++ ++static struct platform_driver clk_mt7622_drv = { ++ .probe = clk_mt7622_probe, ++ .driver = { ++ .name = "clk-mt7622", ++ .of_match_table = of_match_clk_mt7622, ++ }, ++}; ++ ++static int clk_mt7622_init(void) ++{ ++ return platform_driver_register(&clk_mt7622_drv); ++} ++ ++arch_initcall(clk_mt7622_init); diff --git a/target/linux/mediatek/patches-4.14/0151-arm64-dts-mt8173-remove-mediatek-mt8135-mmc-from-mmc.patch b/target/linux/mediatek/patches-4.14/0151-arm64-dts-mt8173-remove-mediatek-mt8135-mmc-from-mmc.patch new file mode 100644 index 000000000..b30604f90 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0151-arm64-dts-mt8173-remove-mediatek-mt8135-mmc-from-mmc.patch @@ -0,0 +1,61 @@ +From fa69904d3b7357a5be43771f764e10fd99ebbb11 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:30 +0800 +Subject: [PATCH 151/224] arm64: dts: mt8173: remove "mediatek, mt8135-mmc" + from mmc nodes + +devicetree bindings has been updated to support multi-platforms, +so that each platform has its owns compatible name. +And, this compatible name may used in driver to distinguish with +other platform. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +Acked-by: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++-------- + 1 file changed, 4 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi +@@ -684,8 +684,7 @@ + }; + + mmc0: mmc@11230000 { +- compatible = "mediatek,mt8173-mmc", +- "mediatek,mt8135-mmc"; ++ compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_0>, +@@ -695,8 +694,7 @@ + }; + + mmc1: mmc@11240000 { +- compatible = "mediatek,mt8173-mmc", +- "mediatek,mt8135-mmc"; ++ compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_1>, +@@ -706,8 +704,7 @@ + }; + + mmc2: mmc@11250000 { +- compatible = "mediatek,mt8173-mmc", +- "mediatek,mt8135-mmc"; ++ compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_2>, +@@ -717,8 +714,7 @@ + }; + + mmc3: mmc@11260000 { +- compatible = "mediatek,mt8173-mmc", +- "mediatek,mt8135-mmc"; ++ compatible = "mediatek,mt8173-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_MSDC30_3>, diff --git a/target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch b/target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch new file mode 100644 index 000000000..cb7f8ffb2 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0152-mmc-mediatek-make-hs400_tune_response-only-for-mt817.patch @@ -0,0 +1,70 @@ +From bc70c7f1174b937af2784977281a1567f69dd2b6 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:31 +0800 +Subject: [PATCH 152/224] mmc: mediatek: make hs400_tune_response only for + mt8173 + +the origin design of hs400_tune_response is for mt8173 because of +mt8173 has a special design. for doing that, we add a new member +"compatible", by now it's only for mt8173. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -300,6 +300,7 @@ struct msdc_save_para { + + struct mtk_mmc_compatible { + u8 clk_div_bits; ++ bool hs400_tune; /* only used for MT8173 */ + }; + + struct msdc_tune_para { +@@ -360,18 +361,22 @@ struct msdc_host { + + static const struct mtk_mmc_compatible mt8135_compat = { + .clk_div_bits = 8, ++ .hs400_tune = false, + }; + + static const struct mtk_mmc_compatible mt8173_compat = { + .clk_div_bits = 8, ++ .hs400_tune = true, + }; + + static const struct mtk_mmc_compatible mt2701_compat = { + .clk_div_bits = 12, ++ .hs400_tune = false, + }; + + static const struct mtk_mmc_compatible mt2712_compat = { + .clk_div_bits = 12, ++ .hs400_tune = false, + }; + + static const struct of_device_id msdc_of_ids[] = { +@@ -666,7 +671,8 @@ static void msdc_set_mclk(struct msdc_ho + host->base + PAD_CMD_TUNE); + } + +- if (timing == MMC_TIMING_MMC_HS400) ++ if (timing == MMC_TIMING_MMC_HS400 && ++ host->dev_comp->hs400_tune) + sdr_set_field(host->base + PAD_CMD_TUNE, + MSDC_PAD_TUNE_CMDRRDLY, + host->hs400_cmd_int_delay); +@@ -1594,7 +1600,8 @@ static int msdc_execute_tuning(struct mm + struct msdc_host *host = mmc_priv(mmc); + int ret; + +- if (host->hs400_mode) ++ if (host->hs400_mode && ++ host->dev_comp->hs400_tune) + ret = hs400_tune_response(mmc, opcode); + else + ret = msdc_tune_response(mmc, opcode); diff --git a/target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch b/target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch new file mode 100644 index 000000000..8c4bbd261 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0153-mmc-mediatek-add-pad_tune0-support.patch @@ -0,0 +1,256 @@ +From a10349f1710a11239c58da3a7e5b353c6b2070c2 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:32 +0800 +Subject: [PATCH 153/224] mmc: mediatek: add pad_tune0 support + +from mt2701, the register of PAD_TUNE has been phased out, +while there is a new register of PAD_TUNE0 + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 51 ++++++++++++++++++++++++++++++----------------- + 1 file changed, 33 insertions(+), 18 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -75,6 +75,7 @@ + #define MSDC_PATCH_BIT 0xb0 + #define MSDC_PATCH_BIT1 0xb4 + #define MSDC_PAD_TUNE 0xec ++#define MSDC_PAD_TUNE0 0xf0 + #define PAD_DS_TUNE 0x188 + #define PAD_CMD_TUNE 0x18c + #define EMMC50_CFG0 0x208 +@@ -301,6 +302,7 @@ struct msdc_save_para { + struct mtk_mmc_compatible { + u8 clk_div_bits; + bool hs400_tune; /* only used for MT8173 */ ++ u32 pad_tune_reg; + }; + + struct msdc_tune_para { +@@ -362,21 +364,25 @@ struct msdc_host { + static const struct mtk_mmc_compatible mt8135_compat = { + .clk_div_bits = 8, + .hs400_tune = false, ++ .pad_tune_reg = MSDC_PAD_TUNE, + }; + + static const struct mtk_mmc_compatible mt8173_compat = { + .clk_div_bits = 8, + .hs400_tune = true, ++ .pad_tune_reg = MSDC_PAD_TUNE, + }; + + static const struct mtk_mmc_compatible mt2701_compat = { + .clk_div_bits = 12, + .hs400_tune = false, ++ .pad_tune_reg = MSDC_PAD_TUNE0, + }; + + static const struct mtk_mmc_compatible mt2712_compat = { + .clk_div_bits = 12, + .hs400_tune = false, ++ .pad_tune_reg = MSDC_PAD_TUNE0, + }; + + static const struct of_device_id msdc_of_ids[] = { +@@ -581,6 +587,7 @@ static void msdc_set_mclk(struct msdc_ho + u32 flags; + u32 div; + u32 sclk; ++ u32 tune_reg = host->dev_comp->pad_tune_reg; + + if (!hz) { + dev_dbg(host->dev, "set mclk to 0\n"); +@@ -663,10 +670,10 @@ static void msdc_set_mclk(struct msdc_ho + */ + if (host->sclk <= 52000000) { + writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); +- writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); ++ writel(host->def_tune_para.pad_tune, host->base + tune_reg); + } else { + writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); +- writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); ++ writel(host->saved_tune_para.pad_tune, host->base + tune_reg); + writel(host->saved_tune_para.pad_cmd_tune, + host->base + PAD_CMD_TUNE); + } +@@ -1224,6 +1231,7 @@ static irqreturn_t msdc_irq(int irq, voi + static void msdc_init_hw(struct msdc_host *host) + { + u32 val; ++ u32 tune_reg = host->dev_comp->pad_tune_reg; + + /* Configure to MMC/SD mode, clock free running */ + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); +@@ -1239,7 +1247,7 @@ static void msdc_init_hw(struct msdc_hos + val = readl(host->base + MSDC_INT); + writel(val, host->base + MSDC_INT); + +- writel(0, host->base + MSDC_PAD_TUNE); ++ writel(0, host->base + tune_reg); + writel(0, host->base + MSDC_IOCON); + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); + writel(0x403c0046, host->base + MSDC_PATCH_BIT); +@@ -1259,7 +1267,7 @@ static void msdc_init_hw(struct msdc_hos + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); + + host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); +- host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); ++ host->def_tune_para.pad_tune = readl(host->base + tune_reg); + dev_dbg(host->dev, "init hardware done!"); + } + +@@ -1402,18 +1410,19 @@ static int msdc_tune_response(struct mmc + struct msdc_delay_phase internal_delay_phase; + u8 final_delay, final_maxlen; + u32 internal_delay = 0; ++ u32 tune_reg = host->dev_comp->pad_tune_reg; + int cmd_err; + int i, j; + + if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || + mmc->ios.timing == MMC_TIMING_UHS_SDR104) +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRRDLY, + host->hs200_cmd_int_delay); + + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); + for (i = 0 ; i < PAD_DELAY_MAX; i++) { +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, i); + /* + * Using the same parameters, it may sometimes pass the test, +@@ -1437,7 +1446,7 @@ static int msdc_tune_response(struct mmc + + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); + for (i = 0; i < PAD_DELAY_MAX; i++) { +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRDLY, i); + /* + * Using the same parameters, it may sometimes pass the test, +@@ -1462,12 +1471,12 @@ skip_fall: + final_maxlen = final_fall_delay.maxlen; + if (final_maxlen == final_rise_delay.maxlen) { + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); +- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, ++ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, + final_rise_delay.final_phase); + final_delay = final_rise_delay.final_phase; + } else { + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); +- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, ++ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, + final_fall_delay.final_phase); + final_delay = final_fall_delay.final_phase; + } +@@ -1475,7 +1484,7 @@ skip_fall: + goto skip_internal; + + for (i = 0; i < PAD_DELAY_MAX; i++) { +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_CMDRRDLY, i); + mmc_send_tuning(mmc, opcode, &cmd_err); + if (!cmd_err) +@@ -1483,7 +1492,7 @@ skip_fall: + } + dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); + internal_delay_phase = get_best_delay(host, internal_delay); +- sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, ++ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, + internal_delay_phase.final_phase); + skip_internal: + dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); +@@ -1545,12 +1554,13 @@ static int msdc_tune_data(struct mmc_hos + u32 rise_delay = 0, fall_delay = 0; + struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; + u8 final_delay, final_maxlen; ++ u32 tune_reg = host->dev_comp->pad_tune_reg; + int i, ret; + + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + for (i = 0 ; i < PAD_DELAY_MAX; i++) { +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, i); + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) +@@ -1565,7 +1575,7 @@ static int msdc_tune_data(struct mmc_hos + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + for (i = 0; i < PAD_DELAY_MAX; i++) { +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, i); + ret = mmc_send_tuning(mmc, opcode, NULL); + if (!ret) +@@ -1578,14 +1588,14 @@ skip_fall: + if (final_maxlen == final_rise_delay.maxlen) { + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, + final_rise_delay.final_phase); + final_delay = final_rise_delay.final_phase; + } else { + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); +- sdr_set_field(host->base + MSDC_PAD_TUNE, ++ sdr_set_field(host->base + tune_reg, + MSDC_PAD_TUNE_DATRRDLY, + final_fall_delay.final_phase); + final_delay = final_fall_delay.final_phase; +@@ -1599,6 +1609,7 @@ static int msdc_execute_tuning(struct mm + { + struct msdc_host *host = mmc_priv(mmc); + int ret; ++ u32 tune_reg = host->dev_comp->pad_tune_reg; + + if (host->hs400_mode && + host->dev_comp->hs400_tune) +@@ -1616,7 +1627,7 @@ static int msdc_execute_tuning(struct mm + } + + host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); +- host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); ++ host->saved_tune_para.pad_tune = readl(host->base + tune_reg); + host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); + return ret; + } +@@ -1857,10 +1868,12 @@ static int msdc_drv_remove(struct platfo + #ifdef CONFIG_PM + static void msdc_save_reg(struct msdc_host *host) + { ++ u32 tune_reg = host->dev_comp->pad_tune_reg; ++ + host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); + host->save_para.iocon = readl(host->base + MSDC_IOCON); + host->save_para.sdc_cfg = readl(host->base + SDC_CFG); +- host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); ++ host->save_para.pad_tune = readl(host->base + tune_reg); + host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); + host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); + host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); +@@ -1870,10 +1883,12 @@ static void msdc_save_reg(struct msdc_ho + + static void msdc_restore_reg(struct msdc_host *host) + { ++ u32 tune_reg = host->dev_comp->pad_tune_reg; ++ + writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); + writel(host->save_para.iocon, host->base + MSDC_IOCON); + writel(host->save_para.sdc_cfg, host->base + SDC_CFG); +- writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); ++ writel(host->save_para.pad_tune, host->base + tune_reg); + writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); + writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); + writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); diff --git a/target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch b/target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch new file mode 100644 index 000000000..abb263b71 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0154-mmc-mediatek-add-async-fifo-and-data-tune-support.patch @@ -0,0 +1,170 @@ +From 830574225e621809600902b69bbdd563e67ef4eb Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:33 +0800 +Subject: [PATCH 154/224] mmc: mediatek: add async fifo and data tune support + +mt2701/mt2712 supports async fifo & data tune, which can improve +host stability. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 52 +++++++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 50 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -74,6 +74,7 @@ + #define MSDC_DMA_CFG 0x9c + #define MSDC_PATCH_BIT 0xb0 + #define MSDC_PATCH_BIT1 0xb4 ++#define MSDC_PATCH_BIT2 0xb8 + #define MSDC_PAD_TUNE 0xec + #define MSDC_PAD_TUNE0 0xf0 + #define PAD_DS_TUNE 0x188 +@@ -216,11 +217,20 @@ + #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ + #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ + ++#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ ++#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ ++#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ ++#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ ++#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ ++ + #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ + #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ + #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ + #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ + #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ ++#define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ ++#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ ++#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ + + #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ + #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ +@@ -294,6 +304,7 @@ struct msdc_save_para { + u32 pad_tune; + u32 patch_bit0; + u32 patch_bit1; ++ u32 patch_bit2; + u32 pad_ds_tune; + u32 pad_cmd_tune; + u32 emmc50_cfg0; +@@ -303,6 +314,8 @@ struct mtk_mmc_compatible { + u8 clk_div_bits; + bool hs400_tune; /* only used for MT8173 */ + u32 pad_tune_reg; ++ bool async_fifo; ++ bool data_tune; + }; + + struct msdc_tune_para { +@@ -365,24 +378,32 @@ static const struct mtk_mmc_compatible m + .clk_div_bits = 8, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE, ++ .async_fifo = false, ++ .data_tune = false, + }; + + static const struct mtk_mmc_compatible mt8173_compat = { + .clk_div_bits = 8, + .hs400_tune = true, + .pad_tune_reg = MSDC_PAD_TUNE, ++ .async_fifo = false, ++ .data_tune = false, + }; + + static const struct mtk_mmc_compatible mt2701_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, ++ .async_fifo = true, ++ .data_tune = true, + }; + + static const struct mtk_mmc_compatible mt2712_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, ++ .async_fifo = true, ++ .data_tune = true, + }; + + static const struct of_device_id msdc_of_ids[] = { +@@ -1252,8 +1273,29 @@ static void msdc_init_hw(struct msdc_hos + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); + writel(0x403c0046, host->base + MSDC_PATCH_BIT); + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); +- writel(0xffff0089, host->base + MSDC_PATCH_BIT1); ++ writel(0xffff4089, host->base + MSDC_PATCH_BIT1); + sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); ++ if (host->dev_comp->async_fifo) { ++ sdr_set_field(host->base + MSDC_PATCH_BIT2, ++ MSDC_PB2_RESPWAIT, 3); ++ sdr_set_field(host->base + MSDC_PATCH_BIT2, ++ MSDC_PB2_RESPSTSENSEL, 2); ++ sdr_set_field(host->base + MSDC_PATCH_BIT2, ++ MSDC_PB2_CRCSTSENSEL, 2); ++ /* use async fifo, then no need tune internal delay */ ++ sdr_clr_bits(host->base + MSDC_PATCH_BIT2, ++ MSDC_PATCH_BIT2_CFGRESP); ++ sdr_set_bits(host->base + MSDC_PATCH_BIT2, ++ MSDC_PATCH_BIT2_CFGCRCSTS); ++ } ++ ++ if (host->dev_comp->data_tune) { ++ sdr_set_bits(host->base + tune_reg, ++ MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); ++ } else { ++ /* choose clock tune */ ++ sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL); ++ } + + /* Configure to enable SDIO mode. + * it's must otherwise sdio cmd5 failed +@@ -1268,6 +1310,8 @@ static void msdc_init_hw(struct msdc_hos + + host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); + host->def_tune_para.pad_tune = readl(host->base + tune_reg); ++ host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); ++ host->saved_tune_para.pad_tune = readl(host->base + tune_reg); + dev_dbg(host->dev, "init hardware done!"); + } + +@@ -1480,7 +1524,7 @@ skip_fall: + final_fall_delay.final_phase); + final_delay = final_fall_delay.final_phase; + } +- if (host->hs200_cmd_int_delay) ++ if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) + goto skip_internal; + + for (i = 0; i < PAD_DELAY_MAX; i++) { +@@ -1638,6 +1682,8 @@ static int msdc_prepare_hs400_tuning(str + host->hs400_mode = true; + + writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); ++ /* hs400 mode must set it to 0 */ ++ sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); + return 0; + } + +@@ -1876,6 +1922,7 @@ static void msdc_save_reg(struct msdc_ho + host->save_para.pad_tune = readl(host->base + tune_reg); + host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); + host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); ++ host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); + host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); + host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); + host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); +@@ -1891,6 +1938,7 @@ static void msdc_restore_reg(struct msdc + writel(host->save_para.pad_tune, host->base + tune_reg); + writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); + writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); ++ writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); + writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); + writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); + writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); diff --git a/target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch b/target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch new file mode 100644 index 000000000..3bb2df6b5 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0155-mmc-mediatek-add-busy_check-support.patch @@ -0,0 +1,67 @@ +From 788d269aee4c612d5cd97b896ea5d22f19137097 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:34 +0800 +Subject: [PATCH 155/224] mmc: mediatek: add busy_check support + +bit7 of PATCH_BIT1 has different meaning in new design, to +compatible with previous platform, clear this bit in new +platform. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -316,6 +316,7 @@ struct mtk_mmc_compatible { + u32 pad_tune_reg; + bool async_fifo; + bool data_tune; ++ bool busy_check; + }; + + struct msdc_tune_para { +@@ -380,6 +381,7 @@ static const struct mtk_mmc_compatible m + .pad_tune_reg = MSDC_PAD_TUNE, + .async_fifo = false, + .data_tune = false, ++ .busy_check = false, + }; + + static const struct mtk_mmc_compatible mt8173_compat = { +@@ -388,6 +390,7 @@ static const struct mtk_mmc_compatible m + .pad_tune_reg = MSDC_PAD_TUNE, + .async_fifo = false, + .data_tune = false, ++ .busy_check = false, + }; + + static const struct mtk_mmc_compatible mt2701_compat = { +@@ -396,6 +399,7 @@ static const struct mtk_mmc_compatible m + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, ++ .busy_check = false, + }; + + static const struct mtk_mmc_compatible mt2712_compat = { +@@ -404,6 +408,7 @@ static const struct mtk_mmc_compatible m + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, ++ .busy_check = true, + }; + + static const struct of_device_id msdc_of_ids[] = { +@@ -1275,6 +1280,8 @@ static void msdc_init_hw(struct msdc_hos + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); + writel(0xffff4089, host->base + MSDC_PATCH_BIT1); + sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); ++ if (host->dev_comp->busy_check) ++ sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); + if (host->dev_comp->async_fifo) { + sdr_set_field(host->base + MSDC_PATCH_BIT2, + MSDC_PB2_RESPWAIT, 3); diff --git a/target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch b/target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch new file mode 100644 index 000000000..8db0a279e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0156-mmc-mediatek-add-stop_clk-fix-and-enhance_rx-support.patch @@ -0,0 +1,168 @@ +From 9257240bcaf8f9ee6878357e00e7ab511ad6d325 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:35 +0800 +Subject: [PATCH 156/224] mmc: mediatek: add stop_clk fix and enhance_rx + support + +mt2712 supports stop_clk fix and enhance_rx, which can improve +host stability. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 47 +++++++++++++++++++++++++++++++++++++++++++---- + 1 file changed, 43 insertions(+), 4 deletions(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -67,6 +67,7 @@ + #define SDC_RESP2 0x48 + #define SDC_RESP3 0x4c + #define SDC_BLK_NUM 0x50 ++#define SDC_ADV_CFG0 0x64 + #define EMMC_IOCON 0x7c + #define SDC_ACMD_RESP 0x80 + #define MSDC_DMA_SA 0x90 +@@ -80,6 +81,7 @@ + #define PAD_DS_TUNE 0x188 + #define PAD_CMD_TUNE 0x18c + #define EMMC50_CFG0 0x208 ++#define SDC_FIFO_CFG 0x228 + + /*--------------------------------------------------------------------------*/ + /* Register Mask */ +@@ -188,6 +190,9 @@ + #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ + #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ + ++/* SDC_ADV_CFG0 mask */ ++#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ ++ + /* MSDC_DMA_CTRL mask */ + #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ + #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ +@@ -217,6 +222,8 @@ + #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ + #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ + ++#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ ++ + #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ + #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ + #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ +@@ -242,6 +249,9 @@ + #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ + #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ + ++#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ ++#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ ++ + #define REQ_CMD_EIO (0x1 << 0) + #define REQ_CMD_TMO (0x1 << 1) + #define REQ_DAT_ERR (0x1 << 2) +@@ -308,6 +318,7 @@ struct msdc_save_para { + u32 pad_ds_tune; + u32 pad_cmd_tune; + u32 emmc50_cfg0; ++ u32 sdc_fifo_cfg; + }; + + struct mtk_mmc_compatible { +@@ -317,6 +328,8 @@ struct mtk_mmc_compatible { + bool async_fifo; + bool data_tune; + bool busy_check; ++ bool stop_clk_fix; ++ bool enhance_rx; + }; + + struct msdc_tune_para { +@@ -382,6 +395,8 @@ static const struct mtk_mmc_compatible m + .async_fifo = false, + .data_tune = false, + .busy_check = false, ++ .stop_clk_fix = false, ++ .enhance_rx = false, + }; + + static const struct mtk_mmc_compatible mt8173_compat = { +@@ -391,6 +406,8 @@ static const struct mtk_mmc_compatible m + .async_fifo = false, + .data_tune = false, + .busy_check = false, ++ .stop_clk_fix = false, ++ .enhance_rx = false, + }; + + static const struct mtk_mmc_compatible mt2701_compat = { +@@ -400,6 +417,8 @@ static const struct mtk_mmc_compatible m + .async_fifo = true, + .data_tune = true, + .busy_check = false, ++ .stop_clk_fix = false, ++ .enhance_rx = false, + }; + + static const struct mtk_mmc_compatible mt2712_compat = { +@@ -409,6 +428,8 @@ static const struct mtk_mmc_compatible m + .async_fifo = true, + .data_tune = true, + .busy_check = true, ++ .stop_clk_fix = true, ++ .enhance_rx = true, + }; + + static const struct of_device_id msdc_of_ids[] = { +@@ -1280,15 +1301,31 @@ static void msdc_init_hw(struct msdc_hos + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); + writel(0xffff4089, host->base + MSDC_PATCH_BIT1); + sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); ++ ++ if (host->dev_comp->stop_clk_fix) { ++ sdr_set_field(host->base + MSDC_PATCH_BIT1, ++ MSDC_PATCH_BIT1_STOP_DLY, 3); ++ sdr_clr_bits(host->base + SDC_FIFO_CFG, ++ SDC_FIFO_CFG_WRVALIDSEL); ++ sdr_clr_bits(host->base + SDC_FIFO_CFG, ++ SDC_FIFO_CFG_RDVALIDSEL); ++ } ++ + if (host->dev_comp->busy_check) + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); ++ + if (host->dev_comp->async_fifo) { + sdr_set_field(host->base + MSDC_PATCH_BIT2, + MSDC_PB2_RESPWAIT, 3); +- sdr_set_field(host->base + MSDC_PATCH_BIT2, +- MSDC_PB2_RESPSTSENSEL, 2); +- sdr_set_field(host->base + MSDC_PATCH_BIT2, +- MSDC_PB2_CRCSTSENSEL, 2); ++ if (host->dev_comp->enhance_rx) { ++ sdr_set_bits(host->base + SDC_ADV_CFG0, ++ SDC_RX_ENHANCE_EN); ++ } else { ++ sdr_set_field(host->base + MSDC_PATCH_BIT2, ++ MSDC_PB2_RESPSTSENSEL, 2); ++ sdr_set_field(host->base + MSDC_PATCH_BIT2, ++ MSDC_PB2_CRCSTSENSEL, 2); ++ } + /* use async fifo, then no need tune internal delay */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT2, + MSDC_PATCH_BIT2_CFGRESP); +@@ -1933,6 +1970,7 @@ static void msdc_save_reg(struct msdc_ho + host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); + host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); + host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); ++ host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); + } + + static void msdc_restore_reg(struct msdc_host *host) +@@ -1949,6 +1987,7 @@ static void msdc_restore_reg(struct msdc + writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); + writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); + writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); ++ writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); + } + + static int msdc_runtime_suspend(struct device *dev) diff --git a/target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch b/target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch new file mode 100644 index 000000000..8a183ceb5 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0157-mmc-mediatek-add-support-of-source_cg-clock.patch @@ -0,0 +1,85 @@ +From 3c6b94d7091f0793445f2faf777e584af643e9da Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:36 +0800 +Subject: [PATCH 157/224] mmc: mediatek: add support of source_cg clock + +source clock need an independent cg to control, when doing clk mode +switch, need gate source clock to avoid hw issue(multi-bit sync hw hang) + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -372,6 +372,7 @@ struct msdc_host { + + struct clk *src_clk; /* msdc source clock */ + struct clk *h_clk; /* msdc h_clk */ ++ struct clk *src_clk_cg; /* msdc source clock control gate */ + u32 mclk; /* mmc subsystem clock frequency */ + u32 src_clk_freq; /* source clock frequency */ + u32 sclk; /* SD/MS bus clock frequency */ +@@ -616,6 +617,7 @@ static void msdc_set_timeout(struct msdc + + static void msdc_gate_clock(struct msdc_host *host) + { ++ clk_disable_unprepare(host->src_clk_cg); + clk_disable_unprepare(host->src_clk); + clk_disable_unprepare(host->h_clk); + } +@@ -624,6 +626,7 @@ static void msdc_ungate_clock(struct msd + { + clk_prepare_enable(host->h_clk); + clk_prepare_enable(host->src_clk); ++ clk_prepare_enable(host->src_clk_cg); + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) + cpu_relax(); + } +@@ -692,6 +695,15 @@ static void msdc_set_mclk(struct msdc_ho + sclk = (host->src_clk_freq >> 2) / div; + } + } ++ sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); ++ /* ++ * As src_clk/HCLK use the same bit to gate/ungate, ++ * So if want to only gate src_clk, need gate its parent(mux). ++ */ ++ if (host->src_clk_cg) ++ clk_disable_unprepare(host->src_clk_cg); ++ else ++ clk_disable_unprepare(clk_get_parent(host->src_clk)); + if (host->dev_comp->clk_div_bits == 8) + sdr_set_field(host->base + MSDC_CFG, + MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, +@@ -700,10 +712,14 @@ static void msdc_set_mclk(struct msdc_ho + sdr_set_field(host->base + MSDC_CFG, + MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, + (mode << 12) | div); ++ if (host->src_clk_cg) ++ clk_prepare_enable(host->src_clk_cg); ++ else ++ clk_prepare_enable(clk_get_parent(host->src_clk)); + +- sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) + cpu_relax(); ++ sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); + host->sclk = sclk; + host->mclk = hz; + host->timing = timing; +@@ -1822,6 +1838,11 @@ static int msdc_drv_probe(struct platfor + goto host_free; + } + ++ /*source clock control gate is optional clock*/ ++ host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); ++ if (IS_ERR(host->src_clk_cg)) ++ host->src_clk_cg = NULL; ++ + host->irq = platform_get_irq(pdev, 0); + if (host->irq < 0) { + ret = -EINVAL; diff --git a/target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch b/target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch new file mode 100644 index 000000000..cad45f6cf --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0158-mmc-mediatek-add-latch-ck-support.patch @@ -0,0 +1,45 @@ +From de14d1d0dc7ecf5c3e7e2a591b4f14e688fa52e6 Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:37 +0800 +Subject: [PATCH 158/224] mmc: mediatek: add latch-ck support + +some platform(eg.mt2701) does not support "stop clk fix", in +this case, need set correct latch-ck to avoid crc error caused +by stop clock block-internally. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -378,6 +378,7 @@ struct msdc_host { + u32 sclk; /* SD/MS bus clock frequency */ + unsigned char timing; + bool vqmmc_enabled; ++ u32 latch_ck; + u32 hs400_ds_delay; + u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ + u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ +@@ -1661,6 +1662,8 @@ static int msdc_tune_data(struct mmc_hos + u32 tune_reg = host->dev_comp->pad_tune_reg; + int i, ret; + ++ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, ++ host->latch_ck); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); + for (i = 0 ; i < PAD_DELAY_MAX; i++) { +@@ -1773,6 +1776,9 @@ static const struct mmc_host_ops mt_msdc + static void msdc_of_property_parse(struct platform_device *pdev, + struct msdc_host *host) + { ++ of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", ++ &host->latch_ck); ++ + of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", + &host->hs400_ds_delay); + diff --git a/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch b/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch new file mode 100644 index 000000000..63aef198c --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0159-mmc-mediatek-improve-eMMC-hs400-mode-read-performanc.patch @@ -0,0 +1,68 @@ +From 29e154716049310bb8c559f742bf2b460d5b6bbc Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:38 +0800 +Subject: [PATCH 159/224] mmc: mediatek: improve eMMC hs400 mode read + performance + +enlarge outstanding value to improve read performance + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -81,6 +81,7 @@ + #define PAD_DS_TUNE 0x188 + #define PAD_CMD_TUNE 0x18c + #define EMMC50_CFG0 0x208 ++#define EMMC50_CFG3 0x220 + #define SDC_FIFO_CFG 0x228 + + /*--------------------------------------------------------------------------*/ +@@ -249,6 +250,8 @@ + #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ + #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ + ++#define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ ++ + #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ + #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ + +@@ -318,6 +321,7 @@ struct msdc_save_para { + u32 pad_ds_tune; + u32 pad_cmd_tune; + u32 emmc50_cfg0; ++ u32 emmc50_cfg3; + u32 sdc_fifo_cfg; + }; + +@@ -1747,6 +1751,9 @@ static int msdc_prepare_hs400_tuning(str + writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); + /* hs400 mode must set it to 0 */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); ++ /* to improve read performance, set outstanding to 2 */ ++ sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); ++ + return 0; + } + +@@ -1997,6 +2004,7 @@ static void msdc_save_reg(struct msdc_ho + host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); + host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); + host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); ++ host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); + host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); + } + +@@ -2014,6 +2022,7 @@ static void msdc_restore_reg(struct msdc + writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); + writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); + writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); ++ writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); + writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); + } + diff --git a/target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch b/target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch new file mode 100644 index 000000000..6da13bec6 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0160-mmc-mediatek-perfer-to-use-rise-edge-latching-for-cm.patch @@ -0,0 +1,28 @@ +From 81fdc4983e33ef01935a9bf01187951aad34e2ac Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Mon, 16 Oct 2017 09:46:39 +0800 +Subject: [PATCH 160/224] mmc: mediatek: perfer to use rise edge latching for + cmd line + +data lines have applied to perfer to use rise edge, also need +apply it to cmd line. + +Signed-off-by: Chaotian Jing +Tested-by: Sean Wang +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mtk-sd.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -1550,7 +1550,8 @@ static int msdc_tune_response(struct mmc + } + final_rise_delay = get_best_delay(host, rise_delay); + /* if rising edge has enough margin, then do not scan falling edge */ +- if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4) ++ if (final_rise_delay.maxlen >= 12 || ++ (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) + goto skip_fall; + + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); diff --git a/target/linux/mediatek/patches-4.14/0161-pwm-mediatek-Add-MT2712-MT7622-support.patch b/target/linux/mediatek/patches-4.14/0161-pwm-mediatek-Add-MT2712-MT7622-support.patch new file mode 100644 index 000000000..bca6ed5bb --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0161-pwm-mediatek-Add-MT2712-MT7622-support.patch @@ -0,0 +1,145 @@ +From 7cc8226e45b2c6b9f06ce82ba6995b8f911afe25 Mon Sep 17 00:00:00 2001 +From: Zhi Mao +Date: Wed, 25 Oct 2017 18:11:01 +0800 +Subject: [PATCH 161/224] pwm: mediatek: Add MT2712/MT7622 support + +Add support for MT2712 and MT7622. Due to register offset address of +pwm7 for MT2712 is not fixed 0x40, add mtk_pwm_reg_offset array for PWM +register offset. + +Reviewed-by: Claudiu Beznea +Reviewed-by: Matthias Brugger +Signed-off-by: Zhi Mao +Signed-off-by: Thierry Reding +--- + drivers/pwm/pwm-mediatek.c | 53 ++++++++++++++++++++++++++++++++++++++-------- + 1 file changed, 44 insertions(+), 9 deletions(-) + +--- a/drivers/pwm/pwm-mediatek.c ++++ b/drivers/pwm/pwm-mediatek.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -40,11 +41,19 @@ enum { + MTK_CLK_PWM3, + MTK_CLK_PWM4, + MTK_CLK_PWM5, ++ MTK_CLK_PWM6, ++ MTK_CLK_PWM7, ++ MTK_CLK_PWM8, + MTK_CLK_MAX, + }; + +-static const char * const mtk_pwm_clk_name[] = { +- "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5" ++static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { ++ "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", ++ "pwm8" ++}; ++ ++struct mtk_pwm_platform_data { ++ unsigned int num_pwms; + }; + + /** +@@ -59,6 +68,10 @@ struct mtk_pwm_chip { + struct clk *clks[MTK_CLK_MAX]; + }; + ++static const unsigned int mtk_pwm_reg_offset[] = { ++ 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 ++}; ++ + static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) + { + return container_of(chip, struct mtk_pwm_chip, chip); +@@ -103,14 +116,14 @@ static void mtk_pwm_clk_disable(struct p + static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, + unsigned int offset) + { +- return readl(chip->regs + 0x10 + (num * 0x40) + offset); ++ return readl(chip->regs + mtk_pwm_reg_offset[num] + offset); + } + + static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, + unsigned int num, unsigned int offset, + u32 value) + { +- writel(value, chip->regs + 0x10 + (num * 0x40) + offset); ++ writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset); + } + + static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, +@@ -185,6 +198,7 @@ static const struct pwm_ops mtk_pwm_ops + + static int mtk_pwm_probe(struct platform_device *pdev) + { ++ const struct mtk_pwm_platform_data *data; + struct mtk_pwm_chip *pc; + struct resource *res; + unsigned int i; +@@ -194,15 +208,22 @@ static int mtk_pwm_probe(struct platform + if (!pc) + return -ENOMEM; + ++ data = of_device_get_match_data(&pdev->dev); ++ if (data == NULL) ++ return -EINVAL; ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pc->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pc->regs)) + return PTR_ERR(pc->regs); + +- for (i = 0; i < MTK_CLK_MAX; i++) { ++ for (i = 0; i < data->num_pwms + 2; i++) { + pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); +- if (IS_ERR(pc->clks[i])) ++ if (IS_ERR(pc->clks[i])) { ++ dev_err(&pdev->dev, "clock: %s fail: %ld\n", ++ mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i])); + return PTR_ERR(pc->clks[i]); ++ } + } + + platform_set_drvdata(pdev, pc); +@@ -210,7 +231,7 @@ static int mtk_pwm_probe(struct platform + pc->chip.dev = &pdev->dev; + pc->chip.ops = &mtk_pwm_ops; + pc->chip.base = -1; +- pc->chip.npwm = 5; ++ pc->chip.npwm = data->num_pwms; + + ret = pwmchip_add(&pc->chip); + if (ret < 0) { +@@ -228,9 +249,23 @@ static int mtk_pwm_remove(struct platfor + return pwmchip_remove(&pc->chip); + } + ++static const struct mtk_pwm_platform_data mt2712_pwm_data = { ++ .num_pwms = 8, ++}; ++ ++static const struct mtk_pwm_platform_data mt7622_pwm_data = { ++ .num_pwms = 6, ++}; ++ ++static const struct mtk_pwm_platform_data mt7623_pwm_data = { ++ .num_pwms = 5, ++}; ++ + static const struct of_device_id mtk_pwm_of_match[] = { +- { .compatible = "mediatek,mt7623-pwm" }, +- { } ++ { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, ++ { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, ++ { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, ++ { }, + }; + MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); + diff --git a/target/linux/mediatek/patches-4.14/0162-mtd-nand-mtk-use-nand_reset-to-reset-NAND-devices-in.patch b/target/linux/mediatek/patches-4.14/0162-mtd-nand-mtk-use-nand_reset-to-reset-NAND-devices-in.patch new file mode 100644 index 000000000..d27209292 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0162-mtd-nand-mtk-use-nand_reset-to-reset-NAND-devices-in.patch @@ -0,0 +1,41 @@ +From fb607c7c1eaeb47ec2ffed99cab571892cb6af7d Mon Sep 17 00:00:00 2001 +From: Xiaolei Li +Date: Thu, 2 Nov 2017 10:05:07 +0800 +Subject: [PATCH 162/224] mtd: nand: mtk: use nand_reset() to reset NAND + devices in resume function + +Previously, we only select chips and then send reset command to a NAND +device during resuming nand driver. There is a lack of deselecting chips. +It is advised to reset and initialize a NAND device using nand_reset(). + +Signed-off-by: Xiaolei Li +Reviewed-by: Matthias Brugger +Signed-off-by: Boris Brezillon +--- + drivers/mtd/nand/mtk_nand.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +--- a/drivers/mtd/nand/mtk_nand.c ++++ b/drivers/mtd/nand/mtk_nand.c +@@ -1540,7 +1540,6 @@ static int mtk_nfc_resume(struct device + struct mtk_nfc *nfc = dev_get_drvdata(dev); + struct mtk_nfc_nand_chip *chip; + struct nand_chip *nand; +- struct mtd_info *mtd; + int ret; + u32 i; + +@@ -1553,11 +1552,8 @@ static int mtk_nfc_resume(struct device + /* reset NAND chip if VCC was powered off */ + list_for_each_entry(chip, &nfc->chips, node) { + nand = &chip->nand; +- mtd = nand_to_mtd(nand); +- for (i = 0; i < chip->nsels; i++) { +- nand->select_chip(mtd, i); +- nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); +- } ++ for (i = 0; i < chip->nsels; i++) ++ nand_reset(nand, i); + } + + return 0; diff --git a/target/linux/mediatek/patches-4.14/0164-cpufreq-mediatek-add-mt2712-into-compatible-list.patch b/target/linux/mediatek/patches-4.14/0164-cpufreq-mediatek-add-mt2712-into-compatible-list.patch new file mode 100644 index 000000000..865e82ee1 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0164-cpufreq-mediatek-add-mt2712-into-compatible-list.patch @@ -0,0 +1,24 @@ +From f027d8b7248cef5b3d3eb8ac68e1040fba340995 Mon Sep 17 00:00:00 2001 +From: Andrew-sh Cheng +Date: Fri, 8 Dec 2017 14:07:55 +0800 +Subject: [PATCH 164/224] cpufreq: mediatek: add mt2712 into compatible list + +Support mt2712 in mediatek-cpufreq.c + +Signed-off-by: Andrew-sh Cheng +Acked-by: Viresh Kumar +Signed-off-by: Rafael J. Wysocki +--- + drivers/cpufreq/mediatek-cpufreq.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -574,6 +574,7 @@ static struct platform_driver mtk_cpufre + /* List of machines supported by this driver */ + static const struct of_device_id mtk_cpufreq_machines[] __initconst = { + { .compatible = "mediatek,mt2701", }, ++ { .compatible = "mediatek,mt2712", }, + { .compatible = "mediatek,mt7622", }, + { .compatible = "mediatek,mt7623", }, + { .compatible = "mediatek,mt817x", }, diff --git a/target/linux/mediatek/patches-4.14/0165-mtd-nand-mtk-update-DT-bindings.patch b/target/linux/mediatek/patches-4.14/0165-mtd-nand-mtk-update-DT-bindings.patch new file mode 100644 index 000000000..d49f8cba0 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0165-mtd-nand-mtk-update-DT-bindings.patch @@ -0,0 +1,41 @@ +From 42611c6d9f12d16ce4247d76b16218e54ef5b949 Mon Sep 17 00:00:00 2001 +From: RogerCC Lin +Date: Thu, 30 Nov 2017 22:10:43 +0800 +Subject: [PATCH 165/224] mtd: nand: mtk: update DT bindings + +Add MT7622 NAND Flash Controller dt bindings documentation. + +Signed-off-by: RogerCC Lin +Reviewed-by: Matthias Brugger +Signed-off-by: Boris Brezillon +--- + Documentation/devicetree/bindings/mtd/mtk-nand.txt | 11 ++++++++--- + 1 file changed, 8 insertions(+), 3 deletions(-) + +--- a/Documentation/devicetree/bindings/mtd/mtk-nand.txt ++++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt +@@ -12,8 +12,10 @@ tree nodes. + + The first part of NFC is NAND Controller Interface (NFI) HW. + Required NFI properties: +-- compatible: Should be one of "mediatek,mt2701-nfc", +- "mediatek,mt2712-nfc". ++- compatible: Should be one of ++ "mediatek,mt2701-nfc", ++ "mediatek,mt2712-nfc", ++ "mediatek,mt7622-nfc". + - reg: Base physical address and size of NFI. + - interrupts: Interrupts of NFI. + - clocks: NFI required clocks. +@@ -142,7 +144,10 @@ Example: + ============== + + Required BCH properties: +-- compatible: Should be one of "mediatek,mt2701-ecc", "mediatek,mt2712-ecc". ++- compatible: Should be one of ++ "mediatek,mt2701-ecc", ++ "mediatek,mt2712-ecc", ++ "mediatek,mt7622-ecc". + - reg: Base physical address and size of ECC. + - interrupts: Interrupts of ECC. + - clocks: ECC required clocks. diff --git a/target/linux/mediatek/patches-4.14/0166-mtd-nand-mtk-Support-different-MTK-NAND-flash-contro.patch b/target/linux/mediatek/patches-4.14/0166-mtd-nand-mtk-Support-different-MTK-NAND-flash-contro.patch new file mode 100644 index 000000000..437901c94 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0166-mtd-nand-mtk-Support-different-MTK-NAND-flash-contro.patch @@ -0,0 +1,380 @@ +From fd1a1eabf2473e769b5cafc704e0336d11f61961 Mon Sep 17 00:00:00 2001 +From: RogerCC Lin +Date: Thu, 30 Nov 2017 22:10:44 +0800 +Subject: [PATCH 166/224] mtd: nand: mtk: Support different MTK NAND flash + controller IP + +MT7622 uses an MTK's earlier NAND flash controller IP which support +different sector size, max spare size per sector and paraity bits..., +some register's offset and definition also been changed in the NAND +flash controller, this patch is the preparation to support MT7622 +NAND flash controller. + +MT7622 NFC and ECC engine are similar to MT2701's, except below +differences: +(1)MT7622 NFC's max sector size(ECC data size) is 512 bytes, and + MT2701's is 1024, and MT7622's max sector number is 8. +(2)The parity bit of MT7622 is 13, MT2701 is 14. +(3)MT7622 ECC supports less ECC strength, max to 16 bit ecc strength. +(4)MT7622 supports less spare size per sector, max spare size per + sector is 28 bytes. +(5)Some register's offset are different, include ECC_ENCIRQ_EN, + ECC_ENCIRQ_STA, ECC_DECDONE, ECC_DECIRQ_EN and ECC_DECIRQ_STA. +(6)ENC_MODE of ECC_ENCCNFG register is moved from bit 5-6 to bit 4-5. + +Signed-off-by: RogerCC Lin +Signed-off-by: Boris Brezillon +--- + drivers/mtd/nand/mtk_ecc.c | 100 ++++++++++++++++++++++++++++++-------------- + drivers/mtd/nand/mtk_ecc.h | 3 +- + drivers/mtd/nand/mtk_nand.c | 27 ++++++++---- + 3 files changed, 89 insertions(+), 41 deletions(-) + +--- a/drivers/mtd/nand/mtk_ecc.c ++++ b/drivers/mtd/nand/mtk_ecc.c +@@ -34,34 +34,28 @@ + + #define ECC_ENCCON (0x00) + #define ECC_ENCCNFG (0x04) +-#define ECC_MODE_SHIFT (5) + #define ECC_MS_SHIFT (16) + #define ECC_ENCDIADDR (0x08) + #define ECC_ENCIDLE (0x0C) +-#define ECC_ENCIRQ_EN (0x80) +-#define ECC_ENCIRQ_STA (0x84) + #define ECC_DECCON (0x100) + #define ECC_DECCNFG (0x104) + #define DEC_EMPTY_EN BIT(31) + #define DEC_CNFG_CORRECT (0x3 << 12) + #define ECC_DECIDLE (0x10C) + #define ECC_DECENUM0 (0x114) +-#define ECC_DECDONE (0x124) +-#define ECC_DECIRQ_EN (0x200) +-#define ECC_DECIRQ_STA (0x204) + + #define ECC_TIMEOUT (500000) + + #define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) + #define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) +-#define ECC_IRQ_REG(op) ((op) == ECC_ENCODE ? \ +- ECC_ENCIRQ_EN : ECC_DECIRQ_EN) + + struct mtk_ecc_caps { + u32 err_mask; + const u8 *ecc_strength; ++ const u32 *ecc_regs; + u8 num_ecc_strength; +- u32 encode_parity_reg0; ++ u8 ecc_mode_shift; ++ u32 parity_bits; + int pg_irq_sel; + }; + +@@ -89,6 +83,33 @@ static const u8 ecc_strength_mt2712[] = + 40, 44, 48, 52, 56, 60, 68, 72, 80 + }; + ++enum mtk_ecc_regs { ++ ECC_ENCPAR00, ++ ECC_ENCIRQ_EN, ++ ECC_ENCIRQ_STA, ++ ECC_DECDONE, ++ ECC_DECIRQ_EN, ++ ECC_DECIRQ_STA, ++}; ++ ++static int mt2701_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt2712_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x300, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ + static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, + enum mtk_ecc_operation op) + { +@@ -107,32 +128,30 @@ static inline void mtk_ecc_wait_idle(str + static irqreturn_t mtk_ecc_irq(int irq, void *id) + { + struct mtk_ecc *ecc = id; +- enum mtk_ecc_operation op; + u32 dec, enc; + +- dec = readw(ecc->regs + ECC_DECIRQ_STA) & ECC_IRQ_EN; ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) ++ & ECC_IRQ_EN; + if (dec) { +- op = ECC_DECODE; +- dec = readw(ecc->regs + ECC_DECDONE); ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); + if (dec & ecc->sectors) { + /* + * Clear decode IRQ status once again to ensure that + * there will be no extra IRQ. + */ +- readw(ecc->regs + ECC_DECIRQ_STA); ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); + ecc->sectors = 0; + complete(&ecc->done); + } else { + return IRQ_HANDLED; + } + } else { +- enc = readl(ecc->regs + ECC_ENCIRQ_STA) & ECC_IRQ_EN; +- if (enc) { +- op = ECC_ENCODE; ++ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (enc) + complete(&ecc->done); +- } else { ++ else + return IRQ_NONE; +- } + } + + return IRQ_HANDLED; +@@ -160,7 +179,7 @@ static int mtk_ecc_config(struct mtk_ecc + /* configure ECC encoder (in bits) */ + enc_sz = config->len << 3; + +- reg = ecc_bit | (config->mode << ECC_MODE_SHIFT); ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); + reg |= (enc_sz << ECC_MS_SHIFT); + writel(reg, ecc->regs + ECC_ENCCNFG); + +@@ -171,9 +190,9 @@ static int mtk_ecc_config(struct mtk_ecc + } else { + /* configure ECC decoder (in bits) */ + dec_sz = (config->len << 3) + +- config->strength * ECC_PARITY_BITS; ++ config->strength * ecc->caps->parity_bits; + +- reg = ecc_bit | (config->mode << ECC_MODE_SHIFT); ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); + reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; + reg |= DEC_EMPTY_EN; + writel(reg, ecc->regs + ECC_DECCNFG); +@@ -291,7 +310,12 @@ int mtk_ecc_enable(struct mtk_ecc *ecc, + */ + if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) + reg_val |= ECC_PG_IRQ_SEL; +- writew(reg_val, ecc->regs + ECC_IRQ_REG(op)); ++ if (op == ECC_ENCODE) ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ else ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_DECIRQ_EN]); + } + + writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); +@@ -310,13 +334,17 @@ void mtk_ecc_disable(struct mtk_ecc *ecc + + /* disable it */ + mtk_ecc_wait_idle(ecc, op); +- if (op == ECC_DECODE) ++ if (op == ECC_DECODE) { + /* + * Clear decode IRQ status in case there is a timeout to wait + * decode IRQ. + */ +- readw(ecc->regs + ECC_DECIRQ_STA); +- writew(0, ecc->regs + ECC_IRQ_REG(op)); ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } else { ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ } ++ + writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); + + mutex_unlock(&ecc->lock); +@@ -367,11 +395,11 @@ int mtk_ecc_encode(struct mtk_ecc *ecc, + mtk_ecc_wait_idle(ecc, ECC_ENCODE); + + /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ +- len = (config->strength * ECC_PARITY_BITS + 7) >> 3; ++ len = (config->strength * ecc->caps->parity_bits + 7) >> 3; + + /* write the parity bytes generated by the ECC back to temp buffer */ + __ioread32_copy(ecc->eccdata, +- ecc->regs + ecc->caps->encode_parity_reg0, ++ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], + round_up(len, 4)); + + /* copy into possibly unaligned OOB region with actual length */ +@@ -404,19 +432,29 @@ void mtk_ecc_adjust_strength(struct mtk_ + } + EXPORT_SYMBOL(mtk_ecc_adjust_strength); + ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) ++{ ++ return ecc->caps->parity_bits; ++} ++EXPORT_SYMBOL(mtk_ecc_get_parity_bits); ++ + static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { + .err_mask = 0x3f, + .ecc_strength = ecc_strength_mt2701, ++ .ecc_regs = mt2701_ecc_regs, + .num_ecc_strength = 20, +- .encode_parity_reg0 = 0x10, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, + .pg_irq_sel = 0, + }; + + static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { + .err_mask = 0x7f, + .ecc_strength = ecc_strength_mt2712, ++ .ecc_regs = mt2712_ecc_regs, + .num_ecc_strength = 23, +- .encode_parity_reg0 = 0x300, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, + .pg_irq_sel = 1, + }; + +@@ -452,7 +490,7 @@ static int mtk_ecc_probe(struct platform + + max_eccdata_size = ecc->caps->num_ecc_strength - 1; + max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; +- max_eccdata_size = (max_eccdata_size * ECC_PARITY_BITS + 7) >> 3; ++ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; + max_eccdata_size = round_up(max_eccdata_size, 4); + ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); + if (!ecc->eccdata) +--- a/drivers/mtd/nand/mtk_ecc.h ++++ b/drivers/mtd/nand/mtk_ecc.h +@@ -14,8 +14,6 @@ + + #include + +-#define ECC_PARITY_BITS (14) +- + enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; + enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; + +@@ -43,6 +41,7 @@ int mtk_ecc_wait_done(struct mtk_ecc *, + int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); + void mtk_ecc_disable(struct mtk_ecc *); + void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); + + struct mtk_ecc *of_mtk_ecc_get(struct device_node *); + void mtk_ecc_release(struct mtk_ecc *); +--- a/drivers/mtd/nand/mtk_nand.c ++++ b/drivers/mtd/nand/mtk_nand.c +@@ -97,7 +97,6 @@ + + #define MTK_TIMEOUT (500000) + #define MTK_RESET_TIMEOUT (1000000) +-#define MTK_MAX_SECTOR (16) + #define MTK_NAND_MAX_NSELS (2) + #define MTK_NFC_MIN_SPARE (16) + #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \ +@@ -109,6 +108,8 @@ struct mtk_nfc_caps { + u8 num_spare_size; + u8 pageformat_spare_shift; + u8 nfi_clk_div; ++ u8 max_sector; ++ u32 max_sector_size; + }; + + struct mtk_nfc_bad_mark_ctl { +@@ -450,7 +451,7 @@ static inline u8 mtk_nfc_read_byte(struc + * set to max sector to allow the HW to continue reading over + * unaligned accesses + */ +- reg = (MTK_MAX_SECTOR << CON_SEC_SHIFT) | CON_BRD; ++ reg = (nfc->caps->max_sector << CON_SEC_SHIFT) | CON_BRD; + nfi_writel(nfc, reg, NFI_CON); + + /* trigger to fetch data */ +@@ -481,7 +482,7 @@ static void mtk_nfc_write_byte(struct mt + reg = nfi_readw(nfc, NFI_CNFG) | CNFG_BYTE_RW; + nfi_writew(nfc, reg, NFI_CNFG); + +- reg = MTK_MAX_SECTOR << CON_SEC_SHIFT | CON_BWR; ++ reg = nfc->caps->max_sector << CON_SEC_SHIFT | CON_BWR; + nfi_writel(nfc, reg, NFI_CON); + + nfi_writew(nfc, STAR_EN, NFI_STRDATA); +@@ -1126,9 +1127,11 @@ static void mtk_nfc_set_fdm(struct mtk_n + { + struct nand_chip *nand = mtd_to_nand(mtd); + struct mtk_nfc_nand_chip *chip = to_mtk_nand(nand); ++ struct mtk_nfc *nfc = nand_get_controller_data(nand); + u32 ecc_bytes; + +- ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8); ++ ecc_bytes = DIV_ROUND_UP(nand->ecc.strength * ++ mtk_ecc_get_parity_bits(nfc->ecc), 8); + + fdm->reg_size = chip->spare_per_sector - ecc_bytes; + if (fdm->reg_size > NFI_FDM_MAX_SIZE) +@@ -1208,7 +1211,8 @@ static int mtk_nfc_ecc_init(struct devic + * this controller only supports 512 and 1024 sizes + */ + if (nand->ecc.size < 1024) { +- if (mtd->writesize > 512) { ++ if (mtd->writesize > 512 && ++ nfc->caps->max_sector_size > 512) { + nand->ecc.size = 1024; + nand->ecc.strength <<= 1; + } else { +@@ -1223,7 +1227,8 @@ static int mtk_nfc_ecc_init(struct devic + return ret; + + /* calculate oob bytes except ecc parity data */ +- free = ((nand->ecc.strength * ECC_PARITY_BITS) + 7) >> 3; ++ free = (nand->ecc.strength * mtk_ecc_get_parity_bits(nfc->ecc) ++ + 7) >> 3; + free = spare - free; + + /* +@@ -1233,10 +1238,12 @@ static int mtk_nfc_ecc_init(struct devic + */ + if (free > NFI_FDM_MAX_SIZE) { + spare -= NFI_FDM_MAX_SIZE; +- nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS; ++ nand->ecc.strength = (spare << 3) / ++ mtk_ecc_get_parity_bits(nfc->ecc); + } else if (free < 0) { + spare -= NFI_FDM_MIN_SIZE; +- nand->ecc.strength = (spare << 3) / ECC_PARITY_BITS; ++ nand->ecc.strength = (spare << 3) / ++ mtk_ecc_get_parity_bits(nfc->ecc); + } + } + +@@ -1389,6 +1396,8 @@ static const struct mtk_nfc_caps mtk_nfc + .num_spare_size = 16, + .pageformat_spare_shift = 4, + .nfi_clk_div = 1, ++ .max_sector = 16, ++ .max_sector_size = 1024, + }; + + static const struct mtk_nfc_caps mtk_nfc_caps_mt2712 = { +@@ -1396,6 +1405,8 @@ static const struct mtk_nfc_caps mtk_nfc + .num_spare_size = 19, + .pageformat_spare_shift = 16, + .nfi_clk_div = 2, ++ .max_sector = 16, ++ .max_sector_size = 1024, + }; + + static const struct of_device_id mtk_nfc_id_table[] = { diff --git a/target/linux/mediatek/patches-4.14/0167-mtd-nand-mtk-Support-MT7622-NAND-flash-controller.patch b/target/linux/mediatek/patches-4.14/0167-mtd-nand-mtk-Support-MT7622-NAND-flash-controller.patch new file mode 100644 index 000000000..7763e0644 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0167-mtd-nand-mtk-Support-MT7622-NAND-flash-controller.patch @@ -0,0 +1,109 @@ +From f395a149fbbc190afbadbdcf9ce95f85f78da22f Mon Sep 17 00:00:00 2001 +From: RogerCC Lin +Date: Thu, 30 Nov 2017 22:10:45 +0800 +Subject: [PATCH 167/224] mtd: nand: mtk: Support MT7622 NAND flash controller. + +Add tables to support MT7622 NAND flash controller. + +Signed-off-by: RogerCC Lin +Signed-off-by: Boris Brezillon +--- + drivers/mtd/nand/mtk_ecc.c | 26 ++++++++++++++++++++++++++ + drivers/mtd/nand/mtk_nand.c | 16 ++++++++++++++++ + 2 files changed, 42 insertions(+) + +--- a/drivers/mtd/nand/mtk_ecc.c ++++ b/drivers/mtd/nand/mtk_ecc.c +@@ -83,6 +83,10 @@ static const u8 ecc_strength_mt2712[] = + 40, 44, 48, 52, 56, 60, 68, 72, 80 + }; + ++static const u8 ecc_strength_mt7622[] = { ++ 4, 6, 8, 10, 12, 14, 16 ++}; ++ + enum mtk_ecc_regs { + ECC_ENCPAR00, + ECC_ENCIRQ_EN, +@@ -110,6 +114,15 @@ static int mt2712_ecc_regs[] = { + [ECC_DECIRQ_STA] = 0x204, + }; + ++static int mt7622_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x30, ++ [ECC_ENCIRQ_STA] = 0x34, ++ [ECC_DECDONE] = 0x11c, ++ [ECC_DECIRQ_EN] = 0x140, ++ [ECC_DECIRQ_STA] = 0x144, ++}; ++ + static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, + enum mtk_ecc_operation op) + { +@@ -458,6 +471,16 @@ static const struct mtk_ecc_caps mtk_ecc + .pg_irq_sel = 1, + }; + ++static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { ++ .err_mask = 0x3f, ++ .ecc_strength = ecc_strength_mt7622, ++ .ecc_regs = mt7622_ecc_regs, ++ .num_ecc_strength = 7, ++ .ecc_mode_shift = 4, ++ .parity_bits = 13, ++ .pg_irq_sel = 0, ++}; ++ + static const struct of_device_id mtk_ecc_dt_match[] = { + { + .compatible = "mediatek,mt2701-ecc", +@@ -465,6 +488,9 @@ static const struct of_device_id mtk_ecc + }, { + .compatible = "mediatek,mt2712-ecc", + .data = &mtk_ecc_caps_mt2712, ++ }, { ++ .compatible = "mediatek,mt7622-ecc", ++ .data = &mtk_ecc_caps_mt7622, + }, + {}, + }; +--- a/drivers/mtd/nand/mtk_nand.c ++++ b/drivers/mtd/nand/mtk_nand.c +@@ -174,6 +174,10 @@ static const u8 spare_size_mt2712[] = { + 74 + }; + ++static const u8 spare_size_mt7622[] = { ++ 16, 26, 27, 28 ++}; ++ + static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) + { + return container_of(nand, struct mtk_nfc_nand_chip, nand); +@@ -1409,6 +1413,15 @@ static const struct mtk_nfc_caps mtk_nfc + .max_sector_size = 1024, + }; + ++static const struct mtk_nfc_caps mtk_nfc_caps_mt7622 = { ++ .spare_size = spare_size_mt7622, ++ .num_spare_size = 4, ++ .pageformat_spare_shift = 4, ++ .nfi_clk_div = 1, ++ .max_sector = 8, ++ .max_sector_size = 512, ++}; ++ + static const struct of_device_id mtk_nfc_id_table[] = { + { + .compatible = "mediatek,mt2701-nfc", +@@ -1416,6 +1429,9 @@ static const struct of_device_id mtk_nfc + }, { + .compatible = "mediatek,mt2712-nfc", + .data = &mtk_nfc_caps_mt2712, ++ }, { ++ .compatible = "mediatek,mt7622-nfc", ++ .data = &mtk_nfc_caps_mt7622, + }, + {} + }; diff --git a/target/linux/mediatek/patches-4.14/0168-mmc-dt-bindings-add-mmc-support-to-MT7623-SoC.patch b/target/linux/mediatek/patches-4.14/0168-mmc-dt-bindings-add-mmc-support-to-MT7623-SoC.patch new file mode 100644 index 000000000..d16728124 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0168-mmc-dt-bindings-add-mmc-support-to-MT7623-SoC.patch @@ -0,0 +1,26 @@ +From bb37b1aa5d1aadfcecd9189a653856099fbed507 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 7 Dec 2017 14:43:22 +0800 +Subject: [PATCH 168/224] mmc: dt-bindings: add mmc support to MT7623 SoC + +Add the devicetree binding for MT7623 SoC using MT2701 as the fallback. + +Cc: devicetree@vger.kernel.org +Signed-off-by: Sean Wang +Acked-by: Rob Herring +Signed-off-by: Ulf Hansson +--- + Documentation/devicetree/bindings/mmc/mtk-sd.txt | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt ++++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt +@@ -12,6 +12,8 @@ Required properties: + "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 + "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 + "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 ++ "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC ++ + - reg: physical base address of the controller and length + - interrupts: Should contain MSDC interrupt number + - clocks: Should contain phandle for the clock feeding the MMC controller diff --git a/target/linux/mediatek/patches-4.14/0169-dt-bindings-pinctrl-add-bindings-for-MediaTek-MT7622.patch b/target/linux/mediatek/patches-4.14/0169-dt-bindings-pinctrl-add-bindings-for-MediaTek-MT7622.patch new file mode 100644 index 000000000..769de29bc --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0169-dt-bindings-pinctrl-add-bindings-for-MediaTek-MT7622.patch @@ -0,0 +1,371 @@ +From 4e4c2d695a5daf6dc55b8713af720ef15b52c0e7 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Tue, 12 Dec 2017 14:24:18 +0800 +Subject: [PATCH 169/224] dt-bindings: pinctrl: add bindings for MediaTek + MT7622 SoC + +Add devicetree bindings for MediaTek MT7622 pinctrl driver. + +Signed-off-by: Sean Wang +Reviewed-by: Biao Huang +Acked-by: Rob Herring +Signed-off-by: Linus Walleij +--- + .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 351 +++++++++++++++++++++ + 1 file changed, 351 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt +@@ -0,0 +1,351 @@ ++== MediaTek MT7622 pinctrl controller == ++ ++Required properties for the root node: ++ - compatible: Should be one of the following ++ "mediatek,mt7622-pinctrl" for MT7622 SoC ++ - reg: offset and length of the pinctrl space ++ ++ - gpio-controller: Marks the device node as a GPIO controller. ++ - #gpio-cells: Should be two. The first cell is the pin number and the ++ second is the GPIO flags. ++ ++Please refer to pinctrl-bindings.txt in this directory for details of the ++common pinctrl bindings used by client devices, including the meaning of the ++phrase "pin configuration node". ++ ++MT7622 pin configuration nodes act as a container for an arbitrary number of ++subnodes. Each of these subnodes represents some desired configuration for a ++pin, a group, or a list of pins or groups. This configuration can include the ++mux function to select on those pin(s)/group(s), and various pin configuration ++parameters, such as pull-up, slew rate, etc. ++ ++We support 2 types of configuration nodes. Those nodes can be either pinmux ++nodes or pinconf nodes. Each configuration node can consist of multiple nodes ++describing the pinmux and pinconf options. ++ ++The name of each subnode doesn't matter as long as it is unique; all subnodes ++should be enumerated and processed purely based on their content. ++ ++== pinmux nodes content == ++ ++The following generic properties as defined in pinctrl-bindings.txt are valid ++to specify in a pinmux subnode: ++ ++Required properties are: ++ - groups: An array of strings. Each string contains the name of a group. ++ Valid values for these names are listed below. ++ - function: A string containing the name of the function to mux to the ++ group. Valid values for function names are listed below. ++ ++== pinconf nodes content == ++ ++The following generic properties as defined in pinctrl-bindings.txt are valid ++to specify in a pinconf subnode: ++ ++Required properties are: ++ - pins: An array of strings. Each string contains the name of a pin. ++ Valid values for these names are listed below. ++ - groups: An array of strings. Each string contains the name of a group. ++ Valid values for these names are listed below. ++ ++Optional properies are: ++ bias-disable, bias-pull, bias-pull-down, input-enable, ++ input-schmitt-enable, input-schmitt-disable, output-enable ++ output-low, output-high, drive-strength, slew-rate ++ ++ Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for ++ slower slew rate respectively. ++ Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA. ++ ++The following specific properties as defined are valid to specify in a pinconf ++subnode: ++ ++Optional properties are: ++ - mediatek,tdsel: An integer describing the steps for output level shifter duty ++ cycle when asserted (high pulse width adjustment). Valid arguments are from 0 ++ to 15. ++ - mediatek,rdsel: An integer describing the steps for input level shifter duty ++ cycle when asserted (high pulse width adjustment). Valid arguments are from 0 ++ to 63. ++ ++== Valid values for pins, function and groups on MT7622 == ++ ++Valid values for pins are: ++pins can be referenced via the pin names as the below table shown and the ++related physical number is also put ahead of those names which helps cross ++references to pins between groups to know whether pins assignment conflict ++happens among devices try to acquire those available pins. ++ ++ Pin #: Valid values for pins ++ ----------------------------- ++ PIN 0: "GPIO_A" ++ PIN 1: "I2S1_IN" ++ PIN 2: "I2S1_OUT" ++ PIN 3: "I2S_BCLK" ++ PIN 4: "I2S_WS" ++ PIN 5: "I2S_MCLK" ++ PIN 6: "TXD0" ++ PIN 7: "RXD0" ++ PIN 8: "SPI_WP" ++ PIN 9: "SPI_HOLD" ++ PIN 10: "SPI_CLK" ++ PIN 11: "SPI_MOSI" ++ PIN 12: "SPI_MISO" ++ PIN 13: "SPI_CS" ++ PIN 14: "I2C_SDA" ++ PIN 15: "I2C_SCL" ++ PIN 16: "I2S2_IN" ++ PIN 17: "I2S3_IN" ++ PIN 18: "I2S4_IN" ++ PIN 19: "I2S2_OUT" ++ PIN 20: "I2S3_OUT" ++ PIN 21: "I2S4_OUT" ++ PIN 22: "GPIO_B" ++ PIN 23: "MDC" ++ PIN 24: "MDIO" ++ PIN 25: "G2_TXD0" ++ PIN 26: "G2_TXD1" ++ PIN 27: "G2_TXD2" ++ PIN 28: "G2_TXD3" ++ PIN 29: "G2_TXEN" ++ PIN 30: "G2_TXC" ++ PIN 31: "G2_RXD0" ++ PIN 32: "G2_RXD1" ++ PIN 33: "G2_RXD2" ++ PIN 34: "G2_RXD3" ++ PIN 35: "G2_RXDV" ++ PIN 36: "G2_RXC" ++ PIN 37: "NCEB" ++ PIN 38: "NWEB" ++ PIN 39: "NREB" ++ PIN 40: "NDL4" ++ PIN 41: "NDL5" ++ PIN 42: "NDL6" ++ PIN 43: "NDL7" ++ PIN 44: "NRB" ++ PIN 45: "NCLE" ++ PIN 46: "NALE" ++ PIN 47: "NDL0" ++ PIN 48: "NDL1" ++ PIN 49: "NDL2" ++ PIN 50: "NDL3" ++ PIN 51: "MDI_TP_P0" ++ PIN 52: "MDI_TN_P0" ++ PIN 53: "MDI_RP_P0" ++ PIN 54: "MDI_RN_P0" ++ PIN 55: "MDI_TP_P1" ++ PIN 56: "MDI_TN_P1" ++ PIN 57: "MDI_RP_P1" ++ PIN 58: "MDI_RN_P1" ++ PIN 59: "MDI_RP_P2" ++ PIN 60: "MDI_RN_P2" ++ PIN 61: "MDI_TP_P2" ++ PIN 62: "MDI_TN_P2" ++ PIN 63: "MDI_TP_P3" ++ PIN 64: "MDI_TN_P3" ++ PIN 65: "MDI_RP_P3" ++ PIN 66: "MDI_RN_P3" ++ PIN 67: "MDI_RP_P4" ++ PIN 68: "MDI_RN_P4" ++ PIN 69: "MDI_TP_P4" ++ PIN 70: "MDI_TN_P4" ++ PIN 71: "PMIC_SCL" ++ PIN 72: "PMIC_SDA" ++ PIN 73: "SPIC1_CLK" ++ PIN 74: "SPIC1_MOSI" ++ PIN 75: "SPIC1_MISO" ++ PIN 76: "SPIC1_CS" ++ PIN 77: "GPIO_D" ++ PIN 78: "WATCHDOG" ++ PIN 79: "RTS3_N" ++ PIN 80: "CTS3_N" ++ PIN 81: "TXD3" ++ PIN 82: "RXD3" ++ PIN 83: "PERST0_N" ++ PIN 84: "PERST1_N" ++ PIN 85: "WLED_N" ++ PIN 86: "EPHY_LED0_N" ++ PIN 87: "AUXIN0" ++ PIN 88: "AUXIN1" ++ PIN 89: "AUXIN2" ++ PIN 90: "AUXIN3" ++ PIN 91: "TXD4" ++ PIN 92: "RXD4" ++ PIN 93: "RTS4_N" ++ PIN 94: "CST4_N" ++ PIN 95: "PWM1" ++ PIN 96: "PWM2" ++ PIN 97: "PWM3" ++ PIN 98: "PWM4" ++ PIN 99: "PWM5" ++ PIN 100: "PWM6" ++ PIN 101: "PWM7" ++ PIN 102: "GPIO_E" ++ ++Valid values for function are: ++ "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie", ++ "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog" ++ ++Valid values for groups are: ++additional data is put followingly with valid value allowing us to know which ++applicable function and which relevant pins (in pin#) are able applied for that ++group. ++ ++ Valid value function pins (in pin#) ++ ------------------------------------------------------------------------- ++ "emmc" "emmc" 40, 41, 42, 43, 44, 45, ++ 47, 48, 49, 50 ++ "emmc_rst" "emmc" 37 ++ "esw" "eth" 51, 52, 53, 54, 55, 56, ++ 57, 58, 59, 60, 61, 62, ++ 63, 64, 65, 66, 67, 68, ++ 69, 70 ++ "esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56, ++ 57, 58 ++ "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64, ++ 65, 66, 67, 68, 69, 70 ++ "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64, ++ 65, 66, 67, 68, 69, 70 ++ "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64, ++ 65, 66, 67, 68, 69, 70 ++ "rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30, ++ 31, 32, 33, 34, 35, 36 ++ "mdc_mdio" "eth" 23, 24 ++ "i2c0" "i2c" 14, 15 ++ "i2c1_0" "i2c" 55, 56 ++ "i2c1_1" "i2c" 73, 74 ++ "i2c1_2" "i2c" 87, 88 ++ "i2c2_0" "i2c" 57, 58 ++ "i2c2_1" "i2c" 75, 76 ++ "i2c2_2" "i2c" 89, 90 ++ "i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5 ++ "i2s1_in_data" "i2s" 1 ++ "i2s2_in_data" "i2s" 16 ++ "i2s3_in_data" "i2s" 17 ++ "i2s4_in_data" "i2s" 18 ++ "i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5 ++ "i2s1_out_data" "i2s" 2 ++ "i2s2_out_data" "i2s" 19 ++ "i2s3_out_data" "i2s" 20 ++ "i2s4_out_data" "i2s" 21 ++ "ir_0_tx" "ir" 16 ++ "ir_1_tx" "ir" 59 ++ "ir_2_tx" "ir" 99 ++ "ir_0_rx" "ir" 17 ++ "ir_1_rx" "ir" 60 ++ "ir_2_rx" "ir" 100 ++ "ephy_leds" "led" 86, 91, 92, 93, 94 ++ "ephy0_led" "led" 86 ++ "ephy1_led" "led" 91 ++ "ephy2_led" "led" 92 ++ "ephy3_led" "led" 93 ++ "ephy4_led" "led" 94 ++ "wled" "led" 85 ++ "par_nand" "flash" 37, 38, 39, 40, 41, 42, ++ 43, 44, 45, 46, 47, 48, ++ 49, 50 ++ "snfi" "flash" 8, 9, 10, 11, 12, 13 ++ "spi_nor" "flash" 8, 9, 10, 11, 12, 13 ++ "pcie0_0_waken" "pcie" 14 ++ "pcie0_1_waken" "pcie" 79 ++ "pcie1_0_waken" "pcie" 14 ++ "pcie0_0_clkreq" "pcie" 15 ++ "pcie0_1_clkreq" "pcie" 80 ++ "pcie1_0_clkreq" "pcie" 15 ++ "pcie0_pad_perst" "pcie" 83 ++ "pcie1_pad_perst" "pcie" 84 ++ "pmic_bus" "pmic" 71, 72 ++ "pwm_ch1_0" "pwm" 51 ++ "pwm_ch1_1" "pwm" 73 ++ "pwm_ch1_2" "pwm" 95 ++ "pwm_ch2_0" "pwm" 52 ++ "pwm_ch2_1" "pwm" 74 ++ "pwm_ch2_2" "pwm" 96 ++ "pwm_ch3_0" "pwm" 53 ++ "pwm_ch3_1" "pwm" 75 ++ "pwm_ch3_2" "pwm" 97 ++ "pwm_ch4_0" "pwm" 54 ++ "pwm_ch4_1" "pwm" 67 ++ "pwm_ch4_2" "pwm" 76 ++ "pwm_ch4_3" "pwm" 98 ++ "pwm_ch5_0" "pwm" 68 ++ "pwm_ch5_1" "pwm" 77 ++ "pwm_ch5_2" "pwm" 99 ++ "pwm_ch6_0" "pwm" 69 ++ "pwm_ch6_1" "pwm" 78 ++ "pwm_ch6_2" "pwm" 81 ++ "pwm_ch6_3" "pwm" 100 ++ "pwm_ch7_0" "pwm" 70 ++ "pwm_ch7_1" "pwm" 82 ++ "pwm_ch7_2" "pwm" 101 ++ "sd_0" "sd" 16, 17, 18, 19, 20, 21 ++ "sd_1" "sd" 25, 26, 27, 28, 29, 30 ++ "spic0_0" "spi" 63, 64, 65, 66 ++ "spic0_1" "spi" 79, 80, 81, 82 ++ "spic1_0" "spi" 67, 68, 69, 70 ++ "spic1_1" "spi" 73, 74, 75, 76 ++ "spic2_0_wp_hold" "spi" 8, 9 ++ "spic2_0" "spi" 10, 11, 12, 13 ++ "tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10 ++ "tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13 ++ "tdm_0_out_data" "tdm" 20 ++ "tdm_0_in_data" "tdm" 21 ++ "tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59 ++ "tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62 ++ "tdm_1_out_data" "tdm" 55 ++ "tdm_1_in_data" "tdm" 56 ++ "uart0_0_tx_rx" "uart" 6, 7 ++ "uart1_0_tx_rx" "uart" 55, 56 ++ "uart1_0_rts_cts" "uart" 57, 58 ++ "uart1_1_tx_rx" "uart" 73, 74 ++ "uart1_1_rts_cts" "uart" 75, 76 ++ "uart2_0_tx_rx" "uart" 3, 4 ++ "uart2_0_rts_cts" "uart" 1, 2 ++ "uart2_1_tx_rx" "uart" 51, 52 ++ "uart2_1_rts_cts" "uart" 53, 54 ++ "uart2_2_tx_rx" "uart" 59, 60 ++ "uart2_2_rts_cts" "uart" 61, 62 ++ "uart2_3_tx_rx" "uart" 95, 96 ++ "uart3_0_tx_rx" "uart" 57, 58 ++ "uart3_1_tx_rx" "uart" 81, 82 ++ "uart3_1_rts_cts" "uart" 79, 80 ++ "uart4_0_tx_rx" "uart" 61, 62 ++ "uart4_1_tx_rx" "uart" 91, 92 ++ "uart4_1_rts_cts" "uart" 93, 94 ++ "uart4_2_tx_rx" "uart" 97, 98 ++ "uart4_2_rts_cts" "uart" 95, 96 ++ "watchdog" "watchdog" 78 ++ ++Example: ++ ++ pio: pinctrl@10211000 { ++ compatible = "mediatek,mt7622-pinctrl"; ++ reg = <0 0x10211000 0 0x1000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ pinctrl_eth_default: eth-default { ++ mux-mdio { ++ groups = "mdc_mdio"; ++ function = "eth"; ++ drive-strength = <12>; ++ }; ++ ++ mux-gmac2 { ++ groups = "gmac2"; ++ function = "eth"; ++ drive-strength = <12>; ++ }; ++ ++ mux-esw { ++ groups = "esw"; ++ function = "eth"; ++ drive-strength = <8>; ++ }; ++ ++ conf-mdio { ++ pins = "MDC"; ++ bias-pull-up; ++ }; ++ }; ++ }; diff --git a/target/linux/mediatek/patches-4.14/0170-pinctrl-mediatek-cleanup-for-placing-all-drivers-und.patch b/target/linux/mediatek/patches-4.14/0170-pinctrl-mediatek-cleanup-for-placing-all-drivers-und.patch new file mode 100644 index 000000000..780cc1086 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0170-pinctrl-mediatek-cleanup-for-placing-all-drivers-und.patch @@ -0,0 +1,32 @@ +From 547700768b2e7a105ed27a3b955fd9b7142987d7 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Tue, 12 Dec 2017 14:24:19 +0800 +Subject: [PATCH 170/224] pinctrl: mediatek: cleanup for placing all drivers + under the menu + +Since lots of MediaTek drivers had been added, it seems slightly better +for that adding cleanup for placing MediaTek pinctrl drivers under the +independent menu as other kinds of drivers usually was done. + +Signed-off-by: Sean Wang +Reviewed-by: Biao Huang +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/Kconfig | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -1,4 +1,5 @@ +-if ARCH_MEDIATEK || COMPILE_TEST ++menu "MediaTek pinctrl drivers" ++ depends on ARCH_MEDIATEK || COMPILE_TEST + + config PINCTRL_MTK + bool +@@ -46,4 +47,4 @@ config PINCTRL_MT6397 + default MFD_MT6397 + select PINCTRL_MTK + +-endif ++endmenu diff --git a/target/linux/mediatek/patches-4.14/0171-pinctrl-mediatek-add-pinctrl-driver-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0171-pinctrl-mediatek-add-pinctrl-driver-for-MT7622-SoC.patch new file mode 100644 index 000000000..c3a09f272 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0171-pinctrl-mediatek-add-pinctrl-driver-for-MT7622-SoC.patch @@ -0,0 +1,1675 @@ +From 4318e143fe3ac617de20cf72aa32fd9d3ad92ee6 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Tue, 12 Dec 2017 14:24:20 +0800 +Subject: [PATCH 171/224] pinctrl: mediatek: add pinctrl driver for MT7622 SoC + +Add support for pinctrl on MT7622 SoC. The IO core found on the SoC has +the registers for pinctrl, pinconf and gpio mixed up in the same register +range. However, the IO core for the MT7622 SoC is completely distinct from +anyone of previous MediaTek SoCs which already had support, such as +the hardware internal, register address map and register detailed +definition for each pin. + +Therefore, instead, the driver is being newly implemented by reusing +generic methods provided from the core layer with GENERIC_PINCONF, +GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code +simplicity and rid of superfluous code. Where the function of pins +determined by groups is utilized in this driver which can help developers +less confused with what combinations of pins effective on the SoC and even +reducing the mistakes during the integration of those relevant boards. + +As the gpio_chip handling is also only a few lines, the driver also +implements the gpio functionality directly through GPIOLIB. + +Signed-off-by: Sean Wang +Reviewed-by: Biao Huang +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/Makefile | 2 +- + drivers/pinctrl/mediatek/Kconfig | 10 + + drivers/pinctrl/mediatek/Makefile | 3 +- + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1595 +++++++++++++++++++++++++++++ + 4 files changed, 1608 insertions(+), 2 deletions(-) + create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c + +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -64,5 +64,5 @@ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ + obj-y += ti/ + obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ + obj-$(CONFIG_ARCH_VT8500) += vt8500/ +-obj-$(CONFIG_PINCTRL_MTK) += mediatek/ ++obj-y += mediatek/ + obj-$(CONFIG_PINCTRL_ZX) += zte/ +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -32,6 +32,16 @@ config PINCTRL_MT8127 + select PINCTRL_MTK + + # For ARMv8 SoCs ++config PINCTRL_MT7622 ++ bool "MediaTek MT7622 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ select GENERIC_PINCONF ++ select GENERIC_PINCTRL_GROUPS ++ select GENERIC_PINMUX_FUNCTIONS ++ select GPIOLIB ++ select OF_GPIO ++ + config PINCTRL_MT8173 + bool "Mediatek MT8173 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -1,10 +1,11 @@ + # SPDX-License-Identifier: GPL-2.0 + # Core +-obj-y += pinctrl-mtk-common.o ++obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o + + # SoC Drivers + obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o + obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o + obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o ++obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +--- /dev/null ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +@@ -0,0 +1,1595 @@ ++/* ++ * MediaTek MT7622 Pinctrl Driver ++ * ++ * Copyright (C) 2017 Sean Wang ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../core.h" ++#include "../pinconf.h" ++#include "../pinmux.h" ++ ++#define PINCTRL_PINCTRL_DEV KBUILD_MODNAME ++#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), } ++#define PINCTRL_PIN_GROUP(name, id) \ ++ { \ ++ name, \ ++ id##_pins, \ ++ ARRAY_SIZE(id##_pins), \ ++ id##_funcs, \ ++ } ++ ++#define MTK_GPIO_MODE 1 ++#define MTK_INPUT 0 ++#define MTK_OUTPUT 1 ++#define MTK_DISABLE 0 ++#define MTK_ENABLE 1 ++ ++/* Custom pinconf parameters */ ++#define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1) ++#define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2) ++ ++/* List these attributes which could be modified for the pin */ ++enum { ++ PINCTRL_PIN_REG_MODE, ++ PINCTRL_PIN_REG_DIR, ++ PINCTRL_PIN_REG_DI, ++ PINCTRL_PIN_REG_DO, ++ PINCTRL_PIN_REG_SR, ++ PINCTRL_PIN_REG_SMT, ++ PINCTRL_PIN_REG_PD, ++ PINCTRL_PIN_REG_PU, ++ PINCTRL_PIN_REG_E4, ++ PINCTRL_PIN_REG_E8, ++ PINCTRL_PIN_REG_TDSEL, ++ PINCTRL_PIN_REG_RDSEL, ++ PINCTRL_PIN_REG_MAX, ++}; ++ ++/* struct mtk_pin_field - the structure that holds the information of the field ++ * used to describe the attribute for the pin ++ * @offset: the register offset relative to the base address ++ * @mask: the mask used to filter out the field from the register ++ * @bitpos: the start bit relative to the register ++ * @next: the indication that the field would be extended to the ++ next register ++ */ ++struct mtk_pin_field { ++ u32 offset; ++ u32 mask; ++ u8 bitpos; ++ u8 next; ++}; ++ ++/* struct mtk_pin_field_calc - the structure that holds the range providing ++ * the guide used to look up the relevant field ++ * @s_pin: the start pin within the range ++ * @e_pin: the end pin within the range ++ * @s_addr: the start address for the range ++ * @x_addrs: the address distance between two consecutive registers ++ * within the range ++ * @s_bit: the start bit for the first register within the range ++ * @x_bits: the bit distance between two consecutive pins within ++ * the range ++ */ ++struct mtk_pin_field_calc { ++ u16 s_pin; ++ u16 e_pin; ++ u32 s_addr; ++ u8 x_addrs; ++ u8 s_bit; ++ u8 x_bits; ++}; ++ ++/* struct mtk_pin_reg_calc - the structure that holds all ranges used to ++ * determine which register the pin would make use of ++ * for certain pin attribute. ++ * @range: the start address for the range ++ * @nranges: the number of items in the range ++ */ ++struct mtk_pin_reg_calc { ++ const struct mtk_pin_field_calc *range; ++ unsigned int nranges; ++}; ++ ++/* struct mtk_pin_soc - the structure that holds SoC-specific data */ ++struct mtk_pin_soc { ++ const struct mtk_pin_reg_calc *reg_cal; ++ const struct pinctrl_pin_desc *pins; ++ unsigned int npins; ++ const struct group_desc *grps; ++ unsigned int ngrps; ++ const struct function_desc *funcs; ++ unsigned int nfuncs; ++}; ++ ++struct mtk_pinctrl { ++ struct pinctrl_dev *pctrl; ++ void __iomem *base; ++ struct device *dev; ++ struct gpio_chip chip; ++ const struct mtk_pin_soc *soc; ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = { ++ {0, 0, 0x320, 0x10, 16, 4}, ++ {1, 4, 0x3a0, 0x10, 16, 4}, ++ {5, 5, 0x320, 0x10, 0, 4}, ++ {6, 6, 0x300, 0x10, 4, 4}, ++ {7, 7, 0x300, 0x10, 4, 4}, ++ {8, 9, 0x350, 0x10, 20, 4}, ++ {10, 10, 0x300, 0x10, 8, 4}, ++ {11, 11, 0x300, 0x10, 8, 4}, ++ {12, 12, 0x300, 0x10, 8, 4}, ++ {13, 13, 0x300, 0x10, 8, 4}, ++ {14, 15, 0x320, 0x10, 4, 4}, ++ {16, 17, 0x320, 0x10, 20, 4}, ++ {18, 21, 0x310, 0x10, 16, 4}, ++ {22, 22, 0x380, 0x10, 16, 4}, ++ {23, 23, 0x300, 0x10, 24, 4}, ++ {24, 24, 0x300, 0x10, 24, 4}, ++ {25, 25, 0x300, 0x10, 12, 4}, ++ {25, 25, 0x300, 0x10, 12, 4}, ++ {26, 26, 0x300, 0x10, 12, 4}, ++ {27, 27, 0x300, 0x10, 12, 4}, ++ {28, 28, 0x300, 0x10, 12, 4}, ++ {29, 29, 0x300, 0x10, 12, 4}, ++ {30, 30, 0x300, 0x10, 12, 4}, ++ {31, 31, 0x300, 0x10, 12, 4}, ++ {32, 32, 0x300, 0x10, 12, 4}, ++ {33, 33, 0x300, 0x10, 12, 4}, ++ {34, 34, 0x300, 0x10, 12, 4}, ++ {35, 35, 0x300, 0x10, 12, 4}, ++ {36, 36, 0x300, 0x10, 12, 4}, ++ {37, 37, 0x300, 0x10, 20, 4}, ++ {38, 38, 0x300, 0x10, 20, 4}, ++ {39, 39, 0x300, 0x10, 20, 4}, ++ {40, 40, 0x300, 0x10, 20, 4}, ++ {41, 41, 0x300, 0x10, 20, 4}, ++ {42, 42, 0x300, 0x10, 20, 4}, ++ {43, 43, 0x300, 0x10, 20, 4}, ++ {44, 44, 0x300, 0x10, 20, 4}, ++ {45, 46, 0x300, 0x10, 20, 4}, ++ {47, 47, 0x300, 0x10, 20, 4}, ++ {48, 48, 0x300, 0x10, 20, 4}, ++ {49, 49, 0x300, 0x10, 20, 4}, ++ {50, 50, 0x300, 0x10, 20, 4}, ++ {51, 70, 0x330, 0x10, 4, 4}, ++ {71, 71, 0x300, 0x10, 16, 4}, ++ {72, 72, 0x300, 0x10, 16, 4}, ++ {73, 76, 0x310, 0x10, 0, 4}, ++ {77, 77, 0x320, 0x10, 28, 4}, ++ {78, 78, 0x320, 0x10, 12, 4}, ++ {79, 82, 0x3a0, 0x10, 0, 4}, ++ {83, 83, 0x350, 0x10, 28, 4}, ++ {84, 84, 0x330, 0x10, 0, 4}, ++ {85, 90, 0x360, 0x10, 4, 4}, ++ {91, 94, 0x390, 0x10, 16, 4}, ++ {95, 97, 0x380, 0x10, 20, 4}, ++ {98, 101, 0x390, 0x10, 0, 4}, ++ {102, 102, 0x360, 0x10, 0, 4}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = { ++ {0, 102, 0x0, 0x10, 0, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_di_range[] = { ++ {0, 102, 0x200, 0x10, 0, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_do_range[] = { ++ {0, 102, 0x100, 0x10, 0, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = { ++ {0, 31, 0x910, 0x10, 0, 1}, ++ {32, 50, 0xa10, 0x10, 0, 1}, ++ {51, 70, 0x810, 0x10, 0, 1}, ++ {71, 72, 0xb10, 0x10, 0, 1}, ++ {73, 86, 0xb10, 0x10, 4, 1}, ++ {87, 90, 0xc10, 0x10, 0, 1}, ++ {91, 102, 0xb10, 0x10, 18, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = { ++ {0, 31, 0x920, 0x10, 0, 1}, ++ {32, 50, 0xa20, 0x10, 0, 1}, ++ {51, 70, 0x820, 0x10, 0, 1}, ++ {71, 72, 0xb20, 0x10, 0, 1}, ++ {73, 86, 0xb20, 0x10, 4, 1}, ++ {87, 90, 0xc20, 0x10, 0, 1}, ++ {91, 102, 0xb20, 0x10, 18, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = { ++ {0, 31, 0x930, 0x10, 0, 1}, ++ {32, 50, 0xa30, 0x10, 0, 1}, ++ {51, 70, 0x830, 0x10, 0, 1}, ++ {71, 72, 0xb30, 0x10, 0, 1}, ++ {73, 86, 0xb30, 0x10, 4, 1}, ++ {87, 90, 0xc30, 0x10, 0, 1}, ++ {91, 102, 0xb30, 0x10, 18, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = { ++ {0, 31, 0x940, 0x10, 0, 1}, ++ {32, 50, 0xa40, 0x10, 0, 1}, ++ {51, 70, 0x840, 0x10, 0, 1}, ++ {71, 72, 0xb40, 0x10, 0, 1}, ++ {73, 86, 0xb40, 0x10, 4, 1}, ++ {87, 90, 0xc40, 0x10, 0, 1}, ++ {91, 102, 0xb40, 0x10, 18, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = { ++ {0, 31, 0x960, 0x10, 0, 1}, ++ {32, 50, 0xa60, 0x10, 0, 1}, ++ {51, 70, 0x860, 0x10, 0, 1}, ++ {71, 72, 0xb60, 0x10, 0, 1}, ++ {73, 86, 0xb60, 0x10, 4, 1}, ++ {87, 90, 0xc60, 0x10, 0, 1}, ++ {91, 102, 0xb60, 0x10, 18, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = { ++ {0, 31, 0x970, 0x10, 0, 1}, ++ {32, 50, 0xa70, 0x10, 0, 1}, ++ {51, 70, 0x870, 0x10, 0, 1}, ++ {71, 72, 0xb70, 0x10, 0, 1}, ++ {73, 86, 0xb70, 0x10, 4, 1}, ++ {87, 90, 0xc70, 0x10, 0, 1}, ++ {91, 102, 0xb70, 0x10, 18, 1}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = { ++ {0, 31, 0x980, 0x4, 0, 4}, ++ {32, 50, 0xa80, 0x4, 0, 4}, ++ {51, 70, 0x880, 0x4, 0, 4}, ++ {71, 72, 0xb80, 0x4, 0, 4}, ++ {73, 86, 0xb80, 0x4, 16, 4}, ++ {87, 90, 0xc80, 0x4, 0, 4}, ++ {91, 102, 0xb88, 0x4, 8, 4}, ++}; ++ ++static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = { ++ {0, 31, 0x990, 0x4, 0, 6}, ++ {32, 50, 0xa90, 0x4, 0, 6}, ++ {51, 58, 0x890, 0x4, 0, 6}, ++ {59, 60, 0x894, 0x4, 28, 6}, ++ {61, 62, 0x894, 0x4, 16, 6}, ++ {63, 66, 0x898, 0x4, 8, 6}, ++ {67, 68, 0x89c, 0x4, 12, 6}, ++ {69, 70, 0x89c, 0x4, 0, 6}, ++ {71, 72, 0xb90, 0x4, 0, 6}, ++ {73, 86, 0xb90, 0x4, 24, 6}, ++ {87, 90, 0xc90, 0x4, 0, 6}, ++ {91, 102, 0xb9c, 0x4, 12, 6}, ++}; ++ ++static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = { ++ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range), ++ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range), ++ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range), ++ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range), ++ [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range), ++ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range), ++ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range), ++ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range), ++ [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range), ++ [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range), ++ [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range), ++ [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range), ++}; ++ ++static const struct pinctrl_pin_desc mt7622_pins[] = { ++ PINCTRL_PIN(0, "GPIO_A"), ++ PINCTRL_PIN(1, "I2S1_IN"), ++ PINCTRL_PIN(2, "I2S1_OUT"), ++ PINCTRL_PIN(3, "I2S_BCLK"), ++ PINCTRL_PIN(4, "I2S_WS"), ++ PINCTRL_PIN(5, "I2S_MCLK"), ++ PINCTRL_PIN(6, "TXD0"), ++ PINCTRL_PIN(7, "RXD0"), ++ PINCTRL_PIN(8, "SPI_WP"), ++ PINCTRL_PIN(9, "SPI_HOLD"), ++ PINCTRL_PIN(10, "SPI_CLK"), ++ PINCTRL_PIN(11, "SPI_MOSI"), ++ PINCTRL_PIN(12, "SPI_MISO"), ++ PINCTRL_PIN(13, "SPI_CS"), ++ PINCTRL_PIN(14, "I2C_SDA"), ++ PINCTRL_PIN(15, "I2C_SCL"), ++ PINCTRL_PIN(16, "I2S2_IN"), ++ PINCTRL_PIN(17, "I2S3_IN"), ++ PINCTRL_PIN(18, "I2S4_IN"), ++ PINCTRL_PIN(19, "I2S2_OUT"), ++ PINCTRL_PIN(20, "I2S3_OUT"), ++ PINCTRL_PIN(21, "I2S4_OUT"), ++ PINCTRL_PIN(22, "GPIO_B"), ++ PINCTRL_PIN(23, "MDC"), ++ PINCTRL_PIN(24, "MDIO"), ++ PINCTRL_PIN(25, "G2_TXD0"), ++ PINCTRL_PIN(26, "G2_TXD1"), ++ PINCTRL_PIN(27, "G2_TXD2"), ++ PINCTRL_PIN(28, "G2_TXD3"), ++ PINCTRL_PIN(29, "G2_TXEN"), ++ PINCTRL_PIN(30, "G2_TXC"), ++ PINCTRL_PIN(31, "G2_RXD0"), ++ PINCTRL_PIN(32, "G2_RXD1"), ++ PINCTRL_PIN(33, "G2_RXD2"), ++ PINCTRL_PIN(34, "G2_RXD3"), ++ PINCTRL_PIN(35, "G2_RXDV"), ++ PINCTRL_PIN(36, "G2_RXC"), ++ PINCTRL_PIN(37, "NCEB"), ++ PINCTRL_PIN(38, "NWEB"), ++ PINCTRL_PIN(39, "NREB"), ++ PINCTRL_PIN(40, "NDL4"), ++ PINCTRL_PIN(41, "NDL5"), ++ PINCTRL_PIN(42, "NDL6"), ++ PINCTRL_PIN(43, "NDL7"), ++ PINCTRL_PIN(44, "NRB"), ++ PINCTRL_PIN(45, "NCLE"), ++ PINCTRL_PIN(46, "NALE"), ++ PINCTRL_PIN(47, "NDL0"), ++ PINCTRL_PIN(48, "NDL1"), ++ PINCTRL_PIN(49, "NDL2"), ++ PINCTRL_PIN(50, "NDL3"), ++ PINCTRL_PIN(51, "MDI_TP_P0"), ++ PINCTRL_PIN(52, "MDI_TN_P0"), ++ PINCTRL_PIN(53, "MDI_RP_P0"), ++ PINCTRL_PIN(54, "MDI_RN_P0"), ++ PINCTRL_PIN(55, "MDI_TP_P1"), ++ PINCTRL_PIN(56, "MDI_TN_P1"), ++ PINCTRL_PIN(57, "MDI_RP_P1"), ++ PINCTRL_PIN(58, "MDI_RN_P1"), ++ PINCTRL_PIN(59, "MDI_RP_P2"), ++ PINCTRL_PIN(60, "MDI_RN_P2"), ++ PINCTRL_PIN(61, "MDI_TP_P2"), ++ PINCTRL_PIN(62, "MDI_TN_P2"), ++ PINCTRL_PIN(63, "MDI_TP_P3"), ++ PINCTRL_PIN(64, "MDI_TN_P3"), ++ PINCTRL_PIN(65, "MDI_RP_P3"), ++ PINCTRL_PIN(66, "MDI_RN_P3"), ++ PINCTRL_PIN(67, "MDI_RP_P4"), ++ PINCTRL_PIN(68, "MDI_RN_P4"), ++ PINCTRL_PIN(69, "MDI_TP_P4"), ++ PINCTRL_PIN(70, "MDI_TN_P4"), ++ PINCTRL_PIN(71, "PMIC_SCL"), ++ PINCTRL_PIN(72, "PMIC_SDA"), ++ PINCTRL_PIN(73, "SPIC1_CLK"), ++ PINCTRL_PIN(74, "SPIC1_MOSI"), ++ PINCTRL_PIN(75, "SPIC1_MISO"), ++ PINCTRL_PIN(76, "SPIC1_CS"), ++ PINCTRL_PIN(77, "GPIO_D"), ++ PINCTRL_PIN(78, "WATCHDOG"), ++ PINCTRL_PIN(79, "RTS3_N"), ++ PINCTRL_PIN(80, "CTS3_N"), ++ PINCTRL_PIN(81, "TXD3"), ++ PINCTRL_PIN(82, "RXD3"), ++ PINCTRL_PIN(83, "PERST0_N"), ++ PINCTRL_PIN(84, "PERST1_N"), ++ PINCTRL_PIN(85, "WLED_N"), ++ PINCTRL_PIN(86, "EPHY_LED0_N"), ++ PINCTRL_PIN(87, "AUXIN0"), ++ PINCTRL_PIN(88, "AUXIN1"), ++ PINCTRL_PIN(89, "AUXIN2"), ++ PINCTRL_PIN(90, "AUXIN3"), ++ PINCTRL_PIN(91, "TXD4"), ++ PINCTRL_PIN(92, "RXD4"), ++ PINCTRL_PIN(93, "RTS4_N"), ++ PINCTRL_PIN(94, "CTS4_N"), ++ PINCTRL_PIN(95, "PWM1"), ++ PINCTRL_PIN(96, "PWM2"), ++ PINCTRL_PIN(97, "PWM3"), ++ PINCTRL_PIN(98, "PWM4"), ++ PINCTRL_PIN(99, "PWM5"), ++ PINCTRL_PIN(100, "PWM6"), ++ PINCTRL_PIN(101, "PWM7"), ++ PINCTRL_PIN(102, "GPIO_E"), ++}; ++ ++/* List all groups consisting of these pins dedicated to the enablement of ++ * certain hardware block and the corresponding mode for all of the pins. The ++ * hardware probably has multiple combinations of these pinouts. ++ */ ++ ++/* EMMC */ ++static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; ++static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++ ++static int mt7622_emmc_rst_pins[] = { 37, }; ++static int mt7622_emmc_rst_funcs[] = { 1, }; ++ ++/* LED for EPHY */ ++static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, }; ++static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, }; ++static int mt7622_ephy0_led_pins[] = { 86, }; ++static int mt7622_ephy0_led_funcs[] = { 0, }; ++static int mt7622_ephy1_led_pins[] = { 91, }; ++static int mt7622_ephy1_led_funcs[] = { 2, }; ++static int mt7622_ephy2_led_pins[] = { 92, }; ++static int mt7622_ephy2_led_funcs[] = { 2, }; ++static int mt7622_ephy3_led_pins[] = { 93, }; ++static int mt7622_ephy3_led_funcs[] = { 2, }; ++static int mt7622_ephy4_led_pins[] = { 94, }; ++static int mt7622_ephy4_led_funcs[] = { 2, }; ++ ++/* Embedded Switch */ ++static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, ++ 62, 63, 64, 65, 66, 67, 68, 69, 70, }; ++static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, }; ++static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, }; ++static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; ++static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67, ++ 68, 69, 70, }; ++static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, }; ++/* RGMII via ESW */ ++static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, ++ 67, 68, 69, 70, }; ++static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, }; ++ ++/* RGMII via GMAC1 */ ++static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, ++ 67, 68, 69, 70, }; ++static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, ++ 2, }; ++ ++/* RGMII via GMAC2 */ ++static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, }; ++static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, }; ++ ++/* I2C */ ++static int mt7622_i2c0_pins[] = { 14, 15, }; ++static int mt7622_i2c0_funcs[] = { 0, 0, }; ++static int mt7622_i2c1_0_pins[] = { 55, 56, }; ++static int mt7622_i2c1_0_funcs[] = { 0, 0, }; ++static int mt7622_i2c1_1_pins[] = { 73, 74, }; ++static int mt7622_i2c1_1_funcs[] = { 3, 3, }; ++static int mt7622_i2c1_2_pins[] = { 87, 88, }; ++static int mt7622_i2c1_2_funcs[] = { 0, 0, }; ++static int mt7622_i2c2_0_pins[] = { 57, 58, }; ++static int mt7622_i2c2_0_funcs[] = { 0, 0, }; ++static int mt7622_i2c2_1_pins[] = { 75, 76, }; ++static int mt7622_i2c2_1_funcs[] = { 3, 3, }; ++static int mt7622_i2c2_2_pins[] = { 89, 90, }; ++static int mt7622_i2c2_2_funcs[] = { 0, 0, }; ++ ++/* I2S */ ++static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, }; ++static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, }; ++static int mt7622_i2s1_in_data_pins[] = { 1, }; ++static int mt7622_i2s1_in_data_funcs[] = { 0, }; ++static int mt7622_i2s2_in_data_pins[] = { 16, }; ++static int mt7622_i2s2_in_data_funcs[] = { 0, }; ++static int mt7622_i2s3_in_data_pins[] = { 17, }; ++static int mt7622_i2s3_in_data_funcs[] = { 0, }; ++static int mt7622_i2s4_in_data_pins[] = { 18, }; ++static int mt7622_i2s4_in_data_funcs[] = { 0, }; ++static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, }; ++static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, }; ++static int mt7622_i2s1_out_data_pins[] = { 2, }; ++static int mt7622_i2s1_out_data_funcs[] = { 0, }; ++static int mt7622_i2s2_out_data_pins[] = { 19, }; ++static int mt7622_i2s2_out_data_funcs[] = { 0, }; ++static int mt7622_i2s3_out_data_pins[] = { 20, }; ++static int mt7622_i2s3_out_data_funcs[] = { 0, }; ++static int mt7622_i2s4_out_data_pins[] = { 21, }; ++static int mt7622_i2s4_out_data_funcs[] = { 0, }; ++ ++/* IR */ ++static int mt7622_ir_0_tx_pins[] = { 16, }; ++static int mt7622_ir_0_tx_funcs[] = { 4, }; ++static int mt7622_ir_1_tx_pins[] = { 59, }; ++static int mt7622_ir_1_tx_funcs[] = { 5, }; ++static int mt7622_ir_2_tx_pins[] = { 99, }; ++static int mt7622_ir_2_tx_funcs[] = { 3, }; ++static int mt7622_ir_0_rx_pins[] = { 17, }; ++static int mt7622_ir_0_rx_funcs[] = { 4, }; ++static int mt7622_ir_1_rx_pins[] = { 60, }; ++static int mt7622_ir_1_rx_funcs[] = { 5, }; ++static int mt7622_ir_2_rx_pins[] = { 100, }; ++static int mt7622_ir_2_rx_funcs[] = { 3, }; ++ ++/* MDIO */ ++static int mt7622_mdc_mdio_pins[] = { 23, 24, }; ++static int mt7622_mdc_mdio_funcs[] = { 0, 0, }; ++ ++/* PCIE */ ++static int mt7622_pcie0_0_waken_pins[] = { 14, }; ++static int mt7622_pcie0_0_waken_funcs[] = { 2, }; ++static int mt7622_pcie0_0_clkreq_pins[] = { 15, }; ++static int mt7622_pcie0_0_clkreq_funcs[] = { 2, }; ++static int mt7622_pcie0_1_waken_pins[] = { 79, }; ++static int mt7622_pcie0_1_waken_funcs[] = { 4, }; ++static int mt7622_pcie0_1_clkreq_pins[] = { 80, }; ++static int mt7622_pcie0_1_clkreq_funcs[] = { 4, }; ++static int mt7622_pcie1_0_waken_pins[] = { 14, }; ++static int mt7622_pcie1_0_waken_funcs[] = { 3, }; ++static int mt7622_pcie1_0_clkreq_pins[] = { 15, }; ++static int mt7622_pcie1_0_clkreq_funcs[] = { 3, }; ++ ++static int mt7622_pcie0_pad_perst_pins[] = { 83, }; ++static int mt7622_pcie0_pad_perst_funcs[] = { 0, }; ++static int mt7622_pcie1_pad_perst_pins[] = { 84, }; ++static int mt7622_pcie1_pad_perst_funcs[] = { 0, }; ++ ++/* PMIC bus */ ++static int mt7622_pmic_bus_pins[] = { 71, 72, }; ++static int mt7622_pmic_bus_funcs[] = { 0, 0, }; ++ ++/* Parallel NAND */ ++static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, }; ++static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, }; ++ ++/* PWM */ ++static int mt7622_pwm_ch1_0_pins[] = { 51, }; ++static int mt7622_pwm_ch1_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch1_1_pins[] = { 73, }; ++static int mt7622_pwm_ch1_1_funcs[] = { 4, }; ++static int mt7622_pwm_ch1_2_pins[] = { 95, }; ++static int mt7622_pwm_ch1_2_funcs[] = { 0, }; ++static int mt7622_pwm_ch2_0_pins[] = { 52, }; ++static int mt7622_pwm_ch2_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch2_1_pins[] = { 74, }; ++static int mt7622_pwm_ch2_1_funcs[] = { 4, }; ++static int mt7622_pwm_ch2_2_pins[] = { 96, }; ++static int mt7622_pwm_ch2_2_funcs[] = { 0, }; ++static int mt7622_pwm_ch3_0_pins[] = { 53, }; ++static int mt7622_pwm_ch3_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch3_1_pins[] = { 75, }; ++static int mt7622_pwm_ch3_1_funcs[] = { 4, }; ++static int mt7622_pwm_ch3_2_pins[] = { 97, }; ++static int mt7622_pwm_ch3_2_funcs[] = { 0, }; ++static int mt7622_pwm_ch4_0_pins[] = { 54, }; ++static int mt7622_pwm_ch4_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch4_1_pins[] = { 67, }; ++static int mt7622_pwm_ch4_1_funcs[] = { 3, }; ++static int mt7622_pwm_ch4_2_pins[] = { 76, }; ++static int mt7622_pwm_ch4_2_funcs[] = { 4, }; ++static int mt7622_pwm_ch4_3_pins[] = { 98, }; ++static int mt7622_pwm_ch4_3_funcs[] = { 0, }; ++static int mt7622_pwm_ch5_0_pins[] = { 68, }; ++static int mt7622_pwm_ch5_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch5_1_pins[] = { 77, }; ++static int mt7622_pwm_ch5_1_funcs[] = { 4, }; ++static int mt7622_pwm_ch5_2_pins[] = { 99, }; ++static int mt7622_pwm_ch5_2_funcs[] = { 0, }; ++static int mt7622_pwm_ch6_0_pins[] = { 69, }; ++static int mt7622_pwm_ch6_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch6_1_pins[] = { 78, }; ++static int mt7622_pwm_ch6_1_funcs[] = { 4, }; ++static int mt7622_pwm_ch6_2_pins[] = { 81, }; ++static int mt7622_pwm_ch6_2_funcs[] = { 4, }; ++static int mt7622_pwm_ch6_3_pins[] = { 100, }; ++static int mt7622_pwm_ch6_3_funcs[] = { 0, }; ++static int mt7622_pwm_ch7_0_pins[] = { 70, }; ++static int mt7622_pwm_ch7_0_funcs[] = { 3, }; ++static int mt7622_pwm_ch7_1_pins[] = { 82, }; ++static int mt7622_pwm_ch7_1_funcs[] = { 4, }; ++static int mt7622_pwm_ch7_2_pins[] = { 101, }; ++static int mt7622_pwm_ch7_2_funcs[] = { 0, }; ++ ++/* SD */ ++static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, }; ++static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, }; ++static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++ ++/* Serial NAND */ ++static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, }; ++static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++ ++/* SPI NOR */ ++static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 }; ++static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, }; ++ ++/* SPIC */ ++static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, }; ++static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, }; ++static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, }; ++static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, }; ++static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, }; ++static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, }; ++static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, }; ++static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, }; ++static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, }; ++static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, }; ++static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, }; ++static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, }; ++ ++/* TDM */ ++static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, }; ++static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, }; ++static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static int mt7622_tdm_0_out_data_pins[] = { 20, }; ++static int mt7622_tdm_0_out_data_funcs[] = { 3, }; ++static int mt7622_tdm_0_in_data_pins[] = { 21, }; ++static int mt7622_tdm_0_in_data_funcs[] = { 3, }; ++static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, }; ++static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, }; ++static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, }; ++static int mt7622_tdm_1_out_data_pins[] = { 55, }; ++static int mt7622_tdm_1_out_data_funcs[] = { 3, }; ++static int mt7622_tdm_1_in_data_pins[] = { 56, }; ++static int mt7622_tdm_1_in_data_funcs[] = { 3, }; ++ ++/* UART */ ++static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, }; ++static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, }; ++static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, }; ++static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, }; ++static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, }; ++static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, }; ++static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, }; ++static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, }; ++static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, }; ++static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, }; ++static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, }; ++static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, }; ++static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, }; ++static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, }; ++static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, }; ++static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, }; ++static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, }; ++static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, }; ++static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, }; ++static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, }; ++static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, }; ++static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, }; ++static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, }; ++static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, }; ++static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, }; ++static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, }; ++static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, }; ++static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, }; ++static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, }; ++static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, }; ++static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, }; ++static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, }; ++static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, }; ++static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, }; ++static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 }; ++static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, }; ++static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, }; ++static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, }; ++static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 }; ++static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, }; ++ ++/* Watchdog */ ++static int mt7622_watchdog_pins[] = { 78, }; ++static int mt7622_watchdog_funcs[] = { 0, }; ++ ++/* WLAN LED */ ++static int mt7622_wled_pins[] = { 85, }; ++static int mt7622_wled_funcs[] = { 0, }; ++ ++static const struct group_desc mt7622_groups[] = { ++ PINCTRL_PIN_GROUP("emmc", mt7622_emmc), ++ PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst), ++ PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds), ++ PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led), ++ PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led), ++ PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led), ++ PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led), ++ PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led), ++ PINCTRL_PIN_GROUP("esw", mt7622_esw), ++ PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1), ++ PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4), ++ PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw), ++ PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1), ++ PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2), ++ PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0), ++ PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0), ++ PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1), ++ PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2), ++ PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0), ++ PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1), ++ PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2), ++ PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws), ++ PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws), ++ PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data), ++ PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data), ++ PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data), ++ PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data), ++ PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data), ++ PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data), ++ PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data), ++ PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data), ++ PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx), ++ PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx), ++ PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx), ++ PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx), ++ PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx), ++ PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx), ++ PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio), ++ PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken), ++ PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq), ++ PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken), ++ PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq), ++ PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken), ++ PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq), ++ PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst), ++ PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst), ++ PINCTRL_PIN_GROUP("par_nand", mt7622_pnand), ++ PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus), ++ PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0), ++ PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1), ++ PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2), ++ PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0), ++ PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1), ++ PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2), ++ PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0), ++ PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1), ++ PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2), ++ PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0), ++ PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1), ++ PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2), ++ PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3), ++ PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0), ++ PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1), ++ PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2), ++ PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0), ++ PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1), ++ PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2), ++ PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3), ++ PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0), ++ PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1), ++ PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2), ++ PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0), ++ PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1), ++ PINCTRL_PIN_GROUP("snfi", mt7622_snfi), ++ PINCTRL_PIN_GROUP("spi_nor", mt7622_spi), ++ PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0), ++ PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1), ++ PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0), ++ PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1), ++ PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0), ++ PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold), ++ PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws", ++ mt7622_tdm_0_out_mclk_bclk_ws), ++ PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws", ++ mt7622_tdm_0_in_mclk_bclk_ws), ++ PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data), ++ PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data), ++ PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws", ++ mt7622_tdm_1_out_mclk_bclk_ws), ++ PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws", ++ mt7622_tdm_1_in_mclk_bclk_ws), ++ PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data), ++ PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data), ++ PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx), ++ PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx), ++ PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts), ++ PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx), ++ PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts), ++ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx), ++ PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts), ++ PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx), ++ PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts), ++ PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx), ++ PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts), ++ PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx), ++ PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx), ++ PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx), ++ PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts), ++ PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx), ++ PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx), ++ PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts), ++ PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx), ++ PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts), ++ PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog), ++ PINCTRL_PIN_GROUP("wled", mt7622_wled), ++}; ++ ++/* Joint those groups owning the same capability in user point of view which ++ * allows that people tend to use through the device tree. ++ */ ++static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", }; ++static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1", ++ "esw_p2_p3_p4", "mdc_mdio", ++ "rgmii_via_gmac1", ++ "rgmii_via_gmac2", ++ "rgmii_via_esw", }; ++static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1", ++ "i2c1_2", "i2c2_0", "i2c2_1", ++ "i2c2_2", }; ++static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws", ++ "i2s_in_mclk_bclk_ws", ++ "i2s1_in_data", "i2s2_in_data", ++ "i2s3_in_data", "i2s4_in_data", ++ "i2s1_out_data", "i2s2_out_data", ++ "i2s3_out_data", "i2s4_out_data", }; ++static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx", ++ "ir_0_rx", "ir_1_rx", "ir_2_rx"}; ++static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led", ++ "ephy1_led", "ephy2_led", ++ "ephy3_led", "ephy4_led", ++ "wled", }; ++static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"}; ++static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq", ++ "pcie0_1_waken", "pcie0_1_clkreq", ++ "pcie1_0_waken", "pcie1_0_clkreq", ++ "pcie0_pad_perst", ++ "pcie1_pad_perst", }; ++static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", }; ++static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1", ++ "pwm_ch1_2", "pwm_ch2_0", ++ "pwm_ch2_1", "pwm_ch2_2", ++ "pwm_ch3_0", "pwm_ch3_1", ++ "pwm_ch3_2", "pwm_ch4_0", ++ "pwm_ch4_1", "pwm_ch4_2", ++ "pwm_ch4_3", "pwm_ch5_0", ++ "pwm_ch5_1", "pwm_ch5_2", ++ "pwm_ch6_0", "pwm_ch6_1", ++ "pwm_ch6_2", "pwm_ch6_3", ++ "pwm_ch7_0", "pwm_ch7_1", ++ "pwm_ch7_2", }; ++static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", }; ++static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0", ++ "spic1_1", "spic2_0", ++ "spic2_0_wp_hold", }; ++static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws", ++ "tdm_0_in_mclk_bclk_ws", ++ "tdm_0_out_data", ++ "tdm_0_in_data", ++ "tdm_1_out_mclk_bclk_ws", ++ "tdm_1_in_mclk_bclk_ws", ++ "tdm_1_out_data", ++ "tdm_1_in_data", }; ++ ++static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx", ++ "uart1_0_tx_rx", "uart1_0_rts_cts", ++ "uart1_1_tx_rx", "uart1_1_rts_cts", ++ "uart2_0_tx_rx", "uart2_0_rts_cts", ++ "uart2_1_tx_rx", "uart2_1_rts_cts", ++ "uart2_2_tx_rx", "uart2_2_rts_cts", ++ "uart2_3_tx_rx", ++ "uart3_0_tx_rx", ++ "uart3_1_tx_rx", "uart3_1_rts_cts", ++ "uart4_0_tx_rx", ++ "uart4_1_tx_rx", "uart4_1_rts_cts", ++ "uart4_2_tx_rx", ++ "uart4_2_rts_cts",}; ++static const char *mt7622_wdt_groups[] = { "watchdog", }; ++ ++static const struct function_desc mt7622_functions[] = { ++ {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)}, ++ {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)}, ++ {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)}, ++ {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)}, ++ {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)}, ++ {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)}, ++ {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)}, ++ {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)}, ++ {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)}, ++ {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)}, ++ {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)}, ++ {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)}, ++ {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)}, ++ {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)}, ++ {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)}, ++}; ++ ++static const struct pinconf_generic_params mtk_custom_bindings[] = { ++ {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0}, ++ {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0}, ++}; ++ ++#ifdef CONFIG_DEBUG_FS ++static const struct pin_config_item mtk_conf_items[] = { ++ PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true), ++ PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true), ++}; ++#endif ++ ++static const struct mtk_pin_soc mt7622_data = { ++ .reg_cal = mt7622_reg_cals, ++ .pins = mt7622_pins, ++ .npins = ARRAY_SIZE(mt7622_pins), ++ .grps = mt7622_groups, ++ .ngrps = ARRAY_SIZE(mt7622_groups), ++ .funcs = mt7622_functions, ++ .nfuncs = ARRAY_SIZE(mt7622_functions), ++}; ++ ++static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val) ++{ ++ writel_relaxed(val, pctl->base + reg); ++} ++ ++static u32 mtk_r32(struct mtk_pinctrl *pctl, u32 reg) ++{ ++ return readl_relaxed(pctl->base + reg); ++} ++ ++static void mtk_rmw(struct mtk_pinctrl *pctl, u32 reg, u32 mask, u32 set) ++{ ++ u32 val; ++ ++ val = mtk_r32(pctl, reg); ++ val &= ~mask; ++ val |= set; ++ mtk_w32(pctl, reg, val); ++} ++ ++static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, int pin, ++ const struct mtk_pin_reg_calc *rc, ++ struct mtk_pin_field *pfd) ++{ ++ const struct mtk_pin_field_calc *c, *e; ++ u32 bits; ++ ++ c = rc->range; ++ e = c + rc->nranges; ++ ++ while (c < e) { ++ if (pin >= c->s_pin && pin <= c->e_pin) ++ break; ++ c++; ++ } ++ ++ if (c >= e) { ++ dev_err(hw->dev, "Out of range for pin = %d\n", pin); ++ return -EINVAL; ++ } ++ ++ /* Caculated bits as the overall offset the pin is located at */ ++ bits = c->s_bit + (pin - c->s_pin) * (c->x_bits); ++ ++ /* Fill pfd from bits and 32-bit register applied is assumed */ ++ pfd->offset = c->s_addr + c->x_addrs * (bits / 32); ++ pfd->bitpos = bits % 32; ++ pfd->mask = (1 << c->x_bits) - 1; ++ ++ /* pfd->next is used for indicating that bit wrapping-around happens ++ * which requires the manipulation for bit 0 starting in the next ++ * register to form the complete field read/write. ++ */ ++ pfd->next = pfd->bitpos + c->x_bits - 1 > 31 ? c->x_addrs : 0; ++ ++ return 0; ++} ++ ++static int mtk_hw_pin_field_get(struct mtk_pinctrl *hw, int pin, ++ int field, struct mtk_pin_field *pfd) ++{ ++ const struct mtk_pin_reg_calc *rc; ++ ++ if (field < 0 || field >= PINCTRL_PIN_REG_MAX) { ++ dev_err(hw->dev, "Invalid Field %d\n", field); ++ return -EINVAL; ++ } ++ ++ if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { ++ rc = &hw->soc->reg_cal[field]; ++ } else { ++ dev_err(hw->dev, "Undefined range for field %d\n", field); ++ return -EINVAL; ++ } ++ ++ return mtk_hw_pin_field_lookup(hw, pin, rc, pfd); ++} ++ ++static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l) ++{ ++ *l = 32 - pf->bitpos; ++ *h = get_count_order(pf->mask) - *l; ++} ++ ++static void mtk_hw_write_cross_field(struct mtk_pinctrl *hw, ++ struct mtk_pin_field *pf, int value) ++{ ++ int nbits_l, nbits_h; ++ ++ mtk_hw_bits_part(pf, &nbits_h, &nbits_l); ++ ++ mtk_rmw(hw, pf->offset, pf->mask << pf->bitpos, ++ (value & pf->mask) << pf->bitpos); ++ ++ mtk_rmw(hw, pf->offset + pf->next, BIT(nbits_h) - 1, ++ (value & pf->mask) >> nbits_l); ++} ++ ++static void mtk_hw_read_cross_field(struct mtk_pinctrl *hw, ++ struct mtk_pin_field *pf, int *value) ++{ ++ int nbits_l, nbits_h, h, l; ++ ++ mtk_hw_bits_part(pf, &nbits_h, &nbits_l); ++ ++ l = (mtk_r32(hw, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1); ++ h = (mtk_r32(hw, pf->offset + pf->next)) & (BIT(nbits_h) - 1); ++ ++ *value = (h << nbits_l) | l; ++} ++ ++static int mtk_hw_set_value(struct mtk_pinctrl *hw, int pin, int field, ++ int value) ++{ ++ struct mtk_pin_field pf; ++ int err; ++ ++ err = mtk_hw_pin_field_get(hw, pin, field, &pf); ++ if (err) ++ return err; ++ ++ if (!pf.next) ++ mtk_rmw(hw, pf.offset, pf.mask << pf.bitpos, ++ (value & pf.mask) << pf.bitpos); ++ else ++ mtk_hw_write_cross_field(hw, &pf, value); ++ ++ return 0; ++} ++ ++static int mtk_hw_get_value(struct mtk_pinctrl *hw, int pin, int field, ++ int *value) ++{ ++ struct mtk_pin_field pf; ++ int err; ++ ++ err = mtk_hw_pin_field_get(hw, pin, field, &pf); ++ if (err) ++ return err; ++ ++ if (!pf.next) ++ *value = (mtk_r32(hw, pf.offset) >> pf.bitpos) & pf.mask; ++ else ++ mtk_hw_read_cross_field(hw, &pf, value); ++ ++ return 0; ++} ++ ++static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, ++ unsigned int selector, unsigned int group) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ struct function_desc *func; ++ struct group_desc *grp; ++ int i; ++ ++ func = pinmux_generic_get_function(pctldev, selector); ++ if (!func) ++ return -EINVAL; ++ ++ grp = pinctrl_generic_get_group(pctldev, group); ++ if (!grp) ++ return -EINVAL; ++ ++ dev_dbg(pctldev->dev, "enable function %s group %s\n", ++ func->name, grp->name); ++ ++ for (i = 0; i < grp->num_pins; i++) { ++ int *pin_modes = grp->data; ++ ++ mtk_hw_set_value(hw, grp->pins[i], PINCTRL_PIN_REG_MODE, ++ pin_modes[i]); ++ } ++ ++ return 0; ++} ++ ++static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int pin) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_MODE, MTK_GPIO_MODE); ++} ++ ++static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int pin, bool input) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ ++ /* hardware would take 0 as input direction */ ++ return mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, !input); ++} ++ ++static int mtk_pinconf_get(struct pinctrl_dev *pctldev, ++ unsigned int pin, unsigned long *config) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ u32 param = pinconf_to_config_param(*config); ++ int val, val2, err, reg, ret = 1; ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PU, &val); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_PD, &val2); ++ if (err) ++ return err; ++ ++ if (val || val2) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_BIAS_PULL_UP: ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ case PIN_CONFIG_SLEW_RATE: ++ reg = (param == PIN_CONFIG_BIAS_PULL_UP) ? ++ PINCTRL_PIN_REG_PU : ++ (param == PIN_CONFIG_BIAS_PULL_DOWN) ? ++ PINCTRL_PIN_REG_PD : PINCTRL_PIN_REG_SR; ++ ++ err = mtk_hw_get_value(hw, pin, reg, &val); ++ if (err) ++ return err; ++ ++ if (!val) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_INPUT_ENABLE: ++ case PIN_CONFIG_OUTPUT_ENABLE: ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); ++ if (err) ++ return -EINVAL; ++ ++ /* HW takes input mode as zero; output mode as non-zero */ ++ if ((val && param == PIN_CONFIG_INPUT_ENABLE) || ++ (!val && param == PIN_CONFIG_OUTPUT_ENABLE)) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE: ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); ++ if (err) ++ return err; ++ ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_SMT, &val2); ++ if (err) ++ return err; ++ ++ if (val || !val2) ++ return -EINVAL; ++ ++ break; ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val); ++ if (err) ++ return -EINVAL; ++ ++ err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2); ++ if (err) ++ return -EINVAL; ++ ++ /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) ++ * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) ++ */ ++ ret = ((val2 << 1) + val + 1) * 4; ++ ++ break; ++ case MTK_PIN_CONFIG_TDSEL: ++ case MTK_PIN_CONFIG_RDSEL: ++ reg = (param == MTK_PIN_CONFIG_TDSEL) ? ++ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; ++ ++ err = mtk_hw_get_value(hw, pin, reg, &val); ++ if (err) ++ return -EINVAL; ++ ++ ret = val; ++ ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ *config = pinconf_to_config_packed(param, ret); ++ ++ return 0; ++} ++ ++static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, ++ unsigned long *configs, unsigned int num_configs) ++{ ++ struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); ++ u32 reg, param, arg; ++ int cfg, err = 0; ++ ++ for (cfg = 0; cfg < num_configs; cfg++) { ++ param = pinconf_to_config_param(configs[cfg]); ++ arg = pinconf_to_config_argument(configs[cfg]); ++ ++ switch (param) { ++ case PIN_CONFIG_BIAS_DISABLE: ++ case PIN_CONFIG_BIAS_PULL_UP: ++ case PIN_CONFIG_BIAS_PULL_DOWN: ++ arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 : ++ (param == PIN_CONFIG_BIAS_PULL_UP) ? 1 : 2; ++ ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PU, ++ arg & 1); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_PD, ++ !!(arg & 2)); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_OUTPUT_ENABLE: ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT, ++ MTK_DISABLE); ++ if (err) ++ goto err; ++ case PIN_CONFIG_INPUT_ENABLE: ++ case PIN_CONFIG_SLEW_RATE: ++ reg = (param == PIN_CONFIG_SLEW_RATE) ? ++ PINCTRL_PIN_REG_SR : PINCTRL_PIN_REG_DIR; ++ ++ arg = (param == PIN_CONFIG_INPUT_ENABLE) ? 0 : ++ (param == PIN_CONFIG_OUTPUT_ENABLE) ? 1 : arg; ++ err = mtk_hw_set_value(hw, pin, reg, arg); ++ if (err) ++ goto err; ++ ++ break; ++ case PIN_CONFIG_OUTPUT: ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, ++ MTK_OUTPUT); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DO, ++ arg); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_INPUT_SCHMITT_ENABLE: ++ /* arg = 1: Input mode & SMT enable ; ++ * arg = 0: Output mode & SMT disable ++ */ ++ arg = arg ? 2 : 1; ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_DIR, ++ arg & 1); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, pin, PINCTRL_PIN_REG_SMT, ++ !!(arg & 2)); ++ if (err) ++ goto err; ++ break; ++ case PIN_CONFIG_DRIVE_STRENGTH: ++ /* 4mA when (e8, e4) = (0, 0); ++ * 8mA when (e8, e4) = (0, 1); ++ * 12mA when (e8, e4) = (1, 0); ++ * 16mA when (e8, e4) = (1, 1) ++ */ ++ if (!(arg % 4) && (arg >= 4 && arg <= 16)) { ++ arg = arg / 4 - 1; ++ err = mtk_hw_set_value(hw, pin, ++ PINCTRL_PIN_REG_E4, ++ arg & 0x1); ++ if (err) ++ goto err; ++ ++ err = mtk_hw_set_value(hw, pin, ++ PINCTRL_PIN_REG_E8, ++ (arg & 0x2) >> 1); ++ if (err) ++ goto err; ++ } else { ++ err = -ENOTSUPP; ++ } ++ break; ++ case MTK_PIN_CONFIG_TDSEL: ++ case MTK_PIN_CONFIG_RDSEL: ++ reg = (param == MTK_PIN_CONFIG_TDSEL) ? ++ PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL; ++ ++ err = mtk_hw_set_value(hw, pin, reg, arg); ++ if (err) ++ goto err; ++ break; ++ default: ++ err = -ENOTSUPP; ++ } ++ } ++err: ++ return err; ++} ++ ++static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev, ++ unsigned int group, unsigned long *config) ++{ ++ const unsigned int *pins; ++ unsigned int i, npins, old = 0; ++ int ret; ++ ++ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < npins; i++) { ++ if (mtk_pinconf_get(pctldev, pins[i], config)) ++ return -ENOTSUPP; ++ ++ /* configs do not match between two pins */ ++ if (i && old != *config) ++ return -ENOTSUPP; ++ ++ old = *config; ++ } ++ ++ return 0; ++} ++ ++static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev, ++ unsigned int group, unsigned long *configs, ++ unsigned int num_configs) ++{ ++ const unsigned int *pins; ++ unsigned int i, npins; ++ int ret; ++ ++ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < npins; i++) { ++ ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops mtk_pctlops = { ++ .get_groups_count = pinctrl_generic_get_group_count, ++ .get_group_name = pinctrl_generic_get_group_name, ++ .get_group_pins = pinctrl_generic_get_group_pins, ++ .dt_node_to_map = pinconf_generic_dt_node_to_map_all, ++ .dt_free_map = pinconf_generic_dt_free_map, ++}; ++ ++static const struct pinmux_ops mtk_pmxops = { ++ .get_functions_count = pinmux_generic_get_function_count, ++ .get_function_name = pinmux_generic_get_function_name, ++ .get_function_groups = pinmux_generic_get_function_groups, ++ .set_mux = mtk_pinmux_set_mux, ++ .gpio_request_enable = mtk_pinmux_gpio_request_enable, ++ .gpio_set_direction = mtk_pinmux_gpio_set_direction, ++ .strict = true, ++}; ++ ++static const struct pinconf_ops mtk_confops = { ++ .is_generic = true, ++ .pin_config_get = mtk_pinconf_get, ++ .pin_config_set = mtk_pinconf_set, ++ .pin_config_group_get = mtk_pinconf_group_get, ++ .pin_config_group_set = mtk_pinconf_group_set, ++ .pin_config_config_dbg_show = pinconf_generic_dump_config, ++}; ++ ++static struct pinctrl_desc mtk_desc = { ++ .name = PINCTRL_PINCTRL_DEV, ++ .pctlops = &mtk_pctlops, ++ .pmxops = &mtk_pmxops, ++ .confops = &mtk_confops, ++ .owner = THIS_MODULE, ++}; ++ ++static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) ++{ ++ struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); ++ int value; ++ ++ mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); ++ ++ return !!value; ++} ++ ++static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) ++{ ++ struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); ++ ++ mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value); ++} ++ ++static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) ++{ ++ return pinctrl_gpio_direction_input(chip->base + gpio); ++} ++ ++static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, ++ int value) ++{ ++ mtk_gpio_set(chip, gpio, value); ++ ++ return pinctrl_gpio_direction_output(chip->base + gpio); ++} ++ ++static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np) ++{ ++ struct gpio_chip *chip = &hw->chip; ++ int ret; ++ ++ chip->label = PINCTRL_PINCTRL_DEV; ++ chip->parent = hw->dev; ++ chip->request = gpiochip_generic_request; ++ chip->free = gpiochip_generic_free; ++ chip->direction_input = mtk_gpio_direction_input; ++ chip->direction_output = mtk_gpio_direction_output; ++ chip->get = mtk_gpio_get; ++ chip->set = mtk_gpio_set; ++ chip->base = -1; ++ chip->ngpio = hw->soc->npins; ++ chip->of_node = np; ++ chip->of_gpio_n_cells = 2; ++ ++ ret = gpiochip_add_data(chip, hw); ++ if (ret < 0) ++ return ret; ++ ++ ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0, ++ chip->ngpio); ++ if (ret < 0) { ++ gpiochip_remove(chip); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mtk_build_groups(struct mtk_pinctrl *hw) ++{ ++ int err, i; ++ ++ for (i = 0; i < hw->soc->ngrps; i++) { ++ const struct group_desc *group = hw->soc->grps + i; ++ ++ err = pinctrl_generic_add_group(hw->pctrl, group->name, ++ group->pins, group->num_pins, ++ group->data); ++ if (err) { ++ dev_err(hw->dev, "Failed to register group %s\n", ++ group->name); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++static int mtk_build_functions(struct mtk_pinctrl *hw) ++{ ++ int i, err; ++ ++ for (i = 0; i < hw->soc->nfuncs ; i++) { ++ const struct function_desc *func = hw->soc->funcs + i; ++ ++ err = pinmux_generic_add_function(hw->pctrl, func->name, ++ func->group_names, ++ func->num_group_names, ++ func->data); ++ if (err) { ++ dev_err(hw->dev, "Failed to register function %s\n", ++ func->name); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id mtk_pinctrl_of_match[] = { ++ { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data}, ++ { } ++}; ++ ++static int mtk_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct mtk_pinctrl *hw; ++ const struct of_device_id *of_id = ++ of_match_device(mtk_pinctrl_of_match, &pdev->dev); ++ int err; ++ ++ hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); ++ if (!hw) ++ return -ENOMEM; ++ ++ hw->soc = of_id->data; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "missing IO resource\n"); ++ return -ENXIO; ++ } ++ ++ hw->dev = &pdev->dev; ++ hw->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hw->base)) ++ return PTR_ERR(hw->base); ++ ++ /* Setup pins descriptions per SoC types */ ++ mtk_desc.pins = hw->soc->pins; ++ mtk_desc.npins = hw->soc->npins; ++ mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings); ++ mtk_desc.custom_params = mtk_custom_bindings; ++#ifdef CONFIG_DEBUG_FS ++ mtk_desc.custom_conf_items = mtk_conf_items; ++#endif ++ ++ hw->pctrl = devm_pinctrl_register(&pdev->dev, &mtk_desc, hw); ++ if (IS_ERR(hw->pctrl)) ++ return PTR_ERR(hw->pctrl); ++ ++ /* Setup groups descriptions per SoC types */ ++ err = mtk_build_groups(hw); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to build groups\n"); ++ return 0; ++ } ++ ++ /* Setup functions descriptions per SoC types */ ++ err = mtk_build_functions(hw); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to build functions\n"); ++ return err; ++ } ++ ++ err = mtk_build_gpiochip(hw, pdev->dev.of_node); ++ if (err) { ++ dev_err(&pdev->dev, "Failed to add gpio_chip\n"); ++ return err; ++ } ++ ++ platform_set_drvdata(pdev, hw); ++ ++ return 0; ++} ++ ++static struct platform_driver mtk_pinctrl_driver = { ++ .driver = { ++ .name = "mtk-pinctrl", ++ .of_match_table = mtk_pinctrl_of_match, ++ }, ++ .probe = mtk_pinctrl_probe, ++}; ++ ++static int __init mtk_pinctrl_init(void) ++{ ++ return platform_driver_register(&mtk_pinctrl_driver); ++} ++arch_initcall(mtk_pinctrl_init); diff --git a/target/linux/mediatek/patches-4.14/0172-clk-mediatek-group-drivers-under-indpendent-menu.patch b/target/linux/mediatek/patches-4.14/0172-clk-mediatek-group-drivers-under-indpendent-menu.patch new file mode 100644 index 000000000..2e4c233e8 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0172-clk-mediatek-group-drivers-under-indpendent-menu.patch @@ -0,0 +1,223 @@ +From 13ee94af58240b75550f413fece707987d563193 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 20 Dec 2017 14:42:58 +0800 +Subject: [PATCH 172/224] clk: mediatek: group drivers under indpendent menu + +Getting much MediaTek clock driver have been added to CCF, so it's +better adding the cleanup for grouping drivers under the independent +menu to simplify configuration selection. In addition, really trivial +fixups for typos are added in the same patch. + +Signed-off-by: Sean Wang +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/Kconfig | 96 +++++++++++++++++++++++--------------------- + 1 file changed, 50 insertions(+), 46 deletions(-) + +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -1,136 +1,139 @@ + # +-# MediaTek SoC drivers ++# MediaTek Clock Drivers + # ++menu "Clock driver for MediaTek SoC" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ + config COMMON_CLK_MEDIATEK + bool + ---help--- +- Mediatek SoCs' clock support. ++ MediaTek SoCs' clock support. + + config COMMON_CLK_MT2701 +- bool "Clock driver for Mediatek MT2701" ++ bool "Clock driver for MediaTek MT2701" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM + ---help--- +- This driver supports Mediatek MT2701 basic clocks. ++ This driver supports MediaTek MT2701 basic clocks. + + config COMMON_CLK_MT2701_MMSYS +- bool "Clock driver for Mediatek MT2701 mmsys" ++ bool "Clock driver for MediaTek MT2701 mmsys" + depends on COMMON_CLK_MT2701 + ---help--- +- This driver supports Mediatek MT2701 mmsys clocks. ++ This driver supports MediaTek MT2701 mmsys clocks. + + config COMMON_CLK_MT2701_IMGSYS +- bool "Clock driver for Mediatek MT2701 imgsys" ++ bool "Clock driver for MediaTek MT2701 imgsys" + depends on COMMON_CLK_MT2701 + ---help--- +- This driver supports Mediatek MT2701 imgsys clocks. ++ This driver supports MediaTek MT2701 imgsys clocks. + + config COMMON_CLK_MT2701_VDECSYS +- bool "Clock driver for Mediatek MT2701 vdecsys" ++ bool "Clock driver for MediaTek MT2701 vdecsys" + depends on COMMON_CLK_MT2701 + ---help--- +- This driver supports Mediatek MT2701 vdecsys clocks. ++ This driver supports MediaTek MT2701 vdecsys clocks. + + config COMMON_CLK_MT2701_HIFSYS +- bool "Clock driver for Mediatek MT2701 hifsys" ++ bool "Clock driver for MediaTek MT2701 hifsys" + depends on COMMON_CLK_MT2701 + ---help--- +- This driver supports Mediatek MT2701 hifsys clocks. ++ This driver supports MediaTek MT2701 hifsys clocks. + + config COMMON_CLK_MT2701_ETHSYS +- bool "Clock driver for Mediatek MT2701 ethsys" ++ bool "Clock driver for MediaTek MT2701 ethsys" + depends on COMMON_CLK_MT2701 + ---help--- +- This driver supports Mediatek MT2701 ethsys clocks. ++ This driver supports MediaTek MT2701 ethsys clocks. + + config COMMON_CLK_MT2701_BDPSYS +- bool "Clock driver for Mediatek MT2701 bdpsys" ++ bool "Clock driver for MediaTek MT2701 bdpsys" + depends on COMMON_CLK_MT2701 + ---help--- +- This driver supports Mediatek MT2701 bdpsys clocks. ++ This driver supports MediaTek MT2701 bdpsys clocks. + + config COMMON_CLK_MT2712 +- bool "Clock driver for Mediatek MT2712" ++ bool "Clock driver for MediaTek MT2712" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM64 + ---help--- +- This driver supports Mediatek MT2712 basic clocks. ++ This driver supports MediaTek MT2712 basic clocks. + + config COMMON_CLK_MT2712_BDPSYS +- bool "Clock driver for Mediatek MT2712 bdpsys" ++ bool "Clock driver for MediaTek MT2712 bdpsys" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 bdpsys clocks. ++ This driver supports MediaTek MT2712 bdpsys clocks. + + config COMMON_CLK_MT2712_IMGSYS +- bool "Clock driver for Mediatek MT2712 imgsys" ++ bool "Clock driver for MediaTek MT2712 imgsys" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 imgsys clocks. ++ This driver supports MediaTek MT2712 imgsys clocks. + + config COMMON_CLK_MT2712_JPGDECSYS +- bool "Clock driver for Mediatek MT2712 jpgdecsys" ++ bool "Clock driver for MediaTek MT2712 jpgdecsys" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 jpgdecsys clocks. ++ This driver supports MediaTek MT2712 jpgdecsys clocks. + + config COMMON_CLK_MT2712_MFGCFG +- bool "Clock driver for Mediatek MT2712 mfgcfg" ++ bool "Clock driver for MediaTek MT2712 mfgcfg" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 mfgcfg clocks. ++ This driver supports MediaTek MT2712 mfgcfg clocks. + + config COMMON_CLK_MT2712_MMSYS +- bool "Clock driver for Mediatek MT2712 mmsys" ++ bool "Clock driver for MediaTek MT2712 mmsys" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 mmsys clocks. ++ This driver supports MediaTek MT2712 mmsys clocks. + + config COMMON_CLK_MT2712_VDECSYS +- bool "Clock driver for Mediatek MT2712 vdecsys" ++ bool "Clock driver for MediaTek MT2712 vdecsys" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 vdecsys clocks. ++ This driver supports MediaTek MT2712 vdecsys clocks. + + config COMMON_CLK_MT2712_VENCSYS +- bool "Clock driver for Mediatek MT2712 vencsys" ++ bool "Clock driver for MediaTek MT2712 vencsys" + depends on COMMON_CLK_MT2712 + ---help--- +- This driver supports Mediatek MT2712 vencsys clocks. ++ This driver supports MediaTek MT2712 vencsys clocks. + + config COMMON_CLK_MT6797 +- bool "Clock driver for Mediatek MT6797" ++ bool "Clock driver for MediaTek MT6797" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM64 + ---help--- +- This driver supports Mediatek MT6797 basic clocks. ++ This driver supports MediaTek MT6797 basic clocks. + + config COMMON_CLK_MT6797_MMSYS +- bool "Clock driver for Mediatek MT6797 mmsys" ++ bool "Clock driver for MediaTek MT6797 mmsys" + depends on COMMON_CLK_MT6797 + ---help--- +- This driver supports Mediatek MT6797 mmsys clocks. ++ This driver supports MediaTek MT6797 mmsys clocks. + + config COMMON_CLK_MT6797_IMGSYS +- bool "Clock driver for Mediatek MT6797 imgsys" ++ bool "Clock driver for MediaTek MT6797 imgsys" + depends on COMMON_CLK_MT6797 + ---help--- +- This driver supports Mediatek MT6797 imgsys clocks. ++ This driver supports MediaTek MT6797 imgsys clocks. + + config COMMON_CLK_MT6797_VDECSYS +- bool "Clock driver for Mediatek MT6797 vdecsys" ++ bool "Clock driver for MediaTek MT6797 vdecsys" + depends on COMMON_CLK_MT6797 + ---help--- +- This driver supports Mediatek MT6797 vdecsys clocks. ++ This driver supports MediaTek MT6797 vdecsys clocks. + + config COMMON_CLK_MT6797_VENCSYS +- bool "Clock driver for Mediatek MT6797 vencsys" ++ bool "Clock driver for MediaTek MT6797 vencsys" + depends on COMMON_CLK_MT6797 + ---help--- +- This driver supports Mediatek MT6797 vencsys clocks. ++ This driver supports MediaTek MT6797 vencsys clocks. + + config COMMON_CLK_MT7622 + bool "Clock driver for MediaTek MT7622" +@@ -163,17 +166,18 @@ config COMMON_CLK_MT7622_AUDSYS + to audio consumers such as I2S and TDM. + + config COMMON_CLK_MT8135 +- bool "Clock driver for Mediatek MT8135" ++ bool "Clock driver for MediaTek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM + ---help--- +- This driver supports Mediatek MT8135 clocks. ++ This driver supports MediaTek MT8135 clocks. + + config COMMON_CLK_MT8173 +- bool "Clock driver for Mediatek MT8173" ++ bool "Clock driver for MediaTek MT8173" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK + ---help--- +- This driver supports Mediatek MT8173 clocks. ++ This driver supports MediaTek MT8173 clocks. ++endmenu diff --git a/target/linux/mediatek/patches-4.14/0173-clk-mediatek-fixup-test-building-of-MediaTek-clock-d.patch b/target/linux/mediatek/patches-4.14/0173-clk-mediatek-fixup-test-building-of-MediaTek-clock-d.patch new file mode 100644 index 000000000..f8a755003 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0173-clk-mediatek-fixup-test-building-of-MediaTek-clock-d.patch @@ -0,0 +1,27 @@ +From 3f963310151f6e630f94acf73ff44493619038ff Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 20 Dec 2017 14:42:59 +0800 +Subject: [PATCH 173/224] clk: mediatek: fixup test-building of MediaTek clock + drivers + +Let the build system looking into the directiory where the clock drivers +resides for the COMPILE_TEST alternative dependency allows test-building +the drivers. + +Signed-off-by: Sean Wang +Signed-off-by: Stephen Boyd +--- + drivers/clk/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -67,7 +67,7 @@ obj-$(CONFIG_ARCH_MXC) += imx/ + obj-$(CONFIG_MACH_INGENIC) += ingenic/ + obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ + obj-$(CONFIG_MACH_LOONGSON32) += loongson1/ +-obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ ++obj-y += mediatek/ + obj-$(CONFIG_COMMON_CLK_AMLOGIC) += meson/ + obj-$(CONFIG_MACH_PIC32) += microchip/ + ifeq ($(CONFIG_COMMON_CLK), y) diff --git a/target/linux/mediatek/patches-4.14/0174-dt-bindings-net-mediatek-add-condition-to-property-m.patch b/target/linux/mediatek/patches-4.14/0174-dt-bindings-net-mediatek-add-condition-to-property-m.patch new file mode 100644 index 000000000..ae63b2f50 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0174-dt-bindings-net-mediatek-add-condition-to-property-m.patch @@ -0,0 +1,27 @@ +From ee687ebf4708fb9e2a64830cdecd8cf992ef9b2b Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 20 Dec 2017 17:47:05 +0800 +Subject: [PATCH 174/224] dt-bindings: net: mediatek: add condition to property + mediatek, pctl + +The property "mediatek,pctl" is only required for SoCs such as MT2701 and +MT7623, so adding a few words for stating the condition. + +Signed-off-by: Sean Wang +Reviewed-by: Rob Herring +Signed-off-by: David S. Miller +--- + Documentation/devicetree/bindings/net/mediatek-net.txt | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/Documentation/devicetree/bindings/net/mediatek-net.txt ++++ b/Documentation/devicetree/bindings/net/mediatek-net.txt +@@ -28,7 +28,7 @@ Required properties: + - mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup + which is required for those SoCs equipped with SGMII such as MT7622 SoC. + - mediatek,pctl: phandle to the syscon node that handles the ports slew rate +- and driver current ++ and driver current: only for MT2701 and MT7623 SoC + + Optional properties: + - interrupt-parent: Should be the phandle for the interrupt controller diff --git a/target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch b/target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch new file mode 100644 index 000000000..86354973b --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0175-net-mediatek-remove-superfluous-pin-setup-for-MT7622.patch @@ -0,0 +1,102 @@ +From d96cf7e724105dc73f623c2019ab5bc78cef036e Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 20 Dec 2017 17:47:06 +0800 +Subject: [PATCH 175/224] net: mediatek: remove superfluous pin setup for + MT7622 SoC + +Remove superfluous pin setup to get out of accessing invalid I/O pin +registers because the way for pin configuring tends to be different from +various SoCs and thus it should be better being managed and controlled by +the pinctrl driver which MT7622 already can support. + +Signed-off-by: Sean Wang +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------ + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++ + 2 files changed, 24 insertions(+), 14 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -1976,14 +1976,16 @@ static int mtk_hw_init(struct mtk_eth *e + } + regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); + +- /* Set GE2 driving and slew rate */ +- regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); ++ if (eth->pctl) { ++ /* Set GE2 driving and slew rate */ ++ regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); + +- /* set GE2 TDSEL */ +- regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); ++ /* set GE2 TDSEL */ ++ regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); + +- /* set GE2 TUNE */ +- regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); ++ /* set GE2 TUNE */ ++ regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); ++ } + + /* Set linkdown as the default for each GMAC. Its own MCR would be set + * up with the more appropriate value when mtk_phy_link_adjust call is +@@ -2568,11 +2570,13 @@ static int mtk_probe(struct platform_dev + } + } + +- eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, +- "mediatek,pctl"); +- if (IS_ERR(eth->pctl)) { +- dev_err(&pdev->dev, "no pctl regmap found\n"); +- return PTR_ERR(eth->pctl); ++ if (eth->soc->required_pctl) { ++ eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, ++ "mediatek,pctl"); ++ if (IS_ERR(eth->pctl)) { ++ dev_err(&pdev->dev, "no pctl regmap found\n"); ++ return PTR_ERR(eth->pctl); ++ } + } + + for (i = 0; i < 3; i++) { +@@ -2698,17 +2702,20 @@ static int mtk_remove(struct platform_de + + static const struct mtk_soc_data mt2701_data = { + .caps = MTK_GMAC1_TRGMII, +- .required_clks = MT7623_CLKS_BITMAP ++ .required_clks = MT7623_CLKS_BITMAP, ++ .required_pctl = true, + }; + + static const struct mtk_soc_data mt7622_data = { + .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW, +- .required_clks = MT7622_CLKS_BITMAP ++ .required_clks = MT7622_CLKS_BITMAP, ++ .required_pctl = false, + }; + + static const struct mtk_soc_data mt7623_data = { + .caps = MTK_GMAC1_TRGMII, +- .required_clks = MT7623_CLKS_BITMAP ++ .required_clks = MT7623_CLKS_BITMAP, ++ .required_pctl = true, + }; + + const struct of_device_id of_mtk_match[] = { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -574,10 +574,13 @@ struct mtk_rx_ring { + * @caps Flags shown the extra capability for the SoC + * @required_clks Flags shown the bitmap for required clocks on + * the target SoC ++ * @required_pctl A bool value to show whether the SoC requires ++ * the extra setup for those pins used by GMAC. + */ + struct mtk_soc_data { + u32 caps; + u32 required_clks; ++ bool required_pctl; + }; + + /* currently no SoC has more than 2 macs */ diff --git a/target/linux/mediatek/patches-4.14/0176-clk-mediatek-Fix-all-warnings-for-missing-struct-clk.patch b/target/linux/mediatek/patches-4.14/0176-clk-mediatek-Fix-all-warnings-for-missing-struct-clk.patch new file mode 100644 index 000000000..ee196a73e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0176-clk-mediatek-Fix-all-warnings-for-missing-struct-clk.patch @@ -0,0 +1,68 @@ +From f42f141077a12e28fe33c0033f698afb1402ec20 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 25 Dec 2017 16:03:57 +0800 +Subject: [PATCH 176/224] clk: mediatek: Fix all warnings for missing struct + clk_onecell_data + +Even though the header file linux/clk-provider.h is already being properly +included in clk-mtk.h, the definition of struct clk_onecell_data still +must depend on CONFIG_COMMON_CLK defined and thus it's possible that +below build warnings occur when CONFIG_COMMON_CLK is not being selected. + +Therefore, these functions which need struct clk_onecell_data without +declaring that structure first requires simply declaring that this struct +exists prior to referencing it in clk-mtk.h + +Changes from v1->v2: +enhance v1 based on two useful solutions Jean Delvare kindly suggested. + +All warnings (new ones prefixed by >>): + +In file included from drivers/clk/mediatek/reset.c:22:0: +>>drivers/clk/mediatek/clk-mtk.h:44:19: warning: 'struct clk_onecell_data' +declared inside parameter list will not be visible outside of +this definition or declaration + int num, struct clk_onecell_data *clk_data); + ^~~~~~~~~~~~~~~~ +drivers/clk/mediatek/clk-mtk.h:63:19: warning: 'struct clk_onecell_data' +declared inside parameter list will not be visible outside of +this definition or declaration + int num, struct clk_onecell_data *clk_data); + ^~~~~~~~~~~~~~~~ +drivers/clk/mediatek/clk-mtk.h:145:10: warning: 'struct clk_onecell_data' +declared inside parameter list will not be visible outside of +this definition or declaration + struct clk_onecell_data *clk_data); + ^~~~~~~~~~~~~~~~ +drivers/clk/mediatek/clk-mtk.h:164:11: warning: 'struct clk_onecell_data' +declared inside parameter list will not be visible outside of +this definition or declaration + struct clk_onecell_data *clk_data); + ^~~~~~~~~~~~~~~~ +drivers/clk/mediatek/clk-mtk.h:190:12: warning: 'struct clk_onecell_data' +declared inside parameter list will not be visible outside of this +definition or declaration + struct clk_onecell_data *clk_data); + ^~~~~~~~~~~~~~~~ + +Reported-by: kbuild test robot +Signed-off-by: Sean Wang +Cc: kbuild-all@01.org +Cc: Stephen Boyd +Cc: Jean Delvare +Cc: linux-clk@vger.kernel.org +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/clk-mtk.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -20,6 +20,7 @@ + #include + + struct clk; ++struct clk_onecell_data; + + #define MAX_MUX_GATE_BIT 31 + #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) diff --git a/target/linux/mediatek/patches-4.14/0177-phy-phy-mtk-tphy-use-auto-instead-of-force-to-bypass.patch b/target/linux/mediatek/patches-4.14/0177-phy-phy-mtk-tphy-use-auto-instead-of-force-to-bypass.patch new file mode 100644 index 000000000..fc993c326 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0177-phy-phy-mtk-tphy-use-auto-instead-of-force-to-bypass.patch @@ -0,0 +1,75 @@ +From dacdae142ffd909ed6718adb05af74ff800da668 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Thu, 7 Dec 2017 19:53:34 +0800 +Subject: [PATCH 177/224] phy: phy-mtk-tphy: use auto instead of force to + bypass utmi signals + +When system is running, if usb2 phy is forced to bypass utmi signals, +all PLL will be turned off, and it can't detect device connection +anymore, so replace force mode with auto mode which can bypass utmi +signals automatically if no device attached for normal flow. +But keep the force mode to fix RX sensitivity degradation issue. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Kishon Vijay Abraham I +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 19 +++++++------------ + 1 file changed, 7 insertions(+), 12 deletions(-) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -440,9 +440,9 @@ static void u2_phy_instance_init(struct + u32 index = instance->index; + u32 tmp; + +- /* switch to USB function. (system register, force ip into usb mode) */ ++ /* switch to USB function, and enable usb pll */ + tmp = readl(com + U3P_U2PHYDTM0); +- tmp &= ~P2C_FORCE_UART_EN; ++ tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); + tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0); + writel(tmp, com + U3P_U2PHYDTM0); + +@@ -502,10 +502,8 @@ static void u2_phy_instance_power_on(str + u32 index = instance->index; + u32 tmp; + +- /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ + tmp = readl(com + U3P_U2PHYDTM0); +- tmp &= ~(P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL); +- tmp &= ~(P2C_RG_DATAIN | P2C_DTM0_PART_MASK); ++ tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); + writel(tmp, com + U3P_U2PHYDTM0); + + /* OTG Enable */ +@@ -540,7 +538,6 @@ static void u2_phy_instance_power_off(st + + tmp = readl(com + U3P_U2PHYDTM0); + tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN); +- tmp |= P2C_FORCE_SUSPENDM; + writel(tmp, com + U3P_U2PHYDTM0); + + /* OTG Disable */ +@@ -548,18 +545,16 @@ static void u2_phy_instance_power_off(st + tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN; + writel(tmp, com + U3P_USBPHYACR6); + +- /* let suspendm=0, set utmi into analog power down */ +- tmp = readl(com + U3P_U2PHYDTM0); +- tmp &= ~P2C_RG_SUSPENDM; +- writel(tmp, com + U3P_U2PHYDTM0); +- udelay(1); +- + tmp = readl(com + U3P_U2PHYDTM1); + tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID); + tmp |= P2C_RG_SESSEND; + writel(tmp, com + U3P_U2PHYDTM1); + + if (tphy->pdata->avoid_rx_sen_degradation && index) { ++ tmp = readl(com + U3P_U2PHYDTM0); ++ tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); ++ writel(tmp, com + U3P_U2PHYDTM0); ++ + tmp = readl(com + U3D_U2PHYDCR0); + tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON; + writel(tmp, com + U3D_U2PHYDCR0); diff --git a/target/linux/mediatek/patches-4.14/0178-phy-phy-mtk-tphy-make-shared-banks-optional-for-V1-T.patch b/target/linux/mediatek/patches-4.14/0178-phy-phy-mtk-tphy-make-shared-banks-optional-for-V1-T.patch new file mode 100644 index 000000000..31e4ade08 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0178-phy-phy-mtk-tphy-make-shared-banks-optional-for-V1-T.patch @@ -0,0 +1,30 @@ +From d7a38584713b00cf9ae97aed89d5e8fb7e3c1bea Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Thu, 7 Dec 2017 19:53:35 +0800 +Subject: [PATCH 178/224] phy: phy-mtk-tphy: make shared banks optional for V1 + TPHY + +V1 TPHY for SATA doesn't have shared banks if it isn't shared +with PCIe or USB, so make it optional. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Kishon Vijay Abraham I +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -1023,9 +1023,10 @@ static int mtk_tphy_probe(struct platfor + tphy->dev = dev; + platform_set_drvdata(pdev, tphy); + +- if (tphy->pdata->version == MTK_PHY_V1) { ++ sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ /* SATA phy of V1 needn't it if not shared with PCIe or USB */ ++ if (sif_res && tphy->pdata->version == MTK_PHY_V1) { + /* get banks shared by multiple phys */ +- sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + tphy->sif_base = devm_ioremap_resource(dev, sif_res); + if (IS_ERR(tphy->sif_base)) { + dev_err(dev, "failed to remap sif regs\n"); diff --git a/target/linux/mediatek/patches-4.14/0179-phy-phy-mtk-tphy-use-of_device_get_match_data.patch b/target/linux/mediatek/patches-4.14/0179-phy-phy-mtk-tphy-use-of_device_get_match_data.patch new file mode 100644 index 000000000..db77ca299 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0179-phy-phy-mtk-tphy-use-of_device_get_match_data.patch @@ -0,0 +1,51 @@ +From 3e53007a55e70d5036a527900befecf9a6316d05 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Thu, 28 Dec 2017 16:40:36 +0530 +Subject: [PATCH 179/224] phy: phy-mtk-tphy: use of_device_get_match_data() + +reduce the boilerplate code to get the specific data + +Signed-off-by: Chunfeng Yun +Signed-off-by: Kishon Vijay Abraham I +--- + drivers/phy/mediatek/phy-mtk-tphy.c | 11 +++++------ + 1 file changed, 5 insertions(+), 6 deletions(-) + +--- a/drivers/phy/mediatek/phy-mtk-tphy.c ++++ b/drivers/phy/mediatek/phy-mtk-tphy.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -995,7 +996,6 @@ MODULE_DEVICE_TABLE(of, mtk_tphy_id_tabl + + static int mtk_tphy_probe(struct platform_device *pdev) + { +- const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct device_node *child_np; +@@ -1005,15 +1005,14 @@ static int mtk_tphy_probe(struct platfor + struct resource res; + int port, retval; + +- match = of_match_node(mtk_tphy_id_table, pdev->dev.of_node); +- if (!match) +- return -EINVAL; +- + tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); + if (!tphy) + return -ENOMEM; + +- tphy->pdata = match->data; ++ tphy->pdata = of_device_get_match_data(dev); ++ if (!tphy->pdata) ++ return -EINVAL; ++ + tphy->nphys = of_get_child_count(np); + tphy->phys = devm_kcalloc(dev, tphy->nphys, + sizeof(*tphy->phys), GFP_KERNEL); diff --git a/target/linux/mediatek/patches-4.14/0180-ASoC-mediatek-fix-error-handling-in-mt2701_afe_pcm_d.patch b/target/linux/mediatek/patches-4.14/0180-ASoC-mediatek-fix-error-handling-in-mt2701_afe_pcm_d.patch new file mode 100644 index 000000000..358f3d3ab --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0180-ASoC-mediatek-fix-error-handling-in-mt2701_afe_pcm_d.patch @@ -0,0 +1,81 @@ +From 17508c32dd65649d2617c1c52b32b02bdb54b793 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 2 Jan 2018 19:47:18 +0800 +Subject: [PATCH 180/224] ASoC: mediatek: fix error handling in + mt2701_afe_pcm_dev_probe() + +Fix unbalanced error handling path which will get incorrect counts +if probe failed. The .remove() should be adjusted accordingly. + +Signed-off-by: Ryder Lee +Tested-by: Garlic Tseng +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 31 ++++++++++++++---------------- + 1 file changed, 14 insertions(+), 17 deletions(-) + +--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c +@@ -1590,12 +1590,16 @@ static int mt2701_afe_pcm_dev_probe(stru + } + + platform_set_drvdata(pdev, afe); +- pm_runtime_enable(&pdev->dev); +- if (!pm_runtime_enabled(&pdev->dev)) +- goto err_pm_disable; +- pm_runtime_get_sync(&pdev->dev); + +- ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform); ++ pm_runtime_enable(dev); ++ if (!pm_runtime_enabled(dev)) { ++ ret = mt2701_afe_runtime_resume(dev); ++ if (ret) ++ goto err_pm_disable; ++ } ++ pm_runtime_get_sync(dev); ++ ++ ret = snd_soc_register_platform(dev, &mtk_afe_pcm_platform); + if (ret) { + dev_warn(dev, "err_platform\n"); + goto err_platform; +@@ -1610,35 +1614,28 @@ static int mt2701_afe_pcm_dev_probe(stru + goto err_dai_component; + } + +- mt2701_afe_runtime_resume(&pdev->dev); +- + return 0; + + err_dai_component: +- snd_soc_unregister_component(&pdev->dev); +- ++ snd_soc_unregister_platform(dev); + err_platform: +- snd_soc_unregister_platform(&pdev->dev); +- ++ pm_runtime_put_sync(dev); + err_pm_disable: +- pm_runtime_disable(&pdev->dev); ++ pm_runtime_disable(dev); + + return ret; + } + + static int mt2701_afe_pcm_dev_remove(struct platform_device *pdev) + { +- struct mtk_base_afe *afe = platform_get_drvdata(pdev); +- ++ pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + if (!pm_runtime_status_suspended(&pdev->dev)) + mt2701_afe_runtime_suspend(&pdev->dev); +- pm_runtime_put_sync(&pdev->dev); + + snd_soc_unregister_component(&pdev->dev); + snd_soc_unregister_platform(&pdev->dev); +- /* disable afe clock */ +- mt2701_afe_disable_clock(afe); ++ + return 0; + } + diff --git a/target/linux/mediatek/patches-4.14/0181-ASoC-mediatek-rework-clock-functions-for-MT2701.patch b/target/linux/mediatek/patches-4.14/0181-ASoC-mediatek-rework-clock-functions-for-MT2701.patch new file mode 100644 index 000000000..59a98a6c8 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0181-ASoC-mediatek-rework-clock-functions-for-MT2701.patch @@ -0,0 +1,919 @@ +From d038da516563d910dd39930777f431d4c65a56cd Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 2 Jan 2018 19:47:19 +0800 +Subject: [PATCH 181/224] ASoC: mediatek: rework clock functions for MT2701 + +Reworks clock part to make it more reasonable. The current changes are: + +- Replace regmap operations by CCF APIs. Doing so, we just need to handle + the element clocks and can also get accurate information via CCF. + +- Rename clocks to make them more generic so that the future revisions + of the IP can adapt gracefully. + +- Regroup 'aud_clks[]' by usage - the basic needs and I2S parts: + + The new code just keep the common clocks in array and let SoC self decide + I2S numbers - If future chips have different sets of channels we will + add a little more abstract here. + + Moreover, this patch moves I2S clocks to the struct mt2701_i2s_data + so that we can easily manage them when calls .prepare() and .shutdown(). + +Signed-off-by: Ryder Lee +Tested-by: Garlic Tseng +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 518 +++++++--------------- + sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h | 15 +- + sound/soc/mediatek/mt2701/mt2701-afe-common.h | 64 +-- + sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 45 +- + 4 files changed, 200 insertions(+), 442 deletions(-) + +--- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c +@@ -21,442 +21,256 @@ + #include "mt2701-afe-common.h" + #include "mt2701-afe-clock-ctrl.h" + +-static const char *aud_clks[MT2701_CLOCK_NUM] = { +- [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk", +- [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel", +- [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel", +- [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div", +- [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div", +- [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing", +- [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing", +- [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel", +- [MT2701_AUD_APLL_SEL] = "top_apll_sel", +- [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M", +- [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M", +- [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M", +- [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M", +- [MT2701_AUD_AUDPLL] = "top_audpll", +- [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4", +- [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8", +- [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16", +- [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24", +- [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel", +- [MT2701_AUD_CLK_26M] = "clk_26m", +- [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4", +- [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel", +- [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel", +- [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel", +- [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel", +- [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel", +- [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel", +- [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div", +- [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div", +- [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div", +- [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div", +- [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div", +- [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div", +- [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk", +- [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk", +- [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk", +- [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk", +- [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk", +- [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk", +- [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel", +- [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel", +- [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4", +- [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2", +- [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5", ++static const char *const base_clks[] = { ++ [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel", ++ [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel", ++ [MT2701_AUDSYS_AFE] = "audio_afe_pd", ++ [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd", ++ [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd", ++ [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd", + }; + + int mt2701_init_clock(struct mtk_base_afe *afe) + { + struct mt2701_afe_private *afe_priv = afe->platform_priv; +- int i = 0; ++ int i; + +- for (i = 0; i < MT2701_CLOCK_NUM; i++) { +- afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); +- if (IS_ERR(afe_priv->clocks[i])) { +- dev_warn(afe->dev, "%s devm_clk_get %s fail\n", +- __func__, aud_clks[i]); +- return PTR_ERR(aud_clks[i]); ++ for (i = 0; i < MT2701_BASE_CLK_NUM; i++) { ++ afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]); ++ if (IS_ERR(afe_priv->base_ck[i])) { ++ dev_err(afe->dev, "failed to get %s\n", base_clks[i]); ++ return PTR_ERR(afe_priv->base_ck[i]); + } + } + +- return 0; +-} ++ /* Get I2S related clocks */ ++ for (i = 0; i < MT2701_I2S_NUM; i++) { ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i]; ++ char name[13]; ++ ++ snprintf(name, sizeof(name), "i2s%d_src_sel", i); ++ i2s_path->sel_ck = devm_clk_get(afe->dev, name); ++ if (IS_ERR(i2s_path->sel_ck)) { ++ dev_err(afe->dev, "failed to get %s\n", name); ++ return PTR_ERR(i2s_path->sel_ck); ++ } + +-int mt2701_afe_enable_clock(struct mtk_base_afe *afe) +-{ +- int ret = 0; ++ snprintf(name, sizeof(name), "i2s%d_src_div", i); ++ i2s_path->div_ck = devm_clk_get(afe->dev, name); ++ if (IS_ERR(i2s_path->div_ck)) { ++ dev_err(afe->dev, "failed to get %s\n", name); ++ return PTR_ERR(i2s_path->div_ck); ++ } + +- ret = mt2701_turn_on_a1sys_clock(afe); +- if (ret) { +- dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n", +- __func__, ret); +- return ret; +- } ++ snprintf(name, sizeof(name), "i2s%d_mclk_en", i); ++ i2s_path->mclk_ck = devm_clk_get(afe->dev, name); ++ if (IS_ERR(i2s_path->mclk_ck)) { ++ dev_err(afe->dev, "failed to get %s\n", name); ++ return PTR_ERR(i2s_path->mclk_ck); ++ } + +- ret = mt2701_turn_on_a2sys_clock(afe); +- if (ret) { +- dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n", +- __func__, ret); +- mt2701_turn_off_a1sys_clock(afe); +- return ret; +- } ++ snprintf(name, sizeof(name), "i2so%d_hop_ck", i); ++ i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name); ++ if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) { ++ dev_err(afe->dev, "failed to get %s\n", name); ++ return PTR_ERR(i2s_path->hop_ck[I2S_OUT]); ++ } + +- ret = mt2701_turn_on_afe_clock(afe); +- if (ret) { +- dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n", +- __func__, ret); +- mt2701_turn_off_a1sys_clock(afe); +- mt2701_turn_off_a2sys_clock(afe); +- return ret; ++ snprintf(name, sizeof(name), "i2si%d_hop_ck", i); ++ i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name); ++ if (IS_ERR(i2s_path->hop_ck[I2S_IN])) { ++ dev_err(afe->dev, "failed to get %s\n", name); ++ return PTR_ERR(i2s_path->hop_ck[I2S_IN]); ++ } ++ ++ snprintf(name, sizeof(name), "asrc%d_out_ck", i); ++ i2s_path->asrco_ck = devm_clk_get(afe->dev, name); ++ if (IS_ERR(i2s_path->asrco_ck)) { ++ dev_err(afe->dev, "failed to get %s\n", name); ++ return PTR_ERR(i2s_path->asrco_ck); ++ } + } + +- regmap_update_bits(afe->regmap, ASYS_TOP_CON, +- AUDIO_TOP_CON0_A1SYS_A2SYS_ON, +- AUDIO_TOP_CON0_A1SYS_A2SYS_ON); +- regmap_update_bits(afe->regmap, AFE_DAC_CON0, +- AFE_DAC_CON0_AFE_ON, +- AFE_DAC_CON0_AFE_ON); +- regmap_write(afe->regmap, PWR2_TOP_CON, +- PWR2_TOP_CON_INIT_VAL); +- regmap_write(afe->regmap, PWR1_ASM_CON1, +- PWR1_ASM_CON1_INIT_VAL); +- regmap_write(afe->regmap, PWR2_ASM_CON1, +- PWR2_ASM_CON1_INIT_VAL); ++ /* Some platforms may support BT path */ ++ afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd"); ++ if (IS_ERR(afe_priv->mrgif_ck)) { ++ if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; + +- return 0; +-} ++ afe_priv->mrgif_ck = NULL; ++ } + +-void mt2701_afe_disable_clock(struct mtk_base_afe *afe) +-{ +- mt2701_turn_off_afe_clock(afe); +- mt2701_turn_off_a1sys_clock(afe); +- mt2701_turn_off_a2sys_clock(afe); +- regmap_update_bits(afe->regmap, ASYS_TOP_CON, +- AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0); +- regmap_update_bits(afe->regmap, AFE_DAC_CON0, +- AFE_DAC_CON0_AFE_ON, 0); ++ return 0; + } + +-int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe) ++int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir) + { + struct mt2701_afe_private *afe_priv = afe->platform_priv; +- int ret = 0; ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; ++ int ret; + +- /* Set Mux */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); ++ ret = clk_prepare_enable(i2s_path->asrco_ck); + if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret); +- goto A1SYS_CLK_AUD_MUX1_SEL_ERR; ++ dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret); ++ return ret; + } + +- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL], +- afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]); ++ ret = clk_prepare_enable(i2s_path->hop_ck[dir]); + if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, +- aud_clks[MT2701_AUD_AUD_MUX1_SEL], +- aud_clks[MT2701_AUD_AUD1PLL_98M], ret); +- goto A1SYS_CLK_AUD_MUX1_SEL_ERR; ++ dev_err(afe->dev, "failed to enable I2S clock %d\n", ret); ++ goto err_hop_ck; + } + +- /* Set Divider */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, +- aud_clks[MT2701_AUD_AUD_MUX1_DIV], +- ret); +- goto A1SYS_CLK_AUD_MUX1_DIV_ERR; +- } ++ return 0; + +- ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV], +- MT2701_AUD_AUD_MUX1_DIV_RATE); +- if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__, +- aud_clks[MT2701_AUD_AUD_MUX1_DIV], +- MT2701_AUD_AUD_MUX1_DIV_RATE, ret); +- goto A1SYS_CLK_AUD_MUX1_DIV_ERR; +- } ++err_hop_ck: ++ clk_disable_unprepare(i2s_path->asrco_ck); + +- /* Enable clock gate */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret); +- goto A1SYS_CLK_AUD_48K_ERR; +- } ++ return ret; ++} + +- /* Enable infra audio */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret); +- goto A1SYS_CLK_INFRA_ERR; +- } ++void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir) ++{ ++ struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; + +- return 0; ++ clk_disable_unprepare(i2s_path->hop_ck[dir]); ++ clk_disable_unprepare(i2s_path->asrco_ck); ++} + +-A1SYS_CLK_INFRA_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +-A1SYS_CLK_AUD_48K_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); +-A1SYS_CLK_AUD_MUX1_DIV_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]); +-A1SYS_CLK_AUD_MUX1_SEL_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); ++int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id) ++{ ++ struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; + +- return ret; ++ return clk_prepare_enable(i2s_path->mclk_ck); + } + +-void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe) ++void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id) + { + struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id]; + +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); ++ clk_disable_unprepare(i2s_path->mclk_ck); + } + +-int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe) ++int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe) + { + struct mt2701_afe_private *afe_priv = afe->platform_priv; +- int ret = 0; + +- /* Set Mux */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret); +- goto A2SYS_CLK_AUD_MUX2_SEL_ERR; +- } ++ return clk_prepare_enable(afe_priv->mrgif_ck); ++} + +- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL], +- afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]); +- if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, +- aud_clks[MT2701_AUD_AUD_MUX2_SEL], +- aud_clks[MT2701_AUD_AUD2PLL_90M], ret); +- goto A2SYS_CLK_AUD_MUX2_SEL_ERR; +- } ++void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe) ++{ ++ struct mt2701_afe_private *afe_priv = afe->platform_priv; + +- /* Set Divider */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret); +- goto A2SYS_CLK_AUD_MUX2_DIV_ERR; +- } ++ clk_disable_unprepare(afe_priv->mrgif_ck); ++} + +- ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV], +- MT2701_AUD_AUD_MUX2_DIV_RATE); +- if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__, +- aud_clks[MT2701_AUD_AUD_MUX2_DIV], +- MT2701_AUD_AUD_MUX2_DIV_RATE, ret); +- goto A2SYS_CLK_AUD_MUX2_DIV_ERR; +- } ++static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe) ++{ ++ struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ int ret; + +- /* Enable clock gate */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret); +- goto A2SYS_CLK_AUD_44K_ERR; +- } ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]); ++ if (ret) ++ return ret; + +- /* Enable infra audio */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret); +- goto A2SYS_CLK_INFRA_ERR; +- } ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); ++ if (ret) ++ goto err_audio_a1sys; ++ ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); ++ if (ret) ++ goto err_audio_a2sys; ++ ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]); ++ if (ret) ++ goto err_afe_conn; + + return 0; + +-A2SYS_CLK_INFRA_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +-A2SYS_CLK_AUD_44K_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); +-A2SYS_CLK_AUD_MUX2_DIV_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); +-A2SYS_CLK_AUD_MUX2_SEL_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); ++err_afe_conn: ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); ++err_audio_a2sys: ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); ++err_audio_a1sys: ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]); + + return ret; + } + +-void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe) ++static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe) + { + struct mt2701_afe_private *afe_priv = afe->platform_priv; + +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]); + } + +-int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe) ++int mt2701_afe_enable_clock(struct mtk_base_afe *afe) + { +- struct mt2701_afe_private *afe_priv = afe->platform_priv; + int ret; + +- /* enable INFRA_SYS */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); ++ /* Enable audio system */ ++ ret = mt2701_afe_enable_audsys(afe); + if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret); +- goto AFE_AUD_INFRA_ERR; +- } +- +- /* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_AUDINTBUS], ret); +- goto AFE_AUD_AUDINTBUS_ERR; +- } +- +- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS], +- afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]); +- if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, +- aud_clks[MT2701_AUD_AUDINTBUS], +- aud_clks[MT2701_AUD_SYSPLL1_D4], ret); +- goto AFE_AUD_AUDINTBUS_ERR; +- } +- +- /* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret); +- goto AFE_AUD_ASM_H_ERR; +- } +- +- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL], +- afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]); +- if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, +- aud_clks[MT2701_AUD_ASM_H_SEL], +- aud_clks[MT2701_AUD_UNIVPLL2_D2], ret); +- goto AFE_AUD_ASM_H_ERR; +- } +- +- /* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */ +- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]); +- if (ret) { +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret); +- goto AFE_AUD_ASM_M_ERR; ++ dev_err(afe->dev, "failed to enable audio system %d\n", ret); ++ return ret; + } + +- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL], +- afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]); +- if (ret) { +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, +- aud_clks[MT2701_AUD_ASM_M_SEL], +- aud_clks[MT2701_AUD_UNIVPLL2_D4], ret); +- goto AFE_AUD_ASM_M_ERR; +- } ++ regmap_update_bits(afe->regmap, ASYS_TOP_CON, ++ AUDIO_TOP_CON0_A1SYS_A2SYS_ON, ++ AUDIO_TOP_CON0_A1SYS_A2SYS_ON); ++ regmap_update_bits(afe->regmap, AFE_DAC_CON0, ++ AFE_DAC_CON0_AFE_ON, ++ AFE_DAC_CON0_AFE_ON); + +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, +- AUDIO_TOP_CON0_PDN_AFE, 0); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, +- AUDIO_TOP_CON0_PDN_APLL_CK, 0); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_A1SYS, 0); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_A2SYS, 0); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_AFE_CONN, 0); ++ /* Configure ASRC */ ++ regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL); ++ regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL); + + return 0; +- +-AFE_AUD_ASM_M_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]); +-AFE_AUD_ASM_H_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]); +-AFE_AUD_AUDINTBUS_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]); +-AFE_AUD_INFRA_ERR: +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); +- +- return ret; + } + +-void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe) ++int mt2701_afe_disable_clock(struct mtk_base_afe *afe) + { +- struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ regmap_update_bits(afe->regmap, ASYS_TOP_CON, ++ AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0); ++ regmap_update_bits(afe->regmap, AFE_DAC_CON0, ++ AFE_DAC_CON0_AFE_ON, 0); + +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); ++ mt2701_afe_disable_audsys(afe); + +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]); +- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]); +- +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, +- AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, +- AUDIO_TOP_CON0_PDN_APLL_CK, +- AUDIO_TOP_CON0_PDN_APLL_CK); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_A1SYS, +- AUDIO_TOP_CON4_PDN_A1SYS); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_A2SYS, +- AUDIO_TOP_CON4_PDN_A2SYS); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_AFE_CONN, +- AUDIO_TOP_CON4_PDN_AFE_CONN); ++ return 0; + } + + void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, + int mclk) + { +- struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ struct mt2701_afe_private *priv = afe->platform_priv; ++ struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id]; + int ret; +- int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id; +- int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id; + +- /* Set MCLK Kx_SRC_SEL(domain) */ +- ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]); +- if (ret) +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[aud_src_clk_id], ret); +- +- if (domain == 0) { +- ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id], +- afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); +- if (ret) +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", +- __func__, aud_clks[aud_src_clk_id], +- aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret); +- } else { +- ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id], +- afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); +- if (ret) +- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", +- __func__, aud_clks[aud_src_clk_id], +- aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret); +- } +- clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]); ++ /* Set mclk source */ ++ if (domain == 0) ++ ret = clk_set_parent(i2s_path->sel_ck, ++ priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]); ++ else ++ ret = clk_set_parent(i2s_path->sel_ck, ++ priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]); + +- /* Set MCLK Kx_SRC_DIV(divider) */ +- ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]); + if (ret) +- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", +- __func__, aud_clks[aud_src_div_id], ret); ++ dev_err(afe->dev, "failed to set domain%d mclk source %d\n", ++ domain, ret); + +- ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk); ++ /* Set mclk divider */ ++ ret = clk_set_rate(i2s_path->div_ck, mclk); + if (ret) +- dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__, +- aud_clks[aud_src_div_id], mclk, ret); +- clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]); ++ dev_err(afe->dev, "failed to set mclk divider %d\n", ret); + } + + MODULE_DESCRIPTION("MT2701 afe clock control"); +--- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h +@@ -21,16 +21,15 @@ struct mtk_base_afe; + + int mt2701_init_clock(struct mtk_base_afe *afe); + int mt2701_afe_enable_clock(struct mtk_base_afe *afe); +-void mt2701_afe_disable_clock(struct mtk_base_afe *afe); ++int mt2701_afe_disable_clock(struct mtk_base_afe *afe); + +-int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe); +-void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe); ++int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir); ++void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir); ++int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id); ++void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id); + +-int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe); +-void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe); +- +-int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe); +-void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe); ++int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe); ++void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe); + + void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, + int mclk); +--- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h +@@ -69,53 +69,14 @@ enum { + MT2701_IRQ_ASYS_END, + }; + +-/* 2701 clock def */ +-enum audio_system_clock_type { +- MT2701_AUD_INFRA_SYS_AUDIO, +- MT2701_AUD_AUD_MUX1_SEL, +- MT2701_AUD_AUD_MUX2_SEL, +- MT2701_AUD_AUD_MUX1_DIV, +- MT2701_AUD_AUD_MUX2_DIV, +- MT2701_AUD_AUD_48K_TIMING, +- MT2701_AUD_AUD_44K_TIMING, +- MT2701_AUD_AUDPLL_MUX_SEL, +- MT2701_AUD_APLL_SEL, +- MT2701_AUD_AUD1PLL_98M, +- MT2701_AUD_AUD2PLL_90M, +- MT2701_AUD_HADDS2PLL_98M, +- MT2701_AUD_HADDS2PLL_294M, +- MT2701_AUD_AUDPLL, +- MT2701_AUD_AUDPLL_D4, +- MT2701_AUD_AUDPLL_D8, +- MT2701_AUD_AUDPLL_D16, +- MT2701_AUD_AUDPLL_D24, +- MT2701_AUD_AUDINTBUS, +- MT2701_AUD_CLK_26M, +- MT2701_AUD_SYSPLL1_D4, +- MT2701_AUD_AUD_K1_SRC_SEL, +- MT2701_AUD_AUD_K2_SRC_SEL, +- MT2701_AUD_AUD_K3_SRC_SEL, +- MT2701_AUD_AUD_K4_SRC_SEL, +- MT2701_AUD_AUD_K5_SRC_SEL, +- MT2701_AUD_AUD_K6_SRC_SEL, +- MT2701_AUD_AUD_K1_SRC_DIV, +- MT2701_AUD_AUD_K2_SRC_DIV, +- MT2701_AUD_AUD_K3_SRC_DIV, +- MT2701_AUD_AUD_K4_SRC_DIV, +- MT2701_AUD_AUD_K5_SRC_DIV, +- MT2701_AUD_AUD_K6_SRC_DIV, +- MT2701_AUD_AUD_I2S1_MCLK, +- MT2701_AUD_AUD_I2S2_MCLK, +- MT2701_AUD_AUD_I2S3_MCLK, +- MT2701_AUD_AUD_I2S4_MCLK, +- MT2701_AUD_AUD_I2S5_MCLK, +- MT2701_AUD_AUD_I2S6_MCLK, +- MT2701_AUD_ASM_M_SEL, +- MT2701_AUD_ASM_H_SEL, +- MT2701_AUD_UNIVPLL2_D4, +- MT2701_AUD_UNIVPLL2_D2, +- MT2701_AUD_SYSPLL_D5, +- MT2701_CLOCK_NUM ++enum audio_base_clock { ++ MT2701_TOP_AUD_MCLK_SRC0, ++ MT2701_TOP_AUD_MCLK_SRC1, ++ MT2701_AUDSYS_AFE, ++ MT2701_AUDSYS_AFE_CONN, ++ MT2701_AUDSYS_A1SYS, ++ MT2701_AUDSYS_A2SYS, ++ MT2701_BASE_CLK_NUM, + }; + + static const unsigned int mt2701_afe_backup_list[] = { +@@ -144,7 +105,6 @@ struct mtk_base_irq_data; + + struct mt2701_i2s_data { + int i2s_ctrl_reg; +- int i2s_pwn_shift; + int i2s_asrc_fs_shift; + int i2s_asrc_fs_mask; + }; +@@ -161,11 +121,17 @@ struct mt2701_i2s_path { + int on[I2S_DIR_NUM]; + int occupied[I2S_DIR_NUM]; + const struct mt2701_i2s_data *i2s_data[2]; ++ struct clk *hop_ck[I2S_DIR_NUM]; ++ struct clk *sel_ck; ++ struct clk *div_ck; ++ struct clk *mclk_ck; ++ struct clk *asrco_ck; + }; + + struct mt2701_afe_private { +- struct clk *clocks[MT2701_CLOCK_NUM]; + struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; ++ struct clk *base_ck[MT2701_BASE_CLK_NUM]; ++ struct clk *mrgif_ck; + bool mrg_enable[MT2701_STREAM_DIR_NUM]; + }; + +--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c +@@ -97,21 +97,12 @@ static int mt2701_afe_i2s_startup(struct + { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); +- struct mt2701_afe_private *afe_priv = afe->platform_priv; + int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); +- int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num; +- int ret = 0; + + if (i2s_num < 0) + return i2s_num; + +- /* enable mclk */ +- ret = clk_prepare_enable(afe_priv->clocks[clk_num]); +- if (ret) +- dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n", +- i2s_num); +- +- return ret; ++ return mt2701_afe_enable_mclk(afe, i2s_num); + } + + static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream, +@@ -151,9 +142,9 @@ static int mt2701_afe_i2s_path_shutdown( + /* disable i2s */ + regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, + ASYS_I2S_CON_I2S_EN, 0); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- 1 << i2s_data->i2s_pwn_shift, +- 1 << i2s_data->i2s_pwn_shift); ++ ++ mt2701_afe_disable_i2s(afe, i2s_num, stream_dir); ++ + return 0; + } + +@@ -165,7 +156,6 @@ static void mt2701_afe_i2s_shutdown(stru + struct mt2701_afe_private *afe_priv = afe->platform_priv; + int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); + struct mt2701_i2s_path *i2s_path; +- int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num; + + if (i2s_num < 0) + return; +@@ -185,7 +175,7 @@ static void mt2701_afe_i2s_shutdown(stru + + I2S_UNSTART: + /* disable mclk */ +- clk_disable_unprepare(afe_priv->clocks[clk_num]); ++ mt2701_afe_disable_mclk(afe, i2s_num); + } + + static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream, +@@ -251,9 +241,7 @@ static int mt2701_i2s_path_prepare_enabl + fs << i2s_data->i2s_asrc_fs_shift); + + /* enable i2s */ +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- 1 << i2s_data->i2s_pwn_shift, +- 0 << i2s_data->i2s_pwn_shift); ++ mt2701_afe_enable_i2s(afe, i2s_num, stream_dir); + + /* reset i2s hw status before enable */ + regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, +@@ -339,9 +327,11 @@ static int mt2701_btmrg_startup(struct s + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mt2701_afe_private *afe_priv = afe->platform_priv; ++ int ret; + +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_MRGIF, 0); ++ ret = mt2701_enable_btmrg_clk(afe); ++ if (ret) ++ return ret; + + afe_priv->mrg_enable[substream->stream] = 1; + return 0; +@@ -406,9 +396,7 @@ static void mt2701_btmrg_shutdown(struct + AFE_MRGIF_CON_MRG_EN, 0); + regmap_update_bits(afe->regmap, AFE_MRGIF_CON, + AFE_MRGIF_CON_MRG_I2S_EN, 0); +- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, +- AUDIO_TOP_CON4_PDN_MRGIF, +- AUDIO_TOP_CON4_PDN_MRGIF); ++ mt2701_disable_btmrg_clk(afe); + } + afe_priv->mrg_enable[substream->stream] = 0; + } +@@ -1386,14 +1374,12 @@ static const struct mt2701_i2s_data mt27 + { + { + .i2s_ctrl_reg = ASYS_I2SO1_CON, +- .i2s_pwn_shift = 6, + .i2s_asrc_fs_shift = 0, + .i2s_asrc_fs_mask = 0x1f, + + }, + { + .i2s_ctrl_reg = ASYS_I2SIN1_CON, +- .i2s_pwn_shift = 0, + .i2s_asrc_fs_shift = 0, + .i2s_asrc_fs_mask = 0x1f, + +@@ -1402,14 +1388,12 @@ static const struct mt2701_i2s_data mt27 + { + { + .i2s_ctrl_reg = ASYS_I2SO2_CON, +- .i2s_pwn_shift = 7, + .i2s_asrc_fs_shift = 5, + .i2s_asrc_fs_mask = 0x1f, + + }, + { + .i2s_ctrl_reg = ASYS_I2SIN2_CON, +- .i2s_pwn_shift = 1, + .i2s_asrc_fs_shift = 5, + .i2s_asrc_fs_mask = 0x1f, + +@@ -1418,14 +1402,12 @@ static const struct mt2701_i2s_data mt27 + { + { + .i2s_ctrl_reg = ASYS_I2SO3_CON, +- .i2s_pwn_shift = 8, + .i2s_asrc_fs_shift = 10, + .i2s_asrc_fs_mask = 0x1f, + + }, + { + .i2s_ctrl_reg = ASYS_I2SIN3_CON, +- .i2s_pwn_shift = 2, + .i2s_asrc_fs_shift = 10, + .i2s_asrc_fs_mask = 0x1f, + +@@ -1434,14 +1416,12 @@ static const struct mt2701_i2s_data mt27 + { + { + .i2s_ctrl_reg = ASYS_I2SO4_CON, +- .i2s_pwn_shift = 9, + .i2s_asrc_fs_shift = 15, + .i2s_asrc_fs_mask = 0x1f, + + }, + { + .i2s_ctrl_reg = ASYS_I2SIN4_CON, +- .i2s_pwn_shift = 3, + .i2s_asrc_fs_shift = 15, + .i2s_asrc_fs_mask = 0x1f, + +@@ -1483,8 +1463,7 @@ static int mt2701_afe_runtime_suspend(st + { + struct mtk_base_afe *afe = dev_get_drvdata(dev); + +- mt2701_afe_disable_clock(afe); +- return 0; ++ return mt2701_afe_disable_clock(afe); + } + + static int mt2701_afe_runtime_resume(struct device *dev) diff --git a/target/linux/mediatek/patches-4.14/0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch b/target/linux/mediatek/patches-4.14/0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch new file mode 100644 index 000000000..afd535c69 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0182-ASoC-mediatek-cleanup-audio-driver-for-MT2701.patch @@ -0,0 +1,428 @@ +From 4087c924ec899881951b2170a7bb8888747ec532 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 2 Jan 2018 19:47:20 +0800 +Subject: [PATCH 182/224] ASoC: mediatek: cleanup audio driver for MT2701 + +Cleanup unused code such as 'i2s_num' guard, headers, indentation +and some defines. + +Signed-off-by: Ryder Lee +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 14 +--- + sound/soc/mediatek/mt2701/mt2701-afe-common.h | 20 +---- + sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 94 ++++------------------- + sound/soc/mediatek/mt2701/mt2701-reg.h | 41 +--------- + 4 files changed, 24 insertions(+), 145 deletions(-) + +--- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c +@@ -14,10 +14,6 @@ + * GNU General Public License for more details. + */ + +-#include +-#include +-#include +- + #include "mt2701-afe-common.h" + #include "mt2701-afe-clock-ctrl.h" + +@@ -223,8 +219,8 @@ int mt2701_afe_enable_clock(struct mtk_b + } + + regmap_update_bits(afe->regmap, ASYS_TOP_CON, +- AUDIO_TOP_CON0_A1SYS_A2SYS_ON, +- AUDIO_TOP_CON0_A1SYS_A2SYS_ON); ++ ASYS_TOP_CON_ASYS_TIMING_ON, ++ ASYS_TOP_CON_ASYS_TIMING_ON); + regmap_update_bits(afe->regmap, AFE_DAC_CON0, + AFE_DAC_CON0_AFE_ON, + AFE_DAC_CON0_AFE_ON); +@@ -239,7 +235,7 @@ int mt2701_afe_enable_clock(struct mtk_b + int mt2701_afe_disable_clock(struct mtk_base_afe *afe) + { + regmap_update_bits(afe->regmap, ASYS_TOP_CON, +- AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0); ++ ASYS_TOP_CON_ASYS_TIMING_ON, 0); + regmap_update_bits(afe->regmap, AFE_DAC_CON0, + AFE_DAC_CON0_AFE_ON, 0); + +@@ -272,7 +268,3 @@ void mt2701_mclk_configuration(struct mt + if (ret) + dev_err(afe->dev, "failed to set mclk divider %d\n", ret); + } +- +-MODULE_DESCRIPTION("MT2701 afe clock control"); +-MODULE_AUTHOR("Garlic Tseng "); +-MODULE_LICENSE("GPL v2"); +--- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h +@@ -16,6 +16,7 @@ + + #ifndef _MT_2701_AFE_COMMON_H_ + #define _MT_2701_AFE_COMMON_H_ ++ + #include + #include + #include +@@ -25,16 +26,7 @@ + #define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) + #define MT2701_PLL_DOMAIN_0_RATE 98304000 + #define MT2701_PLL_DOMAIN_1_RATE 90316800 +-#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2) +-#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2) +- +-enum { +- MT2701_I2S_1, +- MT2701_I2S_2, +- MT2701_I2S_3, +- MT2701_I2S_4, +- MT2701_I2S_NUM, +-}; ++#define MT2701_I2S_NUM 4 + + enum { + MT2701_MEMIF_DL1, +@@ -62,8 +54,7 @@ enum { + }; + + enum { +- MT2701_IRQ_ASYS_START, +- MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START, ++ MT2701_IRQ_ASYS_IRQ1, + MT2701_IRQ_ASYS_IRQ2, + MT2701_IRQ_ASYS_IRQ3, + MT2701_IRQ_ASYS_END, +@@ -100,9 +91,6 @@ static const unsigned int mt2701_afe_bac + AFE_MEMIF_PBUF_SIZE, + }; + +-struct snd_pcm_substream; +-struct mtk_base_irq_data; +- + struct mt2701_i2s_data { + int i2s_ctrl_reg; + int i2s_asrc_fs_shift; +@@ -120,7 +108,7 @@ struct mt2701_i2s_path { + int mclk_rate; + int on[I2S_DIR_NUM]; + int occupied[I2S_DIR_NUM]; +- const struct mt2701_i2s_data *i2s_data[2]; ++ const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM]; + struct clk *hop_ck[I2S_DIR_NUM]; + struct clk *sel_ck; + struct clk *div_ck; +--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c +@@ -20,16 +20,12 @@ + #include + #include + #include +-#include + + #include "mt2701-afe-common.h" +- + #include "mt2701-afe-clock-ctrl.h" + #include "../common/mtk-afe-platform-driver.h" + #include "../common/mtk-afe-fe-dai.h" + +-#define AFE_IRQ_STATUS_BITS 0xff +- + static const struct snd_pcm_hardware mt2701_afe_hardware = { + .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED + | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID, +@@ -107,21 +103,16 @@ static int mt2701_afe_i2s_startup(struct + + static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai, ++ int i2s_num, + int dir_invert) + { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mt2701_afe_private *afe_priv = afe->platform_priv; +- int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); +- struct mt2701_i2s_path *i2s_path; ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num]; + const struct mt2701_i2s_data *i2s_data; + int stream_dir = substream->stream; + +- if (i2s_num < 0) +- return i2s_num; +- +- i2s_path = &afe_priv->i2s_path[i2s_num]; +- + if (dir_invert) { + if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) + stream_dir = SNDRV_PCM_STREAM_CAPTURE; +@@ -167,11 +158,11 @@ static void mt2701_afe_i2s_shutdown(stru + else + goto I2S_UNSTART; + +- mt2701_afe_i2s_path_shutdown(substream, dai, 0); ++ mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0); + + /* need to disable i2s-out path when disable i2s-in */ + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) +- mt2701_afe_i2s_path_shutdown(substream, dai, 1); ++ mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1); + + I2S_UNSTART: + /* disable mclk */ +@@ -180,24 +171,19 @@ I2S_UNSTART: + + static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai, ++ int i2s_num, + int dir_invert) + { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); + struct mt2701_afe_private *afe_priv = afe->platform_priv; +- int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); +- struct mt2701_i2s_path *i2s_path; ++ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num]; + const struct mt2701_i2s_data *i2s_data; + struct snd_pcm_runtime * const runtime = substream->runtime; + int reg, fs, w_len = 1; /* now we support bck 64bits only */ + int stream_dir = substream->stream; + unsigned int mask = 0, val = 0; + +- if (i2s_num < 0) +- return i2s_num; +- +- i2s_path = &afe_priv->i2s_path[i2s_num]; +- + if (dir_invert) { + if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) + stream_dir = SNDRV_PCM_STREAM_CAPTURE; +@@ -288,13 +274,13 @@ static int mt2701_afe_i2s_prepare(struct + mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { +- mt2701_i2s_path_prepare_enable(substream, dai, 0); ++ mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0); + } else { + /* need to enable i2s-out path when enable i2s-in */ + /* prepare for another direction "out" */ +- mt2701_i2s_path_prepare_enable(substream, dai, 1); ++ mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1); + /* prepare for "in" */ +- mt2701_i2s_path_prepare_enable(substream, dai, 0); ++ mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0); + } + + return 0; +@@ -562,7 +548,6 @@ static const struct snd_soc_dai_ops mt27 + .hw_free = mtk_afe_fe_hw_free, + .prepare = mtk_afe_fe_prepare, + .trigger = mtk_afe_fe_trigger, +- + }; + + static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = { +@@ -903,31 +888,6 @@ static const struct snd_kcontrol_new mt2 + PWR2_TOP_CON, 19, 1, 0), + }; + +-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = { +- SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1, +- 1), +-}; +- +-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = { +- SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1, +- 1), +-}; +- +-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = { +- SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1, +- 1), +-}; +- +-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = { +- SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1, +- 1), +-}; +- +-static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = { +- SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1, +- 1), +-}; +- + static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = { + /* inter-connections */ + SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0), +@@ -987,19 +947,6 @@ static const struct snd_soc_dapm_widget + SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0, + mt2701_afe_multi_ch_out_i2s3, + ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)), +- +- SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0, +- mt2701_afe_multi_ch_out_asrc0, +- ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)), +- SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0, +- mt2701_afe_multi_ch_out_asrc1, +- ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)), +- SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0, +- mt2701_afe_multi_ch_out_asrc2, +- ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)), +- SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0, +- mt2701_afe_multi_ch_out_asrc3, +- ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)), + }; + + static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { +@@ -1009,7 +956,6 @@ static const struct snd_soc_dapm_route m + + {"I2S0 Playback", NULL, "O15"}, + {"I2S0 Playback", NULL, "O16"}, +- + {"I2S1 Playback", NULL, "O17"}, + {"I2S1 Playback", NULL, "O18"}, + {"I2S2 Playback", NULL, "O19"}, +@@ -1026,7 +972,6 @@ static const struct snd_soc_dapm_route m + + {"I00", NULL, "I2S0 Capture"}, + {"I01", NULL, "I2S0 Capture"}, +- + {"I02", NULL, "I2S1 Capture"}, + {"I03", NULL, "I2S1 Capture"}, + /* I02,03 link to UL2, also need to open I2S0 */ +@@ -1034,15 +979,10 @@ static const struct snd_soc_dapm_route m + + {"I26", NULL, "BT Capture"}, + +- {"ASRC_O0", "Asrc0 out Switch", "DLM"}, +- {"ASRC_O1", "Asrc1 out Switch", "DLM"}, +- {"ASRC_O2", "Asrc2 out Switch", "DLM"}, +- {"ASRC_O3", "Asrc3 out Switch", "DLM"}, +- +- {"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"}, +- {"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"}, +- {"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"}, +- {"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"}, ++ {"I12I13", "Multich I2S0 Out Switch", "DLM"}, ++ {"I14I15", "Multich I2S1 Out Switch", "DLM"}, ++ {"I16I17", "Multich I2S2 Out Switch", "DLM"}, ++ {"I18I19", "Multich I2S3 Out Switch", "DLM"}, + + { "I12", NULL, "I12I13" }, + { "I13", NULL, "I12I13" }, +@@ -1067,7 +1007,6 @@ static const struct snd_soc_dapm_route m + { "O21", "I18 Switch", "I18" }, + { "O22", "I19 Switch", "I19" }, + { "O31", "I35 Switch", "I35" }, +- + }; + + static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = { +@@ -1484,12 +1423,13 @@ static int mt2701_afe_pcm_dev_probe(stru + afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); + if (!afe) + return -ENOMEM; ++ + afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), + GFP_KERNEL); + if (!afe->platform_priv) + return -ENOMEM; +- afe_priv = afe->platform_priv; + ++ afe_priv = afe->platform_priv; + afe->dev = &pdev->dev; + dev = afe->dev; + +@@ -1524,7 +1464,6 @@ static int mt2701_afe_pcm_dev_probe(stru + afe->memif_size = MT2701_MEMIF_NUM; + afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), + GFP_KERNEL); +- + if (!afe->memif) + return -ENOMEM; + +@@ -1537,7 +1476,6 @@ static int mt2701_afe_pcm_dev_probe(stru + afe->irqs_size = MT2701_IRQ_ASYS_END; + afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), + GFP_KERNEL); +- + if (!afe->irqs) + return -ENOMEM; + +@@ -1555,7 +1493,6 @@ static int mt2701_afe_pcm_dev_probe(stru + afe->mtk_afe_hardware = &mt2701_afe_hardware; + afe->memif_fs = mt2701_memif_fs; + afe->irq_fs = mt2701_irq_fs; +- + afe->reg_back_up_list = mt2701_afe_backup_list; + afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list); + afe->runtime_resume = mt2701_afe_runtime_resume; +@@ -1646,4 +1583,3 @@ module_platform_driver(mt2701_afe_pcm_dr + MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701"); + MODULE_AUTHOR("Garlic Tseng "); + MODULE_LICENSE("GPL v2"); +- +--- a/sound/soc/mediatek/mt2701/mt2701-reg.h ++++ b/sound/soc/mediatek/mt2701/mt2701-reg.h +@@ -17,17 +17,6 @@ + #ifndef _MT2701_REG_H_ + #define _MT2701_REG_H_ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include "mt2701-afe-common.h" +- +-/***************************************************************************** +- * R E G I S T E R D E F I N I T I O N +- *****************************************************************************/ + #define AUDIO_TOP_CON0 0x0000 + #define AUDIO_TOP_CON4 0x0010 + #define AUDIO_TOP_CON5 0x0014 +@@ -109,18 +98,6 @@ + #define AFE_DAI_BASE 0x1370 + #define AFE_DAI_CUR 0x137c + +-/* AUDIO_TOP_CON0 (0x0000) */ +-#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0) +-#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2) +-#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23) +- +-/* AUDIO_TOP_CON4 (0x0010) */ +-#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6) +-#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21) +-#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22) +-#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23) +-#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25) +- + /* AFE_DAIBT_CON0 (0x001c) */ + #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) + #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) +@@ -137,22 +114,8 @@ + #define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) + #define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) + +-/* ASYS_I2SO1_CON (0x061c) */ +-#define ASYS_I2SO1_CON_FS (0x1f << 8) +-#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8) +-#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16) +-#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30) +-#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0) +-/* 0:EIAJ 1:I2S */ +-#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3) +-#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1) +-#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1) +- +-/* PWR2_TOP_CON (0x0634) */ +-#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff) +- +-/* ASYS_IRQ_CLR (0x07c0) */ +-#define ASYS_IRQ_CLR_ALL (0xffffffff) ++/* ASYS_TOP_CON (0x0600) */ ++#define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0) + + /* PWR2_ASM_CON1 (0x1070) */ + #define PWR2_ASM_CON1_INIT_VAL (0x492492) diff --git a/target/linux/mediatek/patches-4.14/0183-ASoC-mediatek-update-clock-related-properties-of-MT2.patch b/target/linux/mediatek/patches-4.14/0183-ASoC-mediatek-update-clock-related-properties-of-MT2.patch new file mode 100644 index 000000000..cfb0e47e0 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0183-ASoC-mediatek-update-clock-related-properties-of-MT2.patch @@ -0,0 +1,258 @@ +From d5b391bb7208c8a7b6b874c1357d3cd110537167 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 2 Jan 2018 19:47:21 +0800 +Subject: [PATCH 183/224] ASoC: mediatek: update clock related properties of + MT2701 AFE + +Add 'assigned-clocks*' properties which are used to initialize default +domain sources of audio system. we could configure different sets of +input clocks through DTS now. Hence driver no longer cares about that. + +Also we change some 'clock-names' to make them more generic so that +other chips can reuse gracefully. + +Signed-off-by: Ryder Lee +Signed-off-by: Mark Brown +--- + .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 207 +++++++++------------ + 1 file changed, 91 insertions(+), 116 deletions(-) + +--- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt ++++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt +@@ -6,51 +6,44 @@ Required properties: + - interrupts: should contain AFE and ASYS interrupts + - interrupt-names: should be "afe" and "asys" + - power-domains: should define the power domain ++- clocks: Must contain an entry for each entry in clock-names ++ See ../clocks/clock-bindings.txt for details + - clock-names: should have these clock names: +- "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", +- "top_audio_mux1_div", +- "top_audio_mux2_div", +- "top_audio_48k_timing", +- "top_audio_44k_timing", +- "top_audpll_mux_sel", +- "top_apll_sel", +- "top_aud1_pll_98M", +- "top_aud2_pll_90M", +- "top_hadds2_pll_98M", +- "top_hadds2_pll_294M", +- "top_audpll", +- "top_audpll_d4", +- "top_audpll_d8", +- "top_audpll_d16", +- "top_audpll_d24", +- "top_audintbus_sel", +- "clk_26m", +- "top_syspll1_d4", +- "top_aud_k1_src_sel", +- "top_aud_k2_src_sel", +- "top_aud_k3_src_sel", +- "top_aud_k4_src_sel", +- "top_aud_k5_src_sel", +- "top_aud_k6_src_sel", +- "top_aud_k1_src_div", +- "top_aud_k2_src_div", +- "top_aud_k3_src_div", +- "top_aud_k4_src_div", +- "top_aud_k5_src_div", +- "top_aud_k6_src_div", +- "top_aud_i2s1_mclk", +- "top_aud_i2s2_mclk", +- "top_aud_i2s3_mclk", +- "top_aud_i2s4_mclk", +- "top_aud_i2s5_mclk", +- "top_aud_i2s6_mclk", +- "top_asm_m_sel", +- "top_asm_h_sel", +- "top_univpll2_d4", +- "top_univpll2_d2", +- "top_syspll_d5"; ++ "i2s0_src_sel", ++ "i2s1_src_sel", ++ "i2s2_src_sel", ++ "i2s3_src_sel", ++ "i2s0_src_div", ++ "i2s1_src_div", ++ "i2s2_src_div", ++ "i2s3_src_div", ++ "i2s0_mclk_en", ++ "i2s1_mclk_en", ++ "i2s2_mclk_en", ++ "i2s3_mclk_en", ++ "i2so0_hop_ck", ++ "i2so1_hop_ck", ++ "i2so2_hop_ck", ++ "i2so3_hop_ck", ++ "i2si0_hop_ck", ++ "i2si1_hop_ck", ++ "i2si2_hop_ck", ++ "i2si3_hop_ck", ++ "asrc0_out_ck", ++ "asrc1_out_ck", ++ "asrc2_out_ck", ++ "asrc3_out_ck", ++ "audio_afe_pd", ++ "audio_afe_conn_pd", ++ "audio_a1sys_pd", ++ "audio_a2sys_pd", ++ "audio_mrgif_pd"; ++- assigned-clocks: list of input clocks and dividers for the audio system. ++ See ../clocks/clock-bindings.txt for details. ++- assigned-clocks-parents: parent of input clocks of assigned clocks. ++- assigned-clock-rates: list of clock frequencies of assigned clocks. + + Example: + +@@ -62,93 +55,75 @@ Example: + ; + interrupt-names = "afe", "asys"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- clocks = <&infracfg CLK_INFRA_AUDIO>, +- <&topckgen CLK_TOP_AUD_MUX1_SEL>, ++ clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_MUX1_DIV>, +- <&topckgen CLK_TOP_AUD_MUX2_DIV>, +- <&topckgen CLK_TOP_AUD_48K_TIMING>, +- <&topckgen CLK_TOP_AUD_44K_TIMING>, +- <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, +- <&topckgen CLK_TOP_APLL_SEL>, +- <&topckgen CLK_TOP_AUD1PLL_98M>, +- <&topckgen CLK_TOP_AUD2PLL_90M>, +- <&topckgen CLK_TOP_HADDS2PLL_98M>, +- <&topckgen CLK_TOP_HADDS2PLL_294M>, +- <&topckgen CLK_TOP_AUDPLL>, +- <&topckgen CLK_TOP_AUDPLL_D4>, +- <&topckgen CLK_TOP_AUDPLL_D8>, +- <&topckgen CLK_TOP_AUDPLL_D16>, +- <&topckgen CLK_TOP_AUDPLL_D24>, +- <&topckgen CLK_TOP_AUDINTBUS_SEL>, +- <&clk26m>, +- <&topckgen CLK_TOP_SYSPLL1_D4>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S5_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S6_MCLK>, +- <&topckgen CLK_TOP_ASM_M_SEL>, +- <&topckgen CLK_TOP_ASM_H_SEL>, +- <&topckgen CLK_TOP_UNIVPLL2_D4>, +- <&topckgen CLK_TOP_UNIVPLL2_D2>, +- <&topckgen CLK_TOP_SYSPLL_D5>; ++ <&audiosys CLK_AUD_I2SO1>, ++ <&audiosys CLK_AUD_I2SO2>, ++ <&audiosys CLK_AUD_I2SO3>, ++ <&audiosys CLK_AUD_I2SO4>, ++ <&audiosys CLK_AUD_I2SIN1>, ++ <&audiosys CLK_AUD_I2SIN2>, ++ <&audiosys CLK_AUD_I2SIN3>, ++ <&audiosys CLK_AUD_I2SIN4>, ++ <&audiosys CLK_AUD_ASRCO1>, ++ <&audiosys CLK_AUD_ASRCO2>, ++ <&audiosys CLK_AUD_ASRCO3>, ++ <&audiosys CLK_AUD_ASRCO4>, ++ <&audiosys CLK_AUD_AFE>, ++ <&audiosys CLK_AUD_AFE_CONN>, ++ <&audiosys CLK_AUD_A1SYS>, ++ <&audiosys CLK_AUD_A2SYS>, ++ <&audiosys CLK_AUD_AFE_MRGIF>; + +- clock-names = "infra_sys_audio_clk", +- "top_audio_mux1_sel", ++ clock-names = "top_audio_mux1_sel", + "top_audio_mux2_sel", +- "top_audio_mux1_div", +- "top_audio_mux2_div", +- "top_audio_48k_timing", +- "top_audio_44k_timing", +- "top_audpll_mux_sel", +- "top_apll_sel", +- "top_aud1_pll_98M", +- "top_aud2_pll_90M", +- "top_hadds2_pll_98M", +- "top_hadds2_pll_294M", +- "top_audpll", +- "top_audpll_d4", +- "top_audpll_d8", +- "top_audpll_d16", +- "top_audpll_d24", +- "top_audintbus_sel", +- "clk_26m", +- "top_syspll1_d4", +- "top_aud_k1_src_sel", +- "top_aud_k2_src_sel", +- "top_aud_k3_src_sel", +- "top_aud_k4_src_sel", +- "top_aud_k5_src_sel", +- "top_aud_k6_src_sel", +- "top_aud_k1_src_div", +- "top_aud_k2_src_div", +- "top_aud_k3_src_div", +- "top_aud_k4_src_div", +- "top_aud_k5_src_div", +- "top_aud_k6_src_div", +- "top_aud_i2s1_mclk", +- "top_aud_i2s2_mclk", +- "top_aud_i2s3_mclk", +- "top_aud_i2s4_mclk", +- "top_aud_i2s5_mclk", +- "top_aud_i2s6_mclk", +- "top_asm_m_sel", +- "top_asm_h_sel", +- "top_univpll2_d4", +- "top_univpll2_d2", +- "top_syspll_d5"; ++ "i2s0_src_sel", ++ "i2s1_src_sel", ++ "i2s2_src_sel", ++ "i2s3_src_sel", ++ "i2s0_src_div", ++ "i2s1_src_div", ++ "i2s2_src_div", ++ "i2s3_src_div", ++ "i2s0_mclk_en", ++ "i2s1_mclk_en", ++ "i2s2_mclk_en", ++ "i2s3_mclk_en", ++ "i2so0_hop_ck", ++ "i2so1_hop_ck", ++ "i2so2_hop_ck", ++ "i2so3_hop_ck", ++ "i2si0_hop_ck", ++ "i2si1_hop_ck", ++ "i2si2_hop_ck", ++ "i2si3_hop_ck", ++ "asrc0_out_ck", ++ "asrc1_out_ck", ++ "asrc2_out_ck", ++ "asrc3_out_ck", ++ "audio_afe_pd", ++ "audio_afe_conn_pd", ++ "audio_a1sys_pd", ++ "audio_a2sys_pd", ++ "audio_mrgif_pd"; ++ ++ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, ++ <&topckgen CLK_TOP_AUD_MUX2_SEL>, ++ <&topckgen CLK_TOP_AUD_MUX1_DIV>, ++ <&topckgen CLK_TOP_AUD_MUX2_DIV>; ++ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, ++ <&topckgen CLK_TOP_AUD2PLL_90M>; ++ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; diff --git a/target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch b/target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch new file mode 100644 index 000000000..937232ed1 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch @@ -0,0 +1,93 @@ +From e0e3768b73daae674c69db1f71718894274b7bfc Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Thu, 4 Jan 2018 15:44:07 +0800 +Subject: [PATCH 184/224] ASoC: mediatek: add some core clocks for MT2701 AFE + +Add three core clocks for MT2701 AFE. + +Signed-off-by: Ryder Lee +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 30 ++++++++++++++++++++++- + sound/soc/mediatek/mt2701/mt2701-afe-common.h | 3 +++ + 2 files changed, 32 insertions(+), 1 deletion(-) + +--- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c +@@ -18,8 +18,11 @@ + #include "mt2701-afe-clock-ctrl.h" + + static const char *const base_clks[] = { ++ [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk", + [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel", + [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel", ++ [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp", ++ [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp", + [MT2701_AUDSYS_AFE] = "audio_afe_pd", + [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd", + [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd", +@@ -169,10 +172,26 @@ static int mt2701_afe_enable_audsys(stru + struct mt2701_afe_private *afe_priv = afe->platform_priv; + int ret; + +- ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]); ++ /* Enable infra clock gate */ ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]); + if (ret) + return ret; + ++ /* Enable top a1sys clock gate */ ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]); ++ if (ret) ++ goto err_a1sys; ++ ++ /* Enable top a2sys clock gate */ ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]); ++ if (ret) ++ goto err_a2sys; ++ ++ /* Internal clock gates */ ++ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]); ++ if (ret) ++ goto err_afe; ++ + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); + if (ret) + goto err_audio_a1sys; +@@ -193,6 +212,12 @@ err_audio_a2sys: + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); + err_audio_a1sys: + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]); ++err_afe: ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]); ++err_a2sys: ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]); ++err_a1sys: ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]); + + return ret; + } +@@ -205,6 +230,9 @@ static void mt2701_afe_disable_audsys(st + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]); + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]); + clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]); ++ clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]); + } + + int mt2701_afe_enable_clock(struct mtk_base_afe *afe) +--- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h +@@ -61,8 +61,11 @@ enum { + }; + + enum audio_base_clock { ++ MT2701_INFRA_SYS_AUDIO, + MT2701_TOP_AUD_MCLK_SRC0, + MT2701_TOP_AUD_MCLK_SRC1, ++ MT2701_TOP_AUD_A1SYS, ++ MT2701_TOP_AUD_A2SYS, + MT2701_AUDSYS_AFE, + MT2701_AUDSYS_AFE_CONN, + MT2701_AUDSYS_A1SYS, diff --git a/target/linux/mediatek/patches-4.14/0185-ASoC-mediatek-modify-MT2701-AFE-driver-to-adapt-mfd-.patch b/target/linux/mediatek/patches-4.14/0185-ASoC-mediatek-modify-MT2701-AFE-driver-to-adapt-mfd-.patch new file mode 100644 index 000000000..462cbbc13 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0185-ASoC-mediatek-modify-MT2701-AFE-driver-to-adapt-mfd-.patch @@ -0,0 +1,128 @@ +From 310ca2954c7cce10d716001ff869bc255494e3df Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Thu, 4 Jan 2018 15:44:08 +0800 +Subject: [PATCH 185/224] ASoC: mediatek: modify MT2701 AFE driver to adapt mfd + device + +As the new MFD parent is in place, modify MT2701 AFE driver to adapt it. + +Signed-off-by: Ryder Lee +Signed-off-by: Mark Brown +--- + sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 45 +++++++++++++----------------- + sound/soc/mediatek/mt2701/mt2701-reg.h | 1 - + 2 files changed, 20 insertions(+), 26 deletions(-) + +--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c ++++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c +@@ -17,6 +17,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -1368,14 +1369,6 @@ static const struct mt2701_i2s_data mt27 + }, + }; + +-static const struct regmap_config mt2701_afe_regmap_config = { +- .reg_bits = 32, +- .reg_stride = 4, +- .val_bits = 32, +- .max_register = AFE_END_ADDR, +- .cache_type = REGCACHE_NONE, +-}; +- + static irqreturn_t mt2701_asys_isr(int irq_id, void *dev) + { + int id; +@@ -1414,9 +1407,9 @@ static int mt2701_afe_runtime_resume(str + + static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) + { ++ struct snd_soc_component *component; + struct mtk_base_afe *afe; + struct mt2701_afe_private *afe_priv; +- struct resource *res; + struct device *dev; + int i, irq_id, ret; + +@@ -1446,17 +1439,11 @@ static int mt2701_afe_pcm_dev_probe(stru + return ret; + } + +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- +- afe->base_addr = devm_ioremap_resource(&pdev->dev, res); +- +- if (IS_ERR(afe->base_addr)) +- return PTR_ERR(afe->base_addr); +- +- afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, +- &mt2701_afe_regmap_config); +- if (IS_ERR(afe->regmap)) +- return PTR_ERR(afe->regmap); ++ afe->regmap = syscon_node_to_regmap(dev->parent->of_node); ++ if (!afe->regmap) { ++ dev_err(dev, "could not get regmap from parent\n"); ++ return -ENODEV; ++ } + + mutex_init(&afe->irq_alloc_lock); + +@@ -1490,6 +1477,12 @@ static int mt2701_afe_pcm_dev_probe(stru + = &mt2701_i2s_data[i][I2S_IN]; + } + ++ component = kzalloc(sizeof(*component), GFP_KERNEL); ++ if (!component) ++ return -ENOMEM; ++ ++ component->regmap = afe->regmap; ++ + afe->mtk_afe_hardware = &mt2701_afe_hardware; + afe->memif_fs = mt2701_memif_fs; + afe->irq_fs = mt2701_irq_fs; +@@ -1502,7 +1495,7 @@ static int mt2701_afe_pcm_dev_probe(stru + ret = mt2701_init_clock(afe); + if (ret) { + dev_err(dev, "init clock error\n"); +- return ret; ++ goto err_init_clock; + } + + platform_set_drvdata(pdev, afe); +@@ -1521,10 +1514,10 @@ static int mt2701_afe_pcm_dev_probe(stru + goto err_platform; + } + +- ret = snd_soc_register_component(&pdev->dev, +- &mt2701_afe_pcm_dai_component, +- mt2701_afe_pcm_dais, +- ARRAY_SIZE(mt2701_afe_pcm_dais)); ++ ret = snd_soc_add_component(dev, component, ++ &mt2701_afe_pcm_dai_component, ++ mt2701_afe_pcm_dais, ++ ARRAY_SIZE(mt2701_afe_pcm_dais)); + if (ret) { + dev_warn(dev, "err_dai_component\n"); + goto err_dai_component; +@@ -1538,6 +1531,8 @@ err_platform: + pm_runtime_put_sync(dev); + err_pm_disable: + pm_runtime_disable(dev); ++err_init_clock: ++ kfree(component); + + return ret; + } +--- a/sound/soc/mediatek/mt2701/mt2701-reg.h ++++ b/sound/soc/mediatek/mt2701/mt2701-reg.h +@@ -145,5 +145,4 @@ + #define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) + #define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) + +-#define AFE_END_ADDR 0x15e0 + #endif diff --git a/target/linux/mediatek/patches-4.14/0186-ASoC-mediatek-update-MT2701-AFE-documentation-to-ada.patch b/target/linux/mediatek/patches-4.14/0186-ASoC-mediatek-update-MT2701-AFE-documentation-to-ada.patch new file mode 100644 index 000000000..87a6158b4 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0186-ASoC-mediatek-update-MT2701-AFE-documentation-to-ada.patch @@ -0,0 +1,214 @@ +From 018219d340c0f7a10098683b8a4733618ea76ba3 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Thu, 4 Jan 2018 15:44:09 +0800 +Subject: [PATCH 186/224] ASoC: mediatek: update MT2701 AFE documentation to + adapt mfd device + +As the new MFD parent is in place, modify MT2701 AFE documentation to +adapt it. Also add three core clocks in example. + +Signed-off-by: Ryder Lee +Signed-off-by: Mark Brown +--- + .../devicetree/bindings/sound/mt2701-afe-pcm.txt | 171 +++++++++++---------- + 1 file changed, 93 insertions(+), 78 deletions(-) + +--- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt ++++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt +@@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701 + + Required properties: + - compatible = "mediatek,mt2701-audio"; +-- reg: register location and size + - interrupts: should contain AFE and ASYS interrupts + - interrupt-names: should be "afe" and "asys" + - power-domains: should define the power domain + - clocks: Must contain an entry for each entry in clock-names + See ../clocks/clock-bindings.txt for details + - clock-names: should have these clock names: ++ "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", ++ "top_audio_a1sys_hp", ++ "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", +@@ -45,85 +47,98 @@ Required properties: + - assigned-clocks-parents: parent of input clocks of assigned clocks. + - assigned-clock-rates: list of clock frequencies of assigned clocks. + ++Must be a subnode of MediaTek audsys device tree node. ++See ../arm/mediatek/mediatek,audsys.txt for details about the parent node. ++ + Example: + +- afe: mt2701-afe-pcm@11220000 { +- compatible = "mediatek,mt2701-audio"; +- reg = <0 0x11220000 0 0x2000>, +- <0 0x112A0000 0 0x20000>; +- interrupts = , +- ; +- interrupt-names = "afe", "asys"; +- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; +- clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, +- <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, +- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, +- <&topckgen CLK_TOP_AUD_I2S1_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S2_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S3_MCLK>, +- <&topckgen CLK_TOP_AUD_I2S4_MCLK>, +- <&audiosys CLK_AUD_I2SO1>, +- <&audiosys CLK_AUD_I2SO2>, +- <&audiosys CLK_AUD_I2SO3>, +- <&audiosys CLK_AUD_I2SO4>, +- <&audiosys CLK_AUD_I2SIN1>, +- <&audiosys CLK_AUD_I2SIN2>, +- <&audiosys CLK_AUD_I2SIN3>, +- <&audiosys CLK_AUD_I2SIN4>, +- <&audiosys CLK_AUD_ASRCO1>, +- <&audiosys CLK_AUD_ASRCO2>, +- <&audiosys CLK_AUD_ASRCO3>, +- <&audiosys CLK_AUD_ASRCO4>, +- <&audiosys CLK_AUD_AFE>, +- <&audiosys CLK_AUD_AFE_CONN>, +- <&audiosys CLK_AUD_A1SYS>, +- <&audiosys CLK_AUD_A2SYS>, +- <&audiosys CLK_AUD_AFE_MRGIF>; +- +- clock-names = "top_audio_mux1_sel", +- "top_audio_mux2_sel", +- "i2s0_src_sel", +- "i2s1_src_sel", +- "i2s2_src_sel", +- "i2s3_src_sel", +- "i2s0_src_div", +- "i2s1_src_div", +- "i2s2_src_div", +- "i2s3_src_div", +- "i2s0_mclk_en", +- "i2s1_mclk_en", +- "i2s2_mclk_en", +- "i2s3_mclk_en", +- "i2so0_hop_ck", +- "i2so1_hop_ck", +- "i2so2_hop_ck", +- "i2so3_hop_ck", +- "i2si0_hop_ck", +- "i2si1_hop_ck", +- "i2si2_hop_ck", +- "i2si3_hop_ck", +- "asrc0_out_ck", +- "asrc1_out_ck", +- "asrc2_out_ck", +- "asrc3_out_ck", +- "audio_afe_pd", +- "audio_afe_conn_pd", +- "audio_a1sys_pd", +- "audio_a2sys_pd", +- "audio_mrgif_pd"; +- +- assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, +- <&topckgen CLK_TOP_AUD_MUX2_SEL>, +- <&topckgen CLK_TOP_AUD_MUX1_DIV>, +- <&topckgen CLK_TOP_AUD_MUX2_DIV>; +- assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, +- <&topckgen CLK_TOP_AUD2PLL_90M>; +- assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; ++ audsys: audio-subsystem@11220000 { ++ compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd"; ++ ... ++ ++ afe: audio-controller { ++ compatible = "mediatek,mt2701-audio"; ++ interrupts = , ++ ; ++ interrupt-names = "afe", "asys"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; ++ ++ clocks = <&infracfg CLK_INFRA_AUDIO>, ++ <&topckgen CLK_TOP_AUD_MUX1_SEL>, ++ <&topckgen CLK_TOP_AUD_MUX2_SEL>, ++ <&topckgen CLK_TOP_AUD_48K_TIMING>, ++ <&topckgen CLK_TOP_AUD_44K_TIMING>, ++ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, ++ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, ++ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, ++ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, ++ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, ++ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, ++ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, ++ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, ++ <&topckgen CLK_TOP_AUD_I2S1_MCLK>, ++ <&topckgen CLK_TOP_AUD_I2S2_MCLK>, ++ <&topckgen CLK_TOP_AUD_I2S3_MCLK>, ++ <&topckgen CLK_TOP_AUD_I2S4_MCLK>, ++ <&audsys CLK_AUD_I2SO1>, ++ <&audsys CLK_AUD_I2SO2>, ++ <&audsys CLK_AUD_I2SO3>, ++ <&audsys CLK_AUD_I2SO4>, ++ <&audsys CLK_AUD_I2SIN1>, ++ <&audsys CLK_AUD_I2SIN2>, ++ <&audsys CLK_AUD_I2SIN3>, ++ <&audsys CLK_AUD_I2SIN4>, ++ <&audsys CLK_AUD_ASRCO1>, ++ <&audsys CLK_AUD_ASRCO2>, ++ <&audsys CLK_AUD_ASRCO3>, ++ <&audsys CLK_AUD_ASRCO4>, ++ <&audsys CLK_AUD_AFE>, ++ <&audsys CLK_AUD_AFE_CONN>, ++ <&audsys CLK_AUD_A1SYS>, ++ <&audsys CLK_AUD_A2SYS>, ++ <&audsys CLK_AUD_AFE_MRGIF>; ++ ++ clock-names = "infra_sys_audio_clk", ++ "top_audio_mux1_sel", ++ "top_audio_mux2_sel", ++ "top_audio_a1sys_hp", ++ "top_audio_a2sys_hp", ++ "i2s0_src_sel", ++ "i2s1_src_sel", ++ "i2s2_src_sel", ++ "i2s3_src_sel", ++ "i2s0_src_div", ++ "i2s1_src_div", ++ "i2s2_src_div", ++ "i2s3_src_div", ++ "i2s0_mclk_en", ++ "i2s1_mclk_en", ++ "i2s2_mclk_en", ++ "i2s3_mclk_en", ++ "i2so0_hop_ck", ++ "i2so1_hop_ck", ++ "i2so2_hop_ck", ++ "i2so3_hop_ck", ++ "i2si0_hop_ck", ++ "i2si1_hop_ck", ++ "i2si2_hop_ck", ++ "i2si3_hop_ck", ++ "asrc0_out_ck", ++ "asrc1_out_ck", ++ "asrc2_out_ck", ++ "asrc3_out_ck", ++ "audio_afe_pd", ++ "audio_afe_conn_pd", ++ "audio_a1sys_pd", ++ "audio_a2sys_pd", ++ "audio_mrgif_pd"; ++ ++ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, ++ <&topckgen CLK_TOP_AUD_MUX2_SEL>, ++ <&topckgen CLK_TOP_AUD_MUX1_DIV>, ++ <&topckgen CLK_TOP_AUD_MUX2_DIV>; ++ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, ++ <&topckgen CLK_TOP_AUD2PLL_90M>; ++ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; ++ }; + }; diff --git a/target/linux/mediatek/patches-4.14/0187-usb-mtu3-fix-error-code-for-getting-extcon-device.patch b/target/linux/mediatek/patches-4.14/0187-usb-mtu3-fix-error-code-for-getting-extcon-device.patch new file mode 100644 index 000000000..2a105eb66 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0187-usb-mtu3-fix-error-code-for-getting-extcon-device.patch @@ -0,0 +1,26 @@ +From 3d5564bbc0a39ba07d1bbdaec1f69a3d39c4495e Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 3 Jan 2018 16:53:17 +0800 +Subject: [PATCH 187/224] usb: mtu3: fix error code for getting extcon device + +When failing to get extcon device, extcon_get_edev_by_phandle() +may return different error codes, but not only -EPROBE_DEFER, +so can't always return -EPROBE_DEFER, and fix it. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/mtu3/mtu3_plat.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -317,7 +317,7 @@ static int get_ssusb_rscs(struct platfor + otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0); + if (IS_ERR(otg_sx->edev)) { + dev_err(ssusb->dev, "couldn't get extcon device\n"); +- return -EPROBE_DEFER; ++ return PTR_ERR(otg_sx->edev); + } + } + diff --git a/target/linux/mediatek/patches-4.14/0188-usb-mtu3-supports-remote-wakeup-for-mt2712-with-two-.patch b/target/linux/mediatek/patches-4.14/0188-usb-mtu3-supports-remote-wakeup-for-mt2712-with-two-.patch new file mode 100644 index 000000000..2e3f0bd12 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0188-usb-mtu3-supports-remote-wakeup-for-mt2712-with-two-.patch @@ -0,0 +1,233 @@ +From 354655aaf0f71ce2b567cbc02afb0664c99e434e Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 3 Jan 2018 16:53:18 +0800 +Subject: [PATCH 188/224] usb: mtu3: supports remote wakeup for mt2712 with two + SSUSB IPs + +The old way of usb wakeup only supports platform with single SSUSB IP, +such as mt8173, but mt2712 has two SSUSB IPs, so rebuild its flow and +also supports the new glue layer of usb wakeup on mt2712 which is +different from mt8173. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/mtu3/mtu3.h | 11 +++-- + drivers/usb/mtu3/mtu3_dr.h | 3 +- + drivers/usb/mtu3/mtu3_host.c | 115 +++++++++++++++++++++---------------------- + drivers/usb/mtu3/mtu3_plat.c | 8 +-- + 4 files changed, 70 insertions(+), 67 deletions(-) + +--- a/drivers/usb/mtu3/mtu3.h ++++ b/drivers/usb/mtu3/mtu3.h +@@ -238,7 +238,10 @@ struct otg_switch_mtk { + * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to + * disable u3port0, bit1==1 to disable u3port1,... etc + * @dbgfs_root: only used when supports manual dual-role switch via debugfs +- * @wakeup_en: it's true when supports remote wakeup in host mode ++ * @uwk_en: it's true when supports remote wakeup in host mode ++ * @uwk: syscon including usb wakeup glue layer between SSUSB IP and SPM ++ * @uwk_reg_base: the base address of the wakeup glue layer in @uwk ++ * @uwk_vers: the version of the wakeup glue layer + */ + struct ssusb_mtk { + struct device *dev; +@@ -262,8 +265,10 @@ struct ssusb_mtk { + int u3p_dis_msk; + struct dentry *dbgfs_root; + /* usb wakeup for host mode */ +- bool wakeup_en; +- struct regmap *pericfg; ++ bool uwk_en; ++ struct regmap *uwk; ++ u32 uwk_reg_base; ++ u32 uwk_vers; + }; + + /** +--- a/drivers/usb/mtu3/mtu3_dr.h ++++ b/drivers/usb/mtu3/mtu3_dr.h +@@ -27,8 +27,7 @@ int ssusb_wakeup_of_property_parse(struc + struct device_node *dn); + int ssusb_host_enable(struct ssusb_mtk *ssusb); + int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend); +-int ssusb_wakeup_enable(struct ssusb_mtk *ssusb); +-void ssusb_wakeup_disable(struct ssusb_mtk *ssusb); ++void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable); + + #else + +--- a/drivers/usb/mtu3/mtu3_host.c ++++ b/drivers/usb/mtu3/mtu3_host.c +@@ -27,66 +27,77 @@ + #include "mtu3.h" + #include "mtu3_dr.h" + +-#define PERI_WK_CTRL1 0x404 +-#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26) +-#define UWK_CTL1_IS_E BIT(25) +-#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */ +-#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */ +-#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */ +-#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */ ++/* mt8173 etc */ ++#define PERI_WK_CTRL1 0x4 ++#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ ++#define WC1_IS_EN BIT(25) ++#define WC1_IS_P BIT(6) /* polarity for ip sleep */ ++ ++/* mt2712 etc */ ++#define PERI_SSUSB_SPM_CTRL 0x0 ++#define SSC_IP_SLEEP_EN BIT(4) ++#define SSC_SPM_INT_EN BIT(1) ++ ++enum ssusb_uwk_vers { ++ SSUSB_UWK_V1 = 1, ++ SSUSB_UWK_V2, ++}; + + /* + * ip-sleep wakeup mode: + * all clocks can be turn off, but power domain should be kept on + */ +-static void ssusb_wakeup_ip_sleep_en(struct ssusb_mtk *ssusb) ++static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable) + { +- u32 tmp; +- struct regmap *pericfg = ssusb->pericfg; ++ u32 reg, msk, val; + +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- tmp &= ~UWK_CTL1_IS_P; +- tmp &= ~(UWK_CTL1_IS_C(0xf)); +- tmp |= UWK_CTL1_IS_C(0x8); +- regmap_write(pericfg, PERI_WK_CTRL1, tmp); +- regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E); +- +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- dev_dbg(ssusb->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", +- __func__, tmp); +-} +- +-static void ssusb_wakeup_ip_sleep_dis(struct ssusb_mtk *ssusb) +-{ +- u32 tmp; +- +- regmap_read(ssusb->pericfg, PERI_WK_CTRL1, &tmp); +- tmp &= ~UWK_CTL1_IS_E; +- regmap_write(ssusb->pericfg, PERI_WK_CTRL1, tmp); ++ switch (ssusb->uwk_vers) { ++ case SSUSB_UWK_V1: ++ reg = ssusb->uwk_reg_base + PERI_WK_CTRL1; ++ msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; ++ val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; ++ break; ++ case SSUSB_UWK_V2: ++ reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL; ++ msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; ++ val = enable ? msk : 0; ++ break; ++ default: ++ return; ++ }; ++ regmap_update_bits(ssusb->uwk, reg, msk, val); + } + + int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb, + struct device_node *dn) + { +- struct device *dev = ssusb->dev; ++ struct of_phandle_args args; ++ int ret; + +- /* +- * Wakeup function is optional, so it is not an error if this property +- * does not exist, and in such case, no need to get relative +- * properties anymore. +- */ +- ssusb->wakeup_en = of_property_read_bool(dn, "mediatek,enable-wakeup"); +- if (!ssusb->wakeup_en) ++ /* wakeup function is optional */ ++ ssusb->uwk_en = of_property_read_bool(dn, "wakeup-source"); ++ if (!ssusb->uwk_en) + return 0; + +- ssusb->pericfg = syscon_regmap_lookup_by_phandle(dn, +- "mediatek,syscon-wakeup"); +- if (IS_ERR(ssusb->pericfg)) { +- dev_err(dev, "fail to get pericfg regs\n"); +- return PTR_ERR(ssusb->pericfg); +- } ++ ret = of_parse_phandle_with_fixed_args(dn, ++ "mediatek,syscon-wakeup", 2, 0, &args); ++ if (ret) ++ return ret; + +- return 0; ++ ssusb->uwk_reg_base = args.args[0]; ++ ssusb->uwk_vers = args.args[1]; ++ ssusb->uwk = syscon_node_to_regmap(args.np); ++ of_node_put(args.np); ++ dev_info(ssusb->dev, "uwk - reg:0x%x, version:%d\n", ++ ssusb->uwk_reg_base, ssusb->uwk_vers); ++ ++ return PTR_ERR_OR_ZERO(ssusb->uwk); ++} ++ ++void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable) ++{ ++ if (ssusb->uwk_en) ++ ssusb_wakeup_ip_sleep_set(ssusb, enable); + } + + static void host_ports_num_get(struct ssusb_mtk *ssusb) +@@ -244,17 +255,3 @@ void ssusb_host_exit(struct ssusb_mtk *s + of_platform_depopulate(ssusb->dev); + ssusb_host_cleanup(ssusb); + } +- +-int ssusb_wakeup_enable(struct ssusb_mtk *ssusb) +-{ +- if (ssusb->wakeup_en) +- ssusb_wakeup_ip_sleep_en(ssusb); +- +- return 0; +-} +- +-void ssusb_wakeup_disable(struct ssusb_mtk *ssusb) +-{ +- if (ssusb->wakeup_en) +- ssusb_wakeup_ip_sleep_dis(ssusb); +-} +--- a/drivers/usb/mtu3/mtu3_plat.c ++++ b/drivers/usb/mtu3/mtu3_plat.c +@@ -291,8 +291,10 @@ static int get_ssusb_rscs(struct platfor + + /* if host role is supported */ + ret = ssusb_wakeup_of_property_parse(ssusb, node); +- if (ret) ++ if (ret) { ++ dev_err(dev, "failed to parse uwk property\n"); + return ret; ++ } + + /* optional property, ignore the error if it does not exist */ + of_property_read_u32(node, "mediatek,u3p-dis-msk", +@@ -466,7 +468,7 @@ static int __maybe_unused mtu3_suspend(s + ssusb_host_disable(ssusb, true); + ssusb_phy_power_off(ssusb); + ssusb_clks_disable(ssusb); +- ssusb_wakeup_enable(ssusb); ++ ssusb_wakeup_set(ssusb, true); + + return 0; + } +@@ -482,7 +484,7 @@ static int __maybe_unused mtu3_resume(st + if (!ssusb->is_host) + return 0; + +- ssusb_wakeup_disable(ssusb); ++ ssusb_wakeup_set(ssusb, false); + ret = ssusb_clks_enable(ssusb); + if (ret) + goto clks_err; diff --git a/target/linux/mediatek/patches-4.14/0189-dt-bindings-usb-mtu3-update-USB-wakeup-properties.patch b/target/linux/mediatek/patches-4.14/0189-dt-bindings-usb-mtu3-update-USB-wakeup-properties.patch new file mode 100644 index 000000000..393127e67 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0189-dt-bindings-usb-mtu3-update-USB-wakeup-properties.patch @@ -0,0 +1,47 @@ +From 067ad5fd18e2e7e38b77ca94eebaaf8d9a35d842 Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 3 Jan 2018 16:53:19 +0800 +Subject: [PATCH 189/224] dt-bindings: usb: mtu3: update USB wakeup properties + +Add two arguments in "mediatek,syscon-wakeup" to support multi +wakeup glue layer between SSUSB and SPM, and use standard property +"wakeup-source" to replace the private "mediatek,enable-wakeup" + +Signed-off-by: Chunfeng Yun +Reviewed-by: Rob Herring +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 15 ++++++++++----- + 1 file changed, 10 insertions(+), 5 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt +@@ -42,9 +42,14 @@ Optional properties: + - enable-manual-drd : supports manual dual-role switch via debugfs; usually + used when receptacle is TYPE-A and also wants to support dual-role + mode. +- - mediatek,enable-wakeup : supports ip sleep wakeup used by host mode +- - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup +- control register, it depends on "mediatek,enable-wakeup". ++ - wakeup-source: enable USB remote wakeup of host mode. ++ - mediatek,syscon-wakeup : phandle to syscon used to access the register ++ of the USB wakeup glue layer between SSUSB and SPM; it depends on ++ "wakeup-source", and has two arguments: ++ - the first one : register base address of the glue layer in syscon; ++ - the second one : hardware version of the glue layer ++ - 1 : used by mt8173 etc ++ - 2 : used by mt2712 etc + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, + bit1 for u3port1, ... etc; + +@@ -71,8 +76,8 @@ ssusb: usb@11271000 { + vbus-supply = <&usb_p0_vbus>; + extcon = <&extcon_usb>; + dr_mode = "otg"; +- mediatek,enable-wakeup; +- mediatek,syscon-wakeup = <&pericfg>; ++ wakeup-source; ++ mediatek,syscon-wakeup = <&pericfg 0x400 1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; diff --git a/target/linux/mediatek/patches-4.14/0190-usb-xhci-mtk-supports-remote-wakeup-for-mt2712-with-.patch b/target/linux/mediatek/patches-4.14/0190-usb-xhci-mtk-supports-remote-wakeup-for-mt2712-with-.patch new file mode 100644 index 000000000..2ae76eda1 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0190-usb-xhci-mtk-supports-remote-wakeup-for-mt2712-with-.patch @@ -0,0 +1,265 @@ +From e6fe50ef22071fe87ce48f79ab4fe21cbec2081b Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 3 Jan 2018 16:53:20 +0800 +Subject: [PATCH 190/224] usb: xhci-mtk: supports remote wakeup for mt2712 with + two xHCI IPs + +The old way of usb wakeup only supports platform with single xHCI IP, +such as mt8173, but mt2712 has two xHCI IPs, so rebuild its flow and +supports the new glue layer of usb wakeup on mt2712 which is different +from mt8173. +Due to there is a hardware bug with the LINE STATE wakeup mode on +mt8173 which causes wakeup failure by low speed devices, and also +because IP SLEEP mode can cover all functions of LINE STATE mode, +it is unused in fact, and will not support it later, so remove it at +the same time. + +Signed-off-by: Chunfeng Yun +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/host/xhci-mtk.c | 177 +++++++++++++++----------------------------- + drivers/usb/host/xhci-mtk.h | 6 +- + 2 files changed, 65 insertions(+), 118 deletions(-) + +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -66,26 +66,21 @@ + /* u2_phy_pll register */ + #define CTRL_U2_FORCE_PLL_STB BIT(28) + +-#define PERI_WK_CTRL0 0x400 +-#define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */ +-#define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/ +-#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1) +-#define UWK_CTL1_1P_LS_E BIT(0) +- +-#define PERI_WK_CTRL1 0x404 +-#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26) +-#define UWK_CTL1_IS_E BIT(25) +-#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21) +-#define UWK_CTL1_0P_LS_E BIT(20) +-#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */ +-#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */ +-#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */ +-#define UWK_CTL1_0P_LS_P BIT(7) +-#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */ +- +-enum ssusb_wakeup_src { +- SSUSB_WK_IP_SLEEP = 1, +- SSUSB_WK_LINE_STATE = 2, ++/* usb remote wakeup registers in syscon */ ++/* mt8173 etc */ ++#define PERI_WK_CTRL1 0x4 ++#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */ ++#define WC1_IS_EN BIT(25) ++#define WC1_IS_P BIT(6) /* polarity for ip sleep */ ++ ++/* mt2712 etc */ ++#define PERI_SSUSB_SPM_CTRL 0x0 ++#define SSC_IP_SLEEP_EN BIT(4) ++#define SSC_SPM_INT_EN BIT(1) ++ ++enum ssusb_uwk_vers { ++ SSUSB_UWK_V1 = 1, ++ SSUSB_UWK_V2, + }; + + static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) +@@ -308,112 +303,58 @@ static void xhci_mtk_clks_disable(struct + } + + /* only clocks can be turn off for ip-sleep wakeup mode */ +-static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk) ++static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) + { +- u32 tmp; +- struct regmap *pericfg = mtk->pericfg; ++ u32 reg, msk, val; + +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- tmp &= ~UWK_CTL1_IS_P; +- tmp &= ~(UWK_CTL1_IS_C(0xf)); +- tmp |= UWK_CTL1_IS_C(0x8); +- regmap_write(pericfg, PERI_WK_CTRL1, tmp); +- regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E); +- +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", +- __func__, tmp); +-} +- +-static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk) +-{ +- u32 tmp; +- +- regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp); +- tmp &= ~UWK_CTL1_IS_E; +- regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp); ++ switch (mtk->uwk_vers) { ++ case SSUSB_UWK_V1: ++ reg = mtk->uwk_reg_base + PERI_WK_CTRL1; ++ msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P; ++ val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0; ++ break; ++ case SSUSB_UWK_V2: ++ reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; ++ msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; ++ val = enable ? msk : 0; ++ break; ++ default: ++ return; ++ }; ++ regmap_update_bits(mtk->uwk, reg, msk, val); + } + +-/* +-* for line-state wakeup mode, phy's power should not power-down +-* and only support cable plug in/out +-*/ +-static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk) ++static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, ++ struct device_node *dn) + { +- u32 tmp; +- struct regmap *pericfg = mtk->pericfg; +- +- /* line-state of u2-port0 */ +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- tmp &= ~UWK_CTL1_0P_LS_P; +- tmp &= ~(UWK_CTL1_0P_LS_C(0xf)); +- tmp |= UWK_CTL1_0P_LS_C(0x8); +- regmap_write(pericfg, PERI_WK_CTRL1, tmp); +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E); ++ struct of_phandle_args args; ++ int ret; + +- /* line-state of u2-port1 */ +- regmap_read(pericfg, PERI_WK_CTRL0, &tmp); +- tmp &= ~(UWK_CTL1_1P_LS_C(0xf)); +- tmp |= UWK_CTL1_1P_LS_C(0x8); +- regmap_write(pericfg, PERI_WK_CTRL0, tmp); +- regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E); +-} ++ /* Wakeup function is optional */ ++ mtk->uwk_en = of_property_read_bool(dn, "wakeup-source"); ++ if (!mtk->uwk_en) ++ return 0; + +-static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk) +-{ +- u32 tmp; +- struct regmap *pericfg = mtk->pericfg; ++ ret = of_parse_phandle_with_fixed_args(dn, ++ "mediatek,syscon-wakeup", 2, 0, &args); ++ if (ret) ++ return ret; + +- /* line-state of u2-port0 */ +- regmap_read(pericfg, PERI_WK_CTRL1, &tmp); +- tmp &= ~UWK_CTL1_0P_LS_E; +- regmap_write(pericfg, PERI_WK_CTRL1, tmp); ++ mtk->uwk_reg_base = args.args[0]; ++ mtk->uwk_vers = args.args[1]; ++ mtk->uwk = syscon_node_to_regmap(args.np); ++ of_node_put(args.np); ++ dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n", ++ mtk->uwk_reg_base, mtk->uwk_vers); + +- /* line-state of u2-port1 */ +- regmap_read(pericfg, PERI_WK_CTRL0, &tmp); +- tmp &= ~UWK_CTL1_1P_LS_E; +- regmap_write(pericfg, PERI_WK_CTRL0, tmp); +-} ++ return PTR_ERR_OR_ZERO(mtk->uwk); + +-static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk) +-{ +- if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP) +- usb_wakeup_ip_sleep_en(mtk); +- else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE) +- usb_wakeup_line_state_en(mtk); + } + +-static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk) ++static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable) + { +- if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP) +- usb_wakeup_ip_sleep_dis(mtk); +- else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE) +- usb_wakeup_line_state_dis(mtk); +-} +- +-static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, +- struct device_node *dn) +-{ +- struct device *dev = mtk->dev; +- +- /* +- * wakeup function is optional, so it is not an error if this property +- * does not exist, and in such case, no need to get relative +- * properties anymore. +- */ +- of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src); +- if (!mtk->wakeup_src) +- return 0; +- +- mtk->pericfg = syscon_regmap_lookup_by_phandle(dn, +- "mediatek,syscon-wakeup"); +- if (IS_ERR(mtk->pericfg)) { +- dev_err(dev, "fail to get pericfg regs\n"); +- return PTR_ERR(mtk->pericfg); +- } +- +- return 0; ++ if (mtk->uwk_en) ++ usb_wakeup_ip_sleep_set(mtk, enable); + } + + static int xhci_mtk_setup(struct usb_hcd *hcd); +@@ -595,8 +536,10 @@ static int xhci_mtk_probe(struct platfor + &mtk->u3p_dis_msk); + + ret = usb_wakeup_of_property_parse(mtk, node); +- if (ret) ++ if (ret) { ++ dev_err(dev, "failed to parse uwk property\n"); + return ret; ++ } + + mtk->num_phys = of_count_phandle_with_args(node, + "phys", "#phy-cells"); +@@ -780,7 +723,7 @@ static int __maybe_unused xhci_mtk_suspe + xhci_mtk_host_disable(mtk); + xhci_mtk_phy_power_off(mtk); + xhci_mtk_clks_disable(mtk); +- usb_wakeup_enable(mtk); ++ usb_wakeup_set(mtk, true); + return 0; + } + +@@ -790,7 +733,7 @@ static int __maybe_unused xhci_mtk_resum + struct usb_hcd *hcd = mtk->hcd; + struct xhci_hcd *xhci = hcd_to_xhci(hcd); + +- usb_wakeup_disable(mtk); ++ usb_wakeup_set(mtk, false); + xhci_mtk_clks_enable(mtk); + xhci_mtk_phy_power_on(mtk); + xhci_mtk_host_enable(mtk); +--- a/drivers/usb/host/xhci-mtk.h ++++ b/drivers/usb/host/xhci-mtk.h +@@ -131,8 +131,12 @@ struct xhci_hcd_mtk { + struct regmap *pericfg; + struct phy **phys; + int num_phys; +- int wakeup_src; + bool lpm_support; ++ /* usb remote wakeup */ ++ bool uwk_en; ++ struct regmap *uwk; ++ u32 uwk_reg_base; ++ u32 uwk_vers; + }; + + static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd) diff --git a/target/linux/mediatek/patches-4.14/0191-usb-xhci-allow-imod-interval-to-be-configurable.patch b/target/linux/mediatek/patches-4.14/0191-usb-xhci-allow-imod-interval-to-be-configurable.patch new file mode 100644 index 000000000..c48db55d7 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0191-usb-xhci-allow-imod-interval-to-be-configurable.patch @@ -0,0 +1,138 @@ +From c5c72d252dc8e417388386d5767ea790ee8f5b44 Mon Sep 17 00:00:00 2001 +From: Adam Wallis +Date: Fri, 8 Dec 2017 17:59:13 +0200 +Subject: [PATCH 191/224] usb: xhci: allow imod-interval to be configurable + +The xHCI driver currently has the IMOD set to 160, which +translates to an IMOD interval of 40,000ns (160 * 250)ns + +Commit 0cbd4b34cda9 ("xhci: mediatek: support MTK xHCI host controller") +introduced a QUIRK for the MTK platform to adjust this interval to 20, +which translates to an IMOD interval of 5,000ns (20 * 250)ns. This is +due to the fact that the MTK controller IMOD interval is 8 times +as much as defined in xHCI spec. + +Instead of adding more quirk bits for additional platforms, this patch +introduces the ability for vendors to set the IMOD_INTERVAL as is +optimal for their platform. By using device_property_read_u32() on +"imod-interval-ns", the IMOD INTERVAL can be specified in nano seconds. +If no interval is specified, the default of 40,000ns (IMOD=160) will be +used. + +No bounds checking has been implemented due to the fact that a vendor +may have violated the spec and would need to specify a value outside of +the max 8,000 IRQs/second limit specified in the xHCI spec. + +Tested-by: Chunfeng Yun +Reviewed-by: Rob Herring +Signed-off-by: Adam Wallis +Signed-off-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 2 ++ + Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 + + drivers/usb/host/xhci-mtk.c | 9 +++++++++ + drivers/usb/host/xhci-pci.c | 3 +++ + drivers/usb/host/xhci-plat.c | 5 +++++ + drivers/usb/host/xhci.c | 6 +----- + drivers/usb/host/xhci.h | 2 ++ + 7 files changed, 23 insertions(+), 5 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +@@ -46,6 +46,7 @@ Optional properties: + - pinctrl-names : a pinctrl state named "default" must be defined + - pinctrl-0 : pin control group + See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt ++ - imod-interval-ns: default interrupt moderation interval is 5000ns + + Example: + usb30: usb@11270000 { +@@ -66,6 +67,7 @@ usb30: usb@11270000 { + usb3-lpm-capable; + mediatek,syscon-wakeup = <&pericfg>; + mediatek,wakeup-src = <1>; ++ imod-interval-ns = <10000>; + }; + + 2nd: dual-role mode with xHCI driver +--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt ++++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt +@@ -29,6 +29,7 @@ Optional properties: + - clocks: reference to a clock + - usb3-lpm-capable: determines if platform is USB3 LPM capable + - quirk-broken-port-ped: set if the controller has broken port disable mechanism ++ - imod-interval-ns: default interrupt moderation interval is 5000ns + + Example: + usb@f0931000 { +--- a/drivers/usb/host/xhci-mtk.c ++++ b/drivers/usb/host/xhci-mtk.c +@@ -629,6 +629,15 @@ static int xhci_mtk_probe(struct platfor + + xhci = hcd_to_xhci(hcd); + xhci->main_hcd = hcd; ++ ++ /* ++ * imod_interval is the interrupt moderation value in nanoseconds. ++ * The increment interval is 8 times as much as that defined in ++ * the xHCI spec on MTK's controller. ++ */ ++ xhci->imod_interval = 5000; ++ device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval); ++ + xhci->shared_hcd = usb_create_shared_hcd(driver, dev, + dev_name(dev), hcd); + if (!xhci->shared_hcd) { +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -266,6 +266,9 @@ static int xhci_pci_setup(struct usb_hcd + if (!xhci->sbrn) + pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn); + ++ /* imod_interval is the interrupt moderation value in nanoseconds. */ ++ xhci->imod_interval = 40000; ++ + retval = xhci_gen_setup(hcd, xhci_pci_quirks); + if (retval) + return retval; +--- a/drivers/usb/host/xhci-plat.c ++++ b/drivers/usb/host/xhci-plat.c +@@ -269,6 +269,11 @@ static int xhci_plat_probe(struct platfo + if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped")) + xhci->quirks |= XHCI_BROKEN_PORT_PED; + ++ /* imod_interval is the interrupt moderation value in nanoseconds. */ ++ xhci->imod_interval = 40000; ++ device_property_read_u32(sysdev, "imod-interval-ns", ++ &xhci->imod_interval); ++ + hcd->usb_phy = devm_usb_get_phy_by_phandle(sysdev, "usb-phy", 0); + if (IS_ERR(hcd->usb_phy)) { + ret = PTR_ERR(hcd->usb_phy); +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -597,11 +597,7 @@ int xhci_run(struct usb_hcd *hcd) + "// Set the interrupt modulation register"); + temp = readl(&xhci->ir_set->irq_control); + temp &= ~ER_IRQ_INTERVAL_MASK; +- /* +- * the increment interval is 8 times as much as that defined +- * in xHCI spec on MTK's controller +- */ +- temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160); ++ temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK; + writel(temp, &xhci->ir_set->irq_control); + + /* Set the HCD state before we enable the irqs */ +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1726,6 +1726,8 @@ struct xhci_hcd { + u8 max_interrupters; + u8 max_ports; + u8 isoc_threshold; ++ /* imod_interval in ns (I * 250ns) */ ++ u32 imod_interval; + int event_ring_max; + /* 4KB min, 128MB max */ + int page_size; diff --git a/target/linux/mediatek/patches-4.14/0192-dt-bindings-usb-mtk-xhci-update-USB-wakeup-propertie.patch b/target/linux/mediatek/patches-4.14/0192-dt-bindings-usb-mtk-xhci-update-USB-wakeup-propertie.patch new file mode 100644 index 000000000..13d5a2cd0 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0192-dt-bindings-usb-mtk-xhci-update-USB-wakeup-propertie.patch @@ -0,0 +1,49 @@ +From bbbbdd36c7311a786d7392f2394b355b1f78cf8b Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Wed, 3 Jan 2018 16:53:21 +0800 +Subject: [PATCH 192/224] dt-bindings: usb: mtk-xhci: update USB wakeup + properties + +Add two arguments in "mediatek,syscon-wakeup" to support multi +wakeup glue layer between SSUSB and SPM, and use standard property +"wakeup-source" to replace the private "mediatek,wakeup-src" + +Signed-off-by: Chunfeng Yun +Reviewed-by: Rob Herring +Signed-off-by: Greg Kroah-Hartman +--- + .../devicetree/bindings/usb/mediatek,mtk-xhci.txt | 16 ++++++++++------ + 1 file changed, 10 insertions(+), 6 deletions(-) + +--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt ++++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +@@ -35,10 +35,14 @@ Required properties: + - phys : a list of phandle + phy specifier pairs + + Optional properties: +- - mediatek,wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup +- mode; +- - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup +- control register, it depends on "mediatek,wakeup-src". ++ - wakeup-source : enable USB remote wakeup; ++ - mediatek,syscon-wakeup : phandle to syscon used to access the register ++ of the USB wakeup glue layer between xHCI and SPM; it depends on ++ "wakeup-source", and has two arguments: ++ - the first one : register base address of the glue layer in syscon; ++ - the second one : hardware version of the glue layer ++ - 1 : used by mt8173 etc ++ - 2 : used by mt2712 etc + - mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0, + bit1 for u3port1, ... etc; + - vbus-supply : reference to the VBUS regulator; +@@ -65,8 +69,8 @@ usb30: usb@11270000 { + vusb33-supply = <&mt6397_vusb_reg>; + vbus-supply = <&usb_p1_vbus>; + usb3-lpm-capable; +- mediatek,syscon-wakeup = <&pericfg>; +- mediatek,wakeup-src = <1>; ++ mediatek,syscon-wakeup = <&pericfg 0x400 1>; ++ wakeup-source; + imod-interval-ns = <10000>; + }; + diff --git a/target/linux/mediatek/patches-4.14/0193-clk-mediatek-adjust-dependency-of-reset.c-to-avoid-u.patch b/target/linux/mediatek/patches-4.14/0193-clk-mediatek-adjust-dependency-of-reset.c-to-avoid-u.patch new file mode 100644 index 000000000..ee7d035fd --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0193-clk-mediatek-adjust-dependency-of-reset.c-to-avoid-u.patch @@ -0,0 +1,71 @@ +From 0f9391b4ee12cad5c93e109b9eb6c0c6298da0d3 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 5 Jan 2018 16:14:06 +0800 +Subject: [PATCH 193/224] clk: mediatek: adjust dependency of reset.c to avoid + unexpectedly being built + +Changes from v1->v2: +Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable +reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should +be quite reasonable because the reset controller is tightly embedded +inside and exported from these clock subsystems. At least it can be found +on infracfg and pericfg subsystem that both are really fundamental block +lots of devices must depend on. + +commit 74cb0d6dde8 ("clk: mediatek: fixup test-building of MediaTek clock +drivers") can let the build system looking into the directory where the +clock drivers resides and then allow test-building the drivers. + +But the change also gives rise to certain incorrect behavior which is +reset.c being built even not depending on either COMPILE_TEST or +ARCH_MEDIATEK alternative dependency. To get rid of reset.c being built +unexpectedly on the other platforms, it would be a good change that the +file should be built depending on its own specific configuration rather +than just on generic RESET_CONTROLLER one. + +Signed-off-by: Sean Wang +Cc: Jean Delvare +Signed-off-by: Stephen Boyd +--- + drivers/clk/mediatek/Kconfig | 1 + + drivers/clk/mediatek/Makefile | 4 ++-- + drivers/clk/mediatek/clk-mtk.h | 7 ------- + 3 files changed, 3 insertions(+), 9 deletions(-) + +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -6,6 +6,7 @@ menu "Clock driver for MediaTek SoC" + + config COMMON_CLK_MEDIATEK + bool ++ select RESET_CONTROLLER + ---help--- + MediaTek SoCs' clock support. + +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -1,6 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 +-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o +-obj-$(CONFIG_RESET_CONTROLLER) += reset.o ++obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o + obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o + obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o + obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -229,14 +229,7 @@ void mtk_clk_register_plls(struct device + struct clk *mtk_clk_register_ref2usb_tx(const char *name, + const char *parent_name, void __iomem *reg); + +-#ifdef CONFIG_RESET_CONTROLLER + void mtk_register_reset_controller(struct device_node *np, + unsigned int num_regs, int regofs); +-#else +-static inline void mtk_register_reset_controller(struct device_node *np, +- unsigned int num_regs, int regofs) +-{ +-} +-#endif + + #endif /* __DRV_CLK_MTK_H */ diff --git a/target/linux/mediatek/patches-4.14/0194-pinctrl-mediatek-mt7622-fix-potential-uninitialized-.patch b/target/linux/mediatek/patches-4.14/0194-pinctrl-mediatek-mt7622-fix-potential-uninitialized-.patch new file mode 100644 index 000000000..fc6c2b915 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0194-pinctrl-mediatek-mt7622-fix-potential-uninitialized-.patch @@ -0,0 +1,49 @@ +From cfcb2cc358f3ff466d4c419d8f6fe0263bdc47b1 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 10 Jan 2018 00:28:24 +0800 +Subject: [PATCH 194/224] pinctrl: mediatek: mt7622: fix potential + uninitialized value being returned + +commit d6ed93551320 ("pinctrl: mediatek: add pinctrl driver for MT7622 +SoC") leads to the following static checker warning: + +drivers/pinctrl/mediatek/pinctrl-mt7622.c:1419 mtk_gpio_get() +error: uninitialized symbol 'value'. +1412 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) +1413 { +1414 struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); +1415 int value; +1416 +1417 mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); +^^^^^^^^^^^^^^^^ +1418 +1419 return !!value; +1420 } + +The appropriate error handling must be added to avoid the potential error +caused by uninitialized value being returned. + +Reported-by: Dan Carpenter +Signed-off-by: Sean Wang +Reviewed-by: Matthias Brugger +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +@@ -1412,9 +1412,11 @@ static struct pinctrl_desc mtk_desc = { + static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) + { + struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent); +- int value; ++ int value, err; + +- mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); ++ err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value); ++ if (err) ++ return err; + + return !!value; + } diff --git a/target/linux/mediatek/patches-4.14/0195-pinctrl-mediatek-mt7622-align-error-handling-of-mtk_.patch b/target/linux/mediatek/patches-4.14/0195-pinctrl-mediatek-mt7622-align-error-handling-of-mtk_.patch new file mode 100644 index 000000000..49842dddb --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0195-pinctrl-mediatek-mt7622-align-error-handling-of-mtk_.patch @@ -0,0 +1,50 @@ +From 8d3e3f3159284dba7a86788464edd4d5cdba4f06 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 10 Jan 2018 00:28:25 +0800 +Subject: [PATCH 195/224] pinctrl: mediatek: mt7622: align error handling of + mtk_hw_get_value call + +Make consistent error handling of all mtk_hw_get_value occurrences using +propagating error code from the internal instead of creating a new one. + +Signed-off-by: Sean Wang +Reviewed-by: Matthias Brugger +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/mediatek/pinctrl-mt7622.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c +@@ -1160,7 +1160,7 @@ static int mtk_pinconf_get(struct pinctr + case PIN_CONFIG_OUTPUT_ENABLE: + err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_DIR, &val); + if (err) +- return -EINVAL; ++ return err; + + /* HW takes input mode as zero; output mode as non-zero */ + if ((val && param == PIN_CONFIG_INPUT_ENABLE) || +@@ -1184,11 +1184,11 @@ static int mtk_pinconf_get(struct pinctr + case PIN_CONFIG_DRIVE_STRENGTH: + err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E4, &val); + if (err) +- return -EINVAL; ++ return err; + + err = mtk_hw_get_value(hw, pin, PINCTRL_PIN_REG_E8, &val2); + if (err) +- return -EINVAL; ++ return err; + + /* 4mA when (e8, e4) = (0, 0); 8mA when (e8, e4) = (0, 1) + * 12mA when (e8, e4) = (1, 0); 16mA when (e8, e4) = (1, 1) +@@ -1203,7 +1203,7 @@ static int mtk_pinconf_get(struct pinctr + + err = mtk_hw_get_value(hw, pin, reg, &val); + if (err) +- return -EINVAL; ++ return err; + + ret = val; + diff --git a/target/linux/mediatek/patches-4.14/0196-mtd-mtk-nor-modify-functions-name-more-generally.patch b/target/linux/mediatek/patches-4.14/0196-mtd-mtk-nor-modify-functions-name-more-generally.patch new file mode 100644 index 000000000..19466bad6 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0196-mtd-mtk-nor-modify-functions-name-more-generally.patch @@ -0,0 +1,554 @@ +From 4dab73d46eb58c142b5d2e7039f12e4e5df357ad Mon Sep 17 00:00:00 2001 +From: Guochun Mao +Date: Mon, 18 Dec 2017 09:47:35 +0800 +Subject: [PATCH 196/224] mtd: mtk-nor: modify functions' name more generally + +Since more and more Mediatek's SoC can use this driver to +control spi-nor flash, functions' name with "mt8173_" is +no longer properly. Replacing "mt8173_" with "mtk_" will +be more accurate to describe these functions' usable scope. + +Signed-off-by: Guochun Mao +Signed-off-by: Cyrille Pitchen +--- + drivers/mtd/spi-nor/mtk-quadspi.c | 240 +++++++++++++++++++------------------- + 1 file changed, 120 insertions(+), 120 deletions(-) + +--- a/drivers/mtd/spi-nor/mtk-quadspi.c ++++ b/drivers/mtd/spi-nor/mtk-quadspi.c +@@ -110,7 +110,7 @@ + #define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) + #define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) + +-struct mt8173_nor { ++struct mtk_nor { + struct spi_nor nor; + struct device *dev; + void __iomem *base; /* nor flash base address */ +@@ -118,48 +118,48 @@ struct mt8173_nor { + struct clk *nor_clk; + }; + +-static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor) ++static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor) + { +- struct spi_nor *nor = &mt8173_nor->nor; ++ struct spi_nor *nor = &mtk_nor->nor; + + switch (nor->read_proto) { + case SNOR_PROTO_1_1_1: +- writeb(nor->read_opcode, mt8173_nor->base + ++ writeb(nor->read_opcode, mtk_nor->base + + MTK_NOR_PRGDATA3_REG); +- writeb(MTK_NOR_FAST_READ, mt8173_nor->base + ++ writeb(MTK_NOR_FAST_READ, mtk_nor->base + + MTK_NOR_CFG1_REG); + break; + case SNOR_PROTO_1_1_2: +- writeb(nor->read_opcode, mt8173_nor->base + ++ writeb(nor->read_opcode, mtk_nor->base + + MTK_NOR_PRGDATA3_REG); +- writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base + ++ writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base + + MTK_NOR_DUAL_REG); + break; + case SNOR_PROTO_1_1_4: +- writeb(nor->read_opcode, mt8173_nor->base + ++ writeb(nor->read_opcode, mtk_nor->base + + MTK_NOR_PRGDATA4_REG); +- writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base + ++ writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base + + MTK_NOR_DUAL_REG); + break; + default: +- writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base + ++ writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base + + MTK_NOR_DUAL_REG); + break; + } + } + +-static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval) ++static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval) + { + int reg; + u8 val = cmdval & 0x1f; + +- writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG); +- return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg, ++ writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG); ++ return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg, + !(reg & val), 100, 10000); + } + +-static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, +- u8 *tx, int txlen, u8 *rx, int rxlen) ++static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op, ++ u8 *tx, int txlen, u8 *rx, int rxlen) + { + int len = 1 + txlen + rxlen; + int i, ret, idx; +@@ -167,26 +167,26 @@ static int mt8173_nor_do_tx_rx(struct mt + if (len > MTK_NOR_MAX_SHIFT) + return -EINVAL; + +- writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG); ++ writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG); + + /* start at PRGDATA5, go down to PRGDATA0 */ + idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; + + /* opcode */ +- writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); ++ writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx)); + idx--; + + /* program TX data */ + for (i = 0; i < txlen; i++, idx--) +- writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx)); ++ writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx)); + + /* clear out rest of TX registers */ + while (idx >= 0) { +- writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); ++ writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx)); + idx--; + } + +- ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD); ++ ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD); + if (ret) + return ret; + +@@ -195,20 +195,20 @@ static int mt8173_nor_do_tx_rx(struct mt + + /* read out RX data */ + for (i = 0; i < rxlen; i++, idx--) +- rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx)); ++ rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx)); + + return 0; + } + + /* Do a WRSR (Write Status Register) command */ +-static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr) ++static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr) + { +- writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG); +- writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG); +- return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD); ++ writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG); ++ writeb(8, mtk_nor->base + MTK_NOR_CNT_REG); ++ return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD); + } + +-static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) ++static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor) + { + u8 reg; + +@@ -216,27 +216,27 @@ static int mt8173_nor_write_buffer_enabl + * 0: pre-fetch buffer use for read + * 1: pre-fetch buffer use for page program + */ +- writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); +- return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, ++ writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG); ++ return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, + 0x01 == (reg & 0x01), 100, 10000); + } + +-static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) ++static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor) + { + u8 reg; + +- writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); +- return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, ++ writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG); ++ return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg, + MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, + 10000); + } + +-static void mt8173_nor_set_addr_width(struct mt8173_nor *mt8173_nor) ++static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor) + { + u8 val; +- struct spi_nor *nor = &mt8173_nor->nor; ++ struct spi_nor *nor = &mtk_nor->nor; + +- val = readb(mt8173_nor->base + MTK_NOR_DUAL_REG); ++ val = readb(mtk_nor->base + MTK_NOR_DUAL_REG); + + switch (nor->addr_width) { + case 3: +@@ -246,115 +246,115 @@ static void mt8173_nor_set_addr_width(st + val |= MTK_NOR_4B_ADDR_EN; + break; + default: +- dev_warn(mt8173_nor->dev, "Unexpected address width %u.\n", ++ dev_warn(mtk_nor->dev, "Unexpected address width %u.\n", + nor->addr_width); + break; + } + +- writeb(val, mt8173_nor->base + MTK_NOR_DUAL_REG); ++ writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG); + } + +-static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) ++static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr) + { + int i; + +- mt8173_nor_set_addr_width(mt8173_nor); ++ mtk_nor_set_addr_width(mtk_nor); + + for (i = 0; i < 3; i++) { +- writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); ++ writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4); + addr >>= 8; + } + /* Last register is non-contiguous */ +- writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG); ++ writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG); + } + +-static ssize_t mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length, +- u_char *buffer) ++static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length, ++ u_char *buffer) + { + int i, ret; + int addr = (int)from; + u8 *buf = (u8 *)buffer; +- struct mt8173_nor *mt8173_nor = nor->priv; ++ struct mtk_nor *mtk_nor = nor->priv; + + /* set mode for fast read mode ,dual mode or quad mode */ +- mt8173_nor_set_read_mode(mt8173_nor); +- mt8173_nor_set_addr(mt8173_nor, addr); ++ mtk_nor_set_read_mode(mtk_nor); ++ mtk_nor_set_addr(mtk_nor, addr); + + for (i = 0; i < length; i++) { +- ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD); ++ ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD); + if (ret < 0) + return ret; +- buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG); ++ buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG); + } + return length; + } + +-static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor, +- int addr, int length, u8 *data) ++static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor, ++ int addr, int length, u8 *data) + { + int i, ret; + +- mt8173_nor_set_addr(mt8173_nor, addr); ++ mtk_nor_set_addr(mtk_nor, addr); + + for (i = 0; i < length; i++) { +- writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG); +- ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD); ++ writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG); ++ ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD); + if (ret < 0) + return ret; + } + return 0; + } + +-static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr, +- const u8 *buf) ++static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr, ++ const u8 *buf) + { + int i, bufidx, data; + +- mt8173_nor_set_addr(mt8173_nor, addr); ++ mtk_nor_set_addr(mtk_nor, addr); + + bufidx = 0; + for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { + data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | + buf[bufidx + 1]<<8 | buf[bufidx]; + bufidx += 4; +- writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG); ++ writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG); + } +- return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD); ++ return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD); + } + +-static ssize_t mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, +- const u_char *buf) ++static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len, ++ const u_char *buf) + { + int ret; +- struct mt8173_nor *mt8173_nor = nor->priv; ++ struct mtk_nor *mtk_nor = nor->priv; + size_t i; + +- ret = mt8173_nor_write_buffer_enable(mt8173_nor); ++ ret = mtk_nor_write_buffer_enable(mtk_nor); + if (ret < 0) { +- dev_warn(mt8173_nor->dev, "write buffer enable failed!\n"); ++ dev_warn(mtk_nor->dev, "write buffer enable failed!\n"); + return ret; + } + + for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) { +- ret = mt8173_nor_write_buffer(mt8173_nor, to, buf); ++ ret = mtk_nor_write_buffer(mtk_nor, to, buf); + if (ret < 0) { +- dev_err(mt8173_nor->dev, "write buffer failed!\n"); ++ dev_err(mtk_nor->dev, "write buffer failed!\n"); + return ret; + } + to += SFLASH_WRBUF_SIZE; + buf += SFLASH_WRBUF_SIZE; + } +- ret = mt8173_nor_write_buffer_disable(mt8173_nor); ++ ret = mtk_nor_write_buffer_disable(mtk_nor); + if (ret < 0) { +- dev_warn(mt8173_nor->dev, "write buffer disable failed!\n"); ++ dev_warn(mtk_nor->dev, "write buffer disable failed!\n"); + return ret; + } + + if (i < len) { +- ret = mt8173_nor_write_single_byte(mt8173_nor, to, +- (int)(len - i), (u8 *)buf); ++ ret = mtk_nor_write_single_byte(mtk_nor, to, ++ (int)(len - i), (u8 *)buf); + if (ret < 0) { +- dev_err(mt8173_nor->dev, "write single byte failed!\n"); ++ dev_err(mtk_nor->dev, "write single byte failed!\n"); + return ret; + } + } +@@ -362,72 +362,72 @@ static ssize_t mt8173_nor_write(struct s + return len; + } + +-static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) ++static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) + { + int ret; +- struct mt8173_nor *mt8173_nor = nor->priv; ++ struct mtk_nor *mtk_nor = nor->priv; + + switch (opcode) { + case SPINOR_OP_RDSR: +- ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD); ++ ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD); + if (ret < 0) + return ret; + if (len == 1) +- *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG); ++ *buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG); + else +- dev_err(mt8173_nor->dev, "len should be 1 for read status!\n"); ++ dev_err(mtk_nor->dev, "len should be 1 for read status!\n"); + break; + default: +- ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len); ++ ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len); + break; + } + return ret; + } + +-static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, +- int len) ++static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, ++ int len) + { + int ret; +- struct mt8173_nor *mt8173_nor = nor->priv; ++ struct mtk_nor *mtk_nor = nor->priv; + + switch (opcode) { + case SPINOR_OP_WRSR: + /* We only handle 1 byte */ +- ret = mt8173_nor_wr_sr(mt8173_nor, *buf); ++ ret = mtk_nor_wr_sr(mtk_nor, *buf); + break; + default: +- ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); ++ ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0); + if (ret) +- dev_warn(mt8173_nor->dev, "write reg failure!\n"); ++ dev_warn(mtk_nor->dev, "write reg failure!\n"); + break; + } + return ret; + } + +-static void mt8173_nor_disable_clk(struct mt8173_nor *mt8173_nor) ++static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor) + { +- clk_disable_unprepare(mt8173_nor->spi_clk); +- clk_disable_unprepare(mt8173_nor->nor_clk); ++ clk_disable_unprepare(mtk_nor->spi_clk); ++ clk_disable_unprepare(mtk_nor->nor_clk); + } + +-static int mt8173_nor_enable_clk(struct mt8173_nor *mt8173_nor) ++static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor) + { + int ret; + +- ret = clk_prepare_enable(mt8173_nor->spi_clk); ++ ret = clk_prepare_enable(mtk_nor->spi_clk); + if (ret) + return ret; + +- ret = clk_prepare_enable(mt8173_nor->nor_clk); ++ ret = clk_prepare_enable(mtk_nor->nor_clk); + if (ret) { +- clk_disable_unprepare(mt8173_nor->spi_clk); ++ clk_disable_unprepare(mtk_nor->spi_clk); + return ret; + } + + return 0; + } + +-static int mtk_nor_init(struct mt8173_nor *mt8173_nor, ++static int mtk_nor_init(struct mtk_nor *mtk_nor, + struct device_node *flash_node) + { + const struct spi_nor_hwcaps hwcaps = { +@@ -439,18 +439,18 @@ static int mtk_nor_init(struct mt8173_no + struct spi_nor *nor; + + /* initialize controller to accept commands */ +- writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG); ++ writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG); + +- nor = &mt8173_nor->nor; +- nor->dev = mt8173_nor->dev; +- nor->priv = mt8173_nor; ++ nor = &mtk_nor->nor; ++ nor->dev = mtk_nor->dev; ++ nor->priv = mtk_nor; + spi_nor_set_flash_node(nor, flash_node); + + /* fill the hooks to spi nor */ +- nor->read = mt8173_nor_read; +- nor->read_reg = mt8173_nor_read_reg; +- nor->write = mt8173_nor_write; +- nor->write_reg = mt8173_nor_write_reg; ++ nor->read = mtk_nor_read; ++ nor->read_reg = mtk_nor_read_reg; ++ nor->write = mtk_nor_write; ++ nor->write_reg = mtk_nor_write_reg; + nor->mtd.name = "mtk_nor"; + /* initialized with NULL */ + ret = spi_nor_scan(nor, NULL, &hwcaps); +@@ -465,34 +465,34 @@ static int mtk_nor_drv_probe(struct plat + struct device_node *flash_np; + struct resource *res; + int ret; +- struct mt8173_nor *mt8173_nor; ++ struct mtk_nor *mtk_nor; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + +- mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL); +- if (!mt8173_nor) ++ mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL); ++ if (!mtk_nor) + return -ENOMEM; +- platform_set_drvdata(pdev, mt8173_nor); ++ platform_set_drvdata(pdev, mtk_nor); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res); +- if (IS_ERR(mt8173_nor->base)) +- return PTR_ERR(mt8173_nor->base); ++ mtk_nor->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(mtk_nor->base)) ++ return PTR_ERR(mtk_nor->base); + +- mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); +- if (IS_ERR(mt8173_nor->spi_clk)) +- return PTR_ERR(mt8173_nor->spi_clk); ++ mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); ++ if (IS_ERR(mtk_nor->spi_clk)) ++ return PTR_ERR(mtk_nor->spi_clk); + +- mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); +- if (IS_ERR(mt8173_nor->nor_clk)) +- return PTR_ERR(mt8173_nor->nor_clk); ++ mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); ++ if (IS_ERR(mtk_nor->nor_clk)) ++ return PTR_ERR(mtk_nor->nor_clk); + +- mt8173_nor->dev = &pdev->dev; ++ mtk_nor->dev = &pdev->dev; + +- ret = mt8173_nor_enable_clk(mt8173_nor); ++ ret = mtk_nor_enable_clk(mtk_nor); + if (ret) + return ret; + +@@ -503,20 +503,20 @@ static int mtk_nor_drv_probe(struct plat + ret = -ENODEV; + goto nor_free; + } +- ret = mtk_nor_init(mt8173_nor, flash_np); ++ ret = mtk_nor_init(mtk_nor, flash_np); + + nor_free: + if (ret) +- mt8173_nor_disable_clk(mt8173_nor); ++ mtk_nor_disable_clk(mtk_nor); + + return ret; + } + + static int mtk_nor_drv_remove(struct platform_device *pdev) + { +- struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); ++ struct mtk_nor *mtk_nor = platform_get_drvdata(pdev); + +- mt8173_nor_disable_clk(mt8173_nor); ++ mtk_nor_disable_clk(mtk_nor); + + return 0; + } +@@ -524,18 +524,18 @@ static int mtk_nor_drv_remove(struct pla + #ifdef CONFIG_PM_SLEEP + static int mtk_nor_suspend(struct device *dev) + { +- struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); ++ struct mtk_nor *mtk_nor = dev_get_drvdata(dev); + +- mt8173_nor_disable_clk(mt8173_nor); ++ mtk_nor_disable_clk(mtk_nor); + + return 0; + } + + static int mtk_nor_resume(struct device *dev) + { +- struct mt8173_nor *mt8173_nor = dev_get_drvdata(dev); ++ struct mtk_nor *mtk_nor = dev_get_drvdata(dev); + +- return mt8173_nor_enable_clk(mt8173_nor); ++ return mtk_nor_enable_clk(mtk_nor); + } + + static const struct dev_pm_ops mtk_nor_dev_pm_ops = { diff --git a/target/linux/mediatek/patches-4.14/0197-hwrng-mediatek-Setup-default-RNG-quality.patch b/target/linux/mediatek/patches-4.14/0197-hwrng-mediatek-Setup-default-RNG-quality.patch new file mode 100644 index 000000000..71b097596 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0197-hwrng-mediatek-Setup-default-RNG-quality.patch @@ -0,0 +1,25 @@ +From cd4a7d700a148f89d599ebe53fd97dc64193683a Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 10 Jan 2018 12:02:46 +0800 +Subject: [PATCH 197/224] hwrng: mediatek - Setup default RNG quality + +When hw_random device's quality is non-zero, it will automatically fill +the kernel's entropy pool at boot. For the purpose, one conservative +quality value is being picked up as the default value. + +Signed-off-by: Sean Wang +Signed-off-by: Herbert Xu +--- + drivers/char/hw_random/mtk-rng.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/char/hw_random/mtk-rng.c ++++ b/drivers/char/hw_random/mtk-rng.c +@@ -135,6 +135,7 @@ static int mtk_rng_probe(struct platform + #endif + priv->rng.read = mtk_rng_read; + priv->rng.priv = (unsigned long)&pdev->dev; ++ priv->rng.quality = 900; + + priv->clk = devm_clk_get(&pdev->dev, "rng"); + if (IS_ERR(priv->clk)) { diff --git a/target/linux/mediatek/patches-4.14/0198-dt-bindings-thermal-add-binding-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0198-dt-bindings-thermal-add-binding-for-MT7622-SoC.patch new file mode 100644 index 000000000..a16e01b10 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0198-dt-bindings-thermal-add-binding-for-MT7622-SoC.patch @@ -0,0 +1,26 @@ +From bdaa6312375055d3e104869ca04cc463ac0a33d1 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 17 Jan 2018 00:00:39 +0800 +Subject: [PATCH 198/224] dt-bindings: thermal: add binding for MT7622 SoC + +Add devicetree bindings for MediaTek MT7622 thermal controller + +Changes v1 -> v2: add tag from Rob + +Signed-off-by: Sean Wang +Signed-off-by: Shunli Wang +Reviewed-by: Rob Herring +--- + Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt ++++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +@@ -12,6 +12,7 @@ Required properties: + - "mediatek,mt8173-thermal" : For MT8173 family of SoCs + - "mediatek,mt2701-thermal" : For MT2701 family of SoCs + - "mediatek,mt2712-thermal" : For MT2712 family of SoCs ++ - "mediatek,mt7622-thermal" : For MT7622 SoC + - reg: Address range of the thermal controller + - interrupts: IRQ for the thermal controller + - clocks, clock-names: Clocks needed for the thermal controller. required diff --git a/target/linux/mediatek/patches-4.14/0199-thermal-mtk-Cleanup-unused-defines.patch b/target/linux/mediatek/patches-4.14/0199-thermal-mtk-Cleanup-unused-defines.patch new file mode 100644 index 000000000..a7288acdf --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0199-thermal-mtk-Cleanup-unused-defines.patch @@ -0,0 +1,51 @@ +From 8bf9b7eeef3f5f4866d66878db75b6b944a8eab4 Mon Sep 17 00:00:00 2001 +From: Matthias Brugger +Date: Fri, 1 Dec 2017 11:43:21 +0100 +Subject: [PATCH 199/224] thermal: mtk: Cleanup unused defines + +The mtk_thermal has some defiens which are never used within the driver. +This patch delets them. + +Signed-off-by: Matthias Brugger +Acked-by: Daniel Lezcano +Signed-off-by: Eduardo Valentin +--- + drivers/thermal/mtk_thermal.c | 9 +-------- + 1 file changed, 1 insertion(+), 8 deletions(-) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -32,15 +32,10 @@ + #include + + /* AUXADC Registers */ +-#define AUXADC_CON0_V 0x000 +-#define AUXADC_CON1_V 0x004 + #define AUXADC_CON1_SET_V 0x008 + #define AUXADC_CON1_CLR_V 0x00c + #define AUXADC_CON2_V 0x010 + #define AUXADC_DATA(channel) (0x14 + (channel) * 4) +-#define AUXADC_MISC_V 0x094 +- +-#define AUXADC_CON1_CHANNEL(x) BIT(x) + + #define APMIXED_SYS_TS_CON1 0x604 + +@@ -158,8 +153,6 @@ + /* The number of sensing points per bank */ + #define MT2712_NUM_SENSORS_PER_ZONE 4 + +-#define THERMAL_NAME "mtk-thermal" +- + struct mtk_thermal; + + struct thermal_bank_cfg { +@@ -765,7 +758,7 @@ static struct platform_driver mtk_therma + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { +- .name = THERMAL_NAME, ++ .name = "mtk-thermal", + .of_match_table = mtk_thermal_of_match, + }, + }; diff --git a/target/linux/mediatek/patches-4.14/0200-thermal-mediatek-add-support-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0200-thermal-mediatek-add-support-for-MT7622-SoC.patch new file mode 100644 index 000000000..731bd163d --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0200-thermal-mediatek-add-support-for-MT7622-SoC.patch @@ -0,0 +1,81 @@ +From b93889b200a963acde20e559dbf51886ad6b6229 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Tue, 16 Jan 2018 23:50:48 +0800 +Subject: [PATCH 200/224] thermal: mediatek: add support for MT7622 SoC + +MT7622 SoC has built-in thermal controller with one sensing point, the +patch just is to extend the functionality of the existing logic. + +Changes v1 -> v2: rebase to 4.16-rc1 + +Signed-off-by: Sean Wang +Signed-off-by: Shunli Wang +--- + drivers/thermal/mtk_thermal.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +--- a/drivers/thermal/mtk_thermal.c ++++ b/drivers/thermal/mtk_thermal.c +@@ -153,6 +153,12 @@ + /* The number of sensing points per bank */ + #define MT2712_NUM_SENSORS_PER_ZONE 4 + ++#define MT7622_TEMP_AUXADC_CHANNEL 11 ++#define MT7622_NUM_SENSORS 1 ++#define MT7622_NUM_ZONES 1 ++#define MT7622_NUM_SENSORS_PER_ZONE 1 ++#define MT7622_TS1 0 ++ + struct mtk_thermal; + + struct thermal_bank_cfg { +@@ -242,6 +248,12 @@ static const int mt2712_adcpnp[MT2712_NU + + static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; + ++/* MT7622 thermal sensor data */ ++static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; ++static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; ++static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; ++static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; ++ + /** + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 +@@ -329,6 +341,25 @@ static const struct mtk_thermal_data mt2 + .sensor_mux_values = mt2712_mux_values, + }; + ++/* ++ * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data ++ * access. ++ */ ++static const struct mtk_thermal_data mt7622_thermal_data = { ++ .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, ++ .num_banks = MT7622_NUM_ZONES, ++ .num_sensors = MT7622_NUM_SENSORS, ++ .bank_data = { ++ { ++ .num_sensors = 1, ++ .sensors = mt7622_bank_data, ++ }, ++ }, ++ .msr = mt7622_msr, ++ .adcpnp = mt7622_adcpnp, ++ .sensor_mux_values = mt7622_mux_values, ++}; ++ + /** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller +@@ -631,6 +662,10 @@ static const struct of_device_id mtk_the + { + .compatible = "mediatek,mt2712-thermal", + .data = (void *)&mt2712_thermal_data, ++ }, ++ { ++ .compatible = "mediatek,mt7622-thermal", ++ .data = (void *)&mt7622_thermal_data, + }, { + }, + }; diff --git a/target/linux/mediatek/patches-4.14/0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch b/target/linux/mediatek/patches-4.14/0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch new file mode 100644 index 000000000..6f22dc241 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0201-dt-bindings-clock-mediatek-add-missing-required-rese.patch @@ -0,0 +1,64 @@ +From 4a1990ee249df257848f9583cef71478e3411c3e Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 28 Dec 2017 11:24:45 +0800 +Subject: [PATCH 201/224] dt-bindings: clock: mediatek: add missing required + #reset-cells + +All ethsys, pciesys and ssusbsys internally include reset controller, so +explicitly add back these missing cell definitions to related bindings +and examples. + +Signed-off-by: Sean Wang +Cc: Rob Herring +Cc: Michael Turquette +Cc: Stephen Boyd +Cc: linux-clk@vger.kernel.org +Reviewed-by: Rob Herring +--- + Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 + + Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++ + Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++ + 3 files changed, 5 insertions(+) + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt +@@ -9,6 +9,7 @@ Required Properties: + - "mediatek,mt2701-ethsys", "syscon" + - "mediatek,mt7622-ethsys", "syscon" + - #clock-cells: Must be 1 ++- #reset-cells: Must be 1 + + The ethsys controller uses the common clk binding from + Documentation/devicetree/bindings/clock/clock-bindings.txt +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +@@ -8,6 +8,7 @@ Required Properties: + - compatible: Should be: + - "mediatek,mt7622-pciesys", "syscon" + - #clock-cells: Must be 1 ++- #reset-cells: Must be 1 + + The PCIESYS controller uses the common clk binding from + Documentation/devicetree/bindings/clock/clock-bindings.txt +@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { + compatible = "mediatek,mt7622-pciesys", "syscon"; + reg = <0 0x1a100800 0 0x1000>; + #clock-cells = <1>; ++ #reset-cells = <1>; + }; +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt +@@ -8,6 +8,7 @@ Required Properties: + - compatible: Should be: + - "mediatek,mt7622-ssusbsys", "syscon" + - #clock-cells: Must be 1 ++- #reset-cells: Must be 1 + + The SSUSBSYS controller uses the common clk binding from + Documentation/devicetree/bindings/clock/clock-bindings.txt +@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; ++ #reset-cells = <1>; + }; diff --git a/target/linux/mediatek/patches-4.14/0202-mmc-dt-bindings-add-support-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0202-mmc-dt-bindings-add-support-for-MT7622-SoC.patch new file mode 100644 index 000000000..0e641b475 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0202-mmc-dt-bindings-add-support-for-MT7622-SoC.patch @@ -0,0 +1,22 @@ +From 5365d402c8c4f0ff2cf2f26cfb8f46b520719ac0 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 5 Mar 2018 14:47:26 +0800 +Subject: [PATCH 202/224] mmc: dt-bindings: add support for MT7622 SoC + +Add the devicetree binding for MT7622 SoC + +Signed-off-by: Sean Wang +--- + Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt ++++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt +@@ -12,6 +12,7 @@ Required properties: + "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 + "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 + "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 ++ "mediatek,mt7622-mmc": for MT7622 SoC + "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC + + - reg: physical base address of the controller and length diff --git a/target/linux/mediatek/patches-4.14/0203-mmc-mediatek-add-support-for-MT7622-SoC.patch b/target/linux/mediatek/patches-4.14/0203-mmc-mediatek-add-support-for-MT7622-SoC.patch new file mode 100644 index 000000000..613adbc89 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0203-mmc-mediatek-add-support-for-MT7622-SoC.patch @@ -0,0 +1,42 @@ +From 9af606beb87182120ab40563cd596a9e1cfc842b Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 2 Feb 2018 14:25:11 +0800 +Subject: [PATCH 203/224] mmc: mediatek: add support for MT7622 SoC + +Just applying the existing logic and adding its own characteristics into +the space pointed by an extra entry of struct of_device_id to have support +of MT7622 SoC. + +Signed-off-by: Chaotian Jing +Signed-off-by: Sean Wang +Tested-by: Jumin Li +--- + drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -438,11 +438,23 @@ static const struct mtk_mmc_compatible m + .enhance_rx = true, + }; + ++static const struct mtk_mmc_compatible mt7622_compat = { ++ .clk_div_bits = 12, ++ .hs400_tune = false, ++ .pad_tune_reg = MSDC_PAD_TUNE0, ++ .async_fifo = true, ++ .data_tune = true, ++ .busy_check = true, ++ .stop_clk_fix = true, ++ .enhance_rx = true, ++}; ++ + static const struct of_device_id msdc_of_ids[] = { + { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, + { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, + { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, + { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, ++ { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, + {} + }; + MODULE_DEVICE_TABLE(of, msdc_of_ids); diff --git a/target/linux/mediatek/patches-4.14/0204-dt-bindings-dmaengine-Add-MediaTek-High-Speed-DMA-co.patch b/target/linux/mediatek/patches-4.14/0204-dt-bindings-dmaengine-Add-MediaTek-High-Speed-DMA-co.patch new file mode 100644 index 000000000..b05903e9e --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0204-dt-bindings-dmaengine-Add-MediaTek-High-Speed-DMA-co.patch @@ -0,0 +1,51 @@ +From 71198859668501ef57450be07da77e9544f59f1e Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Sat, 13 May 2017 15:16:58 +0800 +Subject: [PATCH 204/224] dt-bindings: dmaengine: Add MediaTek High-Speed DMA + controller bindings + +Document the devicetree bindings for MediaTek High-Speed DMA controller +which could be found on MT7623 SoC or other similar Mediatek SoCs. + +Signed-off-by: Sean Wang +--- + .../devicetree/bindings/dma/mtk-hsdma.txt | 33 ++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + create mode 100644 Documentation/devicetree/bindings/dma/mtk-hsdma.txt + +--- /dev/null ++++ b/Documentation/devicetree/bindings/dma/mtk-hsdma.txt +@@ -0,0 +1,33 @@ ++MediaTek High-Speed DMA Controller ++================================== ++ ++This device follows the generic DMA bindings defined in dma/dma.txt. ++ ++Required properties: ++ ++- compatible: Must be one of ++ "mediatek,mt7622-hsdma": for MT7622 SoC ++ "mediatek,mt7623-hsdma": for MT7623 SoC ++- reg: Should contain the register's base address and length. ++- interrupts: Should contain a reference to the interrupt used by this ++ device. ++- clocks: Should be the clock specifiers corresponding to the entry in ++ clock-names property. ++- clock-names: Should contain "hsdma" entries. ++- power-domains: Phandle to the power domain that the device is part of ++- #dma-cells: The length of the DMA specifier, must be <1>. This one cell ++ in dmas property of a client device represents the channel ++ number. ++Example: ++ ++ hsdma: dma-controller@1b007000 { ++ compatible = "mediatek,mt7623-hsdma"; ++ reg = <0 0x1b007000 0 0x1000>; ++ interrupts = ; ++ clocks = <ðsys CLK_ETHSYS_HSDMA>; ++ clock-names = "hsdma"; ++ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; ++ #dma-cells = <1>; ++ }; ++ ++DMA clients must use the format described in dma/dma.txt file. diff --git a/target/linux/mediatek/patches-4.14/0205-dmaengine-mediatek-Add-MediaTek-High-Speed-DMA-contr.patch b/target/linux/mediatek/patches-4.14/0205-dmaengine-mediatek-Add-MediaTek-High-Speed-DMA-contr.patch new file mode 100644 index 000000000..6fd4cdef4 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0205-dmaengine-mediatek-Add-MediaTek-High-Speed-DMA-contr.patch @@ -0,0 +1,1128 @@ +From 2b97c5d7886a920adc8f7c32c2a60583475654f2 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 12 May 2017 17:05:12 +0800 +Subject: [PATCH 205/224] dmaengine: mediatek: Add MediaTek High-Speed DMA + controller for MT7622 and MT7623 SoC + +MediaTek High-Speed DMA controller (HSDMA) on MT7622 and MT7623 SoC has +a single ring is dedicated to memory-to-memory transfer through ring based +descriptor management. + +Even though there is only one physical ring available inside HSDMA, the +driver can be easily extended to the support of multiple virtual channels +processing simultaneously by means of DMA_VIRTUAL_CHANNELS effort. + +Signed-off-by: Sean Wang +Cc: Randy Dunlap +Cc: Fengguang Wu +Cc: Julia Lawall +--- + drivers/dma/Kconfig | 2 + + drivers/dma/Makefile | 1 + + drivers/dma/mediatek/Kconfig | 13 + + drivers/dma/mediatek/Makefile | 1 + + drivers/dma/mediatek/mtk-hsdma.c | 1056 ++++++++++++++++++++++++++++++++++++++ + 5 files changed, 1073 insertions(+) + create mode 100644 drivers/dma/mediatek/Kconfig + create mode 100644 drivers/dma/mediatek/Makefile + create mode 100644 drivers/dma/mediatek/mtk-hsdma.c + +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -604,6 +604,8 @@ config ZX_DMA + # driver files + source "drivers/dma/bestcomm/Kconfig" + ++source "drivers/dma/mediatek/Kconfig" ++ + source "drivers/dma/qcom/Kconfig" + + source "drivers/dma/dw/Kconfig" +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -72,5 +72,6 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o + obj-$(CONFIG_ZX_DMA) += zx_dma.o + obj-$(CONFIG_ST_FDMA) += st_fdma.o + ++obj-y += mediatek/ + obj-y += qcom/ + obj-y += xilinx/ +--- /dev/null ++++ b/drivers/dma/mediatek/Kconfig +@@ -0,0 +1,13 @@ ++ ++config MTK_HSDMA ++ tristate "MediaTek High-Speed DMA controller support" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ ---help--- ++ Enable support for High-Speed DMA controller on MediaTek ++ SoCs. ++ ++ This controller provides the channels which is dedicated to ++ memory-to-memory transfer to offload from CPU through ring- ++ based descriptor management. +--- /dev/null ++++ b/drivers/dma/mediatek/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o +--- /dev/null ++++ b/drivers/dma/mediatek/mtk-hsdma.c +@@ -0,0 +1,1056 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// Copyright (c) 2017-2018 MediaTek Inc. ++ ++/* ++ * Driver for MediaTek High-Speed DMA Controller ++ * ++ * Author: Sean Wang ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../virt-dma.h" ++ ++#define MTK_HSDMA_USEC_POLL 20 ++#define MTK_HSDMA_TIMEOUT_POLL 200000 ++#define MTK_HSDMA_DMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) ++ ++/* The default number of virtual channel */ ++#define MTK_HSDMA_NR_VCHANS 3 ++ ++/* Only one physical channel supported */ ++#define MTK_HSDMA_NR_MAX_PCHANS 1 ++ ++/* Macro for physical descriptor (PD) manipulation */ ++/* The number of PD which must be 2 of power */ ++#define MTK_DMA_SIZE 64 ++#define MTK_HSDMA_NEXT_DESP_IDX(x, y) (((x) + 1) & ((y) - 1)) ++#define MTK_HSDMA_LAST_DESP_IDX(x, y) (((x) - 1) & ((y) - 1)) ++#define MTK_HSDMA_MAX_LEN 0x3f80 ++#define MTK_HSDMA_ALIGN_SIZE 4 ++#define MTK_HSDMA_PLEN_MASK 0x3fff ++#define MTK_HSDMA_DESC_PLEN(x) (((x) & MTK_HSDMA_PLEN_MASK) << 16) ++#define MTK_HSDMA_DESC_PLEN_GET(x) (((x) >> 16) & MTK_HSDMA_PLEN_MASK) ++ ++/* Registers for underlying ring manipulation */ ++#define MTK_HSDMA_TX_BASE 0x0 ++#define MTK_HSDMA_TX_CNT 0x4 ++#define MTK_HSDMA_TX_CPU 0x8 ++#define MTK_HSDMA_TX_DMA 0xc ++#define MTK_HSDMA_RX_BASE 0x100 ++#define MTK_HSDMA_RX_CNT 0x104 ++#define MTK_HSDMA_RX_CPU 0x108 ++#define MTK_HSDMA_RX_DMA 0x10c ++ ++/* Registers for global setup */ ++#define MTK_HSDMA_GLO 0x204 ++#define MTK_HSDMA_GLO_MULTI_DMA BIT(10) ++#define MTK_HSDMA_TX_WB_DDONE BIT(6) ++#define MTK_HSDMA_BURST_64BYTES (0x2 << 4) ++#define MTK_HSDMA_GLO_RX_BUSY BIT(3) ++#define MTK_HSDMA_GLO_RX_DMA BIT(2) ++#define MTK_HSDMA_GLO_TX_BUSY BIT(1) ++#define MTK_HSDMA_GLO_TX_DMA BIT(0) ++#define MTK_HSDMA_GLO_DMA (MTK_HSDMA_GLO_TX_DMA | \ ++ MTK_HSDMA_GLO_RX_DMA) ++#define MTK_HSDMA_GLO_BUSY (MTK_HSDMA_GLO_RX_BUSY | \ ++ MTK_HSDMA_GLO_TX_BUSY) ++#define MTK_HSDMA_GLO_DEFAULT (MTK_HSDMA_GLO_TX_DMA | \ ++ MTK_HSDMA_GLO_RX_DMA | \ ++ MTK_HSDMA_TX_WB_DDONE | \ ++ MTK_HSDMA_BURST_64BYTES | \ ++ MTK_HSDMA_GLO_MULTI_DMA) ++ ++/* Registers for reset */ ++#define MTK_HSDMA_RESET 0x208 ++#define MTK_HSDMA_RST_TX BIT(0) ++#define MTK_HSDMA_RST_RX BIT(16) ++ ++/* Registers for interrupt control */ ++#define MTK_HSDMA_DLYINT 0x20c ++#define MTK_HSDMA_RXDLY_INT_EN BIT(15) ++ ++/* Interrupt fires when the pending number's more than the specified */ ++#define MTK_HSDMA_RXMAX_PINT(x) (((x) & 0x7f) << 8) ++ ++/* Interrupt fires when the pending time's more than the specified in 20 us */ ++#define MTK_HSDMA_RXMAX_PTIME(x) ((x) & 0x7f) ++#define MTK_HSDMA_DLYINT_DEFAULT (MTK_HSDMA_RXDLY_INT_EN | \ ++ MTK_HSDMA_RXMAX_PINT(20) | \ ++ MTK_HSDMA_RXMAX_PTIME(20)) ++#define MTK_HSDMA_INT_STATUS 0x220 ++#define MTK_HSDMA_INT_ENABLE 0x228 ++#define MTK_HSDMA_INT_RXDONE BIT(16) ++ ++enum mtk_hsdma_vdesc_flag { ++ MTK_HSDMA_VDESC_FINISHED = 0x01, ++}; ++ ++#define IS_MTK_HSDMA_VDESC_FINISHED(x) ((x) == MTK_HSDMA_VDESC_FINISHED) ++ ++/** ++ * struct mtk_hsdma_pdesc - This is the struct holding info describing physical ++ * descriptor (PD) and its placement must be kept at ++ * 4-bytes alignment in little endian order. ++ * @desc[1-4]: The control pad used to indicate hardware how to ++ * deal with the descriptor such as source and ++ * destination address and data length. The maximum ++ * data length each pdesc can handle is 0x3f80 bytes ++ */ ++struct mtk_hsdma_pdesc { ++ __le32 desc1; ++ __le32 desc2; ++ __le32 desc3; ++ __le32 desc4; ++} __packed __aligned(4); ++ ++/** ++ * struct mtk_hsdma_vdesc - This is the struct holding info describing virtual ++ * descriptor (VD) ++ * @vd: An instance for struct virt_dma_desc ++ * @len: The total data size device wants to move ++ * @residue: The remaining data size device will move ++ * @dest: The destination address device wants to move to ++ * @src: The source address device wants to move from ++ */ ++struct mtk_hsdma_vdesc { ++ struct virt_dma_desc vd; ++ size_t len; ++ size_t residue; ++ dma_addr_t dest; ++ dma_addr_t src; ++}; ++ ++/** ++ * struct mtk_hsdma_cb - This is the struct holding extra info required for RX ++ * ring to know what relevant VD the the PD is being ++ * mapped to. ++ * @vd: Pointer to the relevant VD. ++ * @flag: Flag indicating what action should be taken when VD ++ * is completed. ++ */ ++struct mtk_hsdma_cb { ++ struct virt_dma_desc *vd; ++ enum mtk_hsdma_vdesc_flag flag; ++}; ++ ++/** ++ * struct mtk_hsdma_ring - This struct holds info describing underlying ring ++ * space ++ * @txd: The descriptor TX ring which describes DMA source ++ * information ++ * @rxd: The descriptor RX ring which describes DMA ++ * destination information ++ * @cb: The extra information pointed at by RX ring ++ * @tphys: The physical addr of TX ring ++ * @rphys: The physical addr of RX ring ++ * @cur_tptr: Pointer to the next free descriptor used by the host ++ * @cur_rptr: Pointer to the last done descriptor by the device ++ */ ++struct mtk_hsdma_ring { ++ struct mtk_hsdma_pdesc *txd; ++ struct mtk_hsdma_pdesc *rxd; ++ struct mtk_hsdma_cb *cb; ++ dma_addr_t tphys; ++ dma_addr_t rphys; ++ u16 cur_tptr; ++ u16 cur_rptr; ++}; ++ ++/** ++ * struct mtk_hsdma_pchan - This is the struct holding info describing physical ++ * channel (PC) ++ * @ring: An instance for the underlying ring ++ * @sz_ring: Total size allocated for the ring ++ * @nr_free: Total number of free rooms in the ring. It would ++ * be accessed and updated frequently between IRQ ++ * context and user context to reflect whether ring ++ * can accept requests from VD. ++ */ ++struct mtk_hsdma_pchan { ++ struct mtk_hsdma_ring ring; ++ size_t sz_ring; ++ atomic_t nr_free; ++}; ++ ++/** ++ * struct mtk_hsdma_vchan - This is the struct holding info describing virtual ++ * channel (VC) ++ * @vc: An instance for struct virt_dma_chan ++ * @issue_completion: The wait for all issued descriptors completited ++ * @issue_synchronize: Bool indicating channel synchronization starts ++ * @desc_hw_processing: List those descriptors the hardware is processing, ++ * which is protected by vc.lock ++ */ ++struct mtk_hsdma_vchan { ++ struct virt_dma_chan vc; ++ struct completion issue_completion; ++ bool issue_synchronize; ++ struct list_head desc_hw_processing; ++}; ++ ++/** ++ * struct mtk_hsdma_soc - This is the struct holding differences among SoCs ++ * @ddone: Bit mask for DDONE ++ * @ls0: Bit mask for LS0 ++ */ ++struct mtk_hsdma_soc { ++ __le32 ddone; ++ __le32 ls0; ++}; ++ ++/** ++ * struct mtk_hsdma_device - This is the struct holding info describing HSDMA ++ * device ++ * @ddev: An instance for struct dma_device ++ * @base: The mapped register I/O base ++ * @clk: The clock that device internal is using ++ * @irq: The IRQ that device are using ++ * @dma_requests: The number of VCs the device supports to ++ * @vc: The pointer to all available VCs ++ * @pc: The pointer to the underlying PC ++ * @pc_refcnt: Track how many VCs are using the PC ++ * @lock: Lock protect agaisting multiple VCs access PC ++ * @soc: The pointer to area holding differences among ++ * vaious platform ++ */ ++struct mtk_hsdma_device { ++ struct dma_device ddev; ++ void __iomem *base; ++ struct clk *clk; ++ u32 irq; ++ ++ u32 dma_requests; ++ struct mtk_hsdma_vchan *vc; ++ struct mtk_hsdma_pchan *pc; ++ refcount_t pc_refcnt; ++ ++ /* Lock used to protect against multiple VCs access PC */ ++ spinlock_t lock; ++ ++ const struct mtk_hsdma_soc *soc; ++}; ++ ++static struct mtk_hsdma_device *to_hsdma_dev(struct dma_chan *chan) ++{ ++ return container_of(chan->device, struct mtk_hsdma_device, ddev); ++} ++ ++static inline struct mtk_hsdma_vchan *to_hsdma_vchan(struct dma_chan *chan) ++{ ++ return container_of(chan, struct mtk_hsdma_vchan, vc.chan); ++} ++ ++static struct mtk_hsdma_vdesc *to_hsdma_vdesc(struct virt_dma_desc *vd) ++{ ++ return container_of(vd, struct mtk_hsdma_vdesc, vd); ++} ++ ++static struct device *hsdma2dev(struct mtk_hsdma_device *hsdma) ++{ ++ return hsdma->ddev.dev; ++} ++ ++static u32 mtk_dma_read(struct mtk_hsdma_device *hsdma, u32 reg) ++{ ++ return readl(hsdma->base + reg); ++} ++ ++static void mtk_dma_write(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) ++{ ++ writel(val, hsdma->base + reg); ++} ++ ++static void mtk_dma_rmw(struct mtk_hsdma_device *hsdma, u32 reg, ++ u32 mask, u32 set) ++{ ++ u32 val; ++ ++ val = mtk_dma_read(hsdma, reg); ++ val &= ~mask; ++ val |= set; ++ mtk_dma_write(hsdma, reg, val); ++} ++ ++static void mtk_dma_set(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) ++{ ++ mtk_dma_rmw(hsdma, reg, 0, val); ++} ++ ++static void mtk_dma_clr(struct mtk_hsdma_device *hsdma, u32 reg, u32 val) ++{ ++ mtk_dma_rmw(hsdma, reg, val, 0); ++} ++ ++static void mtk_hsdma_vdesc_free(struct virt_dma_desc *vd) ++{ ++ kfree(container_of(vd, struct mtk_hsdma_vdesc, vd)); ++} ++ ++static int mtk_hsdma_busy_wait(struct mtk_hsdma_device *hsdma) ++{ ++ u32 status = 0; ++ ++ return readl_poll_timeout(hsdma->base + MTK_HSDMA_GLO, status, ++ !(status & MTK_HSDMA_GLO_BUSY), ++ MTK_HSDMA_USEC_POLL, ++ MTK_HSDMA_TIMEOUT_POLL); ++} ++ ++static int mtk_hsdma_alloc_pchan(struct mtk_hsdma_device *hsdma, ++ struct mtk_hsdma_pchan *pc) ++{ ++ struct mtk_hsdma_ring *ring = &pc->ring; ++ int err; ++ ++ memset(pc, 0, sizeof(*pc)); ++ ++ /* ++ * Allocate ring space where [0 ... MTK_DMA_SIZE - 1] is for TX ring ++ * and [MTK_DMA_SIZE ... 2 * MTK_DMA_SIZE - 1] is for RX ring. ++ */ ++ pc->sz_ring = 2 * MTK_DMA_SIZE * sizeof(*ring->txd); ++ ring->txd = dma_zalloc_coherent(hsdma2dev(hsdma), pc->sz_ring, ++ &ring->tphys, GFP_NOWAIT); ++ if (!ring->txd) ++ return -ENOMEM; ++ ++ ring->rxd = &ring->txd[MTK_DMA_SIZE]; ++ ring->rphys = ring->tphys + MTK_DMA_SIZE * sizeof(*ring->txd); ++ ring->cur_tptr = 0; ++ ring->cur_rptr = MTK_DMA_SIZE - 1; ++ ++ ring->cb = kcalloc(MTK_DMA_SIZE, sizeof(*ring->cb), GFP_NOWAIT); ++ if (!ring->cb) { ++ err = -ENOMEM; ++ goto err_free_dma; ++ } ++ ++ atomic_set(&pc->nr_free, MTK_DMA_SIZE - 1); ++ ++ /* Disable HSDMA and wait for the completion */ ++ mtk_dma_clr(hsdma, MTK_HSDMA_GLO, MTK_HSDMA_GLO_DMA); ++ err = mtk_hsdma_busy_wait(hsdma); ++ if (err) ++ goto err_free_cb; ++ ++ /* Reset */ ++ mtk_dma_set(hsdma, MTK_HSDMA_RESET, ++ MTK_HSDMA_RST_TX | MTK_HSDMA_RST_RX); ++ mtk_dma_clr(hsdma, MTK_HSDMA_RESET, ++ MTK_HSDMA_RST_TX | MTK_HSDMA_RST_RX); ++ ++ /* Setup HSDMA initial pointer in the ring */ ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_BASE, ring->tphys); ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_CNT, MTK_DMA_SIZE); ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_CPU, ring->cur_tptr); ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_DMA, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_BASE, ring->rphys); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_CNT, MTK_DMA_SIZE); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_CPU, ring->cur_rptr); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_DMA, 0); ++ ++ /* Enable HSDMA */ ++ mtk_dma_set(hsdma, MTK_HSDMA_GLO, MTK_HSDMA_GLO_DMA); ++ ++ /* Setup delayed interrupt */ ++ mtk_dma_write(hsdma, MTK_HSDMA_DLYINT, MTK_HSDMA_DLYINT_DEFAULT); ++ ++ /* Enable interrupt */ ++ mtk_dma_set(hsdma, MTK_HSDMA_INT_ENABLE, MTK_HSDMA_INT_RXDONE); ++ ++ return 0; ++ ++err_free_cb: ++ kfree(ring->cb); ++ ++err_free_dma: ++ dma_free_coherent(hsdma2dev(hsdma), ++ pc->sz_ring, ring->txd, ring->tphys); ++ return err; ++} ++ ++static void mtk_hsdma_free_pchan(struct mtk_hsdma_device *hsdma, ++ struct mtk_hsdma_pchan *pc) ++{ ++ struct mtk_hsdma_ring *ring = &pc->ring; ++ ++ /* Disable HSDMA and then wait for the completion */ ++ mtk_dma_clr(hsdma, MTK_HSDMA_GLO, MTK_HSDMA_GLO_DMA); ++ mtk_hsdma_busy_wait(hsdma); ++ ++ /* Reset pointer in the ring */ ++ mtk_dma_clr(hsdma, MTK_HSDMA_INT_ENABLE, MTK_HSDMA_INT_RXDONE); ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_BASE, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_CNT, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_CPU, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_BASE, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_CNT, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_CPU, MTK_DMA_SIZE - 1); ++ ++ kfree(ring->cb); ++ ++ dma_free_coherent(hsdma2dev(hsdma), ++ pc->sz_ring, ring->txd, ring->tphys); ++} ++ ++static int mtk_hsdma_issue_pending_vdesc(struct mtk_hsdma_device *hsdma, ++ struct mtk_hsdma_pchan *pc, ++ struct mtk_hsdma_vdesc *hvd) ++{ ++ struct mtk_hsdma_ring *ring = &pc->ring; ++ struct mtk_hsdma_pdesc *txd, *rxd; ++ u16 reserved, prev, tlen, num_sgs; ++ unsigned long flags; ++ ++ /* Protect against PC is accessed by multiple VCs simultaneously */ ++ spin_lock_irqsave(&hsdma->lock, flags); ++ ++ /* ++ * Reserve rooms, where pc->nr_free is used to track how many free ++ * rooms in the ring being updated in user and IRQ context. ++ */ ++ num_sgs = DIV_ROUND_UP(hvd->len, MTK_HSDMA_MAX_LEN); ++ reserved = min_t(u16, num_sgs, atomic_read(&pc->nr_free)); ++ ++ if (!reserved) { ++ spin_unlock_irqrestore(&hsdma->lock, flags); ++ return -ENOSPC; ++ } ++ ++ atomic_sub(reserved, &pc->nr_free); ++ ++ while (reserved--) { ++ /* Limit size by PD capability for valid data moving */ ++ tlen = (hvd->len > MTK_HSDMA_MAX_LEN) ? ++ MTK_HSDMA_MAX_LEN : hvd->len; ++ ++ /* ++ * Setup PDs using the remaining VD info mapped on those ++ * reserved rooms. And since RXD is shared memory between the ++ * host and the device allocated by dma_alloc_coherent call, ++ * the helper macro WRITE_ONCE can ensure the data written to ++ * RAM would really happens. ++ */ ++ txd = &ring->txd[ring->cur_tptr]; ++ WRITE_ONCE(txd->desc1, hvd->src); ++ WRITE_ONCE(txd->desc2, ++ hsdma->soc->ls0 | MTK_HSDMA_DESC_PLEN(tlen)); ++ ++ rxd = &ring->rxd[ring->cur_tptr]; ++ WRITE_ONCE(rxd->desc1, hvd->dest); ++ WRITE_ONCE(rxd->desc2, MTK_HSDMA_DESC_PLEN(tlen)); ++ ++ /* Associate VD, the PD belonged to */ ++ ring->cb[ring->cur_tptr].vd = &hvd->vd; ++ ++ /* Move forward the pointer of TX ring */ ++ ring->cur_tptr = MTK_HSDMA_NEXT_DESP_IDX(ring->cur_tptr, ++ MTK_DMA_SIZE); ++ ++ /* Update VD with remaining data */ ++ hvd->src += tlen; ++ hvd->dest += tlen; ++ hvd->len -= tlen; ++ } ++ ++ /* ++ * Tagging flag for the last PD for VD will be responsible for ++ * completing VD. ++ */ ++ if (!hvd->len) { ++ prev = MTK_HSDMA_LAST_DESP_IDX(ring->cur_tptr, MTK_DMA_SIZE); ++ ring->cb[prev].flag = MTK_HSDMA_VDESC_FINISHED; ++ } ++ ++ /* Ensure all changes indeed done before we're going on */ ++ wmb(); ++ ++ /* ++ * Updating into hardware the pointer of TX ring lets HSDMA to take ++ * action for those pending PDs. ++ */ ++ mtk_dma_write(hsdma, MTK_HSDMA_TX_CPU, ring->cur_tptr); ++ ++ spin_unlock_irqrestore(&hsdma->lock, flags); ++ ++ return 0; ++} ++ ++static void mtk_hsdma_issue_vchan_pending(struct mtk_hsdma_device *hsdma, ++ struct mtk_hsdma_vchan *hvc) ++{ ++ struct virt_dma_desc *vd, *vd2; ++ int err; ++ ++ lockdep_assert_held(&hvc->vc.lock); ++ ++ list_for_each_entry_safe(vd, vd2, &hvc->vc.desc_issued, node) { ++ struct mtk_hsdma_vdesc *hvd; ++ ++ hvd = to_hsdma_vdesc(vd); ++ ++ /* Map VD into PC and all VCs shares a single PC */ ++ err = mtk_hsdma_issue_pending_vdesc(hsdma, hsdma->pc, hvd); ++ ++ /* ++ * Move VD from desc_issued to desc_hw_processing when entire ++ * VD is fit into available PDs. Otherwise, the uncompleted ++ * VDs would stay in list desc_issued and then restart the ++ * processing as soon as possible once underlying ring space ++ * got freed. ++ */ ++ if (err == -ENOSPC || hvd->len > 0) ++ break; ++ ++ /* ++ * The extra list desc_hw_processing is used because ++ * hardware can't provide sufficient information allowing us ++ * to know what VDs are still working on the underlying ring. ++ * Through the additional list, it can help us to implement ++ * terminate_all, residue calculation and such thing needed ++ * to know detail descriptor status on the hardware. ++ */ ++ list_move_tail(&vd->node, &hvc->desc_hw_processing); ++ } ++} ++ ++static void mtk_hsdma_free_rooms_in_ring(struct mtk_hsdma_device *hsdma) ++{ ++ struct mtk_hsdma_vchan *hvc; ++ struct mtk_hsdma_pdesc *rxd; ++ struct mtk_hsdma_vdesc *hvd; ++ struct mtk_hsdma_pchan *pc; ++ struct mtk_hsdma_cb *cb; ++ int i = MTK_DMA_SIZE; ++ __le32 desc2; ++ u32 status; ++ u16 next; ++ ++ /* Read IRQ status */ ++ status = mtk_dma_read(hsdma, MTK_HSDMA_INT_STATUS); ++ if (unlikely(!(status & MTK_HSDMA_INT_RXDONE))) ++ goto rx_done; ++ ++ pc = hsdma->pc; ++ ++ /* ++ * Using a fail-safe loop with iterations of up to MTK_DMA_SIZE to ++ * reclaim these finished descriptors: The most number of PDs the ISR ++ * can handle at one time shouldn't be more than MTK_DMA_SIZE so we ++ * take it as limited count instead of just using a dangerous infinite ++ * poll. ++ */ ++ while (i--) { ++ next = MTK_HSDMA_NEXT_DESP_IDX(pc->ring.cur_rptr, ++ MTK_DMA_SIZE); ++ rxd = &pc->ring.rxd[next]; ++ ++ /* ++ * If MTK_HSDMA_DESC_DDONE is no specified, that means data ++ * moving for the PD is still under going. ++ */ ++ desc2 = READ_ONCE(rxd->desc2); ++ if (!(desc2 & hsdma->soc->ddone)) ++ break; ++ ++ cb = &pc->ring.cb[next]; ++ if (unlikely(!cb->vd)) { ++ dev_err(hsdma2dev(hsdma), "cb->vd cannot be null\n"); ++ break; ++ } ++ ++ /* Update residue of VD the associated PD belonged to */ ++ hvd = to_hsdma_vdesc(cb->vd); ++ hvd->residue -= MTK_HSDMA_DESC_PLEN_GET(rxd->desc2); ++ ++ /* Complete VD until the relevant last PD is finished */ ++ if (IS_MTK_HSDMA_VDESC_FINISHED(cb->flag)) { ++ hvc = to_hsdma_vchan(cb->vd->tx.chan); ++ ++ spin_lock(&hvc->vc.lock); ++ ++ /* Remove VD from list desc_hw_processing */ ++ list_del(&cb->vd->node); ++ ++ /* Add VD into list desc_completed */ ++ vchan_cookie_complete(cb->vd); ++ ++ if (hvc->issue_synchronize && ++ list_empty(&hvc->desc_hw_processing)) { ++ complete(&hvc->issue_completion); ++ hvc->issue_synchronize = false; ++ } ++ spin_unlock(&hvc->vc.lock); ++ ++ cb->flag = 0; ++ } ++ ++ cb->vd = 0; ++ ++ /* ++ * Recycle the RXD with the helper WRITE_ONCE that can ensure ++ * data written into RAM would really happens. ++ */ ++ WRITE_ONCE(rxd->desc1, 0); ++ WRITE_ONCE(rxd->desc2, 0); ++ pc->ring.cur_rptr = next; ++ ++ /* Release rooms */ ++ atomic_inc(&pc->nr_free); ++ } ++ ++ /* Ensure all changes indeed done before we're going on */ ++ wmb(); ++ ++ /* Update CPU pointer for those completed PDs */ ++ mtk_dma_write(hsdma, MTK_HSDMA_RX_CPU, pc->ring.cur_rptr); ++ ++ /* ++ * Acking the pending IRQ allows hardware no longer to keep the used ++ * IRQ line in certain trigger state when software has completed all ++ * the finished physical descriptors. ++ */ ++ if (atomic_read(&pc->nr_free) >= MTK_DMA_SIZE - 1) ++ mtk_dma_write(hsdma, MTK_HSDMA_INT_STATUS, status); ++ ++ /* ASAP handles pending VDs in all VCs after freeing some rooms */ ++ for (i = 0; i < hsdma->dma_requests; i++) { ++ hvc = &hsdma->vc[i]; ++ spin_lock(&hvc->vc.lock); ++ mtk_hsdma_issue_vchan_pending(hsdma, hvc); ++ spin_unlock(&hvc->vc.lock); ++ } ++ ++rx_done: ++ /* All completed PDs are cleaned up, so enable interrupt again */ ++ mtk_dma_set(hsdma, MTK_HSDMA_INT_ENABLE, MTK_HSDMA_INT_RXDONE); ++} ++ ++static irqreturn_t mtk_hsdma_irq(int irq, void *devid) ++{ ++ struct mtk_hsdma_device *hsdma = devid; ++ ++ /* ++ * Disable interrupt until all completed PDs are cleaned up in ++ * mtk_hsdma_free_rooms call. ++ */ ++ mtk_dma_clr(hsdma, MTK_HSDMA_INT_ENABLE, MTK_HSDMA_INT_RXDONE); ++ ++ mtk_hsdma_free_rooms_in_ring(hsdma); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct virt_dma_desc *mtk_hsdma_find_active_desc(struct dma_chan *c, ++ dma_cookie_t cookie) ++{ ++ struct mtk_hsdma_vchan *hvc = to_hsdma_vchan(c); ++ struct virt_dma_desc *vd; ++ ++ list_for_each_entry(vd, &hvc->desc_hw_processing, node) ++ if (vd->tx.cookie == cookie) ++ return vd; ++ ++ list_for_each_entry(vd, &hvc->vc.desc_issued, node) ++ if (vd->tx.cookie == cookie) ++ return vd; ++ ++ return NULL; ++} ++ ++static enum dma_status mtk_hsdma_tx_status(struct dma_chan *c, ++ dma_cookie_t cookie, ++ struct dma_tx_state *txstate) ++{ ++ struct mtk_hsdma_vchan *hvc = to_hsdma_vchan(c); ++ struct mtk_hsdma_vdesc *hvd; ++ struct virt_dma_desc *vd; ++ enum dma_status ret; ++ unsigned long flags; ++ size_t bytes = 0; ++ ++ ret = dma_cookie_status(c, cookie, txstate); ++ if (ret == DMA_COMPLETE || !txstate) ++ return ret; ++ ++ spin_lock_irqsave(&hvc->vc.lock, flags); ++ vd = mtk_hsdma_find_active_desc(c, cookie); ++ spin_unlock_irqrestore(&hvc->vc.lock, flags); ++ ++ if (vd) { ++ hvd = to_hsdma_vdesc(vd); ++ bytes = hvd->residue; ++ } ++ ++ dma_set_residue(txstate, bytes); ++ ++ return ret; ++} ++ ++static void mtk_hsdma_issue_pending(struct dma_chan *c) ++{ ++ struct mtk_hsdma_device *hsdma = to_hsdma_dev(c); ++ struct mtk_hsdma_vchan *hvc = to_hsdma_vchan(c); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hvc->vc.lock, flags); ++ ++ if (vchan_issue_pending(&hvc->vc)) ++ mtk_hsdma_issue_vchan_pending(hsdma, hvc); ++ ++ spin_unlock_irqrestore(&hvc->vc.lock, flags); ++} ++ ++static struct dma_async_tx_descriptor * ++mtk_hsdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, ++ dma_addr_t src, size_t len, unsigned long flags) ++{ ++ struct mtk_hsdma_vdesc *hvd; ++ ++ hvd = kzalloc(sizeof(*hvd), GFP_NOWAIT); ++ if (!hvd) ++ return NULL; ++ ++ hvd->len = len; ++ hvd->residue = len; ++ hvd->src = src; ++ hvd->dest = dest; ++ ++ return vchan_tx_prep(to_virt_chan(c), &hvd->vd, flags); ++} ++ ++static int mtk_hsdma_free_inactive_desc(struct dma_chan *c) ++{ ++ struct virt_dma_chan *vc = to_virt_chan(c); ++ unsigned long flags; ++ LIST_HEAD(head); ++ ++ spin_lock_irqsave(&vc->lock, flags); ++ list_splice_tail_init(&vc->desc_allocated, &head); ++ list_splice_tail_init(&vc->desc_submitted, &head); ++ list_splice_tail_init(&vc->desc_issued, &head); ++ spin_unlock_irqrestore(&vc->lock, flags); ++ ++ /* At the point, we don't expect users put descriptor into VC again */ ++ vchan_dma_desc_free_list(vc, &head); ++ ++ return 0; ++} ++ ++static void mtk_hsdma_free_active_desc(struct dma_chan *c) ++{ ++ struct mtk_hsdma_vchan *hvc = to_hsdma_vchan(c); ++ bool sync_needed = false; ++ ++ /* ++ * Once issue_synchronize is being set, which means once the hardware ++ * consumes all descriptors for the channel in the ring, the ++ * synchronization must be be notified immediately it is completed. ++ */ ++ spin_lock(&hvc->vc.lock); ++ if (!list_empty(&hvc->desc_hw_processing)) { ++ hvc->issue_synchronize = true; ++ sync_needed = true; ++ } ++ spin_unlock(&hvc->vc.lock); ++ ++ if (sync_needed) ++ wait_for_completion(&hvc->issue_completion); ++ /* ++ * At the point, we expect that all remaining descriptors in the ring ++ * for the channel should be all processing done. ++ */ ++ WARN_ONCE(!list_empty(&hvc->desc_hw_processing), ++ "Desc pending still in list desc_hw_processing\n"); ++ ++ /* Free all descriptors in list desc_completed */ ++ vchan_synchronize(&hvc->vc); ++ ++ WARN_ONCE(!list_empty(&hvc->vc.desc_completed), ++ "Desc pending still in list desc_completed\n"); ++} ++ ++static int mtk_hsdma_terminate_all(struct dma_chan *c) ++{ ++ /* ++ * Free pending descriptors not processed yet by hardware that have ++ * previously been submitted to the channel. ++ */ ++ mtk_hsdma_free_inactive_desc(c); ++ ++ /* ++ * However, the DMA engine doesn't provide any way to stop these ++ * descriptors being processed currently by hardware. The only way is ++ * to just waiting until these descriptors are all processed completely ++ * through mtk_hsdma_free_active_desc call. ++ */ ++ mtk_hsdma_free_active_desc(c); ++ ++ return 0; ++} ++ ++static int mtk_hsdma_alloc_chan_resources(struct dma_chan *c) ++{ ++ struct mtk_hsdma_device *hsdma = to_hsdma_dev(c); ++ int err; ++ ++ /* ++ * Since HSDMA has only one PC, the resource for PC is being allocated ++ * when the first VC is being created and the other VCs would run on ++ * the same PC. ++ */ ++ if (!refcount_read(&hsdma->pc_refcnt)) { ++ err = mtk_hsdma_alloc_pchan(hsdma, hsdma->pc); ++ if (err) ++ return err; ++ /* ++ * refcount_inc would complain increment on 0; use-after-free. ++ * Thus, we need to explicitly set it as 1 initially. ++ */ ++ refcount_set(&hsdma->pc_refcnt, 1); ++ } else { ++ refcount_inc(&hsdma->pc_refcnt); ++ } ++ ++ return 0; ++} ++ ++static void mtk_hsdma_free_chan_resources(struct dma_chan *c) ++{ ++ struct mtk_hsdma_device *hsdma = to_hsdma_dev(c); ++ ++ /* Free all descriptors in all lists on the VC */ ++ mtk_hsdma_terminate_all(c); ++ ++ /* The resource for PC is not freed until all the VCs are destroyed */ ++ if (!refcount_dec_and_test(&hsdma->pc_refcnt)) ++ return; ++ ++ mtk_hsdma_free_pchan(hsdma, hsdma->pc); ++} ++ ++static int mtk_hsdma_hw_init(struct mtk_hsdma_device *hsdma) ++{ ++ int err; ++ ++ pm_runtime_enable(hsdma2dev(hsdma)); ++ pm_runtime_get_sync(hsdma2dev(hsdma)); ++ ++ err = clk_prepare_enable(hsdma->clk); ++ if (err) ++ return err; ++ ++ mtk_dma_write(hsdma, MTK_HSDMA_INT_ENABLE, 0); ++ mtk_dma_write(hsdma, MTK_HSDMA_GLO, MTK_HSDMA_GLO_DEFAULT); ++ ++ return 0; ++} ++ ++static int mtk_hsdma_hw_deinit(struct mtk_hsdma_device *hsdma) ++{ ++ mtk_dma_write(hsdma, MTK_HSDMA_GLO, 0); ++ ++ clk_disable_unprepare(hsdma->clk); ++ ++ pm_runtime_put_sync(hsdma2dev(hsdma)); ++ pm_runtime_disable(hsdma2dev(hsdma)); ++ ++ return 0; ++} ++ ++static const struct mtk_hsdma_soc mt7623_soc = { ++ .ddone = BIT(31), ++ .ls0 = BIT(30), ++}; ++ ++static const struct mtk_hsdma_soc mt7622_soc = { ++ .ddone = BIT(15), ++ .ls0 = BIT(14), ++}; ++ ++static const struct of_device_id mtk_hsdma_match[] = { ++ { .compatible = "mediatek,mt7623-hsdma", .data = &mt7623_soc}, ++ { .compatible = "mediatek,mt7622-hsdma", .data = &mt7622_soc}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, mtk_hsdma_match); ++ ++static int mtk_hsdma_probe(struct platform_device *pdev) ++{ ++ struct mtk_hsdma_device *hsdma; ++ struct mtk_hsdma_vchan *vc; ++ struct dma_device *dd; ++ struct resource *res; ++ int i, err; ++ ++ hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL); ++ if (!hsdma) ++ return -ENOMEM; ++ ++ dd = &hsdma->ddev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ hsdma->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(hsdma->base)) ++ return PTR_ERR(hsdma->base); ++ ++ hsdma->soc = of_device_get_match_data(&pdev->dev); ++ if (!hsdma->soc) { ++ dev_err(&pdev->dev, "No device match found\n"); ++ return -ENODEV; ++ } ++ ++ hsdma->clk = devm_clk_get(&pdev->dev, "hsdma"); ++ if (IS_ERR(hsdma->clk)) { ++ dev_err(&pdev->dev, "No clock for %s\n", ++ dev_name(&pdev->dev)); ++ return PTR_ERR(hsdma->clk); ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "No irq resource for %s\n", ++ dev_name(&pdev->dev)); ++ return -EINVAL; ++ } ++ hsdma->irq = res->start; ++ ++ refcount_set(&hsdma->pc_refcnt, 0); ++ spin_lock_init(&hsdma->lock); ++ ++ dma_cap_set(DMA_MEMCPY, dd->cap_mask); ++ ++ dd->copy_align = MTK_HSDMA_ALIGN_SIZE; ++ dd->device_alloc_chan_resources = mtk_hsdma_alloc_chan_resources; ++ dd->device_free_chan_resources = mtk_hsdma_free_chan_resources; ++ dd->device_tx_status = mtk_hsdma_tx_status; ++ dd->device_issue_pending = mtk_hsdma_issue_pending; ++ dd->device_prep_dma_memcpy = mtk_hsdma_prep_dma_memcpy; ++ dd->device_terminate_all = mtk_hsdma_terminate_all; ++ dd->src_addr_widths = MTK_HSDMA_DMA_BUSWIDTHS; ++ dd->dst_addr_widths = MTK_HSDMA_DMA_BUSWIDTHS; ++ dd->directions = BIT(DMA_MEM_TO_MEM); ++ dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; ++ dd->dev = &pdev->dev; ++ INIT_LIST_HEAD(&dd->channels); ++ ++ hsdma->dma_requests = MTK_HSDMA_NR_VCHANS; ++ if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node, ++ "dma-requests", ++ &hsdma->dma_requests)) { ++ dev_info(&pdev->dev, ++ "Using %u as missing dma-requests property\n", ++ MTK_HSDMA_NR_VCHANS); ++ } ++ ++ hsdma->pc = devm_kcalloc(&pdev->dev, MTK_HSDMA_NR_MAX_PCHANS, ++ sizeof(*hsdma->pc), GFP_KERNEL); ++ if (!hsdma->pc) ++ return -ENOMEM; ++ ++ hsdma->vc = devm_kcalloc(&pdev->dev, hsdma->dma_requests, ++ sizeof(*hsdma->vc), GFP_KERNEL); ++ if (!hsdma->vc) ++ return -ENOMEM; ++ ++ for (i = 0; i < hsdma->dma_requests; i++) { ++ vc = &hsdma->vc[i]; ++ vc->vc.desc_free = mtk_hsdma_vdesc_free; ++ vchan_init(&vc->vc, dd); ++ init_completion(&vc->issue_completion); ++ INIT_LIST_HEAD(&vc->desc_hw_processing); ++ } ++ ++ err = dma_async_device_register(dd); ++ if (err) ++ return err; ++ ++ err = of_dma_controller_register(pdev->dev.of_node, ++ of_dma_xlate_by_chan_id, hsdma); ++ if (err) { ++ dev_err(&pdev->dev, ++ "MediaTek HSDMA OF registration failed %d\n", err); ++ goto err_unregister; ++ } ++ ++ mtk_hsdma_hw_init(hsdma); ++ ++ err = devm_request_irq(&pdev->dev, hsdma->irq, ++ mtk_hsdma_irq, 0, ++ dev_name(&pdev->dev), hsdma); ++ if (err) { ++ dev_err(&pdev->dev, ++ "request_irq failed with err %d\n", err); ++ goto err_unregister; ++ } ++ ++ platform_set_drvdata(pdev, hsdma); ++ ++ dev_info(&pdev->dev, "MediaTek HSDMA driver registered\n"); ++ ++ return 0; ++ ++err_unregister: ++ dma_async_device_unregister(dd); ++ ++ return err; ++} ++ ++static int mtk_hsdma_remove(struct platform_device *pdev) ++{ ++ struct mtk_hsdma_device *hsdma = platform_get_drvdata(pdev); ++ struct mtk_hsdma_vchan *vc; ++ int i; ++ ++ /* Kill VC task */ ++ for (i = 0; i < hsdma->dma_requests; i++) { ++ vc = &hsdma->vc[i]; ++ ++ list_del(&vc->vc.chan.device_node); ++ tasklet_kill(&vc->vc.task); ++ } ++ ++ /* Disable DMA interrupt */ ++ mtk_dma_write(hsdma, MTK_HSDMA_INT_ENABLE, 0); ++ ++ /* Waits for any pending IRQ handlers to complete */ ++ synchronize_irq(hsdma->irq); ++ ++ /* Disable hardware */ ++ mtk_hsdma_hw_deinit(hsdma); ++ ++ dma_async_device_unregister(&hsdma->ddev); ++ of_dma_controller_free(pdev->dev.of_node); ++ ++ return 0; ++} ++ ++static struct platform_driver mtk_hsdma_driver = { ++ .probe = mtk_hsdma_probe, ++ .remove = mtk_hsdma_remove, ++ .driver = { ++ .name = KBUILD_MODNAME, ++ .of_match_table = mtk_hsdma_match, ++ }, ++}; ++module_platform_driver(mtk_hsdma_driver); ++ ++MODULE_DESCRIPTION("MediaTek High-Speed DMA Controller Driver"); ++MODULE_AUTHOR("Sean Wang "); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/mediatek/patches-4.14/0206-dt-bindings-clock-mediatek-update-audsys-documentati.patch b/target/linux/mediatek/patches-4.14/0206-dt-bindings-clock-mediatek-update-audsys-documentati.patch new file mode 100644 index 000000000..649a74d1a --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0206-dt-bindings-clock-mediatek-update-audsys-documentati.patch @@ -0,0 +1,45 @@ +From e6d9c3121f2a8b92bd6202d6a32e7d428990d7d7 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 6 Mar 2018 17:09:29 +0800 +Subject: [PATCH 206/224] dt-bindings: clock: mediatek: update audsys + documentation to adapt MFD device + +The MediaTek audio hardware block that exposes functionalities that are +handled by separate subsystems in the kernel. These functions are all +mapped somewhere at 0x112xxxxx, and there are some control bits are mixed +up with other functions within the same registers. + +This patch modifies example to illustrate child nodes. + +Signed-off-by: Ryder Lee +--- + .../bindings/arm/mediatek/mediatek,audsys.txt | 19 ++++++++++++++----- + 1 file changed, 14 insertions(+), 5 deletions(-) + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +@@ -13,10 +13,19 @@ The AUDSYS controller uses the common cl + Documentation/devicetree/bindings/clock/clock-bindings.txt + The available clocks are defined in dt-bindings/clock/mt*-clk.h. + ++Required sub-nodes: ++------- ++For common binding part and usage, refer to ++../sonud/mt2701-afe-pcm.txt. ++ + Example: + +-audsys: audsys@11220000 { +- compatible = "mediatek,mt7622-audsys", "syscon"; +- reg = <0 0x11220000 0 0x1000>; +- #clock-cells = <1>; +-}; ++ audsys: clock-controller@11220000 { ++ compatible = "mediatek,mt7622-audsys", "syscon"; ++ reg = <0 0x11220000 0 0x2000>; ++ #clock-cells = <1>; ++ ++ afe: audio-controller { ++ ... ++ }; ++ }; diff --git a/target/linux/mediatek/patches-4.14/0207-dt-bindings-clock-mediatek-add-audsys-support-for-MT.patch b/target/linux/mediatek/patches-4.14/0207-dt-bindings-clock-mediatek-add-audsys-support-for-MT.patch new file mode 100644 index 000000000..fde11b923 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0207-dt-bindings-clock-mediatek-add-audsys-support-for-MT.patch @@ -0,0 +1,23 @@ +From 301de0fca7698f1ed5ed34fa7c082c3ae62d1e61 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 6 Mar 2018 17:09:30 +0800 +Subject: [PATCH 207/224] dt-bindings: clock: mediatek: add audsys support for + MT2701 + +This patch adds a compatible string for MT2701. + +Signed-off-by: Ryder Lee +--- + Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt | 1 + + 1 file changed, 1 insertion(+) + +--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt ++++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +@@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides + Required Properties: + + - compatible: Should be one of: ++ - "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt7622-audsys", "syscon" + - #clock-cells: Must be 1 + diff --git a/target/linux/mediatek/patches-4.14/0208-clk-mediatek-update-missing-clock-data-for-MT7622-au.patch b/target/linux/mediatek/patches-4.14/0208-clk-mediatek-update-missing-clock-data-for-MT7622-au.patch new file mode 100644 index 000000000..d396bd93b --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0208-clk-mediatek-update-missing-clock-data-for-MT7622-au.patch @@ -0,0 +1,38 @@ +From 0725349768e96542ef06efbd87925a8603cba16a Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 6 Mar 2018 17:09:26 +0800 +Subject: [PATCH 208/224] clk: mediatek: update missing clock data for MT7622 + audsys + +Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys. + +Signed-off-by: Ryder Lee +Reviewed-by: Rob Herring +Reviewed-by: Matthias Brugger +--- + drivers/clk/mediatek/clk-mt7622-aud.c | 1 + + include/dt-bindings/clock/mt7622-clk.h | 3 ++- + 2 files changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/clk/mediatek/clk-mt7622-aud.c ++++ b/drivers/clk/mediatek/clk-mt7622-aud.c +@@ -106,6 +106,7 @@ static const struct mtk_gate audio_clks[ + GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20), + GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21), + GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22), ++ GATE_AUDIO1(CLK_AUDIO_AFE_CONN, "audio_afe_conn", "a1sys_hp_sel", 23), + /* AUDIO2 */ + GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0), + GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1), +--- a/include/dt-bindings/clock/mt7622-clk.h ++++ b/include/dt-bindings/clock/mt7622-clk.h +@@ -235,7 +235,8 @@ + #define CLK_AUDIO_MEM_ASRC3 43 + #define CLK_AUDIO_MEM_ASRC4 44 + #define CLK_AUDIO_MEM_ASRC5 45 +-#define CLK_AUDIO_NR_CLK 46 ++#define CLK_AUDIO_AFE_CONN 46 ++#define CLK_AUDIO_NR_CLK 47 + + /* SSUSBSYS */ + diff --git a/target/linux/mediatek/patches-4.14/0209-clk-mediatek-add-devm_of_platform_populate-for-MT762.patch b/target/linux/mediatek/patches-4.14/0209-clk-mediatek-add-devm_of_platform_populate-for-MT762.patch new file mode 100644 index 000000000..affd9a62b --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0209-clk-mediatek-add-devm_of_platform_populate-for-MT762.patch @@ -0,0 +1,42 @@ +From 9dbdf33f1f246ecb6d957504781a970590b2d9f0 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Tue, 6 Mar 2018 17:09:27 +0800 +Subject: [PATCH 209/224] clk: mediatek: add devm_of_platform_populate() for + MT7622 audsys + +Add devm_of_platform_populate() to populate devices which are children +of the root node. + +Signed-off-by: Ryder Lee +--- + drivers/clk/mediatek/clk-mt7622-aud.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/clk/mediatek/clk-mt7622-aud.c ++++ b/drivers/clk/mediatek/clk-mt7622-aud.c +@@ -142,6 +142,7 @@ static int clk_mt7622_audiosys_init(stru + { + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; ++ + int r; + + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); +@@ -150,12 +151,15 @@ static int clk_mt7622_audiosys_init(stru + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +- if (r) ++ if (r) { + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + +- return r; ++ return r; ++ } ++ ++ return devm_of_platform_populate(&pdev->dev); + } + + static const struct of_device_id of_match_clk_mt7622_aud[] = { diff --git a/target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch b/target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch new file mode 100644 index 000000000..12f71a3e5 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch @@ -0,0 +1,130 @@ +From 9c76dd09d27dff05207241aa67a2c6054d057b32 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 28 Dec 2017 10:30:32 +0800 +Subject: [PATCH 210/224] arm64: dts: mt7622: add clock controller device nodes + +Add clock controller nodes for MT7622 and include header for topckgen, +infracfg, pericfg, apmixedsys, ethsys, sgmiisys, pciesys and ssusbsys +for those devices nodes to be added afterwards. + +In addition, provides an oscillator node for the source of PLLs and dummy +clock for PWARP to complement missing support of clock gate for the +wrapper circuit in the driver. + +Signed-off-by: Sean Wang +Cc: Stephen Boyd +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 76 ++++++++++++++++++++++++++++++++ + 1 file changed, 76 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -8,6 +8,8 @@ + + #include + #include ++#include ++#include + + / { + compatible = "mediatek,mt7622"; +@@ -48,6 +50,19 @@ + clock-frequency = <280000000>; + }; + ++ pwrap_clk: dummy40m { ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ #clock-cells = <0>; ++ }; ++ ++ clk25m: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <25000000>; ++ clock-output-names = "clkxtal"; ++ }; ++ + psci { + compatible = "arm,psci-0.2"; + method = "smc"; +@@ -78,6 +93,22 @@ + IRQ_TYPE_LEVEL_HIGH)>; + }; + ++ infracfg: infracfg@10000000 { ++ compatible = "mediatek,mt7622-infracfg", ++ "syscon"; ++ reg = <0 0x10000000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pericfg: pericfg@10002000 { ++ compatible = "mediatek,mt7622-pericfg", ++ "syscon"; ++ reg = <0 0x10002000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt7622-sysirq", + "mediatek,mt6577-sysirq"; +@@ -87,6 +118,20 @@ + reg = <0 0x10200620 0 0x20>; + }; + ++ apmixedsys: apmixedsys@10209000 { ++ compatible = "mediatek,mt7622-apmixedsys", ++ "syscon"; ++ reg = <0 0x10209000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ ++ topckgen: topckgen@10210000 { ++ compatible = "mediatek,mt7622-topckgen", ++ "syscon"; ++ reg = <0 0x10210000 0 0x1000>; ++ #clock-cells = <1>; ++ }; ++ + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; +@@ -107,4 +152,35 @@ + clock-names = "baud", "bus"; + status = "disabled"; + }; ++ ++ ssusbsys: ssusbsys@1a000000 { ++ compatible = "mediatek,mt7622-ssusbsys", ++ "syscon"; ++ reg = <0 0x1a000000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ pciesys: pciesys@1a100800 { ++ compatible = "mediatek,mt7622-pciesys", ++ "syscon"; ++ reg = <0 0x1a100800 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ ethsys: syscon@1b000000 { ++ compatible = "mediatek,mt7622-ethsys", ++ "syscon"; ++ reg = <0 0x1b000000 0 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ sgmiisys: sgmiisys@1b128000 { ++ compatible = "mediatek,mt7622-sgmiisys", ++ "syscon"; ++ reg = <0 0x1b128000 0 0x1000>; ++ #clock-cells = <1>; ++ }; + }; diff --git a/target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch b/target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch new file mode 100644 index 000000000..c996c608d --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0211-arm64-dts-mt7622-add-power-domain-controller-device-.patch @@ -0,0 +1,45 @@ +From 79d0293e8f35e87b1f068fc0b7963a86ba56800e Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 28 Dec 2017 15:46:42 +0800 +Subject: [PATCH 211/224] arm64: dts: mt7622: add power domain controller + device nodes + +add power domain controller nodes + +Signed-off-by: Sean Wang +Cc: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + + / { +@@ -109,6 +110,20 @@ + #reset-cells = <1>; + }; + ++ scpsys: scpsys@10006000 { ++ compatible = "mediatek,mt7622-scpsys", ++ "syscon"; ++ #power-domain-cells = <1>; ++ reg = <0 0x10006000 0 0x1000>; ++ interrupts = , ++ , ++ , ++ ; ++ infracfg = <&infracfg>; ++ clocks = <&topckgen CLK_TOP_HIF_SEL>; ++ clock-names = "hif_sel"; ++ }; ++ + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt7622-sysirq", + "mediatek,mt6577-sysirq"; diff --git a/target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch b/target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch new file mode 100644 index 000000000..21dbb3ace --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0212-arm64-dts-mt7622-add-pinctrl-related-device-nodes.patch @@ -0,0 +1,252 @@ +From 927c736a1a169713cd59140db5e82f8ed11dad60 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 29 Dec 2017 11:06:52 +0800 +Subject: [PATCH 212/224] arm64: dts: mt7622: add pinctrl related device nodes + +add pinctrl device nodes and rfb1 board, additionally include all pin +groups possible being used on rfb1 board and available gpio keys. + +Signed-off-by: Sean Wang +Cc: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 200 +++++++++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 + + 2 files changed, 207 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -7,6 +7,8 @@ + */ + + /dts-v1/; ++#include ++ + #include "mt7622.dtsi" + + / { +@@ -17,11 +19,209 @@ + bootargs = "console=ttyS0,115200n1"; + }; + ++ gpio-keys { ++ compatible = "gpio-keys-polled"; ++ poll-interval = <100>; ++ ++ factory { ++ label = "factory"; ++ linux,code = ; ++ gpios = <&pio 0 0>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&pio 102 0>; ++ }; ++ }; ++ + memory { + reg = <0 0x40000000 0 0x3F000000>; + }; + }; + ++&pio { ++ /* eMMC is shared pin with parallel NAND */ ++ emmc_pins_default: emmc-pins-default { ++ mux { ++ function = "emmc", "emmc_rst"; ++ groups = "emmc"; ++ }; ++ }; ++ ++ emmc_pins_uhs: emmc-pins-uhs { ++ mux { ++ function = "emmc"; ++ groups = "emmc"; ++ }; ++ }; ++ ++ eth_pins: eth-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio", "rgmii_via_gmac2"; ++ }; ++ }; ++ ++ i2c1_pins: i2c1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ i2c2_pins: i2c2-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c2_0"; ++ }; ++ }; ++ ++ i2s1_pins: i2s1-pins { ++ mux { ++ function = "i2s"; ++ groups = "i2s_out_bclk_ws_mclk", ++ "i2s1_in_data", ++ "i2s1_out_data"; ++ }; ++ }; ++ ++ irrx_pins: irrx-pins { ++ mux { ++ function = "ir"; ++ groups = "ir_1_rx"; ++ }; ++ }; ++ ++ irtx_pins: irtx-pins { ++ mux { ++ function = "ir"; ++ groups = "ir_1_tx"; ++ }; ++ }; ++ ++ /* Parallel nand is shared pin with eMMC */ ++ parallel_nand_pins: parallel-nand-pins { ++ mux { ++ function = "flash"; ++ groups = "par_nand"; ++ }; ++ }; ++ ++ pcie0_pins: pcie0-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie0_pad_perst", ++ "pcie0_1_waken", ++ "pcie0_1_clkreq"; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie1_pad_perst", ++ "pcie1_0_waken", ++ "pcie1_0_clkreq"; ++ }; ++ }; ++ ++ pmic_bus_pins: pmic-bus-pins { ++ mux { ++ function = "pmic"; ++ groups = "pmic_bus"; ++ }; ++ }; ++ ++ pwm7_pins: pwm1-2-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm_ch7_2"; ++ }; ++ }; ++ ++ wled_pins: wled-pins { ++ mux { ++ function = "led"; ++ groups = "wled"; ++ }; ++ }; ++ ++ sd0_pins_default: sd0-pins-default { ++ mux { ++ function = "sd"; ++ groups = "sd_0"; ++ }; ++ }; ++ ++ sd0_pins_uhs: sd0-pins-uhs { ++ mux { ++ function = "sd"; ++ groups = "sd_0"; ++ }; ++ }; ++ ++ /* Serial NAND is shared pin with SPI-NOR */ ++ serial_nand_pins: serial-nand-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ spic0_pins: spic0-pins { ++ mux { ++ function = "spi"; ++ groups = "spic0_0"; ++ }; ++ }; ++ ++ spic1_pins: spic1-pins { ++ mux { ++ function = "spi"; ++ groups = "spic1_0"; ++ }; ++ }; ++ ++ /* SPI-NOR is shared pin with serial NAND */ ++ spi_nor_pins: spi-nor-pins { ++ mux { ++ function = "flash"; ++ groups = "spi_nor"; ++ }; ++ }; ++ ++ /* serial NAND is shared pin with SPI-NOR */ ++ serial_nand_pins: serial-nand-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ uart0_pins: uart0-pins { ++ mux { ++ function = "uart"; ++ groups = "uart0_0_tx_rx" ; ++ }; ++ }; ++ ++ uart2_pins: uart2-pins { ++ mux { ++ function = "uart"; ++ groups = "uart2_1_tx_rx" ; ++ }; ++ }; ++ ++ watchdog_pins: watchdog-pins { ++ mux { ++ function = "watchdog"; ++ groups = "watchdog"; ++ }; ++ }; ++}; ++ + &uart0 { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -147,6 +147,13 @@ + #clock-cells = <1>; + }; + ++ pio: pinctrl@10211000 { ++ compatible = "mediatek,mt7622-pinctrl"; ++ reg = <0 0x10211000 0 0x1000>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; diff --git a/target/linux/mediatek/patches-4.14/0213-arm64-dts-mt7622-add-PMIC-MT6380-related-nodes.patch b/target/linux/mediatek/patches-4.14/0213-arm64-dts-mt7622-add-PMIC-MT6380-related-nodes.patch new file mode 100644 index 000000000..02c0ad89f --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0213-arm64-dts-mt7622-add-PMIC-MT6380-related-nodes.patch @@ -0,0 +1,155 @@ +From 78e92290c8c9511d0d540dfd0450e64169f08c20 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 5 Feb 2018 22:44:44 +0800 +Subject: [PATCH 213/224] arm64: dts: mt7622: add PMIC MT6380 related nodes + +Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380 +regulator nodes in an alone file to allow similar boards using MT6380 +able to resue the configuration. + +Signed-off-by: Sean Wang +Cc: Mark Brown +Cc: Matthias Brugger +Cc: Philippe Ombredanne +Acked-by: Philippe Ombredanne +--- + arch/arm64/boot/dts/mediatek/mt6380.dtsi | 86 ++++++++++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++ + 3 files changed, 106 insertions(+) + create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi +@@ -0,0 +1,86 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * dts file for MediaTek MT6380 regulator ++ * ++ * Copyright (c) 2018 MediaTek Inc. ++ * Author: Chenglin Xu ++ * Sean Wang ++ */ ++ ++&pwrap { ++ regulators { ++ compatible = "mediatek,mt6380-regulator"; ++ ++ mt6380_vcpu_reg: buck-vcore1 { ++ regulator-name = "vcore1"; ++ regulator-min-microvolt = < 600000>; ++ regulator-max-microvolt = <1393750>; ++ regulator-ramp-delay = <6250>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_vcore_reg: buck-vcore { ++ regulator-name = "vcore"; ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1393750>; ++ regulator-ramp-delay = <6250>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_vrf_reg: buck-vrf { ++ regulator-name = "vrf"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1575000>; ++ regulator-ramp-delay = <0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_vm_reg: ldo-vm { ++ regulator-name = "vm"; ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-ramp-delay = <0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_va_reg: ldo-va { ++ regulator-name = "va"; ++ regulator-min-microvolt = <2200000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_vphy_reg: ldo-vphy { ++ regulator-name = "vphy"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_vddr_reg: ldo-vddr { ++ regulator-name = "vddr"; ++ regulator-min-microvolt = <1240000>; ++ regulator-max-microvolt = <1840000>; ++ regulator-ramp-delay = <0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ mt6380_vt_reg: ldo-vt { ++ regulator-name = "vt"; ++ regulator-min-microvolt = <2200000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <0>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++}; +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -10,6 +10,7 @@ + #include + + #include "mt7622.dtsi" ++#include "mt6380.dtsi" + + / { + model = "MediaTek MT7622 RFB1 board"; +@@ -222,6 +223,13 @@ + }; + }; + ++&pwrap { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_bus_pins>; ++ ++ status = "okay"; ++}; ++ + &uart0 { + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -102,6 +102,18 @@ + #reset-cells = <1>; + }; + ++ pwrap: pwrap@10001000 { ++ compatible = "mediatek,mt7622-pwrap"; ++ reg = <0 0x10001000 0 0x250>; ++ reg-names = "pwrap"; ++ clocks = <&infracfg CLK_INFRA_PMIC_PD>,<&pwrap_clk>; ++ clock-names = "spi","wrap"; ++ resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; ++ reset-names = "pwrap"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ + pericfg: pericfg@10002000 { + compatible = "mediatek,mt7622-pericfg", + "syscon"; diff --git a/target/linux/mediatek/patches-4.14/0214-arm64-dts-mt7622-add-cpufreq-related-device-nodes.patch b/target/linux/mediatek/patches-4.14/0214-arm64-dts-mt7622-add-cpufreq-related-device-nodes.patch new file mode 100644 index 000000000..413c7baa4 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0214-arm64-dts-mt7622-add-cpufreq-related-device-nodes.patch @@ -0,0 +1,112 @@ +From 19fc79333af0d3733d4987bc1e554ae7e8a8cb0d Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 28 Dec 2017 16:26:10 +0800 +Subject: [PATCH 214/224] arm64: dts: mt7622: add cpufreq related device nodes + +Add clocks, regulators and opp information into cpu nodes. +In addition, the power supply for cpu nodes is deployed on +mt7622-rfb1 board. + +Signed-off-by: Sean Wang +Cc: Viresh Kumar +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 52 ++++++++++++++++++++++++++++ + 2 files changed, 64 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -20,6 +20,18 @@ + bootargs = "console=ttyS0,115200n1"; + }; + ++ cpus { ++ cpu@0 { ++ proc-supply = <&mt6380_vcpu_reg>; ++ sram-supply = <&mt6380_vm_reg>; ++ }; ++ ++ cpu@1 { ++ proc-supply = <&mt6380_vcpu_reg>; ++ sram-supply = <&mt6380_vm_reg>; ++ }; ++ }; ++ + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -18,6 +18,50 @@ + #address-cells = <2>; + #size-cells = <2>; + ++ cpu_opp_table: opp-table { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp-300000000 { ++ opp-hz = /bits/ 64 <30000000>; ++ opp-microvolt = <950000>; ++ }; ++ ++ opp-437500000 { ++ opp-hz = /bits/ 64 <437500000>; ++ opp-microvolt = <1000000>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <1050000>; ++ }; ++ ++ opp-812500000 { ++ opp-hz = /bits/ 64 <812500000>; ++ opp-microvolt = <1100000>; ++ }; ++ ++ opp-1025000000 { ++ opp-hz = /bits/ 64 <1025000000>; ++ opp-microvolt = <1150000>; ++ }; ++ ++ opp-1137500000 { ++ opp-hz = /bits/ 64 <1137500000>; ++ opp-microvolt = <1200000>; ++ }; ++ ++ opp-1262500000 { ++ opp-hz = /bits/ 64 <1262500000>; ++ opp-microvolt = <1250000>; ++ }; ++ ++ opp-1350000000 { ++ opp-hz = /bits/ 64 <1350000000>; ++ opp-microvolt = <1310000>; ++ }; ++ }; ++ + cpus { + #address-cells = <2>; + #size-cells = <0>; +@@ -26,6 +70,10 @@ + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; ++ clocks = <&infracfg CLK_INFRA_MUX1_SEL>, ++ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; +@@ -34,6 +82,10 @@ + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; ++ clocks = <&infracfg CLK_INFRA_MUX1_SEL>, ++ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; ++ clock-names = "cpu", "intermediate"; ++ operating-points-v2 = <&cpu_opp_table>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; diff --git a/target/linux/mediatek/patches-4.14/0215-arm64-dts-mt7622-turn-uart0-clock-to-real-ones.patch b/target/linux/mediatek/patches-4.14/0215-arm64-dts-mt7622-turn-uart0-clock-to-real-ones.patch new file mode 100644 index 000000000..39e0a2f00 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0215-arm64-dts-mt7622-turn-uart0-clock-to-real-ones.patch @@ -0,0 +1,45 @@ +From 84b3092b3773777de1ba1ad142e53247fb881ddd Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 28 Dec 2017 18:00:11 +0800 +Subject: [PATCH 215/224] arm64: dts: mt7622: turn uart0 clock to real ones + +This patch also cleans up two oscillators that provide clocks for MT7623. +Switch the uart clocks to the real ones while at it. + +Signed-off-by: Sean Wang +Cc: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 ++------------- + 1 file changed, 2 insertions(+), 13 deletions(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -91,18 +91,6 @@ + }; + }; + +- uart_clk: dummy25m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <25000000>; +- }; +- +- bus_clk: dummy280m { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <280000000>; +- }; +- + pwrap_clk: dummy40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; +@@ -234,7 +222,8 @@ + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; +- clocks = <&uart_clk>, <&bus_clk>; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&pericfg CLK_PERI_UART1_PD>; + clock-names = "baud", "bus"; + status = "disabled"; + }; diff --git a/target/linux/mediatek/patches-4.14/0216-arm64-dts-mt7622-add-SoC-and-peripheral-related-devi.patch b/target/linux/mediatek/patches-4.14/0216-arm64-dts-mt7622-add-SoC-and-peripheral-related-devi.patch new file mode 100644 index 000000000..6bef23041 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0216-arm64-dts-mt7622-add-SoC-and-peripheral-related-devi.patch @@ -0,0 +1,420 @@ +From a69ac853def2f93194e244974f611477a1521a4a Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Thu, 28 Dec 2017 18:18:26 +0800 +Subject: [PATCH 216/224] arm64: dts: mt7622: add SoC and peripheral related + device nodes + +Add watchdog, rtc, auxadc, cir, efuse, rng, uart[1-4], pwm, i2c[0-2], +spi[0-1], btif and thermal related nodes. + +Signed-off-by: Sean Wang +Cc: Andrew-CT Chen +Cc: Zhiyong Tao +Cc: Zhi Mao +Cc: Jun Gao +Cc: Leilk Liu +Cc: Matthias Brugger +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 54 ++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 264 +++++++++++++++++++++++++++ + 2 files changed, 318 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -235,6 +235,34 @@ + }; + }; + ++&btif { ++ status = "okay"; ++}; ++ ++&cir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&irrx_pins>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm7_pins>; ++ status = "okay"; ++}; ++ + &pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; +@@ -242,6 +270,32 @@ + status = "okay"; + }; + ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spic0_pins>; ++ status = "okay"; ++}; ++ ++&spi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spic1_pins>; ++ status = "okay"; ++}; ++ + &uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "okay"; ++}; ++ ++&watchdog { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&watchdog_pins>; + status = "okay"; + }; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + + / { + compatible = "mediatek,mt7622"; +@@ -74,6 +75,7 @@ + <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cpu_opp_table>; ++ #cooling-cells = <2>; + enable-method = "psci"; + clock-frequency = <1300000000>; + }; +@@ -121,6 +123,58 @@ + }; + }; + ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <1000>; ++ ++ thermal-sensors = <&thermal 0>; ++ ++ trips { ++ cpu_passive: cpu-passive { ++ temperature = <47000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_active: cpu-active { ++ temperature = <67000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <87000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ ++ cpu-crit { ++ temperature = <107000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_passive>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map1 { ++ trip = <&cpu_active>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ ++ map2 { ++ trip = <&cpu_hot>; ++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; +@@ -176,6 +230,16 @@ + clock-names = "hif_sel"; + }; + ++ cir: cir@10009000 { ++ compatible = "mediatek,mt7622-cir"; ++ reg = <0 0x10009000 0 0x1000>; ++ interrupts = ; ++ clocks = <&infracfg CLK_INFRA_IRRX_PD>, ++ <&topckgen CLK_TOP_AXI_SEL>; ++ clock-names = "clk", "bus"; ++ status = "disabled"; ++ }; ++ + sysirq: interrupt-controller@10200620 { + compatible = "mediatek,mt7622-sysirq", + "mediatek,mt6577-sysirq"; +@@ -185,6 +249,18 @@ + reg = <0 0x10200620 0 0x20>; + }; + ++ efuse: efuse@10206000 { ++ compatible = "mediatek,mt7622-efuse", ++ "mediatek,efuse"; ++ reg = <0 0x10206000 0 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ thermal_calibration: calib@198 { ++ reg = <0x198 0xc>; ++ }; ++ }; ++ + apmixedsys: apmixedsys@10209000 { + compatible = "mediatek,mt7622-apmixedsys", + "syscon"; +@@ -199,6 +275,14 @@ + #clock-cells = <1>; + }; + ++ rng: rng@1020f000 { ++ compatible = "mediatek,mt7622-rng", ++ "mediatek,mt7623-rng"; ++ reg = <0 0x1020f000 0 0x1000>; ++ clocks = <&infracfg CLK_INFRA_TRNG>; ++ clock-names = "rng"; ++ }; ++ + pio: pinctrl@10211000 { + compatible = "mediatek,mt7622-pinctrl"; + reg = <0 0x10211000 0 0x1000>; +@@ -206,6 +290,21 @@ + #gpio-cells = <2>; + }; + ++ watchdog: watchdog@10212000 { ++ compatible = "mediatek,mt7622-wdt", ++ "mediatek,mt6589-wdt"; ++ reg = <0 0x10212000 0 0x800>; ++ }; ++ ++ rtc: rtc@10212800 { ++ compatible = "mediatek,mt7622-rtc", ++ "mediatek,soc-rtc"; ++ reg = <0 0x10212800 0 0x200>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_RTC>; ++ clock-names = "rtc"; ++ }; ++ + gic: interrupt-controller@10300000 { + compatible = "arm,gic-400"; + interrupt-controller; +@@ -217,6 +316,14 @@ + <0 0x10360000 0 0x2000>; + }; + ++ auxadc: adc@11001000 { ++ compatible = "mediatek,mt7622-auxadc"; ++ reg = <0 0x11001000 0 0x1000>; ++ clocks = <&pericfg CLK_PERI_AUXADC_PD>; ++ clock-names = "main"; ++ #io-channel-cells = <1>; ++ }; ++ + uart0: serial@11002000 { + compatible = "mediatek,mt7622-uart", + "mediatek,mt6577-uart"; +@@ -227,6 +334,163 @@ + clock-names = "baud", "bus"; + status = "disabled"; + }; ++ ++ uart1: serial@11003000 { ++ compatible = "mediatek,mt7622-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11003000 0 0x400>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&pericfg CLK_PERI_UART1_PD>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@11004000 { ++ compatible = "mediatek,mt7622-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11004000 0 0x400>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&pericfg CLK_PERI_UART2_PD>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@11005000 { ++ compatible = "mediatek,mt7622-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11005000 0 0x400>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&pericfg CLK_PERI_UART3_PD>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; ++ ++ pwm: pwm@11006000 { ++ compatible = "mediatek,mt7622-pwm"; ++ reg = <0 0x11006000 0 0x1000>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_PWM_SEL>, ++ <&pericfg CLK_PERI_PWM_PD>, ++ <&pericfg CLK_PERI_PWM1_PD>, ++ <&pericfg CLK_PERI_PWM2_PD>, ++ <&pericfg CLK_PERI_PWM3_PD>, ++ <&pericfg CLK_PERI_PWM4_PD>, ++ <&pericfg CLK_PERI_PWM5_PD>, ++ <&pericfg CLK_PERI_PWM6_PD>; ++ clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", ++ "pwm5", "pwm6"; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@11007000 { ++ compatible = "mediatek,mt7622-i2c"; ++ reg = <0 0x11007000 0 0x90>, ++ <0 0x11000100 0 0x80>; ++ interrupts = ; ++ clock-div = <16>; ++ clocks = <&pericfg CLK_PERI_I2C0_PD>, ++ <&pericfg CLK_PERI_AP_DMA_PD>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@11008000 { ++ compatible = "mediatek,mt7622-i2c"; ++ reg = <0 0x11008000 0 0x90>, ++ <0 0x11000180 0 0x80>; ++ interrupts = ; ++ clock-div = <16>; ++ clocks = <&pericfg CLK_PERI_I2C1_PD>, ++ <&pericfg CLK_PERI_AP_DMA_PD>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@11009000 { ++ compatible = "mediatek,mt7622-i2c"; ++ reg = <0 0x11009000 0 0x90>, ++ <0 0x11000200 0 0x80>; ++ interrupts = ; ++ clock-div = <16>; ++ clocks = <&pericfg CLK_PERI_I2C2_PD>, ++ <&pericfg CLK_PERI_AP_DMA_PD>; ++ clock-names = "main", "dma"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@1100a000 { ++ compatible = "mediatek,mt7622-spi"; ++ reg = <0 0x1100a000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, ++ <&topckgen CLK_TOP_SPI0_SEL>, ++ <&pericfg CLK_PERI_SPI0_PD>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ thermal: thermal@1100b000 { ++ #thermal-sensor-cells = <1>; ++ compatible = "mediatek,mt7622-thermal"; ++ reg = <0 0x1100b000 0 0x1000>; ++ interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&pericfg CLK_PERI_THERM_PD>, ++ <&pericfg CLK_PERI_AUXADC_PD>; ++ clock-names = "therm", "auxadc"; ++ resets = <&pericfg MT7622_PERI_THERM_SW_RST>; ++ reset-names = "therm"; ++ mediatek,auxadc = <&auxadc>; ++ mediatek,apmixedsys = <&apmixedsys>; ++ nvmem-cells = <&thermal_calibration>; ++ nvmem-cell-names = "calibration-data"; ++ }; ++ ++ btif: serial@1100c000 { ++ compatible = "mediatek,mt7622-btif", ++ "mediatek,mtk-btif"; ++ reg = <0 0x1100c000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_BTIF_PD>; ++ clock-names = "main"; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@11016000 { ++ compatible = "mediatek,mt7622-spi"; ++ reg = <0 0x11016000 0 0x100>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, ++ <&topckgen CLK_TOP_SPI1_SEL>, ++ <&pericfg CLK_PERI_SPI1_PD>; ++ clock-names = "parent-clk", "sel-clk", "spi-clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@11019000 { ++ compatible = "mediatek,mt7622-uart", ++ "mediatek,mt6577-uart"; ++ reg = <0 0x11019000 0 0x400>; ++ interrupts = ; ++ clocks = <&topckgen CLK_TOP_UART_SEL>, ++ <&pericfg CLK_PERI_UART4_PD>; ++ clock-names = "baud", "bus"; ++ status = "disabled"; ++ }; + + ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", diff --git a/target/linux/mediatek/patches-4.14/0217-arm64-dts-mt7622-add-flash-related-device-nodes.patch b/target/linux/mediatek/patches-4.14/0217-arm64-dts-mt7622-add-flash-related-device-nodes.patch new file mode 100644 index 000000000..85812878a --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0217-arm64-dts-mt7622-add-flash-related-device-nodes.patch @@ -0,0 +1,96 @@ +From 0a84c72d1c606129b8af670cbcc73be4168ab753 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 29 Dec 2017 10:36:37 +0800 +Subject: [PATCH 217/224] arm64: dts: mt7622: add flash related device nodes + +add nodes for NOR flash, parallel Nand flash with error correction code +support. + +Signed-off-by: Sean Wang +Cc: RogerCC Lin +Cc: Guochun Mao +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 21 +++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 34 ++++++++++++++++++++++++++++ + 2 files changed, 55 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -235,6 +235,10 @@ + }; + }; + ++&bch { ++ status = "disabled"; ++}; ++ + &btif { + status = "okay"; + }; +@@ -257,6 +261,23 @@ + status = "okay"; + }; + ++&nandc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <¶llel_nand_pins>; ++ status = "disabled"; ++}; ++ ++&nor_flash { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_nor_pins>; ++ status = "disabled"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ }; ++}; ++ + &pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -468,6 +468,40 @@ + status = "disabled"; + }; + ++ nandc: nfi@1100d000 { ++ compatible = "mediatek,mt7622-nfc"; ++ reg = <0 0x1100D000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, ++ <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ bch: ecc@1100e000 { ++ compatible = "mediatek,mt7622-ecc"; ++ reg = <0 0x1100e000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFIECC_PD>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; ++ ++ nor_flash: spi@11014000 { ++ compatible = "mediatek,mt7622-nor", ++ "mediatek,mt8173-nor"; ++ reg = <0 0x11014000 0 0xe0>; ++ clocks = <&pericfg CLK_PERI_FLASH_PD>, ++ <&topckgen CLK_TOP_FLASH_SEL>; ++ clock-names = "spi", "sf"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + spi1: spi@11016000 { + compatible = "mediatek,mt7622-spi"; + reg = <0 0x11016000 0 0x100>; diff --git a/target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch b/target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch new file mode 100644 index 000000000..2986cc740 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch @@ -0,0 +1,84 @@ +From 4fbacf244953285ac58cb833060076fafd990588 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 29 Dec 2017 10:45:07 +0800 +Subject: [PATCH 218/224] arm64: dts: mt7622: add ethernet device nodes + +add ethernet device nodes which enable GMAC1 with SGMII interface + +Signed-off-by: Sean Wang +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 31 ++++++++++++++++++++++++++++ + 2 files changed, 53 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -249,6 +249,28 @@ + status = "okay"; + }; + ++ð { ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð_pins>; ++ status = "okay"; ++ ++ gmac1: mac@1 { ++ compatible = "mediatek,eth-mac"; ++ reg = <1>; ++ phy-handle = <&phy5>; ++ }; ++ ++ mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ phy5: ethernet-phy@5 { ++ reg = <5>; ++ phy-mode = "sgmii"; ++ }; ++ }; ++}; ++ + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -550,6 +550,37 @@ + #reset-cells = <1>; + }; + ++ eth: ethernet@1b100000 { ++ compatible = "mediatek,mt7622-eth", ++ "mediatek,mt2701-eth", ++ "syscon"; ++ reg = <0 0x1b100000 0 0x20000>; ++ interrupts = , ++ , ++ ; ++ clocks = <&topckgen CLK_TOP_ETH_SEL>, ++ <ðsys CLK_ETH_ESW_EN>, ++ <ðsys CLK_ETH_GP0_EN>, ++ <ðsys CLK_ETH_GP1_EN>, ++ <ðsys CLK_ETH_GP2_EN>, ++ <&sgmiisys CLK_SGMII_TX250M_EN>, ++ <&sgmiisys CLK_SGMII_RX250M_EN>, ++ <&sgmiisys CLK_SGMII_CDR_REF>, ++ <&sgmiisys CLK_SGMII_CDR_FB>, ++ <&topckgen CLK_TOP_SGMIIPLL>, ++ <&apmixedsys CLK_APMIXED_ETH2PLL>; ++ clock-names = "ethif", "esw", "gp0", "gp1", "gp2", ++ "sgmii_tx250m", "sgmii_rx250m", ++ "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", ++ "eth2pll"; ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; ++ mediatek,ethsys = <ðsys>; ++ mediatek,sgmiisys = <&sgmiisys>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sgmiisys: sgmiisys@1b128000 { + compatible = "mediatek,mt7622-sgmiisys", + "syscon"; diff --git a/target/linux/mediatek/patches-4.14/0219-arm64-dts-mt7622-add-PCIe-device-nodes.patch b/target/linux/mediatek/patches-4.14/0219-arm64-dts-mt7622-add-PCIe-device-nodes.patch new file mode 100644 index 000000000..4908edab8 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0219-arm64-dts-mt7622-add-PCIe-device-nodes.patch @@ -0,0 +1,116 @@ +From e84732bd6022dd12839dd34d508eb27428367c24 Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Wed, 20 Dec 2017 15:57:30 +0800 +Subject: [PATCH 219/224] arm64: dts: mt7622: add PCIe device nodes + +This patch adds PCIe support fot MT7622. + +Signed-off-by: Ryder Lee +Signed-off-by: Sean Wang +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 10 ++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 74 ++++++++++++++++++++++++++++ + 2 files changed, 84 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -54,6 +54,16 @@ + }; + }; + ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_pins>; ++ status = "okay"; ++ ++ pcie@0,0 { ++ status = "okay"; ++ }; ++}; ++ + &pio { + /* eMMC is shared pin with parallel NAND */ + emmc_pins_default: emmc-pins-default { +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -542,6 +542,80 @@ + #reset-cells = <1>; + }; + ++ pcie: pcie@1a140000 { ++ compatible = "mediatek,mt7622-pcie"; ++ device_type = "pci"; ++ reg = <0 0x1a140000 0 0x1000>, ++ <0 0x1a143000 0 0x1000>, ++ <0 0x1a145000 0 0x1000>; ++ reg-names = "subsys", "port0", "port1"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ interrupts = , ++ ; ++ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, ++ <&pciesys CLK_PCIE_P1_MAC_EN>, ++ <&pciesys CLK_PCIE_P0_AHB_EN>, ++ <&pciesys CLK_PCIE_P0_AHB_EN>, ++ <&pciesys CLK_PCIE_P0_AUX_EN>, ++ <&pciesys CLK_PCIE_P1_AUX_EN>, ++ <&pciesys CLK_PCIE_P0_AXI_EN>, ++ <&pciesys CLK_PCIE_P1_AXI_EN>, ++ <&pciesys CLK_PCIE_P0_OBFF_EN>, ++ <&pciesys CLK_PCIE_P1_OBFF_EN>, ++ <&pciesys CLK_PCIE_P0_PIPE_EN>, ++ <&pciesys CLK_PCIE_P1_PIPE_EN>; ++ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", ++ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", ++ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; ++ status = "disabled"; ++ ++ pcie0: pcie@0,0 { ++ reg = <0x0000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ status = "disabled"; ++ ++ num-lanes = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ pcie1: pcie@1,0 { ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges; ++ status = "disabled"; ++ ++ num-lanes = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ }; ++ + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7622-ethsys", + "syscon"; diff --git a/target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch b/target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch new file mode 100644 index 000000000..18f3e63ac --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch @@ -0,0 +1,87 @@ +From 0c8d249a70818f4f8e0d5543dc7157dfd8a5265e Mon Sep 17 00:00:00 2001 +From: Ryder Lee +Date: Wed, 20 Dec 2017 16:04:24 +0800 +Subject: [PATCH 220/224] arm64: dts: mt7622: add SATA device nodes + +This patch adds SATA support fot MT7622. + +Signed-off-by: Ryder Lee +Signed-off-by: Sean Wang +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++ + 2 files changed, 48 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -323,6 +323,14 @@ + status = "okay"; + }; + ++&sata { ++ status = "okay"; ++}; ++ ++&sata_phy { ++ status = "okay"; ++}; ++ + &spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spic0_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -616,6 +617,45 @@ + }; + }; + ++ sata: sata@1a200000 { ++ compatible = "mediatek,mt7622-ahci", ++ "mediatek,mtk-ahci"; ++ reg = <0 0x1a200000 0 0x1100>; ++ interrupts = ; ++ interrupt-names = "hostc"; ++ clocks = <&pciesys CLK_SATA_AHB_EN>, ++ <&pciesys CLK_SATA_AXI_EN>, ++ <&pciesys CLK_SATA_ASIC_EN>, ++ <&pciesys CLK_SATA_RBC_EN>, ++ <&pciesys CLK_SATA_PM_EN>; ++ clock-names = "ahb", "axi", "asic", "rbc", "pm"; ++ phys = <&sata_port PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; ++ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, ++ <&pciesys MT7622_SATA_PHY_SW_RST>, ++ <&pciesys MT7622_SATA_PHY_REG_RST>; ++ reset-names = "axi", "sw", "reg"; ++ mediatek,phy-mode = <&pciesys>; ++ status = "disabled"; ++ }; ++ ++ sata_phy: sata-phy@1a243000 { ++ compatible = "mediatek,generic-tphy-v1"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ sata_port: sata-phy@1a243000 { ++ reg = <0 0x1a243000 0 0x0100>; ++ clocks = <&topckgen CLK_TOP_ETH_500M>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ }; ++ }; ++ + ethsys: syscon@1b000000 { + compatible = "mediatek,mt7622-ethsys", + "syscon"; diff --git a/target/linux/mediatek/patches-4.14/0221-arm64-dts-mt7622-add-usb-device-nodes.patch b/target/linux/mediatek/patches-4.14/0221-arm64-dts-mt7622-add-usb-device-nodes.patch new file mode 100644 index 000000000..03982c96d --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0221-arm64-dts-mt7622-add-usb-device-nodes.patch @@ -0,0 +1,119 @@ +From 3e23988f5c9c5d54732eda1e8017409ef223048b Mon Sep 17 00:00:00 2001 +From: Chunfeng Yun +Date: Fri, 12 Jan 2018 12:28:31 +0800 +Subject: [PATCH 221/224] arm64: dts: mt7622: add usb device nodes + +add xhci node and usb3 phy nodes + +Signed-off-by: Chunfeng Yun +Signed-off-by: Sean Wang +Tested-by: Jumin Li +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 28 +++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 51 ++++++++++++++++++++++++++++ + 2 files changed, 79 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -52,6 +52,24 @@ + memory { + reg = <0 0x40000000 0 0x3F000000>; + }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; + }; + + &pcie { +@@ -343,6 +361,16 @@ + status = "okay"; + }; + ++&ssusb { ++ vusb33-supply = <®_3p3v>; ++ vbus-supply = <®_5v>; ++ status = "okay"; ++}; ++ ++&u3phy { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -535,6 +535,57 @@ + #reset-cells = <1>; + }; + ++ ssusb: usb@1a0c0000 { ++ compatible = "mediatek,mt7622-xhci", ++ "mediatek,mtk-xhci"; ++ reg = <0 0x1a0c0000 0 0x01000>, ++ <0 0x1a0c4700 0 0x0100>; ++ reg-names = "mac", "ippc"; ++ interrupts = ; ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; ++ clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, ++ <&ssusbsys CLK_SSUSB_REF_EN>, ++ <&ssusbsys CLK_SSUSB_MCU_EN>, ++ <&ssusbsys CLK_SSUSB_DMA_EN>; ++ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; ++ phys = <&u2port0 PHY_TYPE_USB2>, ++ <&u3port0 PHY_TYPE_USB3>, ++ <&u2port1 PHY_TYPE_USB2>; ++ ++ status = "disabled"; ++ }; ++ ++ u3phy: usb-phy@1a0c4000 { ++ compatible = "mediatek,mt7622-u3phy", ++ "mediatek,generic-tphy-v1"; ++ reg = <0 0x1a0c4000 0 0x700>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ u2port0: usb-phy@1a0c4800 { ++ reg = <0 0x1a0c4800 0 0x0100>; ++ #phy-cells = <1>; ++ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; ++ clock-names = "ref"; ++ }; ++ ++ u3port0: usb-phy@1a0c4900 { ++ reg = <0 0x1a0c4900 0 0x0700>; ++ #phy-cells = <1>; ++ clocks = <&clk25m>; ++ clock-names = "ref"; ++ }; ++ ++ u2port1: usb-phy@1a0c5000 { ++ reg = <0 0x1a0c5000 0 0x0100>; ++ #phy-cells = <1>; ++ clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; ++ clock-names = "ref"; ++ }; ++ }; ++ + pciesys: pciesys@1a100800 { + compatible = "mediatek,mt7622-pciesys", + "syscon"; diff --git a/target/linux/mediatek/patches-4.14/0222-arm64-dts-mt7622-add-High-Speed-DMA-device-nodes.patch b/target/linux/mediatek/patches-4.14/0222-arm64-dts-mt7622-add-High-Speed-DMA-device-nodes.patch new file mode 100644 index 000000000..5c83ff6ad --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0222-arm64-dts-mt7622-add-High-Speed-DMA-device-nodes.patch @@ -0,0 +1,31 @@ +From c61ef9c4707e38edeafad1bd4d01080d0e0a10da Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Wed, 17 Jan 2018 00:52:27 +0800 +Subject: [PATCH 222/224] arm64: dts: mt7622: add High-Speed DMA device nodes + +add High-Speed DMA (HSDMA) nodes + +Signed-off-by: Sean Wang +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -715,6 +715,16 @@ + #reset-cells = <1>; + }; + ++ hsdma: dma-controller@1b007000 { ++ compatible = "mediatek,mt7622-hsdma"; ++ reg = <0 0x1b007000 0 0x1000>; ++ interrupts = ; ++ clocks = <ðsys CLK_ETH_HSDMA_EN>; ++ clock-names = "hsdma"; ++ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; ++ #dma-cells = <1>; ++ }; ++ + eth: ethernet@1b100000 { + compatible = "mediatek,mt7622-eth", + "mediatek,mt2701-eth", diff --git a/target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch b/target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch new file mode 100644 index 000000000..7d28e2b56 --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0223-arm64-dts-mt7622-add-mmc-related-device-nodes.patch @@ -0,0 +1,200 @@ +From d41d41bfcbd8ad4bcbb1b433f7d5c3b613c58419 Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Mon, 22 Jan 2018 16:58:36 +0800 +Subject: [PATCH 223/224] arm64: dts: mt7622: add mmc related device nodes + +add mmc device nodes and proper setup for used pins + +Signed-off-by: Sean Wang +Signed-off-by: Jimin Wang +--- + arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 106 +++++++++++++++++++++++++++ + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 20 +++++ + 2 files changed, 126 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts ++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +@@ -8,6 +8,7 @@ + + /dts-v1/; + #include ++#include + + #include "mt7622.dtsi" + #include "mt6380.dtsi" +@@ -53,6 +54,14 @@ + reg = <0 0x40000000 0 0x3F000000>; + }; + ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; +@@ -89,6 +98,23 @@ + function = "emmc", "emmc_rst"; + groups = "emmc"; + }; ++ ++ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", ++ * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, ++ * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively ++ */ ++ conf-cmd-dat { ++ pins = "NDL0", "NDL1", "NDL2", ++ "NDL3", "NDL4", "NDL5", ++ "NDL6", "NDL7", "NRB"; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ conf-clk { ++ pins = "NCLE"; ++ bias-pull-down; ++ }; + }; + + emmc_pins_uhs: emmc-pins-uhs { +@@ -96,6 +122,21 @@ + function = "emmc"; + groups = "emmc"; + }; ++ ++ conf-cmd-dat { ++ pins = "NDL0", "NDL1", "NDL2", ++ "NDL3", "NDL4", "NDL5", ++ "NDL6", "NDL7", "NRB"; ++ input-enable; ++ drive-strength = <4>; ++ bias-pull-up; ++ }; ++ ++ conf-clk { ++ pins = "NCLE"; ++ drive-strength = <4>; ++ bias-pull-down; ++ }; + }; + + eth_pins: eth-pins { +@@ -194,6 +235,27 @@ + function = "sd"; + groups = "sd_0"; + }; ++ ++ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", ++ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, ++ * DAT2, DAT3, CMD, CLK for SD respectively. ++ */ ++ conf-cmd-data { ++ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", ++ "I2S2_IN","I2S4_OUT"; ++ input-enable; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ conf-clk { ++ pins = "I2S3_OUT"; ++ drive-strength = <12>; ++ bias-pull-down; ++ }; ++ conf-cd { ++ pins = "TXD3"; ++ bias-pull-up; ++ }; + }; + + sd0_pins_uhs: sd0-pins-uhs { +@@ -201,6 +263,18 @@ + function = "sd"; + groups = "sd_0"; + }; ++ ++ conf-cmd-data { ++ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", ++ "I2S2_IN","I2S4_OUT"; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ conf-clk { ++ pins = "I2S3_OUT"; ++ bias-pull-down; ++ }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ +@@ -311,6 +385,38 @@ + status = "okay"; + }; + ++&mmc0 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&emmc_pins_default>; ++ pinctrl-1 = <&emmc_pins_uhs>; ++ status = "okay"; ++ bus-width = <8>; ++ max-frequency = <50000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; ++ non-removable; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default", "state_uhs"; ++ pinctrl-0 = <&sd0_pins_default>; ++ pinctrl-1 = <&sd0_pins_uhs>; ++ status = "okay"; ++ bus-width = <4>; ++ max-frequency = <50000000>; ++ cap-sd-highspeed; ++ r_smpl = <1>; ++ cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; ++}; ++ + &nandc { + pinctrl-names = "default"; + pinctrl-0 = <¶llel_nand_pins>; +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -527,6 +527,26 @@ + status = "disabled"; + }; + ++ mmc0: mmc@11230000 { ++ compatible = "mediatek,mt7622-mmc"; ++ reg = <0 0x11230000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, ++ <&topckgen CLK_TOP_MSDC50_0_SEL>; ++ clock-names = "source", "hclk"; ++ status = "disabled"; ++ }; ++ ++ mmc1: mmc@11240000 { ++ compatible = "mediatek,mt7622-mmc"; ++ reg = <0 0x11240000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, ++ <&topckgen CLK_TOP_AXI_SEL>; ++ clock-names = "source", "hclk"; ++ status = "disabled"; ++ }; ++ + ssusbsys: ssusbsys@1a000000 { + compatible = "mediatek,mt7622-ssusbsys", + "syscon"; diff --git a/target/linux/mediatek/patches-4.14/0224-add-mt7622-defconfig-for-testing-these-new-drivers.patch b/target/linux/mediatek/patches-4.14/0224-add-mt7622-defconfig-for-testing-these-new-drivers.patch new file mode 100644 index 000000000..a39c5267c --- /dev/null +++ b/target/linux/mediatek/patches-4.14/0224-add-mt7622-defconfig-for-testing-these-new-drivers.patch @@ -0,0 +1,288 @@ +From 4d4581541ee9bc4b7aee5e75db561a8128f3a8bd Mon Sep 17 00:00:00 2001 +From: Sean Wang +Date: Fri, 1 Dec 2017 10:57:57 +0800 +Subject: [PATCH 224/224] add mt7622 defconfig for testing these new drivers + +--- + arch/arm64/configs/mt7622_rfb1_defconfig | 275 +++++++++++++++++++++++++++++++ + 1 file changed, 275 insertions(+) + create mode 100644 arch/arm64/configs/mt7622_rfb1_defconfig + +--- /dev/null ++++ b/arch/arm64/configs/mt7622_rfb1_defconfig +@@ -0,0 +1,275 @@ ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_DEFAULT_HOSTNAME="(mt7622)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_IRQ_TIME_ACCOUNTING=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++# CONFIG_UTS_NS is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="../prebuilt/bootable/7622_loader/rootfs.cpio.gz" ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_XZ is not set ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_PERF_EVENTS=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_IOSCHED_DEADLINE is not set ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_PCI=y ++CONFIG_PCI_DEBUG=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_SCHED_MC=y ++CONFIG_NR_CPUS=2 ++CONFIG_PREEMPT=y ++# CONFIG_COMPACTION is not set ++# CONFIG_BOUNCE is not set ++# CONFIG_EFI is not set ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_COMPAT=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y ++CONFIG_ARM_MEDIATEK_CPUFREQ=y ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_INET=y ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_IPV6 is not set ++CONFIG_BT=y ++CONFIG_BT_RFCOMM=y ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=y ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=y ++# CONFIG_BT_HS is not set ++# CONFIG_BT_LE is not set ++CONFIG_BT_HCIUART=y ++CONFIG_BT_HCIVHCI=y ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_MTD=y ++# CONFIG_MTD_OF_PARTS is not set ++CONFIG_MTD_NAND=y ++CONFIG_MTD_NAND_MTK=y ++CONFIG_MTD_SPI_NOR=y ++CONFIG_MTD_MT81xx_NOR=y ++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set ++# CONFIG_BLK_DEV is not set ++CONFIG_BLK_DEV_SD=y ++CONFIG_ATA=y ++CONFIG_AHCI_MTK=y ++CONFIG_NETDEVICES=y ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++# CONFIG_NET_VENDOR_AGERE is not set ++# CONFIG_NET_VENDOR_ALACRITECH is not set ++# CONFIG_NET_VENDOR_ALTEON is not set ++# CONFIG_NET_VENDOR_AMAZON is not set ++# CONFIG_NET_VENDOR_AMD is not set ++# CONFIG_NET_VENDOR_AQUANTIA is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_VENDOR_ATHEROS is not set ++# CONFIG_NET_CADENCE is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_BROCADE is not set ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++# CONFIG_NET_VENDOR_DEC is not set ++# CONFIG_NET_VENDOR_DLINK is not set ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++# CONFIG_NET_VENDOR_EXAR is not set ++# CONFIG_NET_VENDOR_HISILICON is not set ++# CONFIG_NET_VENDOR_HP is not set ++# CONFIG_NET_VENDOR_HUAWEI is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++CONFIG_NET_VENDOR_MEDIATEK=y ++CONFIG_NET_MEDIATEK_SOC=y ++# CONFIG_NET_VENDOR_MELLANOX is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_MYRI is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_NETRONOME is not set ++# CONFIG_NET_VENDOR_NVIDIA is not set ++# CONFIG_NET_VENDOR_OKI is not set ++# CONFIG_NET_PACKET_ENGINE is not set ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++# CONFIG_NET_VENDOR_REALTEK is not set ++# CONFIG_NET_VENDOR_RENESAS is not set ++# CONFIG_NET_VENDOR_RDC is not set ++# CONFIG_NET_VENDOR_ROCKER is not set ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SILAN is not set ++# CONFIG_NET_VENDOR_SIS is not set ++# CONFIG_NET_VENDOR_SOLARFLARE is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++# CONFIG_NET_VENDOR_SUN is not set ++# CONFIG_NET_VENDOR_TEHUTI is not set ++# CONFIG_NET_VENDOR_TI is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++# CONFIG_NET_VENDOR_SYNOPSYS is not set ++CONFIG_ICPLUS_PHY=y ++CONFIG_REALTEK_PHY=y ++CONFIG_USB_CATC=y ++CONFIG_USB_KAWETH=y ++CONFIG_USB_PEGASUS=y ++CONFIG_USB_RTL8150=y ++CONFIG_USB_RTL8152=y ++CONFIG_USB_LAN78XX=y ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_CDC_EEM=y ++CONFIG_USB_NET_HUAWEI_CDC_NCM=y ++CONFIG_USB_NET_CDC_MBIM=y ++CONFIG_USB_NET_DM9601=y ++CONFIG_USB_NET_SR9700=y ++CONFIG_USB_NET_SR9800=y ++CONFIG_USB_NET_SMSC75XX=y ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=y ++CONFIG_USB_NET_PLUSB=y ++CONFIG_USB_NET_MCS7830=y ++CONFIG_USB_NET_RNDIS_HOST=y ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_CX82310_ETH=y ++CONFIG_USB_NET_KALMIA=y ++CONFIG_USB_NET_QMI_WWAN=y ++CONFIG_USB_NET_INT51X1=y ++CONFIG_USB_IPHETH=y ++CONFIG_USB_SIERRA_NET=y ++CONFIG_USB_VL600=y ++CONFIG_USB_NET_CH9200=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO_POLLED=y ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_SERIO_LIBPS2=y ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_LEGACY_PTY_COUNT=16 ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_CONSOLE=y ++CONFIG_SERIAL_8250_NR_UARTS=3 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=3 ++CONFIG_SERIAL_8250_MT6577=y ++CONFIG_SERIAL_OF_PLATFORM=y ++CONFIG_SERIAL_DEV_BUS=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MT65XX=y ++CONFIG_I2C_SLAVE=y ++CONFIG_I2C_DEBUG_CORE=y ++CONFIG_I2C_DEBUG_ALGO=y ++CONFIG_I2C_DEBUG_BUS=y ++CONFIG_SPI=y ++CONFIG_SPI_MT65XX=y ++CONFIG_DEBUG_PINCTRL=y ++CONFIG_PINCTRL_MT7622=y ++# CONFIG_PINCTRL_MT8173 is not set ++# CONFIG_PINCTRL_MT6397 is not set ++CONFIG_POWER_RESET_SYSCON=y ++# CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_WRITABLE_TRIPS=y ++CONFIG_THERMAL_GOV_FAIR_SHARE=y ++CONFIG_THERMAL_GOV_BANG_BANG=y ++CONFIG_THERMAL_GOV_USER_SPACE=y ++CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y ++CONFIG_CPU_THERMAL=y ++CONFIG_CLOCK_THERMAL=y ++CONFIG_THERMAL_EMULATION=y ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_SYSFS=y ++CONFIG_MEDIATEK_WATCHDOG=y ++CONFIG_WATCHDOG_PRETIMEOUT_GOV=y ++CONFIG_MFD_MT6397=y ++CONFIG_REGULATOR=y ++CONFIG_REGULATOR_DEBUG=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++CONFIG_REGULATOR_MT6323=y ++CONFIG_REGULATOR_MT6380=y ++CONFIG_RC_CORE=y ++CONFIG_RC_DEVICES=y ++CONFIG_IR_MTK=y ++CONFIG_MEDIA_SUPPORT=y ++CONFIG_USB=y ++# CONFIG_USB_PCI is not set ++# CONFIG_USB_DEFAULT_PERSIST is not set ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_DEBUG=y ++CONFIG_MMC=y ++CONFIG_MMC_MTK=y ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_USER=y ++CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_ACTIVITY=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DRV_MT7622=y ++CONFIG_DMADEVICES=y ++CONFIG_MTK_HSDMA=y ++CONFIG_DMATEST=y ++# CONFIG_COMMON_CLK_XGENE is not set ++# CONFIG_COMMON_CLK_MT6797 is not set ++CONFIG_COMMON_CLK_MT7622_ETHSYS=y ++CONFIG_COMMON_CLK_MT7622_HIFSYS=y ++CONFIG_COMMON_CLK_MT7622_AUDSYS=y ++# CONFIG_COMMON_CLK_MT8173 is not set ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_MTK_PMIC_WRAP=y ++CONFIG_IIO=y ++CONFIG_MEDIATEK_MT6577_AUXADC=y ++CONFIG_PWM=y ++CONFIG_PWM_MEDIATEK=y ++CONFIG_RESET_CONTROLLER=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_EFUSE=y ++CONFIG_TMPFS=y ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_PRINTK_TIME=y ++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 ++CONFIG_DYNAMIC_DEBUG=y ++# CONFIG_ENABLE_WARN_DEPRECATED is not set ++# CONFIG_ENABLE_MUST_CHECK is not set ++CONFIG_DEBUG_FS=y ++CONFIG_DEBUG_SECTION_MISMATCH=y ++# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_FTRACE is not set diff --git a/target/linux/mvebu/base-files/etc/board.d/02_network b/target/linux/mvebu/base-files/etc/board.d/02_network index 66d35dda7..2c1015492 100755 --- a/target/linux/mvebu/base-files/etc/board.d/02_network +++ b/target/linux/mvebu/base-files/etc/board.d/02_network @@ -46,9 +46,18 @@ armada-xp-gp) globalscale,espressobin) ucidef_set_interfaces_lan_wan "lan0 lan1" "wan" ;; +marvell,armada-3720-db) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; marvell,armada8040-mcbin) ucidef_set_interfaces_lan_wan "eth0 eth1 eth3" "eth2" ;; +marvell,armada8040-db) + ucidef_set_interfaces_lan_wan "eth0 eth2 eth3" "eth1" + ;; +marvell,armada7040-db) + ucidef_set_interfaces_lan_wan "eth0 eth2" "eth1" + ;; *) ucidef_set_interface_lan "eth0" ;; diff --git a/target/linux/mvebu/base-files/lib/mvebu.sh b/target/linux/mvebu/base-files/lib/mvebu.sh index 33ac83239..5a0d7b293 100755 --- a/target/linux/mvebu/base-files/lib/mvebu.sh +++ b/target/linux/mvebu/base-files/lib/mvebu.sh @@ -20,9 +20,18 @@ mvebu_board_detect() { *"Globalscale Marvell ESPRESSOBin Board") name="globalscale,espressobin" ;; + *"Marvell Armada 3720 Development Board DB-88F3720-DDR3") + name="marvell,armada-3720-db" + ;; *"Marvell 8040 MACHIATOBin") name="marvell,armada8040-mcbin" ;; + *"Marvell Armada 8040 DB board") + name="marvell,armada8040-db" + ;; + *"Marvell Armada 7040 DB board") + name="marvell,armada7040-db" + ;; *"Globalscale Mirabox") name="mirabox" ;; diff --git a/target/linux/mvebu/config-4.14 b/target/linux/mvebu/config-4.14 index 5286bf9b8..694ecdfb8 100644 --- a/target/linux/mvebu/config-4.14 +++ b/target/linux/mvebu/config-4.14 @@ -28,7 +28,6 @@ CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -# CONFIG_ARCH_WANTS_THP_SWAP is not set CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_ARM=y @@ -43,6 +42,7 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARM_CRYPTO=y CONFIG_ARM_ERRATA_720789=y @@ -165,15 +165,11 @@ CONFIG_DEBUG_USER=y CONFIG_DMADEVICES=y CONFIG_DMA_ENGINE=y CONFIG_DMA_ENGINE_RAID=y -# CONFIG_DMA_NOOP_OPS is not set CONFIG_DMA_OF=y -# CONFIG_DMA_VIRT_OPS is not set -# CONFIG_DRM_LIB_RANDOM is not set CONFIG_DTC=y CONFIG_EARLY_PRINTK=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y -CONFIG_EXPORTFS=y CONFIG_EXT4_FS=y CONFIG_EXTCON=y # CONFIG_F2FS_CHECK_FS is not set @@ -184,7 +180,6 @@ CONFIG_F2FS_STAT_FS=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FS_MBCACHE=y -CONFIG_FUTEX_PI=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_BUG=y @@ -459,7 +454,6 @@ CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -CONFIG_THIN_ARCHIVES=y # CONFIG_THUMB2_KERNEL is not set CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_TIMER_OF=y diff --git a/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts b/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts index ea44c8f0d..00a4ee9f3 100644 --- a/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts +++ b/target/linux/mvebu/files-4.14/arch/arm/boot/dts/armada-385-linksys-venom.dts @@ -46,7 +46,13 @@ model = "Linksys WRT32X"; compatible = "linksys,venom", "linksys,armada385", "marvell,armada385", "marvell,armada380"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + append-rootblock = "root=/dev/mtdblock"; }; +}; &expander0 { wan_amber@0 { diff --git a/target/linux/mvebu/image/armada-3720-db.bootscript b/target/linux/mvebu/image/armada-3720-db.bootscript new file mode 100644 index 000000000..65e39a1af --- /dev/null +++ b/target/linux/mvebu/image/armada-3720-db.bootscript @@ -0,0 +1,10 @@ +setenv bootargs "root=PARTUUID=@ROOT@-02 rw rootwait" + +if test -n "${console}"; then + setenv bootargs "${bootargs} ${console}" +fi + +load mmc 0:1 ${fdt_addr} armada-3720-db.dtb +load mmc 0:1 ${kernel_addr} Image + +booti ${kernel_addr} - ${fdt_addr} diff --git a/target/linux/mvebu/image/cortex-a53.mk b/target/linux/mvebu/image/cortex-a53.mk index 711d2c0be..89c336344 100644 --- a/target/linux/mvebu/image/cortex-a53.mk +++ b/target/linux/mvebu/image/cortex-a53.mk @@ -13,4 +13,17 @@ define Device/globalscale-espressobin endef TARGET_DEVICES += globalscale-espressobin +define Device/armada-3720-db + KERNEL_NAME := Image + KERNEL := kernel-bin + DEVICE_TITLE := Marvell Armada 3720 Development Board DB-88F3720-DDR3 + DEVICE_PACKAGES := e2fsprogs ethtool mkf2fs kmod-fs-vfat kmod-usb2 kmod-usb3 kmod-usb-storage + IMAGES := sdcard.img.gz + IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata + DEVICE_DTS := armada-3720-db + DTS_DIR := $(DTS_DIR)/marvell + SUPPORTED_DEVICES := marvell,armada-3720-db +endef +TARGET_DEVICES += armada-3720-db + endif diff --git a/target/linux/mvebu/image/cortex-a72.mk b/target/linux/mvebu/image/cortex-a72.mk index ac9cb50a8..ac5b80233 100644 --- a/target/linux/mvebu/image/cortex-a72.mk +++ b/target/linux/mvebu/image/cortex-a72.mk @@ -13,4 +13,30 @@ define Device/armada-macchiatobin endef TARGET_DEVICES += armada-macchiatobin +define Device/armada-8040-db + KERNEL_NAME := Image + KERNEL := kernel-bin + DEVICE_TITLE := Marvell Armada 8040 DB board + DEVICE_PACKAGES := e2fsprogs ethtool mkf2fs kmod-fs-vfat kmod-mmc + IMAGES := sdcard.img.gz + IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata + DEVICE_DTS := armada-8040-db + DTS_DIR := $(DTS_DIR)/marvell + SUPPORTED_DEVICES := marvell,armada8040-db +endef +TARGET_DEVICES += armada-8040-db + +define Device/armada-7040-db + KERNEL_NAME := Image + KERNEL := kernel-bin + DEVICE_TITLE := Marvell Armada 7040 DB board + DEVICE_PACKAGES := e2fsprogs ethtool mkf2fs kmod-fs-vfat kmod-mmc + IMAGES := sdcard.img.gz + IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata + DEVICE_DTS := armada-7040-db + DTS_DIR := $(DTS_DIR)/marvell + SUPPORTED_DEVICES := marvell,armada7040-db +endef +TARGET_DEVICES += armada-7040-db + endif diff --git a/target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch new file mode 100644 index 000000000..c4ffd0efe --- /dev/null +++ b/target/linux/mvebu/patches-4.14/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch @@ -0,0 +1,201 @@ +From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 +From: Adrian Panella +Date: Thu, 9 Mar 2017 09:37:17 +0100 +Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments + +The command-line arguments provided by the boot loader will be +appended to a new device tree property: bootloader-args. +If there is a property "append-rootblock" in DT under /chosen +and a root= option in bootloaders command line it will be parsed +and added to DT bootargs with the form: XX. +Only command line ATAG will be processed, the rest of the ATAGs +sent by bootloader will be ignored. +This is usefull in dual boot systems, to get the current root partition +without afecting the rest of the system. + +Signed-off-by: Adrian Panella + +This patch has been modified to be mvebu specific. The original patch +did not pass the bootloader cmdline on if no append-rootblock stanza +was found, resulting in blank cmdline and failure to boot. + +Signed-off-by: Michael Gray +--- + arch/arm/Kconfig | 11 +++++ + arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- + init/main.c | 16 ++++++++ + 3 files changed, 98 insertions(+), 1 deletion(-) + +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1938,6 +1938,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN + The command-line arguments provided by the boot loader will be + appended to the the device tree bootargs property. + ++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE ++ bool "Append rootblock parsing bootloader's kernel arguments" ++ help ++ The command-line arguments provided by the boot loader will be ++ appended to a new device tree property: bootloader-args. ++ If there is a property "append-rootblock" in DT under /chosen ++ and a root= option in bootloaders command line it will be parsed ++ and added to DT bootargs with the form: XX. ++ Only command line ATAG will be processed, the rest of the ATAGs ++ sent by bootloader will be ignored. ++ + endchoice + + config CMDLINE +--- a/arch/arm/boot/compressed/atags_to_fdt.c ++++ b/arch/arm/boot/compressed/atags_to_fdt.c +@@ -4,6 +4,8 @@ + + #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) + #define do_extend_cmdline 1 ++#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) ++#define do_extend_cmdline 1 + #else + #define do_extend_cmdline 0 + #endif +@@ -67,6 +69,65 @@ static uint32_t get_cell_size(const void + return cell_size; + } + ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) ++ ++static char *append_rootblock(char *dest, const char *str, int len, void *fdt) ++{ ++ char *ptr, *end; ++ char *root="root="; ++ int i, l; ++ const char *rootblock; ++ ++ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually ++ ptr = str - 1; ++ ++ do { ++ //first find an 'r' at the begining or after a space ++ do { ++ ptr++; ++ ptr = strchr(ptr, 'r'); ++ if(!ptr) return dest; ++ ++ } while (ptr != str && *(ptr-1) != ' '); ++ ++ //then check for the rest ++ for(i = 1; i <= 4; i++) ++ if(*(ptr+i) != *(root+i)) break; ++ ++ } while (i != 5); ++ ++ end = strchr(ptr, ' '); ++ end = end ? (end - 1) : (strchr(ptr, 0) - 1); ++ ++ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX ) ++ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++); ++ ptr = end + 1; ++ ++ /* if append-rootblock property is set use it to append to command line */ ++ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l); ++ if(rootblock != NULL) { ++ if(*dest != ' ') { ++ *dest = ' '; ++ dest++; ++ len++; ++ } ++ if (len + l + i <= COMMAND_LINE_SIZE) { ++ memcpy(dest, rootblock, l); ++ dest += l - 1; ++ memcpy(dest, ptr, i); ++ dest += i; ++ } ++ } else { ++ len = strlen(str); ++ if (len + 1 < COMMAND_LINE_SIZE) { ++ memcpy(dest, str, len); ++ dest += len; ++ } ++ } ++ return dest; ++} ++#endif ++ + static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) + { + char cmdline[COMMAND_LINE_SIZE]; +@@ -86,12 +147,21 @@ static void merge_fdt_bootargs(void *fdt + + /* and append the ATAG_CMDLINE */ + if (fdt_cmdline) { ++ ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) ++ //save original bootloader args ++ //and append ubi.mtd with root partition number to current cmdline ++ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline); ++ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt); ++ ++#else + len = strlen(fdt_cmdline); + if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { + *ptr++ = ' '; + memcpy(ptr, fdt_cmdline, len); + ptr += len; + } ++#endif + } + *ptr = '\0'; + +@@ -148,7 +218,9 @@ int atags_to_fdt(void *atag_list, void * + else + setprop_string(fdt, "/chosen", "bootargs", + atag->u.cmdline.cmdline); +- } else if (atag->hdr.tag == ATAG_MEM) { ++ } ++#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE ++ else if (atag->hdr.tag == ATAG_MEM) { + if (memcount >= sizeof(mem_reg_property)/4) + continue; + if (!atag->u.mem.size) +@@ -187,6 +259,10 @@ int atags_to_fdt(void *atag_list, void * + setprop(fdt, "/memory", "reg", mem_reg_property, + 4 * memcount * memsize); + } ++#else ++ ++ } ++#endif + + return fdt_pack(fdt); + } +--- a/init/main.c ++++ b/init/main.c +@@ -95,6 +95,10 @@ + #include + #include + ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) ++#include ++#endif ++ + static int kernel_init(void *); + + extern void init_IRQ(void); +@@ -574,6 +578,18 @@ asmlinkage __visible void __init start_k + page_alloc_init(); + + pr_notice("Kernel command line: %s\n", boot_command_line); ++ ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) ++ //Show bootloader's original command line for reference ++ if(of_chosen) { ++ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL); ++ if(prop) ++ pr_notice("Bootloader command line (ignored): %s\n", prop); ++ else ++ pr_notice("Bootloader command line not present\n"); ++ } ++#endif ++ + parse_early_param(); + after_dashes = parse_args("Booting kernel", + static_command_line, __start___param, diff --git a/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch index f21f8083e..7ff586cd1 100644 --- a/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch +++ b/target/linux/mvebu/patches-4.14/300-mvneta-tx-queue-workaround.patch @@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau --- --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -3961,6 +3961,15 @@ static int mvneta_ethtool_set_wol(struct +@@ -3962,6 +3962,15 @@ static int mvneta_ethtool_set_wol(struct return ret; } @@ -25,7 +25,7 @@ Signed-off-by: Felix Fietkau static const struct net_device_ops mvneta_netdev_ops = { .ndo_open = mvneta_open, .ndo_stop = mvneta_stop, -@@ -3971,6 +3980,7 @@ static const struct net_device_ops mvnet +@@ -3972,6 +3981,7 @@ static const struct net_device_ops mvnet .ndo_fix_features = mvneta_fix_features, .ndo_get_stats64 = mvneta_get_stats64, .ndo_do_ioctl = mvneta_ioctl, diff --git a/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch b/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch index 10f385461..3549c8997 100644 --- a/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch +++ b/target/linux/mvebu/patches-4.14/403-net-mvneta-convert-to-phylink.patch @@ -132,7 +132,7 @@ Signed-off-by: Russell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; -@@ -1214,10 +1233,6 @@ static void mvneta_port_disable(struct m +@@ -1215,10 +1234,6 @@ static void mvneta_port_disable(struct m val &= ~MVNETA_GMAC0_PORT_ENABLE; mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); @@ -143,7 +143,7 @@ Signed-off-by: Russell King udelay(200); } -@@ -1277,44 +1292,6 @@ static void mvneta_set_other_mcast_table +@@ -1278,44 +1293,6 @@ static void mvneta_set_other_mcast_table mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); } @@ -188,7 +188,7 @@ Signed-off-by: Russell King static void mvneta_percpu_unmask_interrupt(void *arg) { struct mvneta_port *pp = arg; -@@ -1467,7 +1444,6 @@ static void mvneta_defaults_set(struct m +@@ -1468,7 +1445,6 @@ static void mvneta_defaults_set(struct m val &= ~MVNETA_PHY_POLLING_ENABLE; mvreg_write(pp, MVNETA_UNIT_CONTROL, val); @@ -196,7 +196,7 @@ Signed-off-by: Russell King mvneta_set_ucast_table(pp, -1); mvneta_set_special_mcast_table(pp, -1); mvneta_set_other_mcast_table(pp, -1); -@@ -2692,26 +2668,11 @@ static irqreturn_t mvneta_percpu_isr(int +@@ -2693,26 +2669,11 @@ static irqreturn_t mvneta_percpu_isr(int return IRQ_HANDLED; } @@ -225,7 +225,7 @@ Signed-off-by: Russell King } /* NAPI handler -@@ -2727,7 +2688,6 @@ static int mvneta_poll(struct napi_struc +@@ -2728,7 +2689,6 @@ static int mvneta_poll(struct napi_struc u32 cause_rx_tx; int rx_queue; struct mvneta_port *pp = netdev_priv(napi->dev); @@ -233,7 +233,7 @@ Signed-off-by: Russell King struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); if (!netif_running(pp->dev)) { -@@ -2741,12 +2701,11 @@ static int mvneta_poll(struct napi_struc +@@ -2742,12 +2702,11 @@ static int mvneta_poll(struct napi_struc u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); @@ -251,7 +251,7 @@ Signed-off-by: Russell King } /* Release Tx descriptors */ -@@ -3060,7 +3019,6 @@ static int mvneta_setup_txqs(struct mvne +@@ -3061,7 +3020,6 @@ static int mvneta_setup_txqs(struct mvne static void mvneta_start_dev(struct mvneta_port *pp) { int cpu; @@ -259,7 +259,7 @@ Signed-off-by: Russell King mvneta_max_rx_size_set(pp, pp->pkt_size); mvneta_txq_max_tx_size_set(pp, pp->pkt_size); -@@ -3088,16 +3046,15 @@ static void mvneta_start_dev(struct mvne +@@ -3089,16 +3047,15 @@ static void mvneta_start_dev(struct mvne MVNETA_CAUSE_LINK_CHANGE | MVNETA_CAUSE_PSC_SYNC_CHANGE); @@ -278,7 +278,7 @@ Signed-off-by: Russell King if (!pp->neta_armada3700) { for_each_online_cpu(cpu) { -@@ -3251,103 +3208,232 @@ static int mvneta_set_mac_addr(struct ne +@@ -3252,103 +3209,232 @@ static int mvneta_set_mac_addr(struct ne return 0; } @@ -585,7 +585,7 @@ Signed-off-by: Russell King } /* Electing a CPU must be done in an atomic way: it should be done -@@ -3626,10 +3712,9 @@ static int mvneta_stop(struct net_device +@@ -3627,10 +3713,9 @@ static int mvneta_stop(struct net_device static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { @@ -598,7 +598,7 @@ Signed-off-by: Russell King } /* Ethtool methods */ -@@ -3640,44 +3725,25 @@ mvneta_ethtool_set_link_ksettings(struct +@@ -3641,44 +3726,25 @@ mvneta_ethtool_set_link_ksettings(struct const struct ethtool_link_ksettings *cmd) { struct mvneta_port *pp = netdev_priv(ndev); @@ -657,7 +657,7 @@ Signed-off-by: Russell King } /* Set interrupt coalescing for ethtools */ -@@ -3769,6 +3835,22 @@ static int mvneta_ethtool_set_ringparam( +@@ -3770,6 +3836,22 @@ static int mvneta_ethtool_set_ringparam( return 0; } @@ -680,7 +680,7 @@ Signed-off-by: Russell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, u8 *data) { -@@ -3785,26 +3867,35 @@ static void mvneta_ethtool_update_stats( +@@ -3786,26 +3868,35 @@ static void mvneta_ethtool_update_stats( { const struct mvneta_statistic *s; void __iomem *base = pp->base; @@ -721,7 +721,7 @@ Signed-off-by: Russell King } } -@@ -3939,28 +4030,65 @@ static int mvneta_ethtool_get_rxfh(struc +@@ -3940,28 +4031,65 @@ static int mvneta_ethtool_get_rxfh(struc static void mvneta_ethtool_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { @@ -795,7 +795,7 @@ Signed-off-by: Russell King static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb, void *accel_priv, select_queue_fallback_t fallback) -@@ -3984,13 +4112,15 @@ static const struct net_device_ops mvnet +@@ -3985,13 +4113,15 @@ static const struct net_device_ops mvnet }; static const struct ethtool_ops mvneta_eth_tool_ops = { @@ -812,7 +812,7 @@ Signed-off-by: Russell King .get_strings = mvneta_ethtool_get_strings, .get_ethtool_stats = mvneta_ethtool_get_stats, .get_sset_count = mvneta_ethtool_get_sset_count, -@@ -3998,10 +4128,12 @@ static const struct ethtool_ops mvneta_e +@@ -3999,10 +4129,12 @@ static const struct ethtool_ops mvneta_e .get_rxnfc = mvneta_ethtool_get_rxnfc, .get_rxfh = mvneta_ethtool_get_rxfh, .set_rxfh = mvneta_ethtool_set_rxfh, @@ -826,7 +826,7 @@ Signed-off-by: Russell King }; /* Initialize hw */ -@@ -4146,14 +4278,13 @@ static int mvneta_probe(struct platform_ +@@ -4147,14 +4279,13 @@ static int mvneta_probe(struct platform_ { struct resource *res; struct device_node *dn = pdev->dev.of_node; @@ -842,7 +842,7 @@ Signed-off-by: Russell King int tx_csum_limit; int phy_mode; int err; -@@ -4169,31 +4300,11 @@ static int mvneta_probe(struct platform_ +@@ -4170,31 +4301,11 @@ static int mvneta_probe(struct platform_ goto err_free_netdev; } @@ -875,7 +875,7 @@ Signed-off-by: Russell King } dev->tx_queue_len = MVNETA_MAX_TXD; -@@ -4204,12 +4315,7 @@ static int mvneta_probe(struct platform_ +@@ -4205,12 +4316,7 @@ static int mvneta_probe(struct platform_ pp = netdev_priv(dev); spin_lock_init(&pp->lock); @@ -889,7 +889,7 @@ Signed-off-by: Russell King pp->rxq_def = rxq_def; -@@ -4231,7 +4337,7 @@ static int mvneta_probe(struct platform_ +@@ -4232,7 +4338,7 @@ static int mvneta_probe(struct platform_ pp->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(pp->clk)) { err = PTR_ERR(pp->clk); @@ -898,7 +898,7 @@ Signed-off-by: Russell King } clk_prepare_enable(pp->clk); -@@ -4357,6 +4463,14 @@ static int mvneta_probe(struct platform_ +@@ -4358,6 +4464,14 @@ static int mvneta_probe(struct platform_ /* 9676 == 9700 - 20 and rounding to 8 */ dev->max_mtu = 9676; @@ -913,7 +913,7 @@ Signed-off-by: Russell King err = register_netdev(dev); if (err < 0) { dev_err(&pdev->dev, "failed to register\n"); -@@ -4368,14 +4482,6 @@ static int mvneta_probe(struct platform_ +@@ -4369,14 +4483,6 @@ static int mvneta_probe(struct platform_ platform_set_drvdata(pdev, pp->dev); @@ -928,7 +928,7 @@ Signed-off-by: Russell King return 0; err_netdev: -@@ -4386,16 +4492,14 @@ err_netdev: +@@ -4387,16 +4493,14 @@ err_netdev: 1 << pp->id); } err_free_stats: @@ -947,7 +947,7 @@ Signed-off-by: Russell King err_free_irq: irq_dispose_mapping(dev->irq); err_free_netdev: -@@ -4407,7 +4511,6 @@ err_free_netdev: +@@ -4408,7 +4512,6 @@ err_free_netdev: static int mvneta_remove(struct platform_device *pdev) { struct net_device *dev = platform_get_drvdata(pdev); @@ -955,7 +955,7 @@ Signed-off-by: Russell King struct mvneta_port *pp = netdev_priv(dev); unregister_netdev(dev); -@@ -4415,10 +4518,8 @@ static int mvneta_remove(struct platform +@@ -4416,10 +4519,8 @@ static int mvneta_remove(struct platform clk_disable_unprepare(pp->clk); free_percpu(pp->ports); free_percpu(pp->stats); @@ -967,7 +967,7 @@ Signed-off-by: Russell King free_netdev(dev); if (pp->bm_priv) { -@@ -4470,9 +4571,6 @@ static int mvneta_resume(struct device * +@@ -4471,9 +4572,6 @@ static int mvneta_resume(struct device * return err; } diff --git a/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch b/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch index 906c163ac..88ea6973e 100644 --- a/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch +++ b/target/linux/mvebu/patches-4.14/404-net-mvneta-hack-fix-phy_interface.patch @@ -18,7 +18,7 @@ Signed-off-by: Russell King struct device_node *dn; unsigned int tx_csum_limit; struct phylink *phylink; -@@ -4315,6 +4316,7 @@ static int mvneta_probe(struct platform_ +@@ -4316,6 +4317,7 @@ static int mvneta_probe(struct platform_ pp = netdev_priv(dev); spin_lock_init(&pp->lock); diff --git a/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch b/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch index ddb0cc8a2..6f9c4dd59 100644 --- a/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch +++ b/target/linux/mvebu/patches-4.14/405-net-mvneta-disable-MVNETA_CAUSE_PSC_SYNC_CHANGE-inte.patch @@ -14,7 +14,7 @@ Signed-off-by: Russell King --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -2704,8 +2704,7 @@ static int mvneta_poll(struct napi_struc +@@ -2705,8 +2705,7 @@ static int mvneta_poll(struct napi_struc mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | @@ -24,7 +24,7 @@ Signed-off-by: Russell King mvneta_link_change(pp); } -@@ -3044,8 +3043,7 @@ static void mvneta_start_dev(struct mvne +@@ -3045,8 +3044,7 @@ static void mvneta_start_dev(struct mvne mvreg_write(pp, MVNETA_INTR_MISC_MASK, MVNETA_CAUSE_PHY_STATUS_CHANGE | @@ -34,7 +34,7 @@ Signed-off-by: Russell King phylink_start(pp->phylink); netif_tx_start_all_queues(pp->dev); -@@ -3542,8 +3540,7 @@ static int mvneta_cpu_online(unsigned in +@@ -3543,8 +3541,7 @@ static int mvneta_cpu_online(unsigned in on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); mvreg_write(pp, MVNETA_INTR_MISC_MASK, MVNETA_CAUSE_PHY_STATUS_CHANGE | @@ -44,7 +44,7 @@ Signed-off-by: Russell King netif_tx_start_all_queues(pp->dev); spin_unlock(&pp->lock); return 0; -@@ -3584,8 +3581,7 @@ static int mvneta_cpu_dead(unsigned int +@@ -3585,8 +3582,7 @@ static int mvneta_cpu_dead(unsigned int on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); mvreg_write(pp, MVNETA_INTR_MISC_MASK, MVNETA_CAUSE_PHY_STATUS_CHANGE | diff --git a/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch b/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch index 39eb33ac2..f359eb3d7 100644 --- a/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch +++ b/target/linux/mvebu/patches-4.14/406-net-mvneta-add-module-EEPROM-reading-support.patch @@ -10,7 +10,7 @@ Signed-off-by: Russell King --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -4045,6 +4045,22 @@ static int mvneta_ethtool_set_wol(struct +@@ -4046,6 +4046,22 @@ static int mvneta_ethtool_set_wol(struct return ret; } @@ -33,7 +33,7 @@ Signed-off-by: Russell King static int mvneta_ethtool_get_eee(struct net_device *dev, struct ethtool_eee *eee) { -@@ -4129,6 +4145,8 @@ static const struct ethtool_ops mvneta_e +@@ -4130,6 +4146,8 @@ static const struct ethtool_ops mvneta_e .set_link_ksettings = mvneta_ethtool_set_link_ksettings, .get_wol = mvneta_ethtool_get_wol, .set_wol = mvneta_ethtool_set_wol, diff --git a/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch b/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch index 2e135e684..3012fae3d 100644 --- a/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch +++ b/target/linux/mvebu/patches-4.14/408-sfp-move-module-eeprom-ethtool-access-into-netdev-co.patch @@ -15,7 +15,7 @@ Signed-off-by: Russell King --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -4045,22 +4045,6 @@ static int mvneta_ethtool_set_wol(struct +@@ -4046,22 +4046,6 @@ static int mvneta_ethtool_set_wol(struct return ret; } @@ -38,7 +38,7 @@ Signed-off-by: Russell King static int mvneta_ethtool_get_eee(struct net_device *dev, struct ethtool_eee *eee) { -@@ -4145,8 +4129,6 @@ static const struct ethtool_ops mvneta_e +@@ -4146,8 +4130,6 @@ static const struct ethtool_ops mvneta_e .set_link_ksettings = mvneta_ethtool_set_link_ksettings, .get_wol = mvneta_ethtool_get_wol, .set_wol = mvneta_ethtool_set_wol, diff --git a/target/linux/oxnas/Makefile b/target/linux/oxnas/Makefile index 0d9d35673..52d57f336 100644 --- a/target/linux/oxnas/Makefile +++ b/target/linux/oxnas/Makefile @@ -1,29 +1,21 @@ -# -# Copyright (C) 2013 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# include $(TOPDIR)/rules.mk ARCH:=arm BOARD:=oxnas -BOARDNAME:=PLXTECH/Oxford NAS782x/OX82x +BOARDNAME:=PLXTECH/Oxford NAS782x/OX8xx +SUBTARGETS:=ox810se ox820 +FEATURES:=gpio ramdisk rtc squashfs DEVICE_TYPE:=nas -FEATURES:=gpio nand pcie usb ramdisk rtc squashfs ubifs -CPU_TYPE:=mpcore MAINTAINER:=Daniel Golle -KERNEL_PATCHVER:=4.4 +KERNEL_PATCHVER:=4.14 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ - kmod-ata-core kmod-ata-oxnas-sata kmod-button-hotplug \ - kmod-input-gpio-keys-polled kmod-usb-ledtrig-usbport \ - kmod-ledtrig-timer kmod-leds-gpio kmod-usb2-oxnas \ - kmod-usb-storage uboot-envtools uboot-oxnas-ox820 + kmod-button-hotplug kmod-input-gpio-keys-polled \ + kmod-ledtrig-timer kmod-leds-gpio uboot-envtools KERNELNAME:=zImage dtbs diff --git a/target/linux/oxnas/config-4.4 b/target/linux/oxnas/config-4.14 similarity index 51% rename from target/linux/oxnas/config-4.4 rename to target/linux/oxnas/config-4.14 index 0c6e99251..4d6943aea 100644 --- a/target/linux/oxnas/config-4.4 +++ b/target/linux/oxnas/config-4.14 @@ -1,17 +1,21 @@ CONFIG_ALIGNMENT_TRAP=y -# CONFIG_APM_EMULATION is not set -CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set CONFIG_ARCH_OXNAS=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y @@ -21,7 +25,6 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_LIBATA_LEDS=y CONFIG_ARM=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y @@ -29,111 +32,116 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y CONFIG_ARM_CPUIDLE=y -# CONFIG_ARM_CPU_SUSPEND is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y +CONFIG_ARM_CPU_SUSPEND=y CONFIG_ARM_HAS_SG_CHAIN=y CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_SMMU=y +CONFIG_ARM_PMU=y +# CONFIG_ARM_SMMU is not set CONFIG_ARM_THUMB=y +CONFIG_ARM_TIMER_SP804=y CONFIG_ARM_UNWIND=y CONFIG_ATAGS=y -CONFIG_ATA_LEDS=y CONFIG_AUTO_ZRELADDR=y +CONFIG_BINARY_PRINTF=y +CONFIG_BLK_CMDLINE_PARSER=y +CONFIG_BLK_DEBUG_FS=y CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INITRD is not set -CONFIG_BLK_DEV_SD=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1 -# CONFIG_CACHE_L2X0 is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_SCSI_REQUEST=y +# CONFIG_BPF_SYSCALL is not set CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y -CONFIG_CLKSRC_OF=y -CONFIG_CLKSRC_PROBE=y -CONFIG_CLKSRC_RPS_TIMER=y CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="console=ttyS0,115200n8 earlyprintk=serial" -CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=64 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CMDLINE_PARTITION=y CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_OXNAS=y CONFIG_COMPACTION=y -CONFIG_CONSOLE_POLL=y +CONFIG_COMPAT_BRK=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_COREDUMP=y -CONFIG_CPU_32v6=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_ABRT_EV6=y -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_CACHE_V6=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -# CONFIG_CPU_ICACHE_DISABLE is not set -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V6=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -# CONFIG_CPU_SW_DOMAIN_PAN is not set -CONFIG_CPU_TLB_V6=y -CONFIG_CPU_V6K=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CRASH_CORE=y CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ICEDCC=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/icedcc.S" -# CONFIG_DEBUG_UART_8250 is not set +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_USER is not set -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=16 -CONFIG_DEPRECATED_PARAM_STRUCT=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DMADEVICES=y -CONFIG_DMA_CACHE_FIQ_BROADCAST=y -# CONFIG_DMA_CACHE_RWFO is not set -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_DEVMEM=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y CONFIG_DNOTIFY=y CONFIG_DTC=y CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_OXNAS=y -# CONFIG_DWMAC_SUNXI is not set -# CONFIG_DW_DMAC_PCI is not set CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_FIQ=y +# CONFIG_EDAC_SUPPORT is not set +CONFIG_ELF_CORE=y +CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_GENERIC_IO=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_PINCONF=y CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GLOB=y CONFIG_GPIOLIB=y -CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB_IRQCHIP=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_GPIO_SYSFS=y +CONFIG_GRO_CELLS=y CONFIG_HANDLE_DOMAIN_IRQ=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_HAS_DMA=y @@ -147,10 +155,7 @@ CONFIG_HAVE_ARCH_KGDB=y CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_TWD=y # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_HAVE_BPF_JIT=y CONFIG_HAVE_CC_STACKPROTECTOR=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y @@ -158,10 +163,10 @@ CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_DMA_ATTRS=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_EBPF_JIT=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y @@ -178,189 +183,177 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_PROC_CPU=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_SMP=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_UID16=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HOTPLUG_CPU=y +CONFIG_HID=y +CONFIG_HID_GENERIC=y +CONFIG_HWMON=y +CONFIG_HW_CONSOLE=y CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y CONFIG_ICPLUS_PHY=y +CONFIG_INET_DIAG=y +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_INET_RAW_DIAG is not set +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INITRAMFS_SOURCE="" CONFIG_INPUT=y -# CONFIG_INPUT_MISC is not set -CONFIG_IOMMU_API=y CONFIG_IOMMU_HELPER=y -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set CONFIG_IOMMU_SUPPORT=y -# CONFIG_IP_ADVANCED_ROUTER is not set -# CONFIG_IP_MULTICAST is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_BOOTP is not set -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_RARP is not set +CONFIG_IOSCHED_CFQ=y CONFIG_IRQCHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y # CONFIG_ISDN is not set +CONFIG_JBD2=y # CONFIG_JFFS2_FS is not set -CONFIG_JUMP_LABEL=y CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KGDB=y -# CONFIG_KGDB_KDB is not set -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set -# CONFIG_LDM_DEBUG is not set -CONFIG_LDM_PARTITION=y -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KEXEC=y +CONFIG_KEXEC_CORE=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_NETDEV is not set -# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LIBFDT=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOCALVERSION_AUTO=y +CONFIG_LZ4_DECOMPRESS=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y -CONFIG_MACH_OX820=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BOARDINFO=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MEMORY_ISOLATION=y CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_PCI=y CONFIG_MIGRATION=y +CONFIG_MODULES_TREE_LOOKUP=y CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MODULE_STRIPPED is not set -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_OXNAS=y -# CONFIG_MTD_SPLIT_FIRMWARE is not set -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -# CONFIG_MTD_UBI_FASTMAP is not set -# CONFIG_MTD_UBI_GLUEBI is not set -CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MULTI_IRQ_HANDLER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NLS=y +CONFIG_NOP_TRACER=y CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y CONFIG_NO_HZ_COMMON=y CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 CONFIG_OF=y CONFIG_OF_ADDRESS=y CONFIG_OF_ADDRESS_PCI=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_FLATTREE=y CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y CONFIG_OF_IRQ=y CONFIG_OF_MDIO=y -CONFIG_OF_MTD=y CONFIG_OF_NET=y CONFIG_OF_PCI=y CONFIG_OF_PCI_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OXNAS_RPS_TIMER=y CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEBUG is not set -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_PERFORMANCE is not set -# CONFIG_PCIEASPM_POWERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_PME=y -# CONFIG_PCI_DOMAINS_GENERIC is not set -CONFIG_PCI_OXNAS=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y CONFIG_PGTABLE_LEVELS=2 CONFIG_PHYLIB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_OXNAS=y -CONFIG_PLXTECH_RPS=y +# CONFIG_PINCTRL_SINGLE is not set CONFIG_PM=y CONFIG_PM_CLK=y # CONFIG_PM_DEBUG is not set -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_POWER_SUPPLY=y +CONFIG_PM_SLEEP=y CONFIG_PPS=y -CONFIG_PRINTK_TIME=y +CONFIG_PROBE_EVENTS=y CONFIG_PTP_1588_CLOCK=y -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y CONFIG_RAS=y CONFIG_RATIONAL=y -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_TRACE=y +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RD_XZ=y CONFIG_REALTEK_PHY=y CONFIG_REGMAP=y CONFIG_REGMAP_MMIO=y -CONFIG_RELAY=y CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_CONTROLLER_OXNAS=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_CMOS is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RESET_OXNAS=y +CONFIG_RING_BUFFER=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SCHED_DEBUG=y # CONFIG_SCHED_INFO is not set -CONFIG_SCSI=y +# CONFIG_SCSI_DMA is not set +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -# CONFIG_SERIAL_KGDB_NMI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y +CONFIG_SERIO=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_SERPORT=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_SLUB_DEBUG=y +CONFIG_SOCK_DIAG=y +CONFIG_SPARSE_IRQ=y CONFIG_SRCU=y +CONFIG_STACKTRACE=y +# CONFIG_STAGING is not set CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y # CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y CONFIG_SWIOTLB=y +CONFIG_SWPHY=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TREE_RCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -CONFIG_UBIFS_FS_LZO=y -CONFIG_UBIFS_FS_ZLIB=y -CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" -CONFIG_USB=y -CONFIG_USB_COMMON=y -# CONFIG_USB_EHCI_HCD is not set +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UPROBES=y +CONFIG_UPROBE_EVENTS=y CONFIG_USB_SUPPORT=y -# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USERIO is not set CONFIG_USE_OF=y CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_VFIO is not set +CONFIG_VERSATILE_FPGA_IRQ=y +CONFIG_VERSATILE_FPGA_IRQ_NR=4 +CONFIG_VFAT_FS=y # CONFIG_VFP is not set +# CONFIG_VLAN_8021Q is not set CONFIG_VM_EVENT_COUNTERS=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_NOWAYOUT=y -CONFIG_XPS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_WATCHDOG is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_BCJ=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_X86=y CONFIG_ZBOOT_ROM_BSS=0 CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZLIB_DEFLATE=y CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts similarity index 50% rename from target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts rename to target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts index 54aad1d86..c0bf34c3f 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts @@ -1,52 +1,33 @@ -/* - * Copyright (C) 2016 Daniel Golle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - /dts-v1/; + #include "ox820.dtsi" #include / { - model = "Akitio MyCloud mini"; + model = "Akitio MyCloud"; + + compatible = "akitio,mycloud", "oxsemi,ox820"; chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; - pcie-controller@47C00000 { - status = "disabled"; + memory { + /* 128Mbytes DDR */ + reg = <0x60000000 0x8000000>; }; - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - nr-ports = <2>; - }; - - nand@41000000 { - status = "okay"; - - }; - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; + aliases { + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; }; i2c-gpio { compatible = "i2c-gpio"; - gpios = <&GPIOB 9 0 &GPIOB 10 0>; + gpios = <&gpio1 9 0 &gpio1 10 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c>; i2c-gpio,delay-us = <10>; @@ -67,12 +48,12 @@ poll-interval = <100>; power { label = "power"; - gpios = <&GPIOA 11 1>; + gpios = <&gpio0 11 1>; linux,code = ; }; reset { label = "reset"; - gpios = <&GPIOB 6 1>; + gpios = <&gpio1 6 1>; linux,code = ; }; }; @@ -83,7 +64,7 @@ pinctrl-0 = <&pinctrl_leds>; status { label = "akitio:red:status"; - gpios = <&GPIOA 29 0>; + gpios = <&gpio0 29 0>; }; }; @@ -91,42 +72,51 @@ compatible = "gpio-poweroff"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_poweroff>; - gpios = <&GPIOB 13 2>; + gpios = <&gpio1 13 2>; }; +}; - pinctrl { +&pinctrl { + pinctrl_i2c: i2c-0 { i2c { - pinctrl_i2c: i2c-0 { - plxtech,pins = - <1 9 0 4 /* MF_B9 GPIO debounce */ - 1 10 0 4>; /* MF_B10 GPIO debounce */ - }; + pins = "gpio41", "gpio42"; /* MF_B9, MF_B10 */ + function = "gpio"; + /* ToDo: find a way to set debounce for those pins */ }; + }; + pinctrl_buttons: buttons-0 { buttons { - pinctrl_buttons: buttons-0 { - plxtech,pins = - <0 11 0 0 /* MF_A11 GPIO */ - 1 6 0 0>; /* MF_B6 GPIO */ - }; + pins = "gpio11", "gpio38"; /* MF_A11, MF_B6 GPIO */ + function = "gpio"; }; + }; + pinctrl_leds: leds-0 { leds { - pinctrl_leds: leds-0 { - plxtech,pins = - <0 29 0 0>; /* MF_A29 GPIO */ - }; + pins = "gpio29"; /* MF_A29 GPIO */ + function = "gpio"; }; + }; + pinctrl_poweroff: poweroff-0 { poweroff { - pinctrl_poweroff: poweroff-0 { - plxtech,pins = - <1 13 0 0>; /* MF_B13 GPIO */ - }; + pins = "gpio45"; /* MF_B13 GPIO */ + function = "gpio"; }; }; }; +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + &nandc { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand@0 { reg = <0>; #address-cells = <1>; @@ -136,12 +126,32 @@ partition@0 { label = "boot"; - reg = <0x00000000 0x026c0000>; + reg = <0x0 0x26c0000>; }; partition@26c0000 { label = "ubi"; - reg = <0x026c0000 0x0d940000>; + reg = <0x26c0000 0xd940000>; }; }; }; + +ða { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etha_mdio>; +}; + +&ehci { + status = "okay"; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts new file mode 100644 index 000000000..363fd30d2 --- /dev/null +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplug-pro.dts @@ -0,0 +1,98 @@ +/* + * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 + * + * Copyright (C) 2016 Neil Armstrong + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +#include "ox820.dtsi" + +/ { + model = "Cloud Engines PogoPlug Pro"; + + compatible = "cloudengines,pogoplugpro", "oxsemi,ox820"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + memory { + /* 128Mbytes DDR */ + reg = <0x60000000 0x8000000>; + }; + + aliases { + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + leds { + compatible = "gpio-leds"; + + blue { + label = "pogoplug:blue"; + gpios = <&gpio0 2 0>; + default-state = "keep"; + }; + + orange { + label = "pogoplug:orange"; + gpios = <&gpio1 16 1>; + default-state = "keep"; + }; + + green { + label = "pogoplug:green"; + gpios = <&gpio1 17 1>; + default-state = "keep"; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + +&nandc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "soft"; + nand-ecc-algo = "hamming"; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00e00000>; + read-only; + }; + + partition@e00000 { + label = "ubi"; + reg = <0x00e00000 0x07200000>; + }; + }; +}; + +ða { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etha_mdio>; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts similarity index 58% rename from target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts rename to target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts index ad93d4ec1..834ea7765 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-stg212.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg212.dts @@ -1,11 +1,3 @@ -/* - * Copyright (C) 2013 OpenWrt.org - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - /dts-v1/; #include "ox820.dtsi" @@ -15,25 +7,22 @@ / { model = "MitraStar Technology Corp. STG-212"; + compatible = "mitrastar,stg-212", "oxsemi,ox820"; + chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial mem=128M"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; - uart@44200000 { - status = "okay"; + memory { + /* 128Mbytes DDR */ + reg = <0x60000000 0x8000000>; }; - sata@45900000 { - status = "okay"; - }; - - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; + aliases { + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; }; gpio-keys-polled { @@ -44,12 +33,12 @@ reset { label = "reset"; - gpios = <&GPIOB 11 1>; + gpios = <&gpio1 11 1>; linux,code = ; }; copy { label = "copy"; - gpios = <&GPIOB 13 1>; + gpios = <&gpio1 13 1>; linux,code = ; }; }; @@ -58,29 +47,39 @@ compatible = "gpio-leds"; status { label = "zyxel:blue:status"; - gpios = <&GPIOB 5 0>; + gpios = <&gpio1 5 0>; }; status2 { label = "zyxel:red:status"; - gpios = <&GPIOB 6 1>; + gpios = <&gpio1 6 1>; }; copy { label = "zyxel:orange:copy"; - gpios = <&GPIOB 8 1>; + gpios = <&gpio1 8 1>; }; }; i2c-gpio { compatible = "i2c-gpio"; - gpios = <&GPIOB 9 0 &GPIOB 10 0>; + gpios = <&gpio1 9 0 &gpio1 10 0>; i2c-gpio,delay-us = <10>; }; }; +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + &nandc { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand@0 { reg = <0>; #address-cells = <1>; @@ -100,3 +99,18 @@ }; }; }; + +ða { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etha_mdio>; +}; + +&ehci { + status = "okay"; +}; + +&sata { + status = "okay"; +}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts deleted file mode 100644 index 5b087e93f..000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-pro.dts +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2013 Ma Haijun - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "ox820.dtsi" - -/ { - model = "Pogoplug Pro"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial"; - }; - - pcie-controller@47C00000 { - status = "okay"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - }; - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; - }; - - pinctrl { - leds { - pinctrl_leds: leds-0 { - plxtech,pins = - <0 2 0 0 /* MF_A2 */ - 1 16 0 0 /* MF_B16 */ - 1 17 0 0>; /* MF_B17 */ - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - blue { - label = "pogoplug:blue:internal"; - gpios = <&GPIOA 2 0>; - - }; - - orange { - label = "pogoplug:orange:usr"; - gpios = <&GPIOB 16 1>; - }; - - green { - label = "pogoplug:green:usr"; - gpios = <&GPIOB 17 1>; - }; - }; -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - /*read-only;*/ - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts deleted file mode 100644 index be0f6c907..000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-pogoplug-v3.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (C) 2014 Daniel Golle - * Copyright (C) 2013 Ma Haijun - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include "ox820.dtsi" - -/ { - model = "Pogoplug V3"; - - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial"; - }; - - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - }; - - ethernet@40400000 { - status = "okay"; - }; - - ehci@40200100 { - status = "okay"; - }; - - pinctrl { - leds { - pinctrl_leds: leds-0 { - plxtech,pins = - <0 2 0 0 /* MF_A2 */ - 1 16 0 0 /* MF_B16 */ - 1 17 0 0>; /* MF_B17 */ - }; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - blue { - label = "pogoplug:blue:internal"; - gpios = <&GPIOA 2 0>; - }; - - orange { - label = "pogoplug:orange:usr"; - gpios = <&GPIOB 16 1>; - }; - - green { - label = "pogoplug:green:usr"; - gpios = <&GPIOB 17 1>; - }; - }; - -}; - -&nandc { - status = "okay"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - /*read-only;*/ - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts similarity index 65% rename from target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts rename to target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts index a59addcca..badfa2578 100644 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820-kd20.dts +++ b/target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts @@ -1,12 +1,5 @@ -/* - * Copyright (C) 2014 Daniel Golle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - /dts-v1/; + #include "ox820.dtsi" #include @@ -14,40 +7,31 @@ / { model = "Shuttle KD20"; + compatible = "shuttle,kd20", "oxsemi,ox820"; + chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk=serial mem=256M"; + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; }; - pcie-controller@47C00000 { - status = "okay"; + memory { + /* 128Mbytes DDR */ + reg = <0x60000000 0x8000000>; }; - uart@44200000 { - status = "okay"; - }; - - sata@45900000 { - status = "okay"; - nr-ports = <2>; - }; - - ethernet@40400000 { - status = "okay"; - snps,phy-addr = <1>; - phy-mode = "rgmii-id"; - }; - - ehci@40200100 { - status = "okay"; + aliases { + serial0 = &uart0; + gpio0 = &gpio0; + gpio1 = &gpio1; }; i2c-gpio { compatible = "i2c-gpio"; - gpios = <&GPIOB 9 0 &GPIOB 10 0>; + gpios = <&gpio1 9 0 &gpio1 10 0>; i2c-gpio,delay-us = <10>; #address-cells = <1>; #size-cells = <0>; - pcf8563: rtc@51 { + rtc0: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -61,22 +45,22 @@ power { label = "power"; - gpios = <&GPIOA 10 1>; + gpios = <&gpio0 10 1>; linux,code = ; }; reset { label = "reset"; - gpios = <&GPIOA 11 1>; + gpios = <&gpio0 11 1>; linux,code = ; }; eject1 { label = "eject1"; - gpios = <&GPIOA 5 1>; + gpios = <&gpio0 5 1>; linux,code = ; }; eject2 { label = "eject2"; - gpios = <&GPIOA 6 1>; + gpios = <&gpio0 6 1>; linux,code = <162>; }; }; @@ -85,57 +69,67 @@ compatible = "gpio-leds"; status { label = "kd20:blue:status"; - gpios = <&GPIOB 16 0>; + gpios = <&gpio1 16 0>; }; status2 { label = "kd20:red:status"; - gpios = <&GPIOB 17 0>; + gpios = <&gpio1 17 0>; }; hdd1blue { label = "kd20:blue:hdd1"; - gpios = <&GPIOA 27 0>; + gpios = <&gpio0 27 0>; linux,default-trigger = "ata1"; }; hdd1red { label = "kd20:red:hdd1"; - gpios = <&GPIOB 4 0>; + gpios = <&gpio1 4 0>; }; hdd2blue { label = "kd20:blue:hdd2"; - gpios = <&GPIOB 6 0>; + gpios = <&gpio1 6 0>; linux,default-trigger = "ata2"; }; hdd2red { label = "kd20:red:hdd2"; - gpios = <&GPIOB 7 0>; + gpios = <&gpio1 7 0>; }; usb { label = "kd20:blue:usb"; - gpios = <&GPIOB 8 0>; + gpios = <&gpio1 8 0>; }; }; beeper: beeper { compatible = "gpio-beeper"; - gpios = <&GPIOB 11 0>; + gpios = <&gpio1 11 0>; }; gpio-fan { compatible = "gpio-fan"; - gpios = <&GPIOA 2 1>; + gpios = <&gpio0 2 1>; gpio-fan,speed-map = <0 0 3000 1>; }; gpio-poweroff { compatible = "gpio-poweroff"; - gpios = <&GPIOA 9 0>; + gpios = <&gpio0 9 0>; }; }; +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; + &nandc { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand@0 { reg = <0>; #address-cells = <1>; @@ -171,3 +165,23 @@ }; }; }; + +ða { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etha_mdio>; +}; + +&ehci { + status = "okay"; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi b/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi deleted file mode 100644 index c096a7d1c..000000000 --- a/target/linux/oxnas/files/arch/arm/boot/dts/ox820.dtsi +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright (C) 2013 Ma Haijun - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" - -/ { - compatible = "plxtech,nas7820", "plxtech,nas782x"; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - /* alias to determine bank index */ - gpio0 = &GPIOA; - gpio1 = &GPIOB; - - ethernet0 = &gmac; - }; - - cpus { - cpu@0 { - compatible = "arm,arm11mpcore"; - }; - cpu@1 { - compatible = "arm,arm11mpcore"; - }; - }; - - gic: gic@47001000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x47001000 0x1000>, - <0x47000100 0x0100>; - }; - - rst: reset-controller@44E00034 { - compatible = "plxtech,nas782x-reset"; - #reset-cells = <1>; - reg = <0x44E00034 0x8>; /* currently not used */ - }; - - rps: rps@44400000 { - compatible = "plxtech,nas782x-rps"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x44400000 0x14>; - interrupts = <0 5 0x304>; - }; - - /* external oscillator */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&osc>; - }; - - plla: plla@44e001f0 { - compatible = "plxtech,nas782x-plla"; - #clock-cells = <0>; - clocks = <&osc>; - reg = <0x44e001f0 0x10>; - }; - - pllb: pllb@44f001f0 { - compatible = "plxtech,nas782x-pllb"; - #clock-cells = <0>; - clocks = <&osc>; - reg = <0x44f001f0 0x10>; - resets = <&rst 31>; - }; - - stdclk: stdclk { - compatible = "plxtech,nas782x-stdclk"; - #clock-cells = <1>; - clocks = <&osc>; - }; - - twdclk: twdclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&plla>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - pinctrl { - /* act as a simple bus, so children will be probed automatically */ - #address-cells = <1>; - #size-cells = <1>; - compatible = "plxtech,nas782x-pinctrl", "simple-bus"; - ranges; - - plxtech,mux-mask = < - 0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0 - 0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3 - >; - - GPIOA: gpio@44000000 { - compatible = "plxtech,nas782x-gpio"; - reg = <0x44000000 0x100>, <0x44E00000 0x200>; - interrupts = <0 21 0x304>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-lines = <32>; /* real gpio pin count */ - }; - - GPIOB: gpio@44100000 { - compatible = "plxtech,nas782x-gpio"; - reg = <0x44100000 0x100>, <0x44F00000 0x200>; - interrupts = <0 22 0x304>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-lines = <18>; /* real gpio pin count */ - }; - - uart0 { - pinctrl_uart0: uart0-0 { - plxtech,pins = - <0 30 5 0 /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */ - 0 31 5 0>; /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */ - }; - }; - - gmac0 { - pinctrl_gmac0: gmac0-0 { - plxtech,pins = - <0 3 1 0 /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */ - 0 4 1 0>; /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */ - }; - }; - - nand0 { - pinctrl_nand0: nand0-0 { - plxtech,pins = - <0 12 1 0 /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */ - 0 13 1 0 /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */ - 0 14 1 0 /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */ - 0 15 1 0 /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */ - 0 16 1 0 /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */ - 0 17 1 0 /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */ - 0 18 1 0 /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */ - 0 19 1 0 /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */ - - 0 20 1 0 /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */ - 0 21 1 0 /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */ - 0 22 1 0 /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */ - 0 23 1 0 /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */ - 0 24 1 0>; /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */ - }; - }; - }; - - pcie-controller@47C00000 { - compatible = "plxtech,nas782x-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - /* flag & space bus address host address size */ - ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 - 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 - 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 - 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; - - bus-range = <0x00 0x7f>; - - /* cfg inbound translator phy*/ - reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>; - - #interrupt-cells = <1>; - /* wild card mask, match all bus address & interrupt specifier */ - /* format: bus address mask, interrupt specifier mask */ - /* each bit 1 means need match, 0 means ignored when match */ - interrupt-map-mask = <0 0 0 0>; - /* format: a list of: bus address, interrupt specifier, - * parent interrupt controller & specifier */ - interrupt-map = <0 0 0 0 &gic 0 19 0x304>; - - gpios = <&GPIOB 12 0>; - clocks = <&stdclk 8>, <&pllb>; - clock-names = "pcie", "busclk"; - resets = <&rst 7>, <&rst 14>; - reset-names = "pcie", "phy"; - - plxtech,pcie-hcsl-bit = <2>; - plxtech,pcie-ctrl-offset = <0x120>; - plxtech,pcie-outbound-offset = <0x138>; - status = "disabled"; - }; - - pcie-controller@47E00000 { - compatible = "plxtech,nas782x-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - - /* flag & space bus address host address size */ - ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 - 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 - 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 - 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; - - bus-range = <0x80 0xff>; - - /* cfg inbound translator phy*/ - reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>; - - #interrupt-cells = <1>; - /* wild card mask, match all bus address & interrupt specifier */ - /* format: bus address mask, interrupt specifier mask */ - /* each bit 1 means need match, 0 means ignored when match */ - interrupt-map-mask = <0 0 0 0>; - /* format: a list of: bus address, interrupt specifier, - * parent interrupt controller & specifier */ - interrupt-map = <0 0 0 0 &gic 0 20 0x304>; - - /* gpios = <&GPIOB 12 0>; */ - clocks = <&stdclk 11>, <&pllb>; - clock-names = "pcie", "busclk"; - resets = <&rst 23>, <&rst 14>; - reset-names = "pcie", "phy"; - - plxtech,pcie-hcsl-bit = <3>; - plxtech,pcie-ctrl-offset = <0x124>; - plxtech,pcie-outbound-offset = <0x174>; - status = "disabled"; - }; - - local-timer@47000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x47000600 0x20>; - interrupts = <1 13 0x304>; /* percpu, irq 29, cpu mask 3, level high */ - clocks = <&twdclk>; - }; - - watchdog@47000620 { - compatible = "mpcore_wdt"; - reg = <0x47000620 0x20>; - interrupts = <1 14 0x304>; /* percpu, irq 30, cpu mask 3, level high */ - clocks = <&twdclk>; - }; - - timer@44400200 { - compatible = "plxtech,nas782x-rps-timer"; - reg = <0x44400200 0x40>; - clocks = <&sysclk>; - }; - - uart0: uart@44200000 { - compatible = "ns16550a"; - reg = <0x44200000 0x100>; - clock-frequency = <6250000>; - interrupts = <0 23 0x304>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "disabled"; - }; - - sata@45900000 { - compatible = "plxtech,nas782x-sata"; - /* ports dmactl sgdma */ - reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>, - /* core phy descriptors (optional) */ - <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>; - interrupts = <0 18 0x304>; - clocks = <&stdclk 4>; - resets = <&rst 11>, <&rst 12>, <&rst 13>; - reset-names = "sata", "link", "phy"; - nr-ports = <1>; - status = "disabled"; - }; - - nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk 9>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand0>; - resets = <&rst 15>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gmac: ethernet@40400000 { - compatible = "plxtech,nas782x-gmac", "snps,dwmac"; - reg = <0x40400000 0x2000>; - interrupts = <0 8 0x304>, <0 17 0x304>; - interrupt-names = "macirq", "eth_wake_irq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - clocks = <&stdclk 7>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gmac0>; - resets = <&rst 6>; - status = "disabled"; - }; - - ehci@40200100 { - compatible = "plxtech,nas782x-ehci"; - reg = <0x40200100 0xf00>; - interrupts = <0 7 0x304>; - clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>; - clock-names = "usb", "refsrc", "phyref"; - resets = <&rst 4>, <&rst 5>, <&rst 26>; - reset-names = "host", "phya", "phyb"; - /* Otherwise ref300 is used, which is derived from sata phy - * in that case, usb depends on sata initialization */ - /* FIXME: how to make this dependency explicit ? */ - plxtech,ehci_use_pllb; - status = "disabled"; - }; -}; diff --git a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig b/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig deleted file mode 100644 index bb0a9d68a..000000000 --- a/target/linux/oxnas/files/arch/arm/configs/ox820_defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_CROSS_COMPILE="arm-linux-gnueabi-" -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_CGROUPS=y -CONFIG_NAMESPACES=y -CONFIG_EMBEDDED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_JUMP_LABEL=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_ARCH_OXNAS=y -# CONFIG_DMA_CACHE_RWFO is not set -CONFIG_DMA_CACHE_FIQ_BROADCAST=y -CONFIG_PCI=y -CONFIG_PCI_OXNAS=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_NR_CPUS=2 -CONFIG_HOTPLUG_CPU=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_UACCESS_WITH_MEMCPY=y -CONFIG_USE_OF=y -CONFIG_BINFMT_MISC=y -# CONFIG_SUSPEND is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IPV6=y -CONFIG_CFG80211=y -CONFIG_MAC80211=y -CONFIG_MAC80211_RC_PID=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_OXNAS=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_SD=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_ATA=y -CONFIG_SATA_OXNAS=y -CONFIG_NETDEVICES=y -CONFIG_STMMAC_ETH=y -CONFIG_STMMAC_DEBUG_FS=y -CONFIG_STMMAC_DA=y -CONFIG_ATH_CARDS=y -CONFIG_ATH9K=y -CONFIG_ATH9K_LEGACY_RATE_CONTROL=y -# CONFIG_RTL_CARDS is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=1 -CONFIG_SERIAL_8250_RUNTIME_UARTS=1 -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_GPIO_SYSFS=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_OXNAS=y -CONFIG_USB_STORAGE=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_COMMON_CLK_DEBUG=y -CONFIG_EXT2_FS=y -CONFIG_EXT4_FS=y -CONFIG_FUSE_FS=y -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_NTFS_RW=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_PRINTK_TIME=y -# CONFIG_ENABLE_WARN_DEPRECATED is not set -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_UART_8250=y -CONFIG_DEBUG_UART_PHYS=0x44200000 -CONFIG_DEBUG_UART_VIRT=0xF0000000 -CONFIG_DEBUG_UART_8250_SHIFT=0 -CONFIG_EARLY_PRINTK=y -CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h b/target/linux/oxnas/files/arch/arm/include/debug/uncompress-ox820.h similarity index 100% rename from target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/uncompress.h rename to target/linux/oxnas/files/arch/arm/include/debug/uncompress-ox820.h diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig b/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig deleted file mode 100644 index 6bdf3f6ef..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -choice - prompt "Oxnas platform type" - default MACH_OXNAS - depends on ARCH_OXNAS - -config MACH_OX820 - bool "Generic NAS7820 Support" - select ARM_GIC - select GENERIC_CLOCKEVENTS - select CPU_V6K - select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP - select HAVE_SMP - select PLXTECH_RPS - select CLKSRC_OF - select CLKSRC_RPS_TIMER - select USB_ARCH_HAS_EHCI - select PINCTRL_OXNAS - select PINCTRL - select RESET_CONTROLLER_OXNAS - select ARCH_WANT_LIBATA_LEDS - help - Include support for the ox820 platform. - -endchoice diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile deleted file mode 100644 index 6862c3498..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Makefile for the linux kernel. -# - -obj-$(CONFIG_MACH_OX820) += mach-ox820.o -obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_DMA_CACHE_FIQ_BROADCAST) += fiq.o -obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot b/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot deleted file mode 100644 index b52e473d6..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/Makefile.boot +++ /dev/null @@ -1,2 +0,0 @@ - zreladdr-y += 0x60008000 -params_phys-y := 0x60000100 diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S deleted file mode 100644 index 6acd5a739..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2012 Gateworks Corporation - * Chris Lang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include - -#define D_CACHE_LINE_SIZE 32 - - .text - -/* - * R8 - DMA Start Address - * R9 - DMA Length - * R10 - DMA Direction - * R11 - DMA type - * R12 - fiq_buffer Address -*/ - - .global ox820_fiq_end -ENTRY(ox820_fiq_start) - str r8, [r13] - - ldmia r12, {r8, r9, r10} - and r11, r10, #0x3000000 - and r10, r10, #0xff - - teq r11, #0x1000000 - beq ox820_dma_map_area - teq r11, #0x2000000 - beq ox820_dma_unmap_area - /* fall through */ -ox820_dma_flush_range: - bic r8, r8, #D_CACHE_LINE_SIZE - 1 -1: - mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - /* fall through */ -ox820_fiq_exit: - mov r8, #0 - str r8, [r12, #8] - mcr p15, 0, r8, c7, c10, 4 @ drain write buffer - subs pc, lr, #4 - -ox820_dma_map_area: - add r9, r9, r8 - teq r10, #DMA_FROM_DEVICE - beq ox820_dma_inv_range - teq r10, #DMA_TO_DEVICE - bne ox820_dma_flush_range - /* fall through */ -ox820_dma_clean_range: - bic r8, r8, #D_CACHE_LINE_SIZE - 1 -1: - mcr p15, 0, r8, c7, c10, 1 @ clean D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - b ox820_fiq_exit - -ox820_dma_unmap_area: - add r9, r9, r8 - teq r10, #DMA_TO_DEVICE - beq ox820_fiq_exit - /* fall through */ -ox820_dma_inv_range: - tst r8, #D_CACHE_LINE_SIZE - 1 - bic r8, r8, #D_CACHE_LINE_SIZE - 1 - mcrne p15, 0, r8, c7, c10, 1 @ clean D line - tst r9, #D_CACHE_LINE_SIZE - 1 - bic r9, r9, #D_CACHE_LINE_SIZE - 1 - mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line -1: - mcr p15, 0, r8, c7, c6, 1 @ invalidate D line - add r8, r8, #D_CACHE_LINE_SIZE - cmp r8, r9 - blo 1b - b ox820_fiq_exit - -ox820_fiq_end: diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S deleted file mode 100644 index a63edae62..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/headsmp.S +++ /dev/null @@ -1,27 +0,0 @@ -/* - * linux/arch/arm/mach-ox820/headsmp.S - * - * Copyright (c) 2003 ARM Limited - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - - __INIT - -/* - * OX820 specific entry point for secondary CPUs. - */ -ENTRY(ox820_secondary_startup) - mov r4, #0 - /* invalidate both caches and branch target cache */ - mcr p15, 0, r4, c7, c7, 0 - /* - * we've been released from the holding pen: secondary_stack - * should now contain the SVC stack for this core - */ - b secondary_startup diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c deleted file mode 100644 index e3c9cb5db..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/hotplug.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * linux/arch/arm/mach-realview/hotplug.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include - -#include -#include - -static inline void cpu_enter_lowpower(void) -{ - unsigned int v; - - asm volatile( - " mcr p15, 0, %1, c7, c5, 0\n" - " mcr p15, 0, %1, c7, c10, 4\n" - /* - * Turn off coherency - */ - " mrc p15, 0, %0, c1, c0, 1\n" - " bic %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, %2\n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=&r" (v) - : "r" (0), "Ir" (CR_C) - : "cc"); -} - -static inline void cpu_leave_lowpower(void) -{ - unsigned int v; - - asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" - " orr %0, %0, %1\n" - " mcr p15, 0, %0, c1, c0, 0\n" - " mrc p15, 0, %0, c1, c0, 1\n" - " orr %0, %0, #0x20\n" - " mcr p15, 0, %0, c1, c0, 1\n" - : "=&r" (v) - : "Ir" (CR_C) - : "cc"); -} - -static inline void platform_do_lowpower(unsigned int cpu, int *spurious) -{ - /* - * there is no power-control hardware on this platform, so all - * we can do is put the core into WFI; this is safe as the calling - * code will have already disabled interrupts - */ - for (;;) { - /* - * here's the WFI - */ - asm(".word 0xe320f003\n" - : - : - : "memory", "cc"); - - if (pen_release == cpu_logical_map(cpu)) { - /* - * OK, proper wakeup, we're done - */ - break; - } - - /* - * Getting here, means that we have come out of WFI without - * having been woken up - this shouldn't happen - * - * Just note it happening - when we're woken, we can report - * its occurrence. - */ - (*spurious)++; - } -} - -/* - * platform-specific code to shutdown a CPU - * - * Called with IRQs disabled - */ -void ox820_cpu_die(unsigned int cpu) -{ - int spurious = 0; - - /* - * we're ready for shutdown now, so do it - */ - cpu_enter_lowpower(); - platform_do_lowpower(cpu, &spurious); - - /* - * bring this CPU back into the world of cache - * coherency, and then restore interrupts - */ - cpu_leave_lowpower(); - - if (spurious) - pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); -} diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h deleted file mode 100644 index caae772c3..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/hardware.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * arch/arm/mach-0x820/include/mach/hardware.h - * - * Copyright (C) 2009 Oxford Semiconductor Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include -#include - -/* - * Location of flags and vectors in SRAM for controlling the booting of the - * secondary ARM11 processors. - */ - -#define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA -#define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100) - -#define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) -#define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) - -/** - * System block reset and clock control - */ -#define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20) -#define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24) -#define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C) -#define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30) -#define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34) -#define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38) - -#define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48) -#define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64) -#define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C) -#define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78) -#define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100) - -/* Scratch registers */ -#define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) -#define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) -#define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc) -#define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0) - -#define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0) -#define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4) -#define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8) -#define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC) - -#define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40) -#define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44) -#define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8) -#define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84) -#define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90) - -/* pcie */ -#define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114) - -/* System control multi-function pin function selection */ -#define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14) -#define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c) -#define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94) -#define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c) -#define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4) -#define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac) - -/* Secure control multi-function pin function selection */ -#define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14) -#define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c) -#define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94) -#define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c) -#define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4) -#define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac) - -#define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68) -#define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98) -#define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0) -#define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8) -#define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0) -#define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) -#define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) - -#define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10) -#define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108) -#define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C) -#define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC) - -#define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10) -#define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108) -#define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C) -#define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC) - -#define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224) - -#define REF300_DIV_INT_SHIFT 8 -#define REF300_DIV_FRAC_SHIFT 0 -#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) -#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) - -#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 -#define USBHSPHY_SUSPENDM_MANUAL_STATE 15 -#define USBHSPHY_ATE_ESET 14 -#define USBHSPHY_TEST_DIN 6 -#define USBHSPHY_TEST_ADD 2 -#define USBHSPHY_TEST_DOUT_SEL 1 -#define USBHSPHY_TEST_CLK 0 - -#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 -#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) -#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) -#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) - -#define USBAMUX_DEVICE BIT(4) - -#define USBPHY_REFCLKDIV_SHIFT 2 -#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) -#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) -#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) - -#define USB_CTRL_USB_CKO_SEL_BIT 0 - -#define USB_INT_CLK_XTAL 0 -#define USB_INT_CLK_REF300 2 -#define USB_INT_CLK_PLLB 3 - -#define SYS_CTRL_GMAC_CKEN_RX_IN 14 -#define SYS_CTRL_GMAC_CKEN_RXN_OUT 13 -#define SYS_CTRL_GMAC_CKEN_RX_OUT 12 -#define SYS_CTRL_GMAC_CKEN_TX_IN 10 -#define SYS_CTRL_GMAC_CKEN_TXN_OUT 9 -#define SYS_CTRL_GMAC_CKEN_TX_OUT 8 -#define SYS_CTRL_GMAC_RX_SOURCE 7 -#define SYS_CTRL_GMAC_TX_SOURCE 6 -#define SYS_CTRL_GMAC_LOW_TX_SOURCE 4 -#define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3 -#define SYS_CTRL_GMAC_RGMII 2 -#define SYS_CTRL_GMAC_SIMPLE_MUX 1 -#define SYS_CTRL_GMAC_CKEN_GTX 0 -#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0 -#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8 -#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16 -#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24 -#define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)< - -#define OXNAS_UART1_BASE 0x44200000 -#define OXNAS_UART1_SIZE SZ_32 -#define OXNAS_UART1_BASE_VA 0xF0000000 - -#define OXNAS_UART2_BASE 0x44300000 -#define OXNAS_UART2_SIZE SZ_32 - -#define OXNAS_PERCPU_BASE 0x47000000 -#define OXNAS_PERCPU_SIZE SZ_8K -#define OXNAS_PERCPU_BASE_VA 0xF0002000 - -#define OXNAS_SYSCRTL_BASE 0x44E00000 -#define OXNAS_SYSCRTL_SIZE SZ_4K -#define OXNAS_SYSCRTL_BASE_VA 0xF0004000 - -#define OXNAS_SECCRTL_BASE 0x44F00000 -#define OXNAS_SECCRTL_SIZE SZ_4K -#define OXNAS_SECCRTL_BASE_VA 0xF0005000 - -#define OXNAS_RPSA_BASE 0x44400000 -#define OXNAS_RPSA_SIZE SZ_4K -#define OXNAS_RPSA_BASE_VA 0xF0006000 - -#define OXNAS_RPSC_BASE 0x44500000 -#define OXNAS_RPSC_SIZE SZ_4K -#define OXNAS_RPSC_BASE_VA 0xF0007000 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h deleted file mode 100644 index bcafd10ae..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/irqs.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_SOFT 1 -#define NR_IRQS 160 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h deleted file mode 100644 index 112863596..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/smp.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * smp.h - * - * Created on: Sep 24, 2013 - * Author: mahaijun - */ - -#ifndef _NAS782X_SMP_H_ -#define _NAS782X_SMP_H_ - -#include - -extern void ox820_secondary_startup(void); -extern void ox820_cpu_die(unsigned int cpu); - -static inline void write_pen_release(int val) -{ - writel(val, HOLDINGPEN_CPU); -} - -static inline int read_pen_release(void) -{ - return readl(HOLDINGPEN_CPU); -} - -extern struct smp_operations ox820_smp_ops; - -extern unsigned char ox820_fiq_start, ox820_fiq_end; -extern void v6_dma_map_area(const void *, size_t, int); -extern void v6_dma_unmap_area(const void *, size_t, int); -extern void v6_dma_flush_range(const void *, const void *); -extern void v6_flush_kern_dcache_area(void *, size_t); - -#endif /* _NAS782X_SMP_H_ */ diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h deleted file mode 100644 index 4133594d1..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 6250000 - -#endif diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h b/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h deleted file mode 100644 index 910d7019c..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/include/mach/utils.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef _NAS782X_UTILS_H -#define _NAS782X_UTILS_H - -#include -#include - -static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask) -{ - u32 val = readl_relaxed(p); - - val &= ~mask; - writel_relaxed(val, p); -} - -static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask) -{ - u32 val = readl_relaxed(p); - - val |= mask; - writel_relaxed(val, p); -} - -static inline void oxnas_register_value_mask(void __iomem *p, - unsigned mask, unsigned new_value) -{ - /* TODO sanity check mask & new_value = new_value */ - u32 val = readl_relaxed(p); - - val &= ~mask; - val |= new_value; - writel_relaxed(val, p); -} - -#endif /* _NAS782X_UTILS_H */ diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c deleted file mode 100644 index 31b7c9058..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/mach-ox820.c +++ /dev/null @@ -1,183 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct map_desc ox820_io_desc[] __initdata = { - { - .virtual = (unsigned long)OXNAS_PERCPU_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_PERCPU_BASE), - .length = OXNAS_PERCPU_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE), - .length = OXNAS_SYSCRTL_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE), - .length = OXNAS_SECCRTL_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_RPSA_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_RPSA_BASE), - .length = OXNAS_RPSA_SIZE, - .type = MT_DEVICE, - }, - { - .virtual = (unsigned long)OXNAS_RPSC_BASE_VA, - .pfn = __phys_to_pfn(OXNAS_RPSC_BASE), - .length = OXNAS_RPSC_SIZE, - .type = MT_DEVICE, - }, -}; - -void __init ox820_map_common_io(void) -{ - debug_ll_io_init(); - iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc)); -} - -static void __init ox820_dt_init(void) -{ - int ret; - - ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, - NULL); - - if (ret) { - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); - } - -} - -static void __init ox820_timer_init(void) -{ - of_clk_init(NULL); - clocksource_probe(); -} - -void ox820_init_early(void) -{ - -} - -void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd) -{ - u32 value; - -/* Assert reset to cores as per power on defaults - * Don't touch the DDR interface as things will come to an impromptu stop - * NB Possibly should be asserting reset for PLLB, but there are timing - * concerns here according to the docs */ - value = BIT(SYS_CTRL_RST_COPRO) | - BIT(SYS_CTRL_RST_USBHS) | - BIT(SYS_CTRL_RST_USBHSPHYA) | - BIT(SYS_CTRL_RST_MACA) | - BIT(SYS_CTRL_RST_PCIEA) | - BIT(SYS_CTRL_RST_SGDMA) | - BIT(SYS_CTRL_RST_CIPHER) | - BIT(SYS_CTRL_RST_SATA) | - BIT(SYS_CTRL_RST_SATA_LINK) | - BIT(SYS_CTRL_RST_SATA_PHY) | - BIT(SYS_CTRL_RST_PCIEPHY) | - BIT(SYS_CTRL_RST_STATIC) | - BIT(SYS_CTRL_RST_UART1) | - BIT(SYS_CTRL_RST_UART2) | - BIT(SYS_CTRL_RST_MISC) | - BIT(SYS_CTRL_RST_I2S) | - BIT(SYS_CTRL_RST_SD) | - BIT(SYS_CTRL_RST_MACB) | - BIT(SYS_CTRL_RST_PCIEB) | - BIT(SYS_CTRL_RST_VIDEO) | - BIT(SYS_CTRL_RST_USBHSPHYB) | - BIT(SYS_CTRL_RST_USBDEV); - - writel(value, SYS_CTRL_RST_SET_CTRL); - - /* Release reset to cores as per power on defaults */ - writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL); - - /* Disable clocks to cores as per power-on defaults - must leave DDR - * related clocks enabled otherwise we'll stop rather abruptly. */ - value = - BIT(SYS_CTRL_CLK_COPRO) | - BIT(SYS_CTRL_CLK_DMA) | - BIT(SYS_CTRL_CLK_CIPHER) | - BIT(SYS_CTRL_CLK_SD) | - BIT(SYS_CTRL_CLK_SATA) | - BIT(SYS_CTRL_CLK_I2S) | - BIT(SYS_CTRL_CLK_USBHS) | - BIT(SYS_CTRL_CLK_MAC) | - BIT(SYS_CTRL_CLK_PCIEA) | - BIT(SYS_CTRL_CLK_STATIC) | - BIT(SYS_CTRL_CLK_MACB) | - BIT(SYS_CTRL_CLK_PCIEB) | - BIT(SYS_CTRL_CLK_REF600) | - BIT(SYS_CTRL_CLK_USBDEV); - - writel(value, SYS_CTRL_CLK_CLR_CTRL); - - /* Enable clocks to cores as per power-on defaults */ - - /* Set sys-control pin mux'ing as per power-on defaults */ - writel(0, SYS_CTRL_SECONDARY_SEL); - writel(0, SYS_CTRL_TERTIARY_SEL); - writel(0, SYS_CTRL_QUATERNARY_SEL); - writel(0, SYS_CTRL_DEBUG_SEL); - writel(0, SYS_CTRL_ALTERNATIVE_SEL); - writel(0, SYS_CTRL_PULLUP_SEL); - - writel(0, SEC_CTRL_SECONDARY_SEL); - writel(0, SEC_CTRL_TERTIARY_SEL); - writel(0, SEC_CTRL_QUATERNARY_SEL); - writel(0, SEC_CTRL_DEBUG_SEL); - writel(0, SEC_CTRL_ALTERNATIVE_SEL); - writel(0, SEC_CTRL_PULLUP_SEL); - - /* No need to save any state, as the ROM loader can determine whether - * reset is due to power cycling or programatic action, just hit the - * (self-clearing) CPU reset bit of the block reset register */ - value = - BIT(SYS_CTRL_RST_SCU) | - BIT(SYS_CTRL_RST_ARM0) | - BIT(SYS_CTRL_RST_ARM1); - - writel(value, SYS_CTRL_RST_SET_CTRL); -} - -static const char * const ox820_dt_board_compat[] = { - "plxtech,nas7820", - "plxtech,nas7821", - "plxtech,nas7825", - NULL -}; - -DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)") - .map_io = ox820_map_common_io, - .smp = smp_ops(ox820_smp_ops), - .init_early = ox820_init_early, - .init_time = ox820_timer_init, - .init_machine = ox820_dt_init, - .restart = ox820_assert_system_reset, - .dt_compat = ox820_dt_board_compat, -MACHINE_END diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c b/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c deleted file mode 100644 index 8e4e2d827..000000000 --- a/target/linux/oxnas/files/arch/arm/mach-oxnas/platsmp.c +++ /dev/null @@ -1,315 +0,0 @@ -/* - * arch/arm/mach-ox820/platsmp.c - * - * Copyright (C) 2002 ARM Ltd. - * All Rights Reserved - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_DMA_CACHE_FIQ_BROADCAST - -#define FIQ_GENERATE 0x00000002 -#define OXNAS_MAP_AREA 0x01000000 -#define OXNAS_UNMAP_AREA 0x02000000 -#define OXNAS_FLUSH_RANGE 0x03000000 - -struct fiq_req { - union { - struct { - const void *addr; - size_t size; - } map; - struct { - const void *addr; - size_t size; - } unmap; - struct { - const void *start; - const void *end; - } flush; - }; - volatile uint flags; - void __iomem *reg; -} ____cacheline_aligned; - -static struct fiq_handler fh = { - .name = "oxnas-fiq" -}; - -DEFINE_PER_CPU(struct fiq_req, fiq_data); - -static inline void ox820_set_fiq_regs(unsigned int cpu) -{ - struct pt_regs FIQ_regs; - struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu); - - FIQ_regs.ARM_r8 = 0; - FIQ_regs.ARM_ip = (unsigned int)fiq_req; - FIQ_regs.ARM_sp = (int)(cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT); - fiq_req->reg = cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT; - - set_fiq_regs(&FIQ_regs); -} - -static void __init ox820_init_fiq(void) -{ - void *fiqhandler_start; - unsigned int fiqhandler_length; - int ret; - - fiqhandler_start = &ox820_fiq_start; - fiqhandler_length = &ox820_fiq_end - &ox820_fiq_start; - - ret = claim_fiq(&fh); - - if (ret) - return; - - set_fiq_handler(fiqhandler_start, fiqhandler_length); - - writel(IRQ_SOFT, RPSA_FIQ_IRQ_TO_FIQ); - writel(1, RPSA_FIQ_ENABLE); - writel(IRQ_SOFT, RPSC_FIQ_IRQ_TO_FIQ); - writel(1, RPSC_FIQ_ENABLE); -} - -void fiq_dma_map_area(const void *addr, size_t size, int dir) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_map_area(addr, size, dir); - return; - } - - req = this_cpu_ptr(&fiq_data); - req->map.addr = addr; - req->map.size = size; - req->flags = dir | OXNAS_MAP_AREA; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_map_area(addr, size, dir); - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_dma_unmap_area(const void *addr, size_t size, int dir) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_unmap_area(addr, size, dir); - return; - } - - req = this_cpu_ptr(&fiq_data); - req->unmap.addr = addr; - req->unmap.size = size; - req->flags = dir | OXNAS_UNMAP_AREA; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_unmap_area(addr, size, dir); - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_dma_flush_range(const void *start, const void *end) -{ - unsigned long flags; - struct fiq_req *req; - - raw_local_irq_save(flags); - /* currently, not possible to take cpu0 down, so only check cpu1 */ - if (!cpu_online(1)) { - raw_local_irq_restore(flags); - v6_dma_flush_range(start, end); - return; - } - - req = this_cpu_ptr(&fiq_data); - - req->flush.start = start; - req->flush.end = end; - req->flags = OXNAS_FLUSH_RANGE; - smp_mb(); - - writel_relaxed(FIQ_GENERATE, req->reg); - - v6_dma_flush_range(start, end); - - while (req->flags) - barrier(); - - raw_local_irq_restore(flags); -} - -void fiq_flush_kern_dcache_area(void *addr, size_t size) -{ - fiq_dma_flush_range(addr, addr + size); -} -#else - -#define ox820_set_fiq_regs(cpu) do {} while (0) /* nothing */ -#define ox820_init_fiq() do {} while (0) /* nothing */ - -#endif /* DMA_CACHE_FIQ_BROADCAST */ - -static DEFINE_SPINLOCK(boot_lock); - -void ox820_secondary_init(unsigned int cpu) -{ - /* - * Setup Secondary Core FIQ regs - */ - ox820_set_fiq_regs(1); - - /* - * let the primary processor know we're out of the - * pen, then head off into the C entry point - */ - write_pen_release(-1); - - /* - * Synchronise with the boot thread. - */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); -} - -int ox820_boot_secondary(unsigned int cpu, struct task_struct *idle) -{ - unsigned long timeout; - - /* - * Set synchronisation state between this boot processor - * and the secondary one - */ - spin_lock(&boot_lock); - - /* - * This is really belt and braces; we hold unintended secondary - * CPUs in the holding pen until we're ready for them. However, - * since we haven't sent them a soft interrupt, they shouldn't - * be there. - */ - write_pen_release(cpu); - - writel(1, IOMEM(OXNAS_GICN_BASE_VA(cpu) + GIC_CPU_CTRL)); - - /* - * Send the secondary CPU a soft interrupt, thereby causing - * the boot monitor to read the system wide flags register, - * and branch to the address found there. - */ - - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) { - smp_rmb(); - if (read_pen_release() == -1) - break; - - udelay(10); - } - - /* - * now the secondary core is starting up let it run its - * calibrations, then wait for it to finish - */ - spin_unlock(&boot_lock); - - return read_pen_release() != -1 ? -ENOSYS : 0; -} - -void *scu_base_addr(void) -{ - return IOMEM(OXNAS_SCU_BASE_VA); -} - -/* - * Initialise the CPU possible map early - this describes the CPUs - * which may be present or become present in the system. - */ -static void __init ox820_smp_init_cpus(void) -{ - void __iomem *scu_base = scu_base_addr(); - unsigned int i, ncores; - - ncores = scu_base ? scu_get_core_count(scu_base) : 1; - - /* sanity check */ - if (ncores > nr_cpu_ids) { - pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", - ncores, nr_cpu_ids); - ncores = nr_cpu_ids; - } - - for (i = 0; i < ncores; i++) - set_cpu_possible(i, true); -} - -static void __init ox820_smp_prepare_cpus(unsigned int max_cpus) -{ - - scu_enable(scu_base_addr()); - - /* - * Write the address of secondary startup into the - * system-wide flags register. The BootMonitor waits - * until it receives a soft interrupt, and then the - * secondary CPU branches to this address. - */ - writel(virt_to_phys(ox820_secondary_startup), - HOLDINGPEN_LOCATION); - ox820_init_fiq(); - - ox820_set_fiq_regs(0); -} - -struct smp_operations ox820_smp_ops __initdata = { - .smp_init_cpus = ox820_smp_init_cpus, - .smp_prepare_cpus = ox820_smp_prepare_cpus, - .smp_secondary_init = ox820_secondary_init, - .smp_boot_secondary = ox820_boot_secondary, -#ifdef CONFIG_HOTPLUG_CPU - .cpu_die = ox820_cpu_die, -#endif -}; diff --git a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c index 291a06f95..64afa728a 100644 --- a/target/linux/oxnas/files/drivers/ata/sata_oxnas.c +++ b/target/linux/oxnas/files/drivers/ata/sata_oxnas.c @@ -29,7 +29,35 @@ #include #include -#include +#include +#include + +static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask) +{ + u32 val = readl_relaxed(p); + + val &= ~mask; + writel_relaxed(val, p); +} + +static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask) +{ + u32 val = readl_relaxed(p); + + val |= mask; + writel_relaxed(val, p); +} + +static inline void oxnas_register_value_mask(void __iomem *p, + unsigned mask, unsigned new_value) +{ + /* TODO sanity check mask & new_value = new_value */ + u32 val = readl_relaxed(p); + + val &= ~mask; + val |= new_value; + writel_relaxed(val, p); +} /* sgdma request structure */ struct sgdma_request { @@ -848,7 +876,7 @@ wait_for_lock: * list so want to give reentrant accessors a chance to get * access ASAP */ - if (!list_empty(&hd->scsi_wait_queue.task_list)) + if (!list_empty(&hd->scsi_wait_queue.head)) wake_up(&hd->scsi_wait_queue); } @@ -867,7 +895,7 @@ int sata_core_has_fast_waiters(struct ata_host *ah) struct sata_oxnas_host_priv *hd = ah->private_data; spin_lock_irqsave(&hd->core_lock, flags); - has_waiters = !list_empty(&hd->fast_wait_queue.task_list); + has_waiters = !list_empty(&hd->fast_wait_queue.head); spin_unlock_irqrestore(&hd->core_lock, flags); return has_waiters; @@ -882,7 +910,7 @@ int sata_core_has_scsi_waiters(struct ata_host *ah) spin_lock_irqsave(&hd->core_lock, flags); has_waiters = hd->scsi_nonblocking_attempts || - !list_empty(&hd->scsi_wait_queue.task_list); + !list_empty(&hd->scsi_wait_queue.head); spin_unlock_irqrestore(&hd->core_lock, flags); return has_waiters; @@ -954,7 +982,7 @@ static void sata_oxnas_release_hw(struct ata_port *ap) hd->locker_uid = 0; hd->core_locked = 0; released = 1; - wake_up(!list_empty(&hd->scsi_wait_queue.task_list) ? + wake_up(!list_empty(&hd->scsi_wait_queue.head) ? &hd->scsi_wait_queue : &hd->fast_wait_queue); } diff --git a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c b/target/linux/oxnas/files/drivers/clk/clk-oxnas.c deleted file mode 100644 index 4dc6c4499..000000000 --- a/target/linux/oxnas/files/drivers/clk/clk-oxnas.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (C) 2010 Broadcom - * Copyright (C) 2012 Stephen Warren - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MHZ (1000 * 1000) - -struct clk_oxnas_pllb { - struct clk_hw hw; - struct device_node *devnode; - struct reset_control *rstc; -}; - -#define to_clk_oxnas_pllb(_hw) container_of(_hw, struct clk_oxnas_pllb, hw) - -static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - unsigned long fin = parent_rate; - unsigned long pll0; - unsigned long fbdiv, refdiv, outdiv; - - pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0); - refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK; - refdiv += 1; - outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK; - outdiv += 1; - fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1); - - /* seems we will not be here when pll is bypassed, so ignore this - * case */ - - return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ; -} - -static const char *pll_clk_parents[] = { - "oscillator", -}; - -static struct clk_ops plla_ops = { - .recalc_rate = plla_clk_recalc_rate, -}; - -static struct clk_init_data clk_plla_init = { - .name = "plla", - .ops = &plla_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - -static struct clk_hw plla_hw = { - .init = &clk_plla_init, -}; - -static int pllb_clk_is_prepared(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - return !!pllb->rstc; -} - -static int pllb_clk_prepare(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - pllb->rstc = of_reset_control_get(pllb->devnode, NULL); - - return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0; -} - -static void pllb_clk_unprepare(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - BUG_ON(IS_ERR(pllb->rstc)); - - reset_control_put(pllb->rstc); - pllb->rstc = NULL; -} - -static int pllb_clk_enable(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - BUG_ON(IS_ERR(pllb->rstc)); - - /* put PLL into bypass */ - oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); - wmb(); - udelay(10); - reset_control_assert(pllb->rstc); - udelay(10); - /* set PLL B control information */ - writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV), - SEC_CTRL_PLLB_CTRL0); - reset_control_deassert(pllb->rstc); - udelay(100); - oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); - - return 0; -} - -static void pllb_clk_disable(struct clk_hw *hw) -{ - struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw); - - BUG_ON(IS_ERR(pllb->rstc)); - - /* put PLL into bypass */ - oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS)); - wmb(); - udelay(10); - - reset_control_assert(pllb->rstc); -} - -static struct clk_ops pllb_ops = { - .prepare = pllb_clk_prepare, - .unprepare = pllb_clk_unprepare, - .is_prepared = pllb_clk_is_prepared, - .enable = pllb_clk_enable, - .disable = pllb_clk_disable, -}; - -static struct clk_init_data clk_pllb_init = { - .name = "pllb", - .ops = &pllb_ops, - .parent_names = pll_clk_parents, - .num_parents = ARRAY_SIZE(pll_clk_parents), -}; - - -/* standard gate clock */ -struct clk_std { - struct clk_hw hw; - signed char bit; -}; - -#define NUM_STD_CLKS 17 -#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw) - -static int std_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_std *std = to_stdclk(hw); - - return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit); -} - -static int std_clk_enable(struct clk_hw *hw) -{ - struct clk_std *std = to_stdclk(hw); - - writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL); - return 0; -} - -static void std_clk_disable(struct clk_hw *hw) -{ - struct clk_std *std = to_stdclk(hw); - - writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL); -} - -static struct clk_ops std_clk_ops = { - .enable = std_clk_enable, - .disable = std_clk_disable, - .is_enabled = std_clk_is_enabled, -}; - -static const char *std_clk_parents[] = { - "oscillator", -}; - -static const char *eth_parents[] = { - "gmacclk", -}; - -#define DECLARE_STD_CLKP(__clk, __bit, __parent) \ -static struct clk_init_data clk_##__clk##_init = { \ - .name = __stringify(__clk), \ - .ops = &std_clk_ops, \ - .parent_names = __parent, \ - .num_parents = ARRAY_SIZE(__parent), \ -}; \ - \ -static struct clk_std clk_##__clk = { \ - .bit = __bit, \ - .hw = { \ - .init = &clk_##__clk##_init, \ - }, \ -} - -#define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \ - std_clk_parents) - -DECLARE_STD_CLK(leon, 0); -DECLARE_STD_CLK(dma_sgdma, 1); -DECLARE_STD_CLK(cipher, 2); -DECLARE_STD_CLK(sd, 3); -DECLARE_STD_CLK(sata, 4); -DECLARE_STD_CLK(audio, 5); -DECLARE_STD_CLK(usbmph, 6); -DECLARE_STD_CLKP(etha, 7, eth_parents); -DECLARE_STD_CLK(pciea, 8); -DECLARE_STD_CLK(static, 9); -DECLARE_STD_CLK(ethb, 10); -DECLARE_STD_CLK(pcieb, 11); -DECLARE_STD_CLK(ref600, 12); -DECLARE_STD_CLK(usbdev, 13); - -struct clk_hw *std_clk_hw_tbl[] = { - &clk_leon.hw, - &clk_dma_sgdma.hw, - &clk_cipher.hw, - &clk_sd.hw, - &clk_sata.hw, - &clk_audio.hw, - &clk_usbmph.hw, - &clk_etha.hw, - &clk_pciea.hw, - &clk_static.hw, - &clk_ethb.hw, - &clk_pcieb.hw, - &clk_ref600.hw, - &clk_usbdev.hw, -}; - -struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)]; - -static struct clk_onecell_data std_clk_data; - -void __init oxnas_init_stdclk(struct device_node *np) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) { - std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]); - BUG_ON(IS_ERR(std_clk_tbl[i])); - } - std_clk_data.clks = std_clk_tbl; - std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl); - of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data); -} -CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk); - -void __init oxnas_init_plla(struct device_node *np) -{ - struct clk *clk; - - clk = clk_register(NULL, &plla_hw); - BUG_ON(IS_ERR(clk)); - /* mark it as enabled */ - clk_prepare_enable(clk); - of_clk_add_provider(np, of_clk_src_simple_get, clk); -} -CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); - -void __init oxnas_init_pllb(struct device_node *np) -{ - struct clk *clk; - struct clk_oxnas_pllb *pllb; - - pllb = kmalloc(sizeof(*pllb), GFP_KERNEL); - BUG_ON(!pllb); - - pllb->hw.init = &clk_pllb_init; - pllb->devnode = np; - pllb->rstc = NULL; - - clk = clk_register(NULL, &pllb->hw); - BUG_ON(IS_ERR(clk)); - of_clk_add_provider(np, of_clk_src_simple_get, clk); -} -CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb); diff --git a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c b/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c deleted file mode 100644 index 7c8c4cf43..000000000 --- a/target/linux/oxnas/files/drivers/clocksource/oxnas_rps_timer.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-ox820/rps-time.c - * - * Copyright (C) 2009 Oxford Semiconductor Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -enum { - TIMER_LOAD = 0, - TIMER_CURR = 4, - TIMER_CTRL = 8, - TIMER_CLRINT = 0xC, - - TIMER_BITS = 24, - - TIMER_MAX_VAL = (1 << TIMER_BITS) - 1, - - TIMER_PERIODIC = (1 << 6), - TIMER_ENABLE = (1 << 7), - - TIMER_DIV1 = (0 << 2), - TIMER_DIV16 = (1 << 2), - TIMER_DIV256 = (2 << 2), - - TIMER1_OFFSET = 0, - TIMER2_OFFSET = 0x20, - -}; - -static u64 notrace rps_read_sched_clock(void) -{ - return ~readl_relaxed(RPSA_TIMER2_VAL); -} - -static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate) -{ - int ret; - ulong clock_rate; - /* use prescale 16 */ - clock_rate = ref_rate / 16; - - iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD); - iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, - base + TIMER_CTRL); - - ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer", - clock_rate, 250, TIMER_BITS, - clocksource_mmio_readl_down); - if (ret) - panic("can't register clocksource\n"); - - sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate); -} - -static void __init rps_timer_init(struct device_node *np) -{ - struct clk *refclk; - unsigned long ref_rate; - void __iomem *base; - - refclk = of_clk_get(np, 0); - - if (IS_ERR(refclk) || clk_prepare_enable(refclk)) - panic("rps_timer_init: failed to get refclk\n"); - ref_rate = clk_get_rate(refclk); - - base = of_iomap(np, 0); - if (!base) - panic("rps_timer_init: failed to map io\n"); - - rps_clocksource_init(base + TIMER2_OFFSET, ref_rate); -} - -CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init); diff --git a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c b/target/linux/oxnas/files/drivers/irqchip/irq-rps.c deleted file mode 100644 index f2b0829de..000000000 --- a/target/linux/oxnas/files/drivers/irqchip/irq-rps.c +++ /dev/null @@ -1,145 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct rps_chip_data { - void __iomem *base; - struct irq_chip chip; - struct irq_domain *domain; -} rps_data; - -enum { - RPS_IRQ_BASE = 64, - RPS_IRQ_COUNT = 32, - PRS_HWIRQ_BASE = 0, - - RPS_STATUS = 0, - RPS_RAW_STATUS = 4, - RPS_UNMASK = 8, - RPS_MASK = 0xc, -}; - -/* - * Routines to acknowledge, disable and enable interrupts - */ -static void rps_mask_irq(struct irq_data *d) -{ - struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq); - - iowrite32(mask, chip_data->base + RPS_MASK); -} - -static void rps_unmask_irq(struct irq_data *d) -{ - struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d); - u32 mask = BIT(d->hwirq); - - iowrite32(mask, chip_data->base + RPS_UNMASK); -} - -static struct irq_chip rps_chip = { - .name = "RPS", - .irq_mask = rps_mask_irq, - .irq_unmask = rps_unmask_irq, -}; - -static int rps_irq_domain_xlate(struct irq_domain *d, - struct device_node *controller, - const u32 *intspec, unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - if (irq_domain_get_of_node(d) != controller) - return -EINVAL; - if (intsize < 1) - return -EINVAL; - - *out_hwirq = intspec[0]; - /* Honestly I do not know the type */ - *out_type = IRQ_TYPE_LEVEL_HIGH; - - return 0; -} - -static int rps_irq_domain_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hw) -{ - irq_set_chip_and_handler(irq, &rps_chip, handle_level_irq); - irq_set_probe(irq); - irq_set_chip_data(irq, d->host_data); - return 0; -} - -const struct irq_domain_ops rps_irq_domain_ops = { - .map = rps_irq_domain_map, - .xlate = rps_irq_domain_xlate, -}; - -static void rps_handle_cascade_irq(struct irq_desc *desc) -{ - struct rps_chip_data *chip_data = irq_desc_get_handler_data(desc); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned int cascade_irq, rps_irq; - u32 status; - - chained_irq_enter(chip, desc); - - status = ioread32(chip_data->base + RPS_STATUS); - rps_irq = __ffs(status); - cascade_irq = irq_find_mapping(chip_data->domain, rps_irq); - - if (unlikely(rps_irq >= RPS_IRQ_COUNT)) - handle_bad_irq(desc); - else - generic_handle_irq(cascade_irq); - - chained_irq_exit(chip, desc); -} - -#ifdef CONFIG_OF -int __init rps_of_init(struct device_node *node, struct device_node *parent) -{ - void __iomem *rps_base; - int irq_start = RPS_IRQ_BASE; - int irq_base; - int irq; - - if (WARN_ON(!node)) - return -ENODEV; - - rps_base = of_iomap(node, 0); - WARN(!rps_base, "unable to map rps registers\n"); - rps_data.base = rps_base; - - irq_base = irq_alloc_descs(irq_start, 0, RPS_IRQ_COUNT, numa_node_id()); - if (IS_ERR_VALUE(irq_base)) { - WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", - irq_start); - irq_base = irq_start; - } - - rps_data.domain = irq_domain_add_legacy(node, RPS_IRQ_COUNT, irq_base, - PRS_HWIRQ_BASE, &rps_irq_domain_ops, &rps_data); - - if (WARN_ON(!rps_data.domain)) - return -ENOMEM; - - if (parent) { - irq = irq_of_parse_and_map(node, 0); - if (irq_set_handler_data(irq, &rps_data) != 0) - BUG(); - irq_set_chained_handler(irq, rps_handle_cascade_irq); - } - return 0; - -} - -IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init); -#endif diff --git a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c b/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c deleted file mode 100644 index 36807b776..000000000 --- a/target/linux/oxnas/files/drivers/mtd/nand/oxnas_nand.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Oxford Semiconductor OXNAS NAND driver - - * Copyright (C) 2016 Neil Armstrong - * Heavily based on plat_nand.c : - * Author: Vitaly Wool - * Copyright (C) 2013 Ma Haijun - * Copyright (C) 2012 John Crispin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Nand commands */ -#define OXNAS_NAND_CMD_ALE BIT(18) -#define OXNAS_NAND_CMD_CLE BIT(19) - -#define OXNAS_NAND_MAX_CHIPS 1 - -struct oxnas_nand { - struct nand_hw_control base; - void __iomem *io_base; - struct clk *clk; - struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS]; - unsigned long ctrl; - struct mtd_partition *partitions; - int nr_partitions; -}; - -static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - return readb(oxnas->io_base); -} - -static void oxnas_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - ioread8_rep(oxnas->io_base, buf, len); -} - -static void oxnas_nand_write_buf(struct mtd_info *mtd, - const uint8_t *buf, int len) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - iowrite8_rep(oxnas->io_base + oxnas->ctrl, buf, len); -} - -/* Single CS command control */ -static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct oxnas_nand *oxnas = nand_get_controller_data(chip); - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_CLE) - oxnas->ctrl = OXNAS_NAND_CMD_CLE; - else if (ctrl & NAND_ALE) - oxnas->ctrl = OXNAS_NAND_CMD_ALE; - else - oxnas->ctrl = 0; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, oxnas->io_base + oxnas->ctrl); -} - -/* - * Probe for the NAND device. - */ -static int oxnas_nand_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *nand_np; - struct oxnas_nand *oxnas; - struct nand_chip *chip; - struct mtd_info *mtd; - struct resource *res; - int nchips = 0; - int count = 0; - int err = 0; - - /* Allocate memory for the device structure (and zero it) */ - oxnas = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), - GFP_KERNEL); - if (!oxnas) - return -ENOMEM; - - nand_hw_control_init(&oxnas->base); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - oxnas->io_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(oxnas->io_base)) - return PTR_ERR(oxnas->io_base); - - oxnas->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(oxnas->clk)) - oxnas->clk = NULL; - - /* Only a single chip node is supported */ - count = of_get_child_count(np); - if (count > 1) - return -EINVAL; - - clk_prepare_enable(oxnas->clk); - device_reset_optional(&pdev->dev); - - for_each_child_of_node(np, nand_np) { - chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), - GFP_KERNEL); - if (!chip) - return -ENOMEM; - - chip->controller = &oxnas->base; - - nand_set_flash_node(chip, nand_np); - nand_set_controller_data(chip, oxnas); - - mtd = nand_to_mtd(chip); - mtd->dev.parent = &pdev->dev; - mtd->priv = chip; - - chip->cmd_ctrl = oxnas_nand_cmd_ctrl; - chip->read_buf = oxnas_nand_read_buf; - chip->read_byte = oxnas_nand_read_byte; - chip->write_buf = oxnas_nand_write_buf; - chip->chip_delay = 30; - - /* Scan to find existence of the device */ - err = nand_scan(mtd, 1); - if (err) - return err; - - err = mtd_device_register(mtd, NULL, 0); - if (err) { - nand_release(mtd); - return err; - } - - oxnas->chips[nchips] = chip; - ++nchips; - } - - /* Exit if no chips found */ - if (!nchips) - return -ENODEV; - - platform_set_drvdata(pdev, oxnas); - - return 0; -} - -static int oxnas_nand_remove(struct platform_device *pdev) -{ - struct oxnas_nand *oxnas = platform_get_drvdata(pdev); - - if (oxnas->chips[0]) - nand_release(nand_to_mtd(oxnas->chips[0])); - - clk_disable_unprepare(oxnas->clk); - - return 0; -} - -static const struct of_device_id oxnas_nand_match[] = { - { .compatible = "oxsemi,ox820-nand" }, - {}, -}; -MODULE_DEVICE_TABLE(of, oxnas_nand_match); - -static struct platform_driver oxnas_nand_driver = { - .probe = oxnas_nand_probe, - .remove = oxnas_nand_remove, - .driver = { - .name = "oxnas_nand", - .of_match_table = oxnas_nand_match, - }, -}; - -module_platform_driver(oxnas_nand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Neil Armstrong "); -MODULE_DESCRIPTION("Oxnas NAND driver"); -MODULE_ALIAS("platform:oxnas_nand"); diff --git a/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c b/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c deleted file mode 100644 index aafb11814..000000000 --- a/target/linux/oxnas/files/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c +++ /dev/null @@ -1,145 +0,0 @@ -/* Copyright OpenWrt.org (C) 2015. - * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, version 2, - * as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - * - * Adopted from dwmac-socfpga.c - * Based on code found in mach-oxnas.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "stmmac.h" -#include "stmmac_platform.h" - -struct oxnas_gmac { - struct clk *clk; -}; - -static int oxnas_gmac_init(struct platform_device *pdev, void *priv) -{ - struct oxnas_gmac *bsp_priv = priv; - int ret = 0; - unsigned value; - - ret = device_reset(&pdev->dev); - if (ret) - return ret; - - if (IS_ERR(bsp_priv->clk)) - return PTR_ERR(bsp_priv->clk); - clk_prepare_enable(bsp_priv->clk); - - value = readl(SYS_CTRL_GMAC_CTRL); - - /* Enable GMII_GTXCLK to follow GMII_REFCLK, required for gigabit PHY */ - value |= BIT(SYS_CTRL_GMAC_CKEN_GTX); - /* Use simple mux for 25/125 Mhz clock switching */ - value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX); - /* set auto switch tx clock source */ - value |= BIT(SYS_CTRL_GMAC_AUTO_TX_SOURCE); - /* enable tx & rx vardelay */ - value |= BIT(SYS_CTRL_GMAC_CKEN_TX_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_TXN_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_TX_IN); - value |= BIT(SYS_CTRL_GMAC_CKEN_RX_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_RXN_OUT); - value |= BIT(SYS_CTRL_GMAC_CKEN_RX_IN); - writel(value, SYS_CTRL_GMAC_CTRL); - - /* set tx & rx vardelay */ - value = 0; - value |= SYS_CTRL_GMAC_TX_VARDELAY(4); - value |= SYS_CTRL_GMAC_TXN_VARDELAY(2); - value |= SYS_CTRL_GMAC_RX_VARDELAY(10); - value |= SYS_CTRL_GMAC_RXN_VARDELAY(8); - writel(value, SYS_CTRL_GMAC_DELAY_CTRL); - - return 0; -} - -static void oxnas_gmac_exit(struct platform_device *pdev, void *priv) -{ - struct reset_control *rstc; - - clk_disable_unprepare(priv); - devm_clk_put(&pdev->dev, priv); - - rstc = reset_control_get(&pdev->dev, NULL); - if (!IS_ERR(rstc)) { - reset_control_assert(rstc); - reset_control_put(rstc); - } -} - -static int oxnas_gmac_probe(struct platform_device *pdev) -{ - struct plat_stmmacenet_data *plat_dat; - struct stmmac_resources stmmac_res; - int ret; - struct device *dev = &pdev->dev; - struct oxnas_gmac *bsp_priv; - - bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL); - if (!bsp_priv) - return -ENOMEM; - bsp_priv->clk = devm_clk_get(dev, "gmac"); - if (IS_ERR(bsp_priv->clk)) - return PTR_ERR(bsp_priv->clk); - - ret = stmmac_get_platform_resources(pdev, &stmmac_res); - if (ret) - return ret; - - plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); - if (IS_ERR(plat_dat)) - return PTR_ERR(plat_dat); - - plat_dat->bsp_priv = bsp_priv; - plat_dat->init = oxnas_gmac_init; - plat_dat->exit = oxnas_gmac_exit; - - ret = oxnas_gmac_init(pdev, bsp_priv); - if (ret) - return ret; - - return stmmac_dvr_probe(dev, plat_dat, &stmmac_res); -} - -static const struct of_device_id oxnas_gmac_match[] = { - { .compatible = "plxtech,nas782x-gmac" }, - { } -}; -MODULE_DEVICE_TABLE(of, oxnas_gmac_match); - -static struct platform_driver oxnas_gmac_driver = { - .probe = oxnas_gmac_probe, - .remove = stmmac_pltfr_remove, - .driver = { - .name = "oxnas-gmac", - .pm = &stmmac_pltfr_pm_ops, - .of_match_table = oxnas_gmac_match, - }, -}; -module_platform_driver(oxnas_gmac_driver); - -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c index 9e8d6d9f9..7cf3ad167 100644 --- a/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c +++ b/target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c @@ -22,9 +22,279 @@ #include #include #include -#include -#include -#include +#include +#include + +#define OXNAS_UART1_BASE 0x44200000 +#define OXNAS_UART1_SIZE SZ_32 +#define OXNAS_UART1_BASE_VA 0xF0000000 + +#define OXNAS_UART2_BASE 0x44300000 +#define OXNAS_UART2_SIZE SZ_32 + +#define OXNAS_PERCPU_BASE 0x47000000 +#define OXNAS_PERCPU_SIZE SZ_8K +#define OXNAS_PERCPU_BASE_VA 0xF0002000 + +#define OXNAS_SYSCRTL_BASE 0x44E00000 +#define OXNAS_SYSCRTL_SIZE SZ_4K +#define OXNAS_SYSCRTL_BASE_VA 0xF0004000 + +#define OXNAS_SECCRTL_BASE 0x44F00000 +#define OXNAS_SECCRTL_SIZE SZ_4K +#define OXNAS_SECCRTL_BASE_VA 0xF0005000 + +#define OXNAS_RPSA_BASE 0x44400000 +#define OXNAS_RPSA_SIZE SZ_4K +#define OXNAS_RPSA_BASE_VA 0xF0006000 + +#define OXNAS_RPSC_BASE 0x44500000 +#define OXNAS_RPSC_SIZE SZ_4K +#define OXNAS_RPSC_BASE_VA 0xF0007000 + + +/* + * Location of flags and vectors in SRAM for controlling the booting of the + * secondary ARM11 processors. + */ + +#define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA +#define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100) + +#define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) +#define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) + +/** + * System block reset and clock control + */ +#define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20) +#define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24) +#define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C) +#define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30) +#define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34) +#define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38) + +#define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48) +#define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64) +#define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C) +#define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78) +#define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100) + +/* Scratch registers */ +#define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4) +#define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8) +#define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc) +#define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0) + +#define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0) +#define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4) +#define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8) +#define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC) + +#define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40) +#define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44) +#define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8) +#define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84) +#define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90) + +/* pcie */ +#define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114) + +/* System control multi-function pin function selection */ +#define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14) +#define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c) +#define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94) +#define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c) +#define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4) +#define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac) + +/* Secure control multi-function pin function selection */ +#define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14) +#define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c) +#define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94) +#define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c) +#define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4) +#define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac) + +#define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68) +#define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98) +#define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0) +#define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8) +#define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0) +#define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) +#define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4) + +#define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10) +#define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108) +#define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C) +#define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC) + +#define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10) +#define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108) +#define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C) +#define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC) + +#define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224) + +#define REF300_DIV_INT_SHIFT 8 +#define REF300_DIV_FRAC_SHIFT 0 +#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) +#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) + +#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 +#define USBHSPHY_SUSPENDM_MANUAL_STATE 15 +#define USBHSPHY_ATE_ESET 14 +#define USBHSPHY_TEST_DIN 6 +#define USBHSPHY_TEST_ADD 2 +#define USBHSPHY_TEST_DOUT_SEL 1 +#define USBHSPHY_TEST_CLK 0 + +#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 +#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) +#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) +#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) + +#define USBAMUX_DEVICE BIT(4) + +#define USBPHY_REFCLKDIV_SHIFT 2 +#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) +#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) +#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) + +#define USB_CTRL_USB_CKO_SEL_BIT 0 + +#define USB_INT_CLK_XTAL 0 +#define USB_INT_CLK_REF300 2 +#define USB_INT_CLK_PLLB 3 + +#define SYS_CTRL_GMAC_CKEN_RX_IN 14 +#define SYS_CTRL_GMAC_CKEN_RXN_OUT 13 +#define SYS_CTRL_GMAC_CKEN_RX_OUT 12 +#define SYS_CTRL_GMAC_CKEN_TX_IN 10 +#define SYS_CTRL_GMAC_CKEN_TXN_OUT 9 +#define SYS_CTRL_GMAC_CKEN_TX_OUT 8 +#define SYS_CTRL_GMAC_RX_SOURCE 7 +#define SYS_CTRL_GMAC_TX_SOURCE 6 +#define SYS_CTRL_GMAC_LOW_TX_SOURCE 4 +#define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3 +#define SYS_CTRL_GMAC_RGMII 2 +#define SYS_CTRL_GMAC_SIMPLE_MUX 1 +#define SYS_CTRL_GMAC_CKEN_GTX 0 +#define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0 +#define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8 +#define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16 +#define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24 +#define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)< - * - * Under GPLv2 only - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -/* Since we request GPIOs from ourself */ -#include -#include - -#include "core.h" - -#include - -#define MAX_NB_GPIO_PER_BANK 32 -#define MAX_GPIO_BANKS 2 - -struct oxnas_gpio_chip { - struct gpio_chip chip; - struct pinctrl_gpio_range range; - void __iomem *regbase; /* GPIOA/B virtual address */ - void __iomem *ctrlbase; /* SYS/SEC_CTRL virtual address */ - struct irq_domain *domain; /* associated irq domain */ - spinlock_t lock; -}; - -#define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip) - -static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; - -static int gpio_banks; - -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) -#define DEBOUNCE (1 << 2) - -/** - * struct oxnas_pmx_func - describes pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @ngroups: the number of groups - */ -struct oxnas_pmx_func { - const char *name; - const char **groups; - unsigned ngroups; -}; - -enum oxnas_mux { - OXNAS_PINMUX_GPIO, - OXNAS_PINMUX_FUNC2, - OXNAS_PINMUX_FUNC3, - OXNAS_PINMUX_FUNC4, - OXNAS_PINMUX_DEBUG, - OXNAS_PINMUX_ALT, -}; - -enum { - INPUT_VALUE = 0, - OUTPUT_ENABLE = 4, - IRQ_PENDING = 0xC, - OUTPUT_VALUE = 0x10, - OUTPUT_SET = 0x14, - OUTPUT_CLEAR = 0x18, - OUTPUT_EN_SET = 0x1C, - OUTPUT_EN_CLEAR = 0x20, - DEBOUNCE_ENABLE = 0x24, - RE_IRQ_ENABLE = 0x28, /* rising edge */ - FE_IRQ_ENABLE = 0x2C, /* falling edge */ - RE_IRQ_PENDING = 0x30, /* rising edge */ - FE_IRQ_PENDING = 0x34, /* falling edge */ - CLOCK_DIV = 0x48, - PULL_ENABLE = 0x50, - PULL_SENSE = 0x54, /* 1 up, 0 down */ - - - DEBOUNCE_MASK = 0x3FFF0000, - /* put hw debounce and soft config at same bit position*/ - DEBOUNCE_SHIFT = 16 -}; - -enum { - PINMUX_SECONDARY_SEL = 0x14, - PINMUX_TERTIARY_SEL = 0x8c, - PINMUX_QUATERNARY_SEL = 0x94, - PINMUX_DEBUG_SEL = 0x9c, - PINMUX_ALTERNATIVE_SEL = 0xa4, - PINMUX_PULLUP_SEL = 0xac, -}; - -/** - * struct oxnas_pmx_pin - describes an pin mux - * @bank: the bank of the pin - * @pin: the pin number in the @bank - * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. - * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... - */ -struct oxnas_pmx_pin { - uint32_t bank; - uint32_t pin; - enum oxnas_mux mux; - unsigned long conf; -}; - -/** - * struct oxnas_pin_group - describes an pin group - * @name: the name of this specific pin group - * @pins_conf: the mux mode for each pin in this group. The size of this - * array is the same as pins. - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - */ -struct oxnas_pin_group { - const char *name; - struct oxnas_pmx_pin *pins_conf; - unsigned int *pins; - unsigned npins; -}; - -struct oxnas_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - - int nbanks; - - uint32_t *mux_mask; - int nmux; - - struct oxnas_pmx_func *functions; - int nfunctions; - - struct oxnas_pin_group *groups; - int ngroups; -}; - -static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name( - const struct oxnas_pinctrl *info, - const char *name) -{ - const struct oxnas_pin_group *grp = NULL; - int i; - - for (i = 0; i < info->ngroups; i++) { - if (strcmp(info->groups[i].name, name)) - continue; - - grp = &info->groups[i]; - dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, - grp->pins[0]); - break; - } - - return grp; -} - -static int oxnas_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->ngroups; -} - -static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->groups[selector].name; -} - -static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *npins) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pins; - *npins = info->groups[selector].npins; - - return 0; -} - -static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, "%s", dev_name(pctldev->dev)); -} - -static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pin_group *grp; - struct pinctrl_map *new_map; - struct device_node *parent; - int map_num = 1; - int i; - - /* - * first find the group of this node and check if we need create - * config maps for pins - */ - grp = oxnas_pinctrl_find_group_by_name(info, np->name); - if (!grp) { - dev_err(info->dev, "unable to find group for node %s\n", - np->name); - return -EINVAL; - } - - map_num += grp->npins; - new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, - GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - *map = new_map; - *num_maps = map_num; - - /* create mux map */ - parent = of_get_parent(np); - if (!parent) { - devm_kfree(pctldev->dev, new_map); - return -EINVAL; - } - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = parent->name; - new_map[0].data.mux.group = np->name; - of_node_put(parent); - - /* create config map */ - new_map++; - for (i = 0; i < grp->npins; i++) { - new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i]); - new_map[i].data.configs.configs = &grp->pins_conf[i].conf; - new_map[i].data.configs.num_configs = 1; - } - - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", - (*map)->data.mux.function, (*map)->data.mux.group, map_num); - - return 0; -} - -static void oxnas_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ -} - -static const struct pinctrl_ops oxnas_pctrl_ops = { - .get_groups_count = oxnas_get_groups_count, - .get_group_name = oxnas_get_group_name, - .get_group_pins = oxnas_get_group_pins, - .pin_dbg_show = oxnas_pin_dbg_show, - .dt_node_to_map = oxnas_dt_node_to_map, - .dt_free_map = oxnas_dt_free_map, -}; - -static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info, - unsigned int bank) -{ - return gpio_chips[bank]->regbase; -} - -static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info, - unsigned int bank) -{ - return gpio_chips[bank]->ctrlbase; -} - - -static inline int pin_to_bank(unsigned pin) -{ - return pin / MAX_NB_GPIO_PER_BANK; -} - -static unsigned pin_to_mask(unsigned int pin) -{ - return 1 << pin; -} - -static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask) -{ - oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask); - oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask); -} - -static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin) -{ - return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) && - (readl_relaxed(pio + PULL_SENSE) & BIT(pin)); -} - -static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) -{ - if (on) { - oxnas_register_set_mask(pio + PULL_SENSE, mask); - oxnas_register_set_mask(pio + PULL_ENABLE, mask); - } else { - oxnas_register_clear_mask(pio + PULL_ENABLE, mask); - } -} - -static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin) -{ - return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) && - (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin))); -} - -static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on) -{ - if (on) { - oxnas_register_clear_mask(pio + PULL_SENSE, mask); - oxnas_register_set_mask(pio + PULL_ENABLE, mask); - } else { - oxnas_register_clear_mask(pio + PULL_ENABLE, mask); - }; -} - -/* unfortunately debounce control are shared */ -static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div) -{ - *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK; - return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin); -} - -static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask, - bool is_on, u32 div) -{ - if (is_on) { - oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div); - oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask); - } else { - oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask); - } -} - - -static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask) -{ -/* in fact, SECONDARY takes precedence, so clear others is not necessary */ - oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask) -{ - oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask); - oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask); -} - -static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask) -{ - if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask) - return OXNAS_PINMUX_FUNC2; - if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask) - return OXNAS_PINMUX_FUNC3; - if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask) - return OXNAS_PINMUX_FUNC4; - if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask) - return OXNAS_PINMUX_DEBUG; - if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask) - return OXNAS_PINMUX_ALT; - return OXNAS_PINMUX_GPIO; -} - - -static void oxnas_pin_dbg(const struct device *dev, - const struct oxnas_pmx_pin *pin) -{ - if (pin->mux) { - dev_dbg(dev, - "MF_%c%d configured as periph%c with conf = 0x%lu\n", - pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', - pin->conf); - } else { - dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n", - pin->bank + 'A', pin->pin, pin->conf); - } -} - -static int pin_check_config(struct oxnas_pinctrl *info, const char *name, - int index, const struct oxnas_pmx_pin *pin) -{ - int mux; - - /* check if it's a valid config */ - if (pin->bank >= info->nbanks) { - dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", - name, index, pin->bank, info->nbanks); - return -EINVAL; - } - - if (pin->pin >= MAX_NB_GPIO_PER_BANK) { - dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", - name, index, pin->pin, MAX_NB_GPIO_PER_BANK); - return -EINVAL; - } - /* gpio always allowed */ - if (!pin->mux) - return 0; - - mux = pin->mux - 1; - - if (mux >= info->nmux) { - dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", - name, index, mux, info->nmux); - return -EINVAL; - } - - if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { - dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n", - name, index, mux, pin->bank + 'A', pin->pin); - return -EINVAL; - } - - return 0; -} - -static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio, - unsigned mask, bool input) -{ - oxnas_mux_set_gpio(cio, mask); - if (input) - writel_relaxed(mask, pio + OUTPUT_EN_CLEAR); - else - writel_relaxed(mask, pio + OUTPUT_EN_SET); -} - -static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio, - unsigned mask) -{ - /* when switch to other function, gpio is disabled automatically */ - return; -} - -static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf; - const struct oxnas_pmx_pin *pin; - uint32_t npins = info->groups[group].npins; - int i, ret; - unsigned mask; - void __iomem *pio; - void __iomem *cio; - - dev_dbg(info->dev, "enable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); - - /* first check that all the pins of the group are valid with a valid - * paramter */ - for (i = 0; i < npins; i++) { - pin = &pins_conf[i]; - ret = pin_check_config(info, info->groups[group].name, i, pin); - if (ret) - return ret; - } - - for (i = 0; i < npins; i++) { - pin = &pins_conf[i]; - oxnas_pin_dbg(info->dev, pin); - - pio = pin_to_gpioctrl(info, pin->bank); - cio = pin_to_muxctrl(info, pin->bank); - - mask = pin_to_mask(pin->pin); - oxnas_mux_disable_interrupt(pio, mask); - - switch (pin->mux) { - case OXNAS_PINMUX_GPIO: - oxnas_mux_gpio_enable(cio, pio, mask, 1); - break; - case OXNAS_PINMUX_FUNC2: - oxnas_mux_set_func2(cio, mask); - break; - case OXNAS_PINMUX_FUNC3: - oxnas_mux_set_func3(cio, mask); - break; - case OXNAS_PINMUX_FUNC4: - oxnas_mux_set_func4(cio, mask); - break; - case OXNAS_PINMUX_DEBUG: - oxnas_mux_set_func_dbg(cio, mask); - break; - case OXNAS_PINMUX_ALT: - oxnas_mux_set_func_alt(cio, mask); - break; - } - if (pin->mux) - oxnas_mux_gpio_disable(cio, pio, mask); - } - - return 0; -} - -static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->nfunctions; -} - -static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - return info->functions[selector].name; -} - -static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].ngroups; - - return 0; -} - -static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - struct oxnas_gpio_chip *oxnas_chip; - struct gpio_chip *chip; - unsigned mask; - - if (!range) { - dev_err(npct->dev, "invalid range\n"); - return -EINVAL; - } - if (!range->gc) { - dev_err(npct->dev, "missing GPIO chip in range\n"); - return -EINVAL; - } - chip = range->gc; - oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip); - - dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); - - mask = 1 << (offset - chip->base); - - dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n", - offset, 'A' + range->id, offset - chip->base, mask); - - oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask); - - return 0; -} - -static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); - - dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); - /* Set the pin to some default state, GPIO is usually default */ -} - -static const struct pinmux_ops oxnas_pmx_ops = { - .get_functions_count = oxnas_pmx_get_funcs_count, - .get_function_name = oxnas_pmx_get_func_name, - .get_function_groups = oxnas_pmx_get_groups, - .set_mux = oxnas_pmx_set_mux, - .gpio_request_enable = oxnas_gpio_request_enable, - .gpio_disable_free = oxnas_gpio_disable_free, -}; - -static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - void __iomem *pio; - unsigned pin; - int div; - - dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, - __LINE__, pin_id, *config); - pio = pin_to_gpioctrl(info, pin_to_bank(pin_id)); - pin = pin_id % MAX_NB_GPIO_PER_BANK; - - if (oxnas_mux_get_pullup(pio, pin)) - *config |= PULL_UP; - - if (oxnas_mux_get_pulldown(pio, pin)) - *config |= PULL_DOWN; - - if (oxnas_mux_get_debounce(pio, pin, &div)) - *config |= DEBOUNCE | div; - return 0; -} - -static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) -{ - struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); - unsigned mask; - void __iomem *pio; - int i; - unsigned long config; - - pio = pin_to_gpioctrl(info, pin_to_bank(pin_id)); - mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); - - for (i = 0; i < num_configs; i++) { - config = configs[i]; - - dev_dbg(info->dev, - "%s:%d, pin_id=%d, config=0x%lx", - __func__, __LINE__, pin_id, config); - - if ((config & PULL_UP) && (config & PULL_DOWN)) - return -EINVAL; - - oxnas_mux_set_pullup(pio, mask, config & PULL_UP); - oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN); - oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE, - config & DEBOUNCE_MASK); - - } /* for each config */ - - return 0; -} - -static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) -{ - -} - -static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ -} - -static const struct pinconf_ops oxnas_pinconf_ops = { - .pin_config_get = oxnas_pinconf_get, - .pin_config_set = oxnas_pinconf_set, - .pin_config_dbg_show = oxnas_pinconf_dbg_show, - .pin_config_group_dbg_show = oxnas_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc oxnas_pinctrl_desc = { - .pctlops = &oxnas_pctrl_ops, - .pmxops = &oxnas_pmx_ops, - .confops = &oxnas_pinconf_ops, - .owner = THIS_MODULE, -}; - -static const char *gpio_compat = "plxtech,nas782x-gpio"; - -static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info, - struct device_node *np) -{ - struct device_node *child; - - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) { - info->nbanks++; - } else { - info->nfunctions++; - info->ngroups += of_get_child_count(child); - } - } -} - -static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info, - struct device_node *np) -{ - int ret = 0; - int size; - const __be32 *list; - - list = of_get_property(np, "plxtech,mux-mask", &size); - if (!list) { - dev_err(info->dev, "can not read the mux-mask of %d\n", size); - return -EINVAL; - } - - size /= sizeof(*list); - if (!size || size % info->nbanks) { - dev_err(info->dev, "wrong mux mask array should be by %d\n", - info->nbanks); - return -EINVAL; - } - info->nmux = size / info->nbanks; - - info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); - if (!info->mux_mask) { - dev_err(info->dev, "could not alloc mux_mask\n"); - return -ENOMEM; - } - - ret = of_property_read_u32_array(np, "plxtech,mux-mask", - info->mux_mask, size); - if (ret) - dev_err(info->dev, "can not read the mux-mask of %d\n", size); - return ret; -} - -static int oxnas_pinctrl_parse_groups(struct device_node *np, - struct oxnas_pin_group *grp, - struct oxnas_pinctrl *info, u32 index) -{ - struct oxnas_pmx_pin *pin; - int size; - const __be32 *list; - int i, j; - - dev_dbg(info->dev, "group(%d): %s\n", index, np->name); - - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is plxtech,pins = , - * do sanity check and calculate pins number - */ - list = of_get_property(np, "plxtech,pins", &size); - /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size || size % 4) { - dev_err(info->dev, "wrong pins number or pins and configs" - " should be divisible by 4\n"); - return -EINVAL; - } - - grp->npins = size / 4; - pin = grp->pins_conf = devm_kzalloc(info->dev, - grp->npins * sizeof(struct oxnas_pmx_pin), - GFP_KERNEL); - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - if (!grp->pins_conf || !grp->pins) - return -ENOMEM; - - for (i = 0, j = 0; i < size; i += 4, j++) { - pin->bank = be32_to_cpu(*list++); - pin->pin = be32_to_cpu(*list++); - grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; - pin->mux = be32_to_cpu(*list++); - pin->conf = be32_to_cpu(*list++); - - oxnas_pin_dbg(info->dev, pin); - pin++; - } - - return 0; -} - -static int oxnas_pinctrl_parse_functions(struct device_node *np, - struct oxnas_pinctrl *info, u32 index) -{ - struct device_node *child; - struct oxnas_pmx_func *func; - struct oxnas_pin_group *grp; - int ret; - static u32 grp_index; - u32 i = 0; - - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - - func = &info->functions[index]; - - /* Initialise function */ - func->name = np->name; - func->ngroups = of_get_child_count(np); - if (func->ngroups <= 0) { - dev_err(info->dev, "no groups defined\n"); - return -EINVAL; - } - func->groups = devm_kzalloc(info->dev, - func->ngroups * sizeof(char *), GFP_KERNEL); - if (!func->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[grp_index++]; - ret = oxnas_pinctrl_parse_groups(child, grp, info, i++); - if (ret) - return ret; - } - - return 0; -} - -static struct of_device_id oxnas_pinctrl_of_match[] = { - { .compatible = "plxtech,nas782x-pinctrl"}, - { /* sentinel */ } -}; - -static int oxnas_pinctrl_probe_dt(struct platform_device *pdev, - struct oxnas_pinctrl *info) -{ - int ret = 0; - int i, j; - uint32_t *tmp; - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - - if (!np) - return -ENODEV; - - info->dev = &pdev->dev; - - oxnas_pinctrl_child_count(info, np); - - if (info->nbanks < 1) { - dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); - return -EINVAL; - } - - ret = oxnas_pinctrl_mux_mask(info, np); - if (ret) - return ret; - - dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); - - dev_dbg(&pdev->dev, "mux-mask\n"); - tmp = info->mux_mask; - for (i = 0; i < info->nbanks; i++) - for (j = 0; j < info->nmux; j++, tmp++) - dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); - - dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); - info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * - sizeof(struct oxnas_pmx_func), - GFP_KERNEL); - if (!info->functions) - return -ENOMEM; - - info->groups = devm_kzalloc(&pdev->dev, info->ngroups * - sizeof(struct oxnas_pin_group), - GFP_KERNEL); - if (!info->groups) - return -ENOMEM; - - dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); - dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); - dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); - - i = 0; - - for_each_child_of_node(np, child) { - if (of_device_is_compatible(child, gpio_compat)) - continue; - ret = oxnas_pinctrl_parse_functions(child, info, i++); - if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); - return ret; - } - } - - return 0; -} - -static int oxnas_pinctrl_probe(struct platform_device *pdev) -{ - struct oxnas_pinctrl *info; - struct pinctrl_pin_desc *pdesc; - int ret, i, j, k; - - info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - ret = oxnas_pinctrl_probe_dt(pdev, info); - if (ret) - return ret; - - /* - * We need all the GPIO drivers to probe FIRST, or we will not be able - * to obtain references to the struct gpio_chip * for them, and we - * need this to proceed. - */ - for (i = 0; i < info->nbanks; i++) { - if (!gpio_chips[i]) { - dev_warn(&pdev->dev, - "GPIO chip %d not registered yet\n", i); - devm_kfree(&pdev->dev, info); - return -EPROBE_DEFER; - } - } - - oxnas_pinctrl_desc.name = dev_name(&pdev->dev); - oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; - oxnas_pinctrl_desc.pins = pdesc = - devm_kzalloc(&pdev->dev, sizeof(*pdesc) * - oxnas_pinctrl_desc.npins, GFP_KERNEL); - - if (!oxnas_pinctrl_desc.pins) - return -ENOMEM; - - for (i = 0 , k = 0; i < info->nbanks; i++) { - for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { - pdesc->number = k; - pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A', - j); - pdesc++; - } - } - - platform_set_drvdata(pdev, info); - info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info); - - if (!info->pctl) { - dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n"); - ret = -EINVAL; - goto err; - } - - /* We will handle a range of GPIO pins */ - for (i = 0; i < info->nbanks; i++) - pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); - - dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n"); - - return 0; - -err: - return ret; -} - -static int oxnas_pinctrl_remove(struct platform_device *pdev) -{ - struct oxnas_pinctrl *info = platform_get_drvdata(pdev); - - pinctrl_unregister(info->pctl); - - return 0; -} - -static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset) -{ - /* - * Map back to global GPIO space and request muxing, the direction - * parameter does not matter for this controller. - */ - int gpio = chip->base + offset; - int bank = chip->base / chip->ngpio; - - dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__, - 'A' + bank, offset, gpio); - - return pinctrl_request_gpio(gpio); -} - -static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset) -{ - int gpio = chip->base + offset; - - pinctrl_free_gpio(gpio); -} - -static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - - writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR); - return 0; -} - -static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - unsigned mask = 1 << offset; - u32 pdsr; - - pdsr = readl_relaxed(pio + INPUT_VALUE); - return (pdsr & mask) != 0; -} - -static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - - if (val) - writel_relaxed(BIT(offset), pio + OUTPUT_SET); - else - writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR); - -} - -static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset, - int val) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - - if (val) - writel_relaxed(BIT(offset), pio + OUTPUT_SET); - else - writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR); - - writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET); - - return 0; -} - -static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - int virq; - - if (offset < chip->ngpio) - virq = irq_create_mapping(oxnas_gpio->domain, offset); - else - virq = -ENXIO; - - dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", - chip->label, offset + chip->base, virq); - return virq; -} - -#ifdef CONFIG_DEBUG_FS -static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) -{ - enum oxnas_mux mode; - int i; - struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip); - void __iomem *pio = oxnas_gpio->regbase; - void __iomem *cio = oxnas_gpio->ctrlbase; - - for (i = 0; i < chip->ngpio; i++) { - unsigned pin = chip->base + i; - unsigned mask = pin_to_mask(pin); - const char *gpio_label; - u32 pdsr; - - gpio_label = gpiochip_is_requested(chip, i); - if (!gpio_label) - continue; - /* FIXME */ - mode = oxnas_mux_get_func(cio, mask); - seq_printf(s, "[%s] GPIO%s%d: ", - gpio_label, chip->label, i); - if (mode == OXNAS_PINMUX_GPIO) { - pdsr = readl_relaxed(pio + INPUT_VALUE); - - seq_printf(s, "[gpio] %s\n", - pdsr & mask ? - "set" : "clear"); - } else { - seq_printf(s, "[periph %c]\n", - mode + 'A' - 1); - } - } -} -#else -#define oxnas_gpio_dbg_show NULL -#endif - -/* Several AIC controller irqs are dispatched through this GPIO handler. - * To use any AT91_PIN_* as an externally triggered IRQ, first call - * oxnas_set_gpio_input() then maybe enable its glitch filter. - * Then just request_irq() with the pin ID; it works like any ARM IRQ - * handler. - */ - -static void gpio_irq_mask(struct irq_data *d) -{ - struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d); - void __iomem *pio = oxnas_gpio->regbase; - unsigned mask = 1 << d->hwirq; - unsigned type = irqd_get_trigger_type(d); - unsigned long flags; - - if (!(type & IRQ_TYPE_EDGE_BOTH)) - return; - - spin_lock_irqsave(&oxnas_gpio->lock, flags); - if (type & IRQ_TYPE_EDGE_RISING) - oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask); - if (type & IRQ_TYPE_EDGE_FALLING) - oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask); - spin_unlock_irqrestore(&oxnas_gpio->lock, flags); -} - -static void gpio_irq_unmask(struct irq_data *d) -{ - struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d); - void __iomem *pio = oxnas_gpio->regbase; - unsigned mask = 1 << d->hwirq; - unsigned type = irqd_get_trigger_type(d); - unsigned long flags; - - if (!(type & IRQ_TYPE_EDGE_BOTH)) - return; - - spin_lock_irqsave(&oxnas_gpio->lock, flags); - if (type & IRQ_TYPE_EDGE_RISING) - oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask); - if (type & IRQ_TYPE_EDGE_FALLING) - oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask); - spin_unlock_irqrestore(&oxnas_gpio->lock, flags); -} - - -static int gpio_irq_type(struct irq_data *d, unsigned type) -{ - if ((type & IRQ_TYPE_EDGE_BOTH) == 0) { - pr_warn("OX820: Unsupported type for irq %d\n", - gpio_to_irq(d->irq)); - return -EINVAL; - } - /* seems no way to set trigger type without enable irq, so leave it to unmask time */ - - return 0; -} - -static struct irq_chip gpio_irqchip = { - .name = "GPIO", - .irq_disable = gpio_irq_mask, - .irq_mask = gpio_irq_mask, - .irq_unmask = gpio_irq_unmask, - .irq_set_type = gpio_irq_type, -}; - -static void gpio_irq_handler(struct irq_desc *desc) -{ - struct irq_chip *chip = irq_desc_get_chip(desc); - struct irq_data *idata = irq_desc_get_irq_data(desc); - struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata); - void __iomem *pio = oxnas_gpio->regbase; - unsigned long isr; - int n; - - chained_irq_enter(chip, desc); - for (;;) { - /* TODO: see if it works */ - isr = readl_relaxed(pio + IRQ_PENDING); - if (!isr) - break; - /* acks pending interrupts */ - writel_relaxed(isr, pio + IRQ_PENDING); - - for_each_set_bit(n, &isr, BITS_PER_LONG) { - generic_handle_irq(irq_find_mapping(oxnas_gpio->domain, - n)); - } - } - chained_irq_exit(chip, desc); - /* now it may re-trigger */ -} - -/* - * This lock class tells lockdep that GPIO irqs are in a different - * category than their parents, so it won't report false recursion. - */ -static struct lock_class_key gpio_lock_class; - -static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct oxnas_gpio_chip *oxnas_gpio = h->host_data; - - irq_set_lockdep_class(virq, &gpio_lock_class); - - irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq); - irq_set_chip_data(virq, oxnas_gpio); - - return 0; -} - -static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d, - struct device_node *ctrlr, - const u32 *intspec, - unsigned int intsize, - irq_hw_number_t *out_hwirq, - unsigned int *out_type) -{ - struct oxnas_gpio_chip *oxnas_gpio = d->host_data; - int ret; - int pin = oxnas_gpio->chip.base + intspec[0]; - - if (WARN_ON(intsize < 2)) - return -EINVAL; - *out_hwirq = intspec[0]; - *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; - - ret = gpio_request(pin, ctrlr->full_name); - if (ret) - return ret; - - ret = gpio_direction_input(pin); - if (ret) - return ret; - - return 0; -} - -static struct irq_domain_ops oxnas_gpio_ops = { - .map = oxnas_gpio_irq_map, - .xlate = oxnas_gpio_irq_domain_xlate, -}; - -static int oxnas_gpio_of_irq_setup(struct device_node *node, - struct oxnas_gpio_chip *oxnas_gpio, - unsigned int irq) -{ - /* Disable irqs of this controller */ - writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE); - writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE); - - /* Setup irq domain */ - oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio, - &oxnas_gpio_ops, oxnas_gpio); - if (!oxnas_gpio->domain) - panic("oxnas_gpio: couldn't allocate irq domain (DT).\n"); - - irq_set_chip_data(irq, oxnas_gpio); - irq_set_chained_handler(irq, gpio_irq_handler); - - return 0; -} - -/* This structure is replicated for each GPIO block allocated at probe time */ -static struct gpio_chip oxnas_gpio_template = { - .request = oxnas_gpio_request, - .free = oxnas_gpio_free, - .direction_input = oxnas_gpio_direction_input, - .get = oxnas_gpio_get, - .direction_output = oxnas_gpio_direction_output, - .set = oxnas_gpio_set, - .to_irq = oxnas_gpio_to_irq, - .dbg_show = oxnas_gpio_dbg_show, - .can_sleep = 0, - .ngpio = MAX_NB_GPIO_PER_BANK, -}; - -static struct of_device_id oxnas_gpio_of_match[] = { - { .compatible = "plxtech,nas782x-gpio"}, - { /* sentinel */ } -}; - -static int oxnas_gpio_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct resource *res; - struct oxnas_gpio_chip *oxnas_chip = NULL; - struct gpio_chip *chip; - struct pinctrl_gpio_range *range; - int ret = 0; - int irq, i; - int alias_idx = of_alias_get_id(np, "gpio"); - uint32_t ngpio; - char **names; - - BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); - if (gpio_chips[alias_idx]) { - ret = -EBUSY; - goto err; - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - ret = irq; - goto err; - } - - oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL); - if (!oxnas_chip) { - ret = -ENOMEM; - goto err; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(oxnas_chip->regbase)) { - ret = PTR_ERR(oxnas_chip->regbase); - goto err; - } - - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(oxnas_chip->ctrlbase)) { - ret = PTR_ERR(oxnas_chip->ctrlbase); - goto err; - } - - oxnas_chip->chip = oxnas_gpio_template; - - spin_lock_init(&oxnas_chip->lock); - - chip = &oxnas_chip->chip; - chip->of_node = np; - chip->label = dev_name(&pdev->dev); - chip->dev = &pdev->dev; - chip->owner = THIS_MODULE; - chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; - - if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { - if (ngpio > MAX_NB_GPIO_PER_BANK) - pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n", - alias_idx, MAX_NB_GPIO_PER_BANK, - MAX_NB_GPIO_PER_BANK); - else - chip->ngpio = ngpio; - } - - names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, - GFP_KERNEL); - - if (!names) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < chip->ngpio; i++) - names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i); - - chip->names = (const char *const *)names; - - range = &oxnas_chip->range; - range->name = chip->label; - range->id = alias_idx; - range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; - - range->npins = chip->ngpio; - range->gc = chip; - - ret = gpiochip_add(chip); - if (ret) - goto err; - - gpio_chips[alias_idx] = oxnas_chip; - gpio_banks = max(gpio_banks, alias_idx + 1); - - oxnas_gpio_of_irq_setup(np, oxnas_chip, irq); - - dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase); - - return 0; -err: - dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); - - return ret; -} - -static struct platform_driver oxnas_gpio_driver = { - .driver = { - .name = "gpio-oxnas", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(oxnas_gpio_of_match), - }, - .probe = oxnas_gpio_probe, -}; - -static struct platform_driver oxnas_pinctrl_driver = { - .driver = { - .name = "pinctrl-oxnas", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(oxnas_pinctrl_of_match), - }, - .probe = oxnas_pinctrl_probe, - .remove = oxnas_pinctrl_remove, -}; - -static int __init oxnas_pinctrl_init(void) -{ - int ret; - - ret = platform_driver_register(&oxnas_gpio_driver); - if (ret) - return ret; - return platform_driver_register(&oxnas_pinctrl_driver); -} -arch_initcall(oxnas_pinctrl_init); - -static void __exit oxnas_pinctrl_exit(void) -{ - platform_driver_unregister(&oxnas_pinctrl_driver); -} - -module_exit(oxnas_pinctrl_exit); -MODULE_AUTHOR("Ma Hajun "); -MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/target/linux/oxnas/files/drivers/reset/reset-ox820.c b/target/linux/oxnas/files/drivers/reset/reset-ox820.c deleted file mode 100644 index 0a28de55f..000000000 --- a/target/linux/oxnas/files/drivers/reset/reset-ox820.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int ox820_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) -{ - writel(BIT(id), SYS_CTRL_RST_SET_CTRL); - writel(BIT(id), SYS_CTRL_RST_CLR_CTRL); - return 0; -} - -static int ox820_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - writel(BIT(id), SYS_CTRL_RST_SET_CTRL); - - return 0; -} - -static int ox820_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) -{ - writel(BIT(id), SYS_CTRL_RST_CLR_CTRL); - - return 0; -} - -static struct reset_control_ops ox820_reset_ops = { - .reset = ox820_reset_reset, - .assert = ox820_reset_assert, - .deassert = ox820_reset_deassert, -}; - -static const struct of_device_id ox820_reset_dt_ids[] = { - { .compatible = "plxtech,nas782x-reset", }, - { /* sentinel */ }, -}; -MODULE_DEVICE_TABLE(of, ox820_reset_dt_ids); - -struct reset_controller_dev rcdev; - -static int ox820_reset_probe(struct platform_device *pdev) -{ - struct reset_controller_dev *rcdev; - - rcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL); - if (!rcdev) - return -ENOMEM; - - /* note: reset controller is statically mapped */ - - rcdev->owner = THIS_MODULE; - rcdev->nr_resets = 32; - rcdev->ops = &ox820_reset_ops; - rcdev->of_node = pdev->dev.of_node; - reset_controller_register(rcdev); - platform_set_drvdata(pdev, rcdev); - - return 0; -} - -static int ox820_reset_remove(struct platform_device *pdev) -{ - struct reset_controller_dev *rcdev = platform_get_drvdata(pdev); - - reset_controller_unregister(rcdev); - - return 0; -} - -static struct platform_driver ox820_reset_driver = { - .probe = ox820_reset_probe, - .remove = ox820_reset_remove, - .driver = { - .name = "ox820-reset", - .owner = THIS_MODULE, - .of_match_table = ox820_reset_dt_ids, - }, -}; - -static int __init ox820_reset_init(void) -{ - return platform_driver_probe(&ox820_reset_driver, - ox820_reset_probe); -} -/* - * reset controller does not support probe deferral, so it has to be - * initialized before any user, in particular, PCIE uses subsys_initcall. - */ -arch_initcall(ox820_reset_init); - -MODULE_AUTHOR("Ma Haijun"); -MODULE_LICENSE("GPL"); diff --git a/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c b/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c index 15578a302..79c4fa3a9 100644 --- a/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c +++ b/target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c @@ -14,13 +14,59 @@ #include #include #include +#include #include #include #include #include +#include #include -#include -#include + +#define USBHSMPH_CTRL_REGOFFSET 0x40 +#define USBHSMPH_STAT_REGOFFSET 0x44 +#define REF300_DIV_REGOFFSET 0xF8 +#define USBHSPHY_CTRL_REGOFFSET 0x84 +#define USB_CTRL_REGOFFSET 0x90 +#define PLLB_DIV_CTRL_REGOFFSET 0x1000F8 +#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16 +#define USBHSPHY_SUSPENDM_MANUAL_STATE 15 +#define USBHSPHY_ATE_ESET 14 +#define USBHSPHY_TEST_DIN 6 +#define USBHSPHY_TEST_ADD 2 +#define USBHSPHY_TEST_DOUT_SEL 1 +#define USBHSPHY_TEST_CLK 0 + +#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5 +#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT) +#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT) +#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT) + +#define USBAMUX_DEVICE BIT(4) + +#define USBPHY_REFCLKDIV_SHIFT 2 +#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT) +#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT) +#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT) + +#define USB_CTRL_USB_CKO_SEL_BIT 0 + +#define USB_INT_CLK_XTAL 0 +#define USB_INT_CLK_REF300 2 +#define USB_INT_CLK_PLLB 3 + +#define REF300_DIV_INT_SHIFT 8 +#define REF300_DIV_FRAC_SHIFT 0 +#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) +#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) + +#define PLLB_BYPASS 1 +#define PLLB_ENSAT 3 +#define PLLB_OUTDIV 4 +#define PLLB_REFDIV 8 +#define PLLB_DIV_INT_SHIFT 8 +#define PLLB_DIV_FRAC_SHIFT 0 +#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) +#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) #include "ehci.h" @@ -33,6 +79,7 @@ struct oxnas_hcd { struct reset_control *rst_host; struct reset_control *rst_phya; struct reset_control *rst_phyb; + struct regmap *syscon; }; #define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller" @@ -41,21 +88,16 @@ static struct hc_driver __read_mostly oxnas_hc_driver; static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas) { - u32 reg; - if (oxnas->use_pllb) { /* enable pllb */ clk_prepare_enable(oxnas->refsrc); /* enable ref600 */ clk_prepare_enable(oxnas->phyref); /* 600MHz pllb divider for 12MHz */ - writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), - SEC_CTRL_PLLB_DIV_CTRL); - + regmap_write_bits(oxnas->syscon, PLLB_DIV_CTRL_REGOFFSET, 0xffff, PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0)); } else { /* ref 300 divider for 12MHz */ - writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), - SYS_CTRL_REF300_DIV); + regmap_write_bits(oxnas->syscon, REF300_DIV_REGOFFSET, 0xffff, REF300_DIV_INT(25) | REF300_DIV_FRAC(0)); } /* Ensure the USB block is properly reset */ @@ -65,31 +107,34 @@ static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas) /* Force the high speed clock to be generated all the time, via serial programming of the USB HS PHY */ - writel((2UL << USBHSPHY_TEST_ADD) | - (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff, + (2UL << USBHSPHY_TEST_ADD) | + (0xe0UL << USBHSPHY_TEST_DIN)); - writel((1UL << USBHSPHY_TEST_CLK) | - (2UL << USBHSPHY_TEST_ADD) | - (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff, + (1UL << USBHSPHY_TEST_CLK) | + (2UL << USBHSPHY_TEST_ADD) | + (0xe0UL << USBHSPHY_TEST_DIN)); - writel((0xfUL << USBHSPHY_TEST_ADD) | - (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff, + (0xfUL << USBHSPHY_TEST_ADD) | + (0xaaUL << USBHSPHY_TEST_DIN)); - writel((1UL << USBHSPHY_TEST_CLK) | - (0xfUL << USBHSPHY_TEST_ADD) | - (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL); + regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff, + (1UL << USBHSPHY_TEST_CLK) | + (0xfUL << USBHSPHY_TEST_ADD) | + (0xaaUL << USBHSPHY_TEST_DIN)); if (oxnas->use_pllb) /* use pllb clock */ - writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL); + regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff, + USB_CLK_INTERNAL | USB_INT_CLK_PLLB); else /* use ref300 derived clock */ - writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, - SYS_CTRL_USB_CTRL); + regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff, + USB_CLK_INTERNAL | USB_INT_CLK_REF300); if (oxnas->use_phya) { /* Configure USB PHYA as a host */ - reg = readl(SYS_CTRL_USB_CTRL); - reg &= ~USBAMUX_DEVICE; - writel(reg, SYS_CTRL_USB_CTRL); + regmap_update_bits(oxnas->syscon, USB_CTRL_REGOFFSET, USBAMUX_DEVICE, 0); } /* Enable the clock to the USB block */ @@ -172,8 +217,14 @@ static int ehci_oxnas_drv_probe(struct platform_device *ofdev) oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv; - oxnas->use_pllb = of_property_read_bool(np, "plxtech,ehci_use_pllb"); - oxnas->use_phya = of_property_read_bool(np, "plxtech,ehci_use_phya"); + oxnas->use_pllb = of_property_read_bool(np, "oxsemi,ehci_use_pllb"); + oxnas->use_phya = of_property_read_bool(np, "oxsemi,ehci_use_phya"); + + oxnas->syscon = syscon_regmap_lookup_by_phandle(np, "oxsemi,sys-ctrl"); + if (IS_ERR(oxnas->syscon)) { + err = PTR_ERR(oxnas->syscon); + goto err_syscon; + } oxnas->clk = of_clk_get_by_name(np, "usb"); if (IS_ERR(oxnas->clk)) { @@ -249,6 +300,7 @@ err_phyref: clk_put(oxnas->refsrc); err_refsrc: clk_put(oxnas->clk); +err_syscon: err_clk: err_ioremap: err_res: diff --git a/target/linux/oxnas/image/Makefile b/target/linux/oxnas/image/Makefile index bfa0f0cca..644c2b879 100644 --- a/target/linux/oxnas/image/Makefile +++ b/target/linux/oxnas/image/Makefile @@ -1,107 +1,15 @@ -# -# Copyright (C) 2013-2016 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/image.mk -UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 - -DEVICE_VARS += DTS UBIFS_OPTS - -KERNEL_LOADADDR := 0x60008000 - -define Build/ubootable - (dd if="$(STAGING_DIR_IMAGE)/u-boot.bin" bs=128k conv=sync; \ - dd if="$@" bs=128k conv=sync ) >> $@.new - @mv "$@.new" "$@" -endef - -define Device/Default - KERNEL_DEPENDS = $$(wildcard $$(DTS_DIR)/ox820-$$(DTS).dts) - KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/ox820-$$(DTS).dtb - KERNEL_NAME := zImage - KERNEL_SUFFIX := -uImage - KERNEL_INSTALL := 1 - KERNEL_INITRAMFS = kernel-bin | lzma | fit lzma $$(DTS_DIR)/ox820-$$(DTS).dtb | ubootable - KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-u-boot-initramfs - KERNEL_INITRAMFS_SUFFIX := .bin - BLOCKSIZE := 128k - PAGESIZE := 2048 - SUBPAGESIZE := 512 - FILESYSTEMS := squashfs ubifs - PROFILES = Default $$(DTS) - IMAGES := ubinized.bin sysupgrade.tar - IMAGE/ubinized.bin := append-ubi - IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata - KERNEL_IN_UBI := 1 - UBOOTENV_IN_UBI := 1 -endef - -define Device/akitio - DTS := akitio - DEVICE_TITLE := Akitio MyCloud mini / Silverstone DC01 - DEVICE_PACKAGES := kmod-i2c-gpio kmod-rtc-ds1307 -endef -TARGET_DEVICES += akitio - -define Build/omninas-factory - rm -rf $@.tmp $@.dummy $@.dummy.gz - mkdir -p $@.tmp - $(CP) $@ $@.tmp/uImage - dd if=/dev/zero bs=64k count=4 of=$@.dummy - gzip $@.dummy - mkimage -A arm -T ramdisk -C gzip -n "dummy" \ - -d $@.dummy.gz \ - $@.tmp/rdimg.gz - echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version - chmod 0744 $@.tmp/* - $(TAR) -C $@.tmp -czvf $@ \ - $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") . -endef - -define Build/encrypt-3des - openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@ -endef - -define Device/kd20 - DEVICE_DTS := ox820-kd20 - DEVICE_TITLE := Shuttle KD20 - KERNEL := kernel-bin | append-dtb | uImage none - KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-factory - KERNEL_INITRAMFS_SUFFIX := .tar.gz - KERNEL_INITRAMFS = kernel-bin | append-dtb | uImage none | omninas-factory | encrypt-3des sohmuntitnlaes - KERNEL_IMAGE := zImage - DEVICE_PACKAGES := kmod-usb3 kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper \ - kmod-hwmon-core kmod-hwmon-gpiofan \ - kmod-md-mod kmod-md-raid0 kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs - KERNEL_IN_UBI := - UBOOTENV_IN_UBI := -endef -TARGET_DEVICES += kd20 - -define Device/pogoplug-pro - DTS := pogoplug-pro - DEVICE_TITLE := Cloud Engines Pogoplug Pro (with mPCIe) -endef -TARGET_DEVICES += pogoplug-pro - -define Device/pogoplug-v3 - DTS := pogoplug-v3 - DEVICE_TITLE := Cloud Engines Pogoplug V3 (no mPCIe) -endef -TARGET_DEVICES += pogoplug-v3 - -define Device/stg212 - DTS := stg212 - DEVICE_TITLE := MitraStar STG-212 -endef -TARGET_DEVICES += stg212 - VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage +ifeq ($(SUBTARGET),ox810se) +include ox810se.mk +endif + +ifeq ($(SUBTARGET),ox820) +include ox820.mk +endif + $(eval $(call BuildImage)) diff --git a/target/linux/oxnas/image/ox810se.mk b/target/linux/oxnas/image/ox810se.mk new file mode 100644 index 000000000..52170a26f --- /dev/null +++ b/target/linux/oxnas/image/ox810se.mk @@ -0,0 +1,18 @@ +KERNEL_LOADADDR := 0x48008000 + +define Device/Default + KERNEL_NAME := zImage + KERNEL_SUFFIX := -uImage + KERNEL_INSTALL := 1 + FILESYSTEMS := squashfs ext4 + PROFILES = Default $$(DTS) + IMAGES := sysupgrade.tar + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata +endef + +define Device/wd-mbwe + DEVICE_DTS := ox810se-wd-mbwe + DEVICE_TITLE := Western Digital My Book World Edition + KERNEL := kernel-bin | append-dtb | uImage none +endef +TARGET_DEVICES += wd-mbwe diff --git a/target/linux/oxnas/image/ox820.mk b/target/linux/oxnas/image/ox820.mk new file mode 100644 index 000000000..9d41270a3 --- /dev/null +++ b/target/linux/oxnas/image/ox820.mk @@ -0,0 +1,81 @@ +UBIFS_OPTS = -m 2048 -e 126KiB -c 4096 +DEVICE_VARS += DTS UBIFS_OPTS +KERNEL_LOADADDR := 0x60008000 + +define Device/Default + KERNEL_NAME := zImage + KERNEL_SUFFIX := -uImage + KERNEL_INSTALL := 1 + BLOCKSIZE := 128k + PAGESIZE := 2048 + SUBPAGESIZE := 512 + FILESYSTEMS := squashfs ubifs + PROFILES = Default $$(DTS) + KERNEL := kernel-bin | append-dtb | uImage none + IMAGES := ubinized.bin sysupgrade.tar + IMAGE/ubinized.bin := append-ubi + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata +endef + +define Build/omninas-factory + rm -rf $@.tmp $@.dummy $@.dummy.gz + mkdir -p $@.tmp + $(CP) $@ $@.tmp/uImage + dd if=/dev/zero bs=64k count=4 of=$@.dummy + gzip $@.dummy + mkimage -A arm -T ramdisk -C gzip -n "dummy" \ + -d $@.dummy.gz \ + $@.tmp/rdimg.gz + echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version + chmod 0744 $@.tmp/* + $(TAR) -C $@.tmp -czvf $@ \ + $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") . +endef + +define Build/encrypt-3des + openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@ +endef + +define Device/akitio-mycloud + DEVICE_DTS := ox820-akitio-mycloud + DEVICE_TITLE := Akition myCloud (mini) / SilverStone DC01 + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev \ + kmod-i2c-gpio kmod-rtc-ds1307 +endef +TARGET_DEVICES += akitio-mycloud + +define Device/cloudengines-pogoplug-pro + DEVICE_DTS := ox820-cloudengines-pogoplug-pro + DEVICE_TITLE := Cloud Engines PogoPlug Pro (with mPCIe) + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ledtrig-usbdev +endef +TARGET_DEVICES += cloudengines-pogoplug-pro + +define Device/cloudengines-pogoplug-series-3 + DEVICE_DTS := ox820-cloudengines-pogoplug-series-3 + DEVICE_TITLE := Cloud Engines PogoPlug Series V3 (without mPCIe) + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ledtrig-usbdev +endef +TARGET_DEVICES += cloudengines-pogoplug-series-3 + +define Device/shuttle-kd20 + DEVICE_DTS := ox820-shuttle-kd20 + DEVICE_TITLE := Shuttle KD20 + KERNEL := kernel-bin | append-dtb | uImage none + KERNEL_INITRAMFS_PREFIX = $$(IMAGE_PREFIX)-factory + KERNEL_INITRAMFS_SUFFIX := .tar.gz + KERNEL_INITRAMFS = kernel-bin | append-dtb | uImage none | omninas-factory | encrypt-3des sohmuntitnlaes + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev \ + kmod-usb3 kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper \ + kmod-hwmon-core kmod-hwmon-gpiofan \ + kmod-md-mod kmod-md-raid0 kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs +endef +TARGET_DEVICES += shuttle-kd20 + +define Device/mitrastar-stg212 + DEVICE_DTS := ox820-mitrastar-stg212 + DEVICE_TITLE := MitraStar STG-212 + KERNEL := kernel-bin | append-dtb | uImage none + DEVICE_PACKAGES := kmod-usb2-oxnas kmod-ata-oxnas-sata kmod-ledtrig-usbdev +endef +TARGET_DEVICES += mitrastar-stg212 diff --git a/target/linux/oxnas/modules.mk b/target/linux/oxnas/modules.mk index 701639861..e7c959579 100644 --- a/target/linux/oxnas/modules.mk +++ b/target/linux/oxnas/modules.mk @@ -1,11 +1,3 @@ -# -# Copyright (C) 2006-2014 OpenWrt.org -# Copyright (C) 2016 LEDE project -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - define KernelPackage/ata-oxnas-sata SUBMENU:=$(BLOCK_MENU) TITLE:=oxnas Serial ATA support @@ -17,7 +9,7 @@ define KernelPackage/ata-oxnas-sata endef define KernelPackage/ata-oxnas-sata/description - SATA support for OX934 core found in the OX82x/PLX782x SoCs + SATA support for OX934 core found in the OX8xx/PLX782x SoCs endef $(eval $(call KernelPackage,ata-oxnas-sata)) @@ -25,8 +17,8 @@ $(eval $(call KernelPackage,ata-oxnas-sata)) define KernelPackage/usb2-oxnas SUBMENU:=$(BLOCK_MENU) - TITLE:=OXNAS USB controller driver - DEPENDS:=@TARGET_oxnas +kmod-usb2 + TITLE:=OX820 EHCI driver + DEPENDS:=@TARGET_oxnas_ox820 +kmod-usb2 KCONFIG:=CONFIG_USB_EHCI_OXNAS FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1) @@ -35,7 +27,7 @@ endef define KernelPackage/usb2-oxnas/description This driver provides USB Device Controller support for the - EHCI USB host built-in to the PLXTECH NAS782x SoC + EHCI USB host built-in to the OX820 SoC. endef $(eval $(call KernelPackage,usb2-oxnas)) diff --git a/target/linux/oxnas/ox810se/config-default b/target/linux/oxnas/ox810se/config-default new file mode 100644 index 000000000..e8257cef4 --- /dev/null +++ b/target/linux/oxnas/ox810se/config-default @@ -0,0 +1,39 @@ +CONFIG_ARCH_MULTI_CPU_AUTO=y +# CONFIG_ARCH_MULTI_V4 is not set +# CONFIG_ARCH_MULTI_V4T is not set +CONFIG_ARCH_MULTI_V4_V5=y +CONFIG_ARCH_MULTI_V5=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_ARM926T=y +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_PM=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_USE_DOMAINS=y +# CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_UNCOMPRESS is not set +CONFIG_GENERIC_ATOMIC64=y +CONFIG_MACH_OX810SE=y +CONFIG_NEED_KUSER_HELPERS=y +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_RCU_EXPERT is not set +# CONFIG_RCU_NEED_SEGCBLIST is not set +# CONFIG_RCU_STALL_COMMON is not set +CONFIG_SPLIT_PTLOCK_CPUS=999999 +CONFIG_TINY_SRCU=y +CONFIG_EXT4_FS=y +CONFIG_FAT_FS=y +CONFIG_FS_MBCACHE=y diff --git a/target/linux/oxnas/ox810se/profiles/00-default.mk b/target/linux/oxnas/ox810se/profiles/00-default.mk new file mode 100644 index 000000000..275a9e1fb --- /dev/null +++ b/target/linux/oxnas/ox810se/profiles/00-default.mk @@ -0,0 +1,10 @@ +define Profile/Default + NAME:=Default Profile + PRIORITY:=1 +endef + +define Profile/Default/Description + Default package set compatible with most boards. +endef + +$(eval $(call Profile,Default)) diff --git a/target/linux/oxnas/ox810se/target.mk b/target/linux/oxnas/ox810se/target.mk new file mode 100644 index 000000000..4031fc57c --- /dev/null +++ b/target/linux/oxnas/ox810se/target.mk @@ -0,0 +1,9 @@ +FEATURES+=source-only + +SUBTARGET:=ox810se +BOARDNAME:=OX810SE +CPU_TYPE:=arm926ej-s + +define Target/Description + Oxford OX810SE +endef diff --git a/target/linux/oxnas/ox820/config-default b/target/linux/oxnas/ox820/config-default new file mode 100644 index 000000000..47cd89d0d --- /dev/null +++ b/target/linux/oxnas/ox820/config-default @@ -0,0 +1,106 @@ +CONFIG_ARCH_HAS_TICK_BROADCAST=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_CACHE_L2X0=y +# CONFIG_CACHE_L2X0_PMU is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_ABRT_EV6=y +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_V6K=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" +CONFIG_DEBUG_LL_UART_8250=y +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set +CONFIG_DEBUG_UART_8250_SHIFT=0 +CONFIG_DEBUG_UART_PHYS=0x44200000 +CONFIG_DEBUG_UART_VIRT=0xf4200000 +CONFIG_DEBUG_UNCOMPRESS=y +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress-ox820.h" +CONFIG_DMA_CACHE_RWFO=y +CONFIG_FIXED_PHY=y +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_MACH_OX820=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NR_CPUS=16 +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_PM_SLEEP_SMP=y +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_XPS=y +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_OXNAS=y +CONFIG_PCIE_PME=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_OXNAS=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_SECURITY=y +CONFIG_UBIFS_FS_ZLIB=y +CONFIG_ARCH_WANT_LIBATA_LEDS=y +CONFIG_ATA_LEDS=y diff --git a/target/linux/oxnas/profiles/00-default.mk b/target/linux/oxnas/ox820/profiles/00-default.mk similarity index 100% rename from target/linux/oxnas/profiles/00-default.mk rename to target/linux/oxnas/ox820/profiles/00-default.mk diff --git a/target/linux/oxnas/ox820/target.mk b/target/linux/oxnas/ox820/target.mk new file mode 100644 index 000000000..7c5745814 --- /dev/null +++ b/target/linux/oxnas/ox820/target.mk @@ -0,0 +1,12 @@ +SUBTARGET:=ox820 +BOARDNAME:=OX820/NAS782x +CPU_TYPE:=mpcore +FEATURES+=nand pci pcie ubifs usb + +DEFAULT_PACKAGES += \ + uboot-oxnas-ox820 + + +define Target/Description + Oxford/PLXTECH OX820/NAS782x +endef \ No newline at end of file diff --git a/target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch b/target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch new file mode 100644 index 000000000..db6144c39 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/0001-ARM-dts-rename-oxnas-dts-files.patch @@ -0,0 +1,459 @@ +From a9d2b105ccd23e07e3dd99d010a34bd5d1c95b42 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sat, 13 Jan 2018 18:35:59 +0100 +Subject: [PATCH 1/3] ARM: dts: rename oxnas dts files + +Other platforms' device-tree files start with a platform prefix, such as +sun7i-a20-*.dts or at91-*.dts. +This naming scheme turns out to be handy when using multi-platform build +systems such as OpenWrt. +Prepend oxnas files with their platform prefix to comply with the naming +scheme already used for most other platforms. + +Signed-off-by: Daniel Golle +Signed-off-by: Arnd Bergmann +--- + arch/arm/boot/dts/Makefile | 4 ++-- + arch/arm/boot/dts/{wd-mbwe.dts => ox810se-wd-mbwe.dts} | 0 + ...-series-3.dts => ox820-cloudengines-pogoplug-series-3.dts} | 0 + 3 files changed, 2 insertions(+), 2 deletions(-) + rename arch/arm/boot/dts/{wd-mbwe.dts => ox810se-wd-mbwe.dts} (100%) + rename arch/arm/boot/dts/{cloudengines-pogoplug-series-3.dts => ox820-cloudengines-pogoplug-series-3.dts} (100%) + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -685,8 +685,8 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \ + dtb-$(CONFIG_ARCH_PRIMA2) += \ + prima2-evb.dtb + dtb-$(CONFIG_ARCH_OXNAS) += \ +- wd-mbwe.dtb \ +- cloudengines-pogoplug-series-3.dtb ++ ox810se-wd-mbwe.dtb \ ++ ox820-cloudengines-pogoplug-series-3.dtb + dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8060-dragonboard.dtb \ + qcom-apq8064-arrow-sd-600eval.dtb \ +--- a/arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts ++++ /dev/null +@@ -1,94 +0,0 @@ +-/* +- * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 +- * +- * Copyright (C) 2016 Neil Armstrong +- * +- * Licensed under GPLv2 or later +- */ +- +-/dts-v1/; +-#include "ox820.dtsi" +- +-/ { +- model = "Cloud Engines PogoPlug Series 3"; +- +- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; +- +- chosen { +- bootargs = "earlyprintk"; +- stdout-path = "serial0:115200n8"; +- }; +- +- memory { +- /* 128Mbytes DDR */ +- reg = <0x60000000 0x8000000>; +- }; +- +- aliases { +- serial0 = &uart0; +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- blue { +- label = "pogoplug:blue"; +- gpios = <&gpio0 2 0>; +- default-state = "keep"; +- }; +- +- orange { +- label = "pogoplug:orange"; +- gpios = <&gpio1 16 1>; +- default-state = "keep"; +- }; +- +- green { +- label = "pogoplug:green"; +- gpios = <&gpio1 17 1>; +- default-state = "keep"; +- }; +- }; +-}; +- +-&uart0 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart0>; +-}; +- +-&nandc { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_nand>; +- +- nand@0 { +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- nand-ecc-mode = "soft"; +- nand-ecc-algo = "hamming"; +- +- partition@0 { +- label = "boot"; +- reg = <0x00000000 0x00e00000>; +- read-only; +- }; +- +- partition@e00000 { +- label = "ubi"; +- reg = <0x00e00000 0x07200000>; +- }; +- }; +-}; +- +-ða { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_etha_mdio>; +-}; +--- /dev/null ++++ b/arch/arm/boot/dts/ox810se-wd-mbwe.dts +@@ -0,0 +1,112 @@ ++/* ++ * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition ++ * ++ * Copyright (C) 2016 Neil Armstrong ++ * ++ * Licensed under GPLv2 or later ++ */ ++ ++/dts-v1/; ++#include "ox810se.dtsi" ++ ++/ { ++ model = "Western Digital My Book World Edition"; ++ ++ compatible = "wd,mbwe", "oxsemi,ox810se"; ++ ++ chosen { ++ bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; ++ }; ++ ++ memory { ++ /* 128Mbytes DDR */ ++ reg = <0x48000000 0x8000000>; ++ }; ++ ++ aliases { ++ serial1 = &uart1; ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ }; ++ ++ gpio-keys-polled { ++ compatible = "gpio-keys-polled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ poll-interval = <100>; ++ ++ power { ++ label = "power"; ++ gpios = <&gpio0 0 1>; ++ linux,code = <0x198>; ++ }; ++ ++ recovery { ++ label = "recovery"; ++ gpios = <&gpio0 4 1>; ++ linux,code = <0xab>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ a0 { ++ label = "activity0"; ++ gpios = <&gpio0 25 0>; ++ default-state = "keep"; ++ }; ++ ++ a1 { ++ label = "activity1"; ++ gpios = <&gpio0 26 0>; ++ default-state = "keep"; ++ }; ++ ++ a2 { ++ label = "activity2"; ++ gpios = <&gpio0 5 0>; ++ default-state = "keep"; ++ }; ++ ++ a3 { ++ label = "activity3"; ++ gpios = <&gpio0 6 0>; ++ default-state = "keep"; ++ }; ++ ++ a4 { ++ label = "activity4"; ++ gpios = <&gpio0 7 0>; ++ default-state = "keep"; ++ }; ++ ++ a5 { ++ label = "activity5"; ++ gpios = <&gpio1 2 0>; ++ default-state = "keep"; ++ }; ++ }; ++ ++ i2c-gpio { ++ compatible = "i2c-gpio"; ++ gpios = <&gpio0 3 0 /* sda */ ++ &gpio0 2 0 /* scl */ ++ >; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rtc0: rtc@48 { ++ compatible = "st,m41t00"; ++ reg = <0x68>; ++ }; ++ }; ++}; ++ ++&uart1 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1>; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +@@ -0,0 +1,94 @@ ++/* ++ * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 ++ * ++ * Copyright (C) 2016 Neil Armstrong ++ * ++ * Licensed under GPLv2 or later ++ */ ++ ++/dts-v1/; ++#include "ox820.dtsi" ++ ++/ { ++ model = "Cloud Engines PogoPlug Series 3"; ++ ++ compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; ++ ++ chosen { ++ bootargs = "earlyprintk"; ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ /* 128Mbytes DDR */ ++ reg = <0x60000000 0x8000000>; ++ }; ++ ++ aliases { ++ serial0 = &uart0; ++ gpio0 = &gpio0; ++ gpio1 = &gpio1; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ blue { ++ label = "pogoplug:blue"; ++ gpios = <&gpio0 2 0>; ++ default-state = "keep"; ++ }; ++ ++ orange { ++ label = "pogoplug:orange"; ++ gpios = <&gpio1 16 1>; ++ default-state = "keep"; ++ }; ++ ++ green { ++ label = "pogoplug:green"; ++ gpios = <&gpio1 17 1>; ++ default-state = "keep"; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart0>; ++}; ++ ++&nandc { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_nand>; ++ ++ nand@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ nand-ecc-mode = "soft"; ++ nand-ecc-algo = "hamming"; ++ ++ partition@0 { ++ label = "boot"; ++ reg = <0x00000000 0x00e00000>; ++ read-only; ++ }; ++ ++ partition@e00000 { ++ label = "ubi"; ++ reg = <0x00e00000 0x07200000>; ++ }; ++ }; ++}; ++ ++ða { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_etha_mdio>; ++}; +--- a/arch/arm/boot/dts/wd-mbwe.dts ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* +- * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition +- * +- * Copyright (C) 2016 Neil Armstrong +- * +- * Licensed under GPLv2 or later +- */ +- +-/dts-v1/; +-#include "ox810se.dtsi" +- +-/ { +- model = "Western Digital My Book World Edition"; +- +- compatible = "wd,mbwe", "oxsemi,ox810se"; +- +- chosen { +- bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; +- }; +- +- memory { +- /* 128Mbytes DDR */ +- reg = <0x48000000 0x8000000>; +- }; +- +- aliases { +- serial1 = &uart1; +- gpio0 = &gpio0; +- gpio1 = &gpio1; +- }; +- +- gpio-keys-polled { +- compatible = "gpio-keys-polled"; +- #address-cells = <1>; +- #size-cells = <0>; +- poll-interval = <100>; +- +- power { +- label = "power"; +- gpios = <&gpio0 0 1>; +- linux,code = <0x198>; +- }; +- +- recovery { +- label = "recovery"; +- gpios = <&gpio0 4 1>; +- linux,code = <0xab>; +- }; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- a0 { +- label = "activity0"; +- gpios = <&gpio0 25 0>; +- default-state = "keep"; +- }; +- +- a1 { +- label = "activity1"; +- gpios = <&gpio0 26 0>; +- default-state = "keep"; +- }; +- +- a2 { +- label = "activity2"; +- gpios = <&gpio0 5 0>; +- default-state = "keep"; +- }; +- +- a3 { +- label = "activity3"; +- gpios = <&gpio0 6 0>; +- default-state = "keep"; +- }; +- +- a4 { +- label = "activity4"; +- gpios = <&gpio0 7 0>; +- default-state = "keep"; +- }; +- +- a5 { +- label = "activity5"; +- gpios = <&gpio1 2 0>; +- default-state = "keep"; +- }; +- }; +- +- i2c-gpio { +- compatible = "i2c-gpio"; +- gpios = <&gpio0 3 0 /* sda */ +- &gpio0 2 0 /* scl */ +- >; +- i2c-gpio,delay-us = <2>; /* ~100 kHz */ +- #address-cells = <1>; +- #size-cells = <0>; +- +- rtc0: rtc@48 { +- compatible = "st,m41t00"; +- reg = <0x68>; +- }; +- }; +-}; +- +-&uart1 { +- status = "okay"; +- +- pinctrl-names = "default"; +- pinctrl-0 = <&pinctrl_uart1>; +-}; diff --git a/target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch b/target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch new file mode 100644 index 000000000..44e1d0351 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/0002-MAINTAINERS-update-ARM-OXNAS-platform-support-patter.patch @@ -0,0 +1,34 @@ +From a018141970d80677d2822fef9d391b85bf9cf99f Mon Sep 17 00:00:00 2001 +From: Joe Perches +Date: Tue, 6 Feb 2018 15:42:33 -0800 +Subject: [PATCH 2/3] MAINTAINERS: update "ARM/OXNAS platform support" patterns + +Commit 9e6c62b05c1b ("ARM: dts: rename oxnas dts files") renamed the +files, update the patterns. + +[akpm@linux-foundation.org: crunch into a single globbed term, per Arnd] +Link: http://lkml.kernel.org/r/b39d779e143b3c0a4e7dff827346e509447e3e8e.1517147485.git.joe@perches.com +Signed-off-by: Joe Perches +Reviewed-by: Andrew Morton +Cc: Daniel Golle +Cc: Arnd Bergmann +Cc: Neil Armstrong +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +--- + MAINTAINERS | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1677,9 +1677,7 @@ L: linux-arm-kernel@lists.infradead.org + L: linux-oxnas@lists.tuxfamily.org (moderated for non-subscribers) + S: Maintained + F: arch/arm/mach-oxnas/ +-F: arch/arm/boot/dts/ox8*.dtsi +-F: arch/arm/boot/dts/wd-mbwe.dts +-F: arch/arm/boot/dts/cloudengines-pogoplug-series-3.dts ++F: arch/arm/boot/dts/ox8*.dts* + N: oxnas + + ARM/PALM TREO SUPPORT diff --git a/target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch b/target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch new file mode 100644 index 000000000..be9f1ecac --- /dev/null +++ b/target/linux/oxnas/patches-4.14/0003-ARM-configs-add-OXNAS-v6-defconfig.patch @@ -0,0 +1,111 @@ +From 22c1774af921a1cdb33bd37b44977b5b34ea58d0 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Wed, 14 Mar 2018 09:35:44 +0100 +Subject: [PATCH 3/3] ARM: configs: add OXNAS v6 defconfig + +This patchs adds the minimal defconfig for the OXNAS ARMv6 SoCs +including the OX820 SoC and needed minimal configurations. + +Signed-off-by: Neil Armstrong +Signed-off-by: Arnd Bergmann +--- + arch/arm/configs/oxnas_v6_defconfig | 93 +++++++++++++++++++++++++++++ + 1 file changed, 93 insertions(+) + create mode 100644 arch/arm/configs/oxnas_v6_defconfig + +--- /dev/null ++++ b/arch/arm/configs/oxnas_v6_defconfig +@@ -0,0 +1,93 @@ ++CONFIG_SYSVIPC=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_CGROUPS=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EMBEDDED=y ++CONFIG_PERF_EVENTS=y ++CONFIG_STRICT_KERNEL_RWX=y ++CONFIG_STRICT_MODULE_RWX=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_CMDLINE_PARTITION=y ++CONFIG_ARCH_MULTI_V6=y ++CONFIG_ARCH_OXNAS=y ++CONFIG_MACH_OX820=y ++CONFIG_SMP=y ++CONFIG_NR_CPUS=16 ++CONFIG_CMA=y ++CONFIG_FORCE_MAX_ZONEORDER=12 ++CONFIG_SECCOMP=y ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_KEXEC=y ++CONFIG_EFI=y ++CONFIG_CPU_IDLE=y ++CONFIG_ARM_CPUIDLE=y ++CONFIG_VFP=y ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_INET=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_BOOTP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_IPV6_ROUTER_PREF=y ++CONFIG_IPV6_OPTIMISTIC_DAD=y ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_MIP6=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=64 ++CONFIG_SIMPLE_PM_BUS=y ++CONFIG_MTD=y ++CONFIG_MTD_CMDLINE_PARTS=y ++CONFIG_MTD_BLOCK=y ++CONFIG_MTD_NAND=y ++CONFIG_MTD_NAND_OXNAS=y ++CONFIG_MTD_UBI=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_SIZE=65536 ++CONFIG_NETDEVICES=y ++CONFIG_STMMAC_ETH=y ++CONFIG_REALTEK_PHY=y ++CONFIG_INPUT_EVDEV=y ++CONFIG_SERIAL_8250=y ++CONFIG_SERIAL_8250_CONSOLE=y ++CONFIG_SERIAL_OF_PLATFORM=y ++CONFIG_GPIO_GENERIC_PLATFORM=y ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_FLASH=m ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_ARM_TIMER_SP804=y ++CONFIG_EXT4_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_UBIFS_FS=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_PMSG=y ++CONFIG_PSTORE_RAM=y ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_UTF8=y ++CONFIG_PRINTK_TIME=y ++CONFIG_MAGIC_SYSRQ=y diff --git a/target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch b/target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch new file mode 100644 index 000000000..ad0df9199 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/050-ox820-remove-left-overs.patch @@ -0,0 +1,63 @@ +From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 1 Jun 2018 02:41:15 +0200 +Subject: [PATCH] arm: ox820: remove left-overs + +Signed-off-by: Daniel Golle +--- + drivers/clk/clk-oxnas.c | 2 -- + include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++------------- + 2 files changed, 14 insertions(+), 20 deletions(-) + +--- a/drivers/clk/clk-oxnas.c ++++ b/drivers/clk/clk-oxnas.c +@@ -40,8 +40,6 @@ struct oxnas_stdclk_data { + struct clk_hw_onecell_data *onecell_data; + struct clk_oxnas_gate **gates; + unsigned int ngates; +- struct clk_oxnas_pll **plls; +- unsigned int nplls; + }; + + /* Regmap offsets */ +--- a/include/dt-bindings/clock/oxsemi,ox820.h ++++ b/include/dt-bindings/clock/oxsemi,ox820.h +@@ -17,24 +17,20 @@ + #ifndef DT_CLOCK_OXSEMI_OX820_H + #define DT_CLOCK_OXSEMI_OX820_H + +-/* PLLs */ +-#define CLK_820_PLLA 0 +-#define CLK_820_PLLB 1 +- + /* Gate Clocks */ +-#define CLK_820_LEON 2 +-#define CLK_820_DMA_SGDMA 3 +-#define CLK_820_CIPHER 4 +-#define CLK_820_SD 5 +-#define CLK_820_SATA 6 +-#define CLK_820_AUDIO 7 +-#define CLK_820_USBMPH 8 +-#define CLK_820_ETHA 9 +-#define CLK_820_PCIEA 10 +-#define CLK_820_NAND 11 +-#define CLK_820_PCIEB 12 +-#define CLK_820_ETHB 13 +-#define CLK_820_REF600 14 +-#define CLK_820_USBDEV 15 ++#define CLK_820_LEON 0 ++#define CLK_820_DMA_SGDMA 1 ++#define CLK_820_CIPHER 2 ++#define CLK_820_SD 3 ++#define CLK_820_SATA 4 ++#define CLK_820_AUDIO 5 ++#define CLK_820_USBMPH 6 ++#define CLK_820_ETHA 7 ++#define CLK_820_PCIEA 8 ++#define CLK_820_NAND 9 ++#define CLK_820_PCIEB 10 ++#define CLK_820_ETHB 11 ++#define CLK_820_REF600 12 ++#define CLK_820_USBDEV 13 + + #endif /* DT_CLOCK_OXSEMI_OX820_H */ diff --git a/target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch b/target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch new file mode 100644 index 000000000..d3bf9a9e4 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch @@ -0,0 +1,273 @@ +--- a/drivers/clk/clk-oxnas.c ++++ b/drivers/clk/clk-oxnas.c +@@ -16,19 +16,42 @@ + * along with this program. If not, see . + */ + ++#include ++#include + #include + #include + #include ++#include + #include + #include + #include + #include + #include + #include ++#include + + #include + #include + ++#define REF300_DIV_INT_SHIFT 8 ++#define REF300_DIV_FRAC_SHIFT 0 ++#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT) ++#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT) ++ ++#define PLLB_BYPASS 1 ++#define PLLB_ENSAT 3 ++#define PLLB_OUTDIV 4 ++#define PLLB_REFDIV 8 ++#define PLLB_DIV_INT_SHIFT 8 ++#define PLLB_DIV_FRAC_SHIFT 0 ++#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT) ++#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT) ++ ++#define PLLA_REFDIV_MASK 0x3F ++#define PLLA_REFDIV_SHIFT 8 ++#define PLLA_OUTDIV_MASK 0x7 ++#define PLLA_OUTDIV_SHIFT 4 ++ + /* Standard regmap gate clocks */ + struct clk_oxnas_gate { + struct clk_hw hw; +@@ -47,6 +70,135 @@ struct oxnas_stdclk_data { + #define CLK_SET_REGOFFSET 0x2c + #define CLK_CLR_REGOFFSET 0x30 + ++#define PLLA_CTRL0_REGOFFSET 0x1f0 ++#define PLLA_CTRL1_REGOFFSET 0x1f4 ++#define PLLB_CTRL0_REGOFFSET 0x1001f0 ++#define MHZ (1000 * 1000) ++ ++struct clk_oxnas_pll { ++ struct clk_hw hw; ++ struct device_node *devnode; ++ struct reset_control *rstc; ++ struct regmap *syscon; ++}; ++ ++#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw) ++ ++static unsigned long plla_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw); ++ unsigned long fin = parent_rate; ++ unsigned long refdiv, outdiv; ++ unsigned int pll0, fbdiv; ++ ++ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0)); ++ ++ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK; ++ refdiv += 1; ++ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK; ++ outdiv += 1; ++ ++ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv)); ++ /* seems we will not be here when pll is bypassed, so ignore this ++ * case */ ++ ++ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ; ++} ++ ++static const char *pll_clk_parents[] = { ++ "oscillator", ++}; ++ ++static struct clk_ops plla_ops = { ++ .recalc_rate = plla_clk_recalc_rate, ++}; ++ ++static struct clk_init_data clk_plla_init = { ++ .name = "plla", ++ .ops = &plla_ops, ++ .parent_names = pll_clk_parents, ++ .num_parents = ARRAY_SIZE(pll_clk_parents), ++}; ++ ++static int pllb_clk_is_prepared(struct clk_hw *hw) ++{ ++ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); ++ ++ return !!pllb->rstc; ++} ++ ++static int pllb_clk_prepare(struct clk_hw *hw) ++{ ++ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); ++ ++ pllb->rstc = of_reset_control_get(pllb->devnode, NULL); ++ ++ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0; ++} ++ ++static void pllb_clk_unprepare(struct clk_hw *hw) ++{ ++ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); ++ ++ BUG_ON(IS_ERR(pllb->rstc)); ++ ++ reset_control_put(pllb->rstc); ++ pllb->rstc = NULL; ++} ++ ++static int pllb_clk_enable(struct clk_hw *hw) ++{ ++ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); ++ ++ BUG_ON(IS_ERR(pllb->rstc)); ++ ++ /* put PLL into bypass */ ++ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS)); ++ wmb(); ++ udelay(10); ++ reset_control_assert(pllb->rstc); ++ udelay(10); ++ /* set PLL B control information */ ++ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff, ++ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV)); ++ reset_control_deassert(pllb->rstc); ++ udelay(100); ++ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0); ++ ++ return 0; ++} ++ ++static void pllb_clk_disable(struct clk_hw *hw) ++{ ++ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw); ++ ++ BUG_ON(IS_ERR(pllb->rstc)); ++ ++ /* put PLL into bypass */ ++ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS)); ++ ++ wmb(); ++ udelay(10); ++ ++ reset_control_assert(pllb->rstc); ++} ++ ++static struct clk_ops pllb_ops = { ++ .prepare = pllb_clk_prepare, ++ .unprepare = pllb_clk_unprepare, ++ .is_prepared = pllb_clk_is_prepared, ++ .enable = pllb_clk_enable, ++ .disable = pllb_clk_disable, ++}; ++ ++static struct clk_init_data clk_pllb_init = { ++ .name = "pllb", ++ .ops = &pllb_ops, ++ .parent_names = pll_clk_parents, ++ .num_parents = ARRAY_SIZE(pll_clk_parents), ++}; ++ + static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw) + { + return container_of(hw, struct clk_oxnas_gate, hw); +@@ -260,3 +412,42 @@ static struct platform_driver oxnas_stdc + }, + }; + builtin_platform_driver(oxnas_stdclk_driver); ++ ++void __init oxnas_init_plla(struct device_node *np) ++{ ++ struct clk *clk; ++ struct clk_oxnas_pll *plla; ++ ++ plla = kmalloc(sizeof(*plla), GFP_KERNEL); ++ BUG_ON(!plla); ++ ++ plla->syscon = syscon_node_to_regmap(of_get_parent(np)); ++ plla->hw.init = &clk_plla_init; ++ plla->devnode = np; ++ plla->rstc = NULL; ++ clk = clk_register(NULL, &plla->hw); ++ BUG_ON(IS_ERR(clk)); ++ /* mark it as enabled */ ++ clk_prepare_enable(clk); ++ of_clk_add_provider(np, of_clk_src_simple_get, clk); ++} ++CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla); ++ ++void __init oxnas_init_pllb(struct device_node *np) ++{ ++ struct clk *clk; ++ struct clk_oxnas_pll *pllb; ++ ++ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL); ++ BUG_ON(!pllb); ++ ++ pllb->syscon = syscon_node_to_regmap(of_get_parent(np)); ++ pllb->hw.init = &clk_pllb_init; ++ pllb->devnode = np; ++ pllb->rstc = NULL; ++ ++ clk = clk_register(NULL, &pllb->hw); ++ BUG_ON(IS_ERR(clk)); ++ of_clk_add_provider(np, of_clk_src_simple_get, clk); ++} ++CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb); +--- a/arch/arm/boot/dts/ox820.dtsi ++++ b/arch/arm/boot/dts/ox820.dtsi +@@ -60,12 +60,6 @@ + clocks = <&osc>; + }; + +- plla: plla { +- compatible = "fixed-clock"; +- #clock-cells = <0>; +- clock-frequency = <850000000>; +- }; +- + armclk: armclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; +@@ -265,6 +259,19 @@ + compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; + #clock-cells = <1>; + }; ++ ++ plla: plla { ++ compatible = "plxtech,nas782x-plla"; ++ #clock-cells = <0>; ++ clocks = <&osc>; ++ }; ++ ++ pllb: pllb { ++ compatible = "plxtech,nas782x-pllb"; ++ #clock-cells = <0>; ++ clocks = <&osc>; ++ resets = <&reset RESET_PLLB>; ++ }; + }; + }; + +@@ -286,6 +293,13 @@ + clocks = <&armclk>; + }; + ++ watchdog@620 { ++ compatible = "mpcore_wdt"; ++ reg = <0x620 0x20>; ++ interrupts = ; ++ clocks = <&armclk>; ++ }; ++ + gic: gic@1000 { + compatible = "arm,arm11mp-gic"; + interrupt-controller; diff --git a/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch b/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch new file mode 100644 index 000000000..4681888da --- /dev/null +++ b/target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch @@ -0,0 +1,108 @@ +--- a/drivers/pci/host/Kconfig ++++ b/drivers/pci/host/Kconfig +@@ -220,4 +220,9 @@ config VMD + To compile this driver as a module, choose M here: the + module will be called vmd. + ++config PCIE_OXNAS ++ bool "PLX Oxnas PCIe controller" ++ depends on ARCH_OXNAS ++ select PCIEPORTBUS ++ + endmenu +--- a/drivers/pci/host/Makefile ++++ b/drivers/pci/host/Makefile +@@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera + obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o + obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o + obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o ++obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o + obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o + obj-$(CONFIG_VMD) += vmd.o + +--- a/arch/arm/boot/dts/ox820.dtsi ++++ b/arch/arm/boot/dts/ox820.dtsi +@@ -307,6 +307,83 @@ + reg = <0x1000 0x1000>, + <0x100 0x500>; + }; ++ ++ pcie0: pcie-controller@c00000 { ++ compatible = "plxtech,nas782x-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ /* flag & space bus address host address size */ ++ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000 ++ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000 ++ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000 ++ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>; ++ ++ bus-range = <0x00 0x7f>; ++ ++ /* cfg inbound translator phy*/ ++ reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>; ++ ++ #interrupt-cells = <1>; ++ /* wild card mask, match all bus address & interrupt specifier */ ++ /* format: bus address mask, interrupt specifier mask */ ++ /* each bit 1 means need match, 0 means ignored when match */ ++ interrupt-map-mask = <0 0 0 0>; ++ /* format: a list of: bus address, interrupt specifier, ++ * parent interrupt controller & specifier */ ++ interrupt-map = <0 0 0 0 &gic 0 19 0x304>; ++ ++ gpios = <&gpio1 12 0>; ++ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>; ++ clock-names = "pcie", "busclk"; ++ resets = <&reset RESET_PCIEA>, <&reset RESET_PCIEPHY>; ++ reset-names = "pcie", "phy"; ++ ++ plxtech,pcie-hcsl-bit = <2>; ++ plxtech,pcie-ctrl-offset = <0x120>; ++ plxtech,pcie-outbound-offset = <0x138>; ++ status = "disabled"; ++ }; ++ ++ pcie1: pcie-controller@e00000 { ++ compatible = "plxtech,nas782x-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ /* flag & space bus address host address size */ ++ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000 ++ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000 ++ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000 ++ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>; ++ ++ bus-range = <0x80 0xff>; ++ ++ /* cfg inbound translator phy*/ ++ reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>; ++ ++ #interrupt-cells = <1>; ++ /* wild card mask, match all bus address & interrupt specifier */ ++ /* format: bus address mask, interrupt specifier mask */ ++ /* each bit 1 means need match, 0 means ignored when match */ ++ interrupt-map-mask = <0 0 0 0>; ++ /* format: a list of: bus address, interrupt specifier, ++ * parent interrupt controller & specifier */ ++ interrupt-map = <0 0 0 0 &gic 0 20 0x304>; ++ ++ /* gpios = <&gpio1 12 0>; */ ++ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>; ++ clock-names = "pcie", "busclk"; ++ resets = <&reset RESET_PCIEB>, <&reset RESET_PCIEPHY>; ++ reset-names = "pcie", "phy"; ++ ++ plxtech,pcie-hcsl-bit = <3>; ++ plxtech,pcie-ctrl-offset = <0x124>; ++ plxtech,pcie-outbound-offset = <0x174>; ++ status = "disabled"; ++ }; ++ + }; + }; + }; diff --git a/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch b/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch new file mode 100644 index 000000000..f79b100a5 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/500-oxnas-sata.patch @@ -0,0 +1,49 @@ +--- a/drivers/ata/Kconfig ++++ b/drivers/ata/Kconfig +@@ -492,6 +492,13 @@ config SATA_VITESSE + + If unsure, say N. + ++config SATA_OXNAS ++ tristate "PLXTECH NAS782X SATA support" ++ help ++ This option enables support for Nas782x Serial ATA controller. ++ ++ If unsure, say N. ++ + comment "PATA SFF controllers with BMDMA" + + config PATA_ALI +--- a/drivers/ata/Makefile ++++ b/drivers/ata/Makefile +@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o + obj-$(CONFIG_SATA_ULI) += sata_uli.o + obj-$(CONFIG_SATA_VIA) += sata_via.o + obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o ++obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o + + # SFF PATA w/ BMDMA + obj-$(CONFIG_PATA_ALI) += pata_ali.o +--- a/arch/arm/boot/dts/ox820.dtsi ++++ b/arch/arm/boot/dts/ox820.dtsi +@@ -385,5 +385,20 @@ + }; + + }; ++ ++ sata: sata@45900000 { ++ compatible = "plxtech,nas782x-sata"; ++ /* ports dmactl sgdma */ ++ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>, ++ /* core phy descriptors (optional) */ ++ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>; ++ interrupts = ; ++ clocks = <&stdclk CLK_820_SATA>; ++ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>; ++ reset-names = "sata", "link", "phy"; ++ nr-ports = <1>; ++ status = "disabled"; ++ }; ++ + }; + }; diff --git a/target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch b/target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch new file mode 100644 index 000000000..6d85a046b --- /dev/null +++ b/target/linux/oxnas/patches-4.14/510-ox820-libata-leds.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/mach-oxnas/Kconfig ++++ b/arch/arm/mach-oxnas/Kconfig +@@ -1,6 +1,7 @@ + menuconfig ARCH_OXNAS + bool "Oxford Semiconductor OXNAS Family SoCs" + select ARCH_HAS_RESET_CONTROLLER ++ select ARCH_WANT_LIBATA_LEDS + select COMMON_CLK_OXNAS + select GPIOLIB + select MFD_SYSCON diff --git a/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch b/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch new file mode 100644 index 000000000..b4e34e5e3 --- /dev/null +++ b/target/linux/oxnas/patches-4.14/800-oxnas-ehci.patch @@ -0,0 +1,51 @@ +--- a/drivers/usb/host/Kconfig ++++ b/drivers/usb/host/Kconfig +@@ -334,6 +334,13 @@ config USB_OCTEON_EHCI + USB 2.0 device support. All CN6XXX based chips with USB are + supported. + ++config USB_EHCI_OXNAS ++ tristate "OXNAS EHCI Module" ++ depends on USB_EHCI_HCD && ARCH_OXNAS ++ select USB_EHCI_ROOT_HUB_TT ++ ---help--- ++ Enable support for the OX820 SOC's on-chip EHCI controller. ++ + endif # USB_EHCI_HCD + + config USB_OXU210HP_HCD +--- a/drivers/usb/host/Makefile ++++ b/drivers/usb/host/Makefile +@@ -43,6 +43,7 @@ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci- + obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o + obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o + obj-$(CONFIG_USB_W90X900_EHCI) += ehci-w90x900.o ++obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o + + obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o + obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o +--- a/arch/arm/boot/dts/ox820.dtsi ++++ b/arch/arm/boot/dts/ox820.dtsi +@@ -105,6 +105,22 @@ + status = "disabled"; + }; + ++ ehci: ehci@40200100 { ++ compatible = "plxtech,nas782x-ehci"; ++ reg = <0x40200100 0xf00>; ++ interrupts = ; ++ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>; ++ clock-names = "usb", "refsrc", "phyref"; ++ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>; ++ reset-names = "host", "phya", "phyb"; ++ oxsemi,sys-ctrl = <&sys>; ++ /* Otherwise ref300 is used, which is derived from sata phy ++ * in that case, usb depends on sata initialization */ ++ /* FIXME: how to make this dependency explicit ? */ ++ oxsemi,ehci_use_pllb; ++ status = "disabled"; ++ }; ++ + apb-bridge@44000000 { + #address-cells = <1>; + #size-cells = <1>; diff --git a/target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch b/target/linux/oxnas/patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch similarity index 84% rename from target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch rename to target/linux/oxnas/patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch index 6bffa6fe6..85947b197 100644 --- a/target/linux/oxnas/patches-4.4/996-ATAG_DTB_COMPAT_CMDLINE_MANGLE.patch +++ b/target/linux/oxnas/patches-4.14/996-generic-Mangle-bootloader-s-kernel-arguments.patch @@ -1,7 +1,7 @@ -Author: Adrian Panella -Date: Fri Jun 10 19:10:15 2016 -0500 - -generic: Mangle bootloader's kernel arguments +From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001 +From: Adrian Panella +Date: Thu, 9 Mar 2017 09:37:17 +0100 +Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments The command-line arguments provided by the boot loader will be appended to a new device tree property: bootloader-args. @@ -13,12 +13,16 @@ sent by bootloader will be ignored. This is usefull in dual boot systems, to get the current root partition without afecting the rest of the system. - Signed-off-by: Adrian Panella +--- + arch/arm/Kconfig | 11 +++++ + arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++- + init/main.c | 16 ++++++++ + 3 files changed, 98 insertions(+), 1 deletion(-) --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1943,6 +1943,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1938,6 +1938,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN The command-line arguments provided by the boot loader will be appended to the the device tree bootargs property. @@ -38,7 +42,7 @@ Signed-off-by: Adrian Panella config CMDLINE --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c -@@ -3,6 +3,8 @@ +@@ -4,6 +4,8 @@ #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) #define do_extend_cmdline 1 @@ -47,7 +51,7 @@ Signed-off-by: Adrian Panella #else #define do_extend_cmdline 0 #endif -@@ -66,6 +68,59 @@ static uint32_t get_cell_size(const void +@@ -67,6 +69,59 @@ static uint32_t get_cell_size(const void return cell_size; } @@ -107,7 +111,7 @@ Signed-off-by: Adrian Panella static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) { char cmdline[COMMAND_LINE_SIZE]; -@@ -85,12 +140,21 @@ static void merge_fdt_bootargs(void *fdt +@@ -86,12 +141,21 @@ static void merge_fdt_bootargs(void *fdt /* and append the ATAG_CMDLINE */ if (fdt_cmdline) { @@ -129,7 +133,7 @@ Signed-off-by: Adrian Panella } *ptr = '\0'; -@@ -147,7 +211,9 @@ int atags_to_fdt(void *atag_list, void * +@@ -148,7 +212,9 @@ int atags_to_fdt(void *atag_list, void * else setprop_string(fdt, "/chosen", "bootargs", atag->u.cmdline.cmdline); @@ -140,7 +144,7 @@ Signed-off-by: Adrian Panella if (memcount >= sizeof(mem_reg_property)/4) continue; if (!atag->u.mem.size) -@@ -186,6 +252,10 @@ int atags_to_fdt(void *atag_list, void * +@@ -187,6 +253,10 @@ int atags_to_fdt(void *atag_list, void * setprop(fdt, "/memory", "reg", mem_reg_property, 4 * memcount * memsize); } @@ -153,7 +157,7 @@ Signed-off-by: Adrian Panella } --- a/init/main.c +++ b/init/main.c -@@ -89,6 +89,10 @@ +@@ -95,6 +95,10 @@ #include #include @@ -164,7 +168,7 @@ Signed-off-by: Adrian Panella static int kernel_init(void *); extern void init_IRQ(void); -@@ -562,6 +566,18 @@ asmlinkage __visible void __init start_k +@@ -574,6 +578,18 @@ asmlinkage __visible void __init start_k page_alloc_init(); pr_notice("Kernel command line: %s\n", boot_command_line); diff --git a/target/linux/oxnas/patches-4.4/999-libata-hacks.patch b/target/linux/oxnas/patches-4.14/999-libata-hacks.patch similarity index 82% rename from target/linux/oxnas/patches-4.4/999-libata-hacks.patch rename to target/linux/oxnas/patches-4.14/999-libata-hacks.patch index ac278ab23..6d0f23140 100644 --- a/target/linux/oxnas/patches-4.4/999-libata-hacks.patch +++ b/target/linux/oxnas/patches-4.14/999-libata-hacks.patch @@ -1,6 +1,6 @@ --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c -@@ -1589,6 +1589,14 @@ unsigned ata_exec_internal_sg(struct ata +@@ -1599,6 +1599,14 @@ unsigned ata_exec_internal_sg(struct ata return AC_ERR_SYSTEM; } @@ -15,7 +15,7 @@ /* initialize internal qc */ /* XXX: Tag 0 is used for drivers with legacy EH as some -@@ -4788,6 +4796,9 @@ struct ata_queued_cmd *ata_qc_new_init(s +@@ -5127,6 +5135,9 @@ struct ata_queued_cmd *ata_qc_new_init(s if (unlikely(ap->pflags & ATA_PFLAG_FROZEN)) return NULL; @@ -25,7 +25,7 @@ /* libsas case */ if (ap->flags & ATA_FLAG_SAS_HOST) { tag = ata_sas_allocate_tag(ap); -@@ -4833,6 +4844,8 @@ void ata_qc_free(struct ata_queued_cmd * +@@ -5172,6 +5183,8 @@ void ata_qc_free(struct ata_queued_cmd * qc->tag = ATA_TAG_POISON; if (ap->flags & ATA_FLAG_SAS_HOST) ata_sas_free_tag(tag, ap); @@ -36,7 +36,7 @@ --- a/include/linux/libata.h +++ b/include/linux/libata.h -@@ -906,6 +906,8 @@ struct ata_port_operations { +@@ -918,6 +918,8 @@ struct ata_port_operations { void (*qc_prep)(struct ata_queued_cmd *qc); unsigned int (*qc_issue)(struct ata_queued_cmd *qc); bool (*qc_fill_rtf)(struct ata_queued_cmd *qc); @@ -45,7 +45,7 @@ /* * Configuration and exception handling -@@ -996,6 +998,9 @@ struct ata_port_operations { +@@ -1008,6 +1010,9 @@ struct ata_port_operations { void (*phy_reset)(struct ata_port *ap); void (*eng_timeout)(struct ata_port *ap); diff --git a/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch b/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch deleted file mode 100644 index 204d6e0bc..000000000 --- a/target/linux/oxnas/patches-4.4/0072-mtd-backport-v4.7-0day-patches-from-Boris.patch +++ /dev/null @@ -1,5281 +0,0 @@ -From a369af5149e6eb442b22ce89b564dd7a76e03638 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 26 Apr 2016 19:05:01 +0200 -Subject: [PATCH 072/102] mtd: backport v4.7-0day patches from Boris - -Signed-off-by: John Crispin ---- - drivers/mtd/Kconfig | 4 +- - drivers/mtd/cmdlinepart.c | 3 +- - drivers/mtd/devices/m25p80.c | 44 +-- - drivers/mtd/maps/physmap_of.c | 6 +- - drivers/mtd/mtdchar.c | 123 ++++++-- - drivers/mtd/mtdconcat.c | 2 +- - drivers/mtd/mtdcore.c | 428 ++++++++++++++++++++++++-- - drivers/mtd/mtdcore.h | 7 +- - drivers/mtd/mtdpart.c | 161 ++++++---- - drivers/mtd/mtdswap.c | 24 +- - drivers/mtd/nand/Kconfig | 21 +- - drivers/mtd/nand/Makefile | 2 + - drivers/mtd/nand/nand_base.c | 571 +++++++++++++++++++---------------- - drivers/mtd/nand/nand_bbt.c | 34 +-- - drivers/mtd/nand/nand_bch.c | 52 ++-- - drivers/mtd/nand/nand_ecc.c | 6 +- - drivers/mtd/nand/nand_ids.c | 4 +- - drivers/mtd/nand/nandsim.c | 43 +-- - drivers/mtd/ofpart.c | 53 ++-- - drivers/mtd/spi-nor/Kconfig | 10 +- - drivers/mtd/spi-nor/Makefile | 1 + - drivers/mtd/spi-nor/mtk-quadspi.c | 485 +++++++++++++++++++++++++++++ - drivers/mtd/spi-nor/spi-nor.c | 321 +++++++++++++------- - drivers/mtd/tests/mtd_nandecctest.c | 2 +- - drivers/mtd/tests/oobtest.c | 49 ++- - drivers/mtd/tests/pagetest.c | 3 +- - include/linux/mtd/bbm.h | 1 - - include/linux/mtd/fsmc.h | 18 -- - include/linux/mtd/inftl.h | 1 - - include/linux/mtd/map.h | 9 +- - include/linux/mtd/mtd.h | 80 ++++- - include/linux/mtd/nand.h | 94 ++++-- - include/linux/mtd/nand_bch.h | 10 +- - include/linux/mtd/nftl.h | 1 - - include/linux/mtd/onenand.h | 2 - - include/linux/mtd/partitions.h | 27 +- - include/linux/mtd/sh_flctl.h | 4 +- - include/linux/mtd/sharpsl.h | 2 +- - include/linux/mtd/spi-nor.h | 23 +- - include/uapi/mtd/mtd-abi.h | 2 +- - 45 files changed, 2077 insertions(+), 748 deletions(-) - create mode 100644 drivers/mtd/spi-nor/mtk-quadspi.c - ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -131,7 +131,7 @@ config MTD_CMDLINE_PARTS - - config MTD_AFS_PARTS - tristate "ARM Firmware Suite partition parsing" -- depends on ARM -+ depends on (ARM || ARM64) - ---help--- - The ARM Firmware Suite allows the user to divide flash devices into - multiple 'images'. Each such image has a header containing its name -@@ -161,7 +161,7 @@ config MTD_AR7_PARTS - - config MTD_BCM63XX_PARTS - tristate "BCM63XX CFE partitioning support" -- depends on BCM63XX -+ depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST - select CRC32 - help - This provides partions parsing for BCM63xx devices with CFE ---- a/drivers/mtd/cmdlinepart.c -+++ b/drivers/mtd/cmdlinepart.c -@@ -304,7 +304,7 @@ static int mtdpart_setup_real(char *s) - * the first one in the chain if a NULL mtd_id is passed in. - */ - static int parse_cmdline_partitions(struct mtd_info *master, -- struct mtd_partition **pparts, -+ const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { - unsigned long long offset; -@@ -382,7 +382,6 @@ static int __init mtdpart_setup(char *s) - __setup("mtdparts=", mtdpart_setup); - - static struct mtd_part_parser cmdline_parser = { -- .owner = THIS_MODULE, - .parse_fn = parse_cmdline_partitions, - .name = "cmdlinepart", - }; ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -174,22 +174,6 @@ static int m25p80_read(struct spi_nor *n - return 0; - } - --static int m25p80_erase(struct spi_nor *nor, loff_t offset) --{ -- struct m25p *flash = nor->priv; -- -- dev_dbg(nor->dev, "%dKiB at 0x%08x\n", -- flash->spi_nor.mtd.erasesize / 1024, (u32)offset); -- -- /* Set up command buffer. */ -- flash->command[0] = nor->erase_opcode; -- m25p_addr2cmd(nor, offset, flash->command); -- -- spi_write(flash->spi, flash->command, m25p_cmdsz(nor)); -- -- return 0; --} -- - /* - * board specific setup should have ensured the SPI clock used here - * matches what the READ command supports, at least until this driver -@@ -197,12 +181,11 @@ static int m25p80_erase(struct spi_nor * - */ - static int m25p_probe(struct spi_device *spi) - { -- struct mtd_part_parser_data ppdata; - struct flash_platform_data *data; - struct m25p *flash; - struct spi_nor *nor; - enum read_mode mode = SPI_NOR_NORMAL; -- char *flash_name = NULL; -+ char *flash_name; - int ret; - - data = dev_get_platdata(&spi->dev); -@@ -216,12 +199,11 @@ static int m25p_probe(struct spi_device - /* install the hooks */ - nor->read = m25p80_read; - nor->write = m25p80_write; -- nor->erase = m25p80_erase; - nor->write_reg = m25p80_write_reg; - nor->read_reg = m25p80_read_reg; - - nor->dev = &spi->dev; -- nor->flash_node = spi->dev.of_node; -+ spi_nor_set_flash_node(nor, spi->dev.of_node); - nor->priv = flash; - - spi_set_drvdata(spi, flash); -@@ -242,6 +224,8 @@ static int m25p_probe(struct spi_device - */ - if (data && data->type) - flash_name = data->type; -+ else if (!strcmp(spi->modalias, "spi-nor")) -+ flash_name = NULL; /* auto-detect */ - else - flash_name = spi->modalias; - -@@ -249,11 +233,8 @@ static int m25p_probe(struct spi_device - if (ret) - return ret; - -- ppdata.of_node = spi->dev.of_node; -- -- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata, -- data ? data->parts : NULL, -- data ? data->nr_parts : 0); -+ return mtd_device_register(&nor->mtd, data ? data->parts : NULL, -+ data ? data->nr_parts : 0); - } - - -@@ -279,14 +260,21 @@ static int m25p_remove(struct spi_device - */ - static const struct spi_device_id m25p_ids[] = { - /* -+ * Allow non-DT platform devices to bind to the "spi-nor" modalias, and -+ * hack around the fact that the SPI core does not provide uevent -+ * matching for .of_match_table -+ */ -+ {"spi-nor"}, -+ -+ /* - * Entries not used in DTs that should be safe to drop after replacing -- * them with "nor-jedec" in platform data. -+ * them with "spi-nor" in platform data. - */ - {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"}, - - /* -- * Entries that were used in DTs without "nor-jedec" fallback and should -- * be kept for backward compatibility. -+ * Entries that were used in DTs without "jedec,spi-nor" fallback and -+ * should be kept for backward compatibility. - */ - {"at25df321a"}, {"at25df641"}, {"at26df081a"}, - {"mr25h256"}, ---- a/drivers/mtd/maps/physmap_of.c -+++ b/drivers/mtd/maps/physmap_of.c -@@ -128,7 +128,6 @@ static int of_flash_probe(struct platfor - int reg_tuple_size; - struct mtd_info **mtd_list = NULL; - resource_size_t res_size; -- struct mtd_part_parser_data ppdata; - bool map_indirect; - const char *mtd_name = NULL; - -@@ -272,8 +271,9 @@ static int of_flash_probe(struct platfor - if (err) - goto err_out; - -- ppdata.of_node = dp; -- mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, -+ info->cmtd->dev.parent = &dev->dev; -+ mtd_set_of_node(info->cmtd, dp); -+ mtd_device_parse_register(info->cmtd, part_probe_types_def, NULL, - NULL, 0); - - kfree(mtd_list); ---- a/drivers/mtd/mtdchar.c -+++ b/drivers/mtd/mtdchar.c -@@ -465,38 +465,111 @@ static int mtdchar_readoob(struct file * - } - - /* -- * Copies (and truncates, if necessary) data from the larger struct, -- * nand_ecclayout, to the smaller, deprecated layout struct, -- * nand_ecclayout_user. This is necessary only to support the deprecated -- * API ioctl ECCGETLAYOUT while allowing all new functionality to use -- * nand_ecclayout flexibly (i.e. the struct may change size in new -- * releases without requiring major rewrites). -+ * Copies (and truncates, if necessary) OOB layout information to the -+ * deprecated layout struct, nand_ecclayout_user. This is necessary only to -+ * support the deprecated API ioctl ECCGETLAYOUT while allowing all new -+ * functionality to use mtd_ooblayout_ops flexibly (i.e. mtd_ooblayout_ops -+ * can describe any kind of OOB layout with almost zero overhead from a -+ * memory usage point of view). - */ --static int shrink_ecclayout(const struct nand_ecclayout *from, -- struct nand_ecclayout_user *to) -+static int shrink_ecclayout(struct mtd_info *mtd, -+ struct nand_ecclayout_user *to) - { -- int i; -+ struct mtd_oob_region oobregion; -+ int i, section = 0, ret; - -- if (!from || !to) -+ if (!mtd || !to) - return -EINVAL; - - memset(to, 0, sizeof(*to)); - -- to->eccbytes = min((int)from->eccbytes, MTD_MAX_ECCPOS_ENTRIES); -- for (i = 0; i < to->eccbytes; i++) -- to->eccpos[i] = from->eccpos[i]; -+ to->eccbytes = 0; -+ for (i = 0; i < MTD_MAX_ECCPOS_ENTRIES;) { -+ u32 eccpos; -+ -+ ret = mtd_ooblayout_ecc(mtd, section, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ -+ break; -+ } -+ -+ eccpos = oobregion.offset; -+ for (; i < MTD_MAX_ECCPOS_ENTRIES && -+ eccpos < oobregion.offset + oobregion.length; i++) { -+ to->eccpos[i] = eccpos++; -+ to->eccbytes++; -+ } -+ } - - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++) { -- if (from->oobfree[i].length == 0 && -- from->oobfree[i].offset == 0) -+ ret = mtd_ooblayout_free(mtd, i, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ - break; -- to->oobavail += from->oobfree[i].length; -- to->oobfree[i] = from->oobfree[i]; -+ } -+ -+ to->oobfree[i].offset = oobregion.offset; -+ to->oobfree[i].length = oobregion.length; -+ to->oobavail += to->oobfree[i].length; - } - - return 0; - } - -+static int get_oobinfo(struct mtd_info *mtd, struct nand_oobinfo *to) -+{ -+ struct mtd_oob_region oobregion; -+ int i, section = 0, ret; -+ -+ if (!mtd || !to) -+ return -EINVAL; -+ -+ memset(to, 0, sizeof(*to)); -+ -+ to->eccbytes = 0; -+ for (i = 0; i < ARRAY_SIZE(to->eccpos);) { -+ u32 eccpos; -+ -+ ret = mtd_ooblayout_ecc(mtd, section, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ -+ break; -+ } -+ -+ if (oobregion.length + i > ARRAY_SIZE(to->eccpos)) -+ return -EINVAL; -+ -+ eccpos = oobregion.offset; -+ for (; eccpos < oobregion.offset + oobregion.length; i++) { -+ to->eccpos[i] = eccpos++; -+ to->eccbytes++; -+ } -+ } -+ -+ for (i = 0; i < 8; i++) { -+ ret = mtd_ooblayout_free(mtd, i, &oobregion); -+ if (ret < 0) { -+ if (ret != -ERANGE) -+ return ret; -+ -+ break; -+ } -+ -+ to->oobfree[i][0] = oobregion.offset; -+ to->oobfree[i][1] = oobregion.length; -+ } -+ -+ to->useecc = MTD_NANDECC_AUTOPLACE; -+ -+ return 0; -+} -+ - static int mtdchar_blkpg_ioctl(struct mtd_info *mtd, - struct blkpg_ioctl_arg *arg) - { -@@ -815,16 +888,12 @@ static int mtdchar_ioctl(struct file *fi - { - struct nand_oobinfo oi; - -- if (!mtd->ecclayout) -+ if (!mtd->ooblayout) - return -EOPNOTSUPP; -- if (mtd->ecclayout->eccbytes > ARRAY_SIZE(oi.eccpos)) -- return -EINVAL; - -- oi.useecc = MTD_NANDECC_AUTOPLACE; -- memcpy(&oi.eccpos, mtd->ecclayout->eccpos, sizeof(oi.eccpos)); -- memcpy(&oi.oobfree, mtd->ecclayout->oobfree, -- sizeof(oi.oobfree)); -- oi.eccbytes = mtd->ecclayout->eccbytes; -+ ret = get_oobinfo(mtd, &oi); -+ if (ret) -+ return ret; - - if (copy_to_user(argp, &oi, sizeof(struct nand_oobinfo))) - return -EFAULT; -@@ -913,14 +982,14 @@ static int mtdchar_ioctl(struct file *fi - { - struct nand_ecclayout_user *usrlay; - -- if (!mtd->ecclayout) -+ if (!mtd->ooblayout) - return -EOPNOTSUPP; - - usrlay = kmalloc(sizeof(*usrlay), GFP_KERNEL); - if (!usrlay) - return -ENOMEM; - -- shrink_ecclayout(mtd->ecclayout, usrlay); -+ shrink_ecclayout(mtd, usrlay); - - if (copy_to_user(argp, usrlay, sizeof(*usrlay))) - ret = -EFAULT; ---- a/drivers/mtd/mtdconcat.c -+++ b/drivers/mtd/mtdconcat.c -@@ -777,7 +777,7 @@ struct mtd_info *mtd_concat_create(struc - - } - -- concat->mtd.ecclayout = subdev[0]->ecclayout; -+ mtd_set_ooblayout(&concat->mtd, subdev[0]->ooblayout); - - concat->num_subdev = num_devs; - concat->mtd.name = name; ---- a/drivers/mtd/mtdcore.c -+++ b/drivers/mtd/mtdcore.c -@@ -32,6 +32,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -446,6 +447,7 @@ int add_mtd_device(struct mtd_info *mtd) - mtd->dev.devt = MTD_DEVT(i); - dev_set_name(&mtd->dev, "mtd%d", i); - dev_set_drvdata(&mtd->dev, mtd); -+ of_node_get(mtd_get_of_node(mtd)); - error = device_register(&mtd->dev); - if (error) - goto fail_added; -@@ -477,6 +479,7 @@ int add_mtd_device(struct mtd_info *mtd) - return 0; - - fail_added: -+ of_node_put(mtd_get_of_node(mtd)); - idr_remove(&mtd_idr, i); - fail_locked: - mutex_unlock(&mtd_table_mutex); -@@ -518,6 +521,7 @@ int del_mtd_device(struct mtd_info *mtd) - device_unregister(&mtd->dev); - - idr_remove(&mtd_idr, mtd->index); -+ of_node_put(mtd_get_of_node(mtd)); - - module_put(THIS_MODULE); - ret = 0; -@@ -529,9 +533,10 @@ out_error: - } - - static int mtd_add_device_partitions(struct mtd_info *mtd, -- struct mtd_partition *real_parts, -- int nbparts) -+ struct mtd_partitions *parts) - { -+ const struct mtd_partition *real_parts = parts->parts; -+ int nbparts = parts->nr_parts; - int ret; - - if (nbparts == 0 || IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) { -@@ -600,29 +605,29 @@ int mtd_device_parse_register(struct mtd - const struct mtd_partition *parts, - int nr_parts) - { -+ struct mtd_partitions parsed; - int ret; -- struct mtd_partition *real_parts = NULL; - - mtd_set_dev_defaults(mtd); - -- ret = parse_mtd_partitions(mtd, types, &real_parts, parser_data); -- if (ret <= 0 && nr_parts && parts) { -- real_parts = kmemdup(parts, sizeof(*parts) * nr_parts, -- GFP_KERNEL); -- if (!real_parts) -- ret = -ENOMEM; -- else -- ret = nr_parts; -- } -- /* Didn't come up with either parsed OR fallback partitions */ -- if (ret < 0) { -- pr_info("mtd: failed to find partitions; one or more parsers reports errors (%d)\n", -+ memset(&parsed, 0, sizeof(parsed)); -+ -+ ret = parse_mtd_partitions(mtd, types, &parsed, parser_data); -+ if ((ret < 0 || parsed.nr_parts == 0) && parts && nr_parts) { -+ /* Fall back to driver-provided partitions */ -+ parsed = (struct mtd_partitions){ -+ .parts = parts, -+ .nr_parts = nr_parts, -+ }; -+ } else if (ret < 0) { -+ /* Didn't come up with parsed OR fallback partitions */ -+ pr_info("mtd: failed to find partitions; one or more parsers reports errors (%d)\n", - ret); - /* Don't abort on errors; we can still use unpartitioned MTD */ -- ret = 0; -+ memset(&parsed, 0, sizeof(parsed)); - } - -- ret = mtd_add_device_partitions(mtd, real_parts, ret); -+ ret = mtd_add_device_partitions(mtd, &parsed); - if (ret) - goto out; - -@@ -642,7 +647,8 @@ int mtd_device_parse_register(struct mtd - } - - out: -- kfree(real_parts); -+ /* Cleanup any parsed partitions */ -+ mtd_part_parser_cleanup(&parsed); - return ret; - } - EXPORT_SYMBOL_GPL(mtd_device_parse_register); -@@ -767,7 +773,6 @@ out: - } - EXPORT_SYMBOL_GPL(get_mtd_device); - -- - int __get_mtd_device(struct mtd_info *mtd) - { - int err; -@@ -1001,6 +1006,366 @@ int mtd_read_oob(struct mtd_info *mtd, l - } - EXPORT_SYMBOL_GPL(mtd_read_oob); - -+/** -+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section -+ * @mtd: MTD device structure -+ * @section: ECC section. Depending on the layout you may have all the ECC -+ * bytes stored in a single contiguous section, or one section -+ * per ECC chunk (and sometime several sections for a single ECC -+ * ECC chunk) -+ * @oobecc: OOB region struct filled with the appropriate ECC position -+ * information -+ * -+ * This functions return ECC section information in the OOB area. I you want -+ * to get all the ECC bytes information, then you should call -+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc) -+{ -+ memset(oobecc, 0, sizeof(*oobecc)); -+ -+ if (!mtd || section < 0) -+ return -EINVAL; -+ -+ if (!mtd->ooblayout || !mtd->ooblayout->ecc) -+ return -ENOTSUPP; -+ -+ return mtd->ooblayout->ecc(mtd, section, oobecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc); -+ -+/** -+ * mtd_ooblayout_free - Get the OOB region definition of a specific free -+ * section -+ * @mtd: MTD device structure -+ * @section: Free section you are interested in. Depending on the layout -+ * you may have all the free bytes stored in a single contiguous -+ * section, or one section per ECC chunk plus an extra section -+ * for the remaining bytes (or other funky layout). -+ * @oobfree: OOB region struct filled with the appropriate free position -+ * information -+ * -+ * This functions return free bytes position in the OOB area. I you want -+ * to get all the free bytes information, then you should call -+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree) -+{ -+ memset(oobfree, 0, sizeof(*oobfree)); -+ -+ if (!mtd || section < 0) -+ return -EINVAL; -+ -+ if (!mtd->ooblayout || !mtd->ooblayout->free) -+ return -ENOTSUPP; -+ -+ return mtd->ooblayout->free(mtd, section, oobfree); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_free); -+ -+/** -+ * mtd_ooblayout_find_region - Find the region attached to a specific byte -+ * @mtd: mtd info structure -+ * @byte: the byte we are searching for -+ * @sectionp: pointer where the section id will be stored -+ * @oobregion: used to retrieve the ECC position -+ * @iter: iterator function. Should be either mtd_ooblayout_free or -+ * mtd_ooblayout_ecc depending on the region type you're searching for -+ * -+ * This functions returns the section id and oobregion information of a -+ * specific byte. For example, say you want to know where the 4th ECC byte is -+ * stored, you'll use: -+ * -+ * mtd_ooblayout_find_region(mtd, 3, §ion, &oobregion, mtd_ooblayout_ecc); -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte, -+ int *sectionp, struct mtd_oob_region *oobregion, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ int pos = 0, ret, section = 0; -+ -+ memset(oobregion, 0, sizeof(*oobregion)); -+ -+ while (1) { -+ ret = iter(mtd, section, oobregion); -+ if (ret) -+ return ret; -+ -+ if (pos + oobregion->length > byte) -+ break; -+ -+ pos += oobregion->length; -+ section++; -+ } -+ -+ /* -+ * Adjust region info to make it start at the beginning at the -+ * 'start' ECC byte. -+ */ -+ oobregion->offset += byte - pos; -+ oobregion->length -= byte - pos; -+ *sectionp = section; -+ -+ return 0; -+} -+ -+/** -+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific -+ * ECC byte -+ * @mtd: mtd info structure -+ * @eccbyte: the byte we are searching for -+ * @sectionp: pointer where the section id will be stored -+ * @oobregion: OOB region information -+ * -+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC -+ * byte. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte, -+ int *section, -+ struct mtd_oob_region *oobregion) -+{ -+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion, -+ mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion); -+ -+/** -+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer -+ * @mtd: mtd info structure -+ * @buf: destination buffer to store OOB bytes -+ * @oobbuf: OOB buffer -+ * @start: first byte to retrieve -+ * @nbytes: number of bytes to retrieve -+ * @iter: section iterator -+ * -+ * Extract bytes attached to a specific category (ECC or free) -+ * from the OOB buffer and copy them into buf. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf, -+ const u8 *oobbuf, int start, int nbytes, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ struct mtd_oob_region oobregion = { }; -+ int section = 0, ret; -+ -+ ret = mtd_ooblayout_find_region(mtd, start, §ion, -+ &oobregion, iter); -+ -+ while (!ret) { -+ int cnt; -+ -+ cnt = oobregion.length > nbytes ? nbytes : oobregion.length; -+ memcpy(buf, oobbuf + oobregion.offset, cnt); -+ buf += cnt; -+ nbytes -= cnt; -+ -+ if (!nbytes) -+ break; -+ -+ ret = iter(mtd, ++section, &oobregion); -+ } -+ -+ return ret; -+} -+ -+/** -+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer -+ * @mtd: mtd info structure -+ * @buf: source buffer to get OOB bytes from -+ * @oobbuf: OOB buffer -+ * @start: first OOB byte to set -+ * @nbytes: number of OOB bytes to set -+ * @iter: section iterator -+ * -+ * Fill the OOB buffer with data provided in buf. The category (ECC or free) -+ * is selected by passing the appropriate iterator. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf, -+ u8 *oobbuf, int start, int nbytes, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ struct mtd_oob_region oobregion = { }; -+ int section = 0, ret; -+ -+ ret = mtd_ooblayout_find_region(mtd, start, §ion, -+ &oobregion, iter); -+ -+ while (!ret) { -+ int cnt; -+ -+ cnt = oobregion.length > nbytes ? nbytes : oobregion.length; -+ memcpy(oobbuf + oobregion.offset, buf, cnt); -+ buf += cnt; -+ nbytes -= cnt; -+ -+ if (!nbytes) -+ break; -+ -+ ret = iter(mtd, ++section, &oobregion); -+ } -+ -+ return ret; -+} -+ -+/** -+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category -+ * @mtd: mtd info structure -+ * @iter: category iterator -+ * -+ * Count the number of bytes in a given category. -+ * -+ * Returns a positive value on success, a negative error code otherwise. -+ */ -+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd, -+ int (*iter)(struct mtd_info *, -+ int section, -+ struct mtd_oob_region *oobregion)) -+{ -+ struct mtd_oob_region oobregion = { }; -+ int section = 0, ret, nbytes = 0; -+ -+ while (1) { -+ ret = iter(mtd, section++, &oobregion); -+ if (ret) { -+ if (ret == -ERANGE) -+ ret = nbytes; -+ break; -+ } -+ -+ nbytes += oobregion.length; -+ } -+ -+ return ret; -+} -+ -+/** -+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer -+ * @mtd: mtd info structure -+ * @eccbuf: destination buffer to store ECC bytes -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to retrieve -+ * @nbytes: number of ECC bytes to retrieve -+ * -+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf, -+ const u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes, -+ mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes); -+ -+/** -+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer -+ * @mtd: mtd info structure -+ * @eccbuf: source buffer to get ECC bytes from -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to set -+ * @nbytes: number of ECC bytes to set -+ * -+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf, -+ u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes, -+ mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes); -+ -+/** -+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer -+ * @mtd: mtd info structure -+ * @databuf: destination buffer to store ECC bytes -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to retrieve -+ * @nbytes: number of ECC bytes to retrieve -+ * -+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf, -+ const u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes, -+ mtd_ooblayout_free); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes); -+ -+/** -+ * mtd_ooblayout_get_eccbytes - set data bytes into the oob buffer -+ * @mtd: mtd info structure -+ * @eccbuf: source buffer to get data bytes from -+ * @oobbuf: OOB buffer -+ * @start: first ECC byte to set -+ * @nbytes: number of ECC bytes to set -+ * -+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf, -+ u8 *oobbuf, int start, int nbytes) -+{ -+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes, -+ mtd_ooblayout_free); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes); -+ -+/** -+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB -+ * @mtd: mtd info structure -+ * -+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd) -+{ -+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes); -+ -+/** -+ * mtd_ooblayout_count_freebytes - count the number of ECC bytes in OOB -+ * @mtd: mtd info structure -+ * -+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes. -+ * -+ * Returns zero on success, a negative error code otherwise. -+ */ -+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd) -+{ -+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc); -+} -+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes); -+ - /* - * Method to access the protection register area, present in some flash - * devices. The user data is one time programmable but the factory data is read ---- a/drivers/mtd/mtdcore.h -+++ b/drivers/mtd/mtdcore.h -@@ -10,10 +10,15 @@ int add_mtd_device(struct mtd_info *mtd) - int del_mtd_device(struct mtd_info *mtd); - int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); - int del_mtd_partitions(struct mtd_info *); -+ -+struct mtd_partitions; -+ - int parse_mtd_partitions(struct mtd_info *master, const char * const *types, -- struct mtd_partition **pparts, -+ struct mtd_partitions *pparts, - struct mtd_part_parser_data *data); - -+void mtd_part_parser_cleanup(struct mtd_partitions *parts); -+ - int __init init_mtdchar(void); - void __exit cleanup_mtdchar(void); - ---- a/drivers/mtd/mtdpart.c -+++ b/drivers/mtd/mtdpart.c -@@ -55,9 +55,12 @@ static void mtd_partition_split(struct m - - /* - * Given a pointer to the MTD object in the mtd_part structure, we can retrieve -- * the pointer to that structure with this macro. -+ * the pointer to that structure. - */ --#define PART(x) ((struct mtd_part *)(x)) -+static inline struct mtd_part *mtd_to_part(const struct mtd_info *mtd) -+{ -+ return container_of(mtd, struct mtd_part, mtd); -+} - - - /* -@@ -68,7 +71,7 @@ static void mtd_partition_split(struct m - static int part_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - struct mtd_ecc_stats stats; - int res; - -@@ -87,7 +90,7 @@ static int part_read(struct mtd_info *mt - static int part_point(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, void **virt, resource_size_t *phys) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - return part->master->_point(part->master, from + part->offset, len, - retlen, virt, phys); -@@ -95,7 +98,7 @@ static int part_point(struct mtd_info *m - - static int part_unpoint(struct mtd_info *mtd, loff_t from, size_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - return part->master->_unpoint(part->master, from + part->offset, len); - } -@@ -105,7 +108,7 @@ static unsigned long part_get_unmapped_a - unsigned long offset, - unsigned long flags) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - offset += part->offset; - return part->master->_get_unmapped_area(part->master, len, offset, -@@ -115,7 +118,7 @@ static unsigned long part_get_unmapped_a - static int part_read_oob(struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - int res; - - if (from >= mtd->size) -@@ -130,10 +133,7 @@ static int part_read_oob(struct mtd_info - if (ops->oobbuf) { - size_t len, pages; - -- if (ops->mode == MTD_OPS_AUTO_OOB) -- len = mtd->oobavail; -- else -- len = mtd->oobsize; -+ len = mtd_oobavail(mtd, ops); - pages = mtd_div_by_ws(mtd->size, mtd); - pages -= mtd_div_by_ws(from, mtd); - if (ops->ooboffs + ops->ooblen > pages * len) -@@ -153,7 +153,7 @@ static int part_read_oob(struct mtd_info - static int part_read_user_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_read_user_prot_reg(part->master, from, len, - retlen, buf); - } -@@ -161,7 +161,7 @@ static int part_read_user_prot_reg(struc - static int part_get_user_prot_info(struct mtd_info *mtd, size_t len, - size_t *retlen, struct otp_info *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_get_user_prot_info(part->master, len, retlen, - buf); - } -@@ -169,7 +169,7 @@ static int part_get_user_prot_info(struc - static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_read_fact_prot_reg(part->master, from, len, - retlen, buf); - } -@@ -177,7 +177,7 @@ static int part_read_fact_prot_reg(struc - static int part_get_fact_prot_info(struct mtd_info *mtd, size_t len, - size_t *retlen, struct otp_info *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_get_fact_prot_info(part->master, len, retlen, - buf); - } -@@ -185,7 +185,7 @@ static int part_get_fact_prot_info(struc - static int part_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_write(part->master, to + part->offset, len, - retlen, buf); - } -@@ -193,7 +193,7 @@ static int part_write(struct mtd_info *m - static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_panic_write(part->master, to + part->offset, len, - retlen, buf); - } -@@ -201,7 +201,7 @@ static int part_panic_write(struct mtd_i - static int part_write_oob(struct mtd_info *mtd, loff_t to, - struct mtd_oob_ops *ops) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - if (to >= mtd->size) - return -EINVAL; -@@ -213,7 +213,7 @@ static int part_write_oob(struct mtd_inf - static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len, size_t *retlen, u_char *buf) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_write_user_prot_reg(part->master, from, len, - retlen, buf); - } -@@ -221,21 +221,21 @@ static int part_write_user_prot_reg(stru - static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, - size_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_lock_user_prot_reg(part->master, from, len); - } - - static int part_writev(struct mtd_info *mtd, const struct kvec *vecs, - unsigned long count, loff_t to, size_t *retlen) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_writev(part->master, vecs, count, - to + part->offset, retlen); - } - - static int part_erase(struct mtd_info *mtd, struct erase_info *instr) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - int ret; - - -@@ -299,7 +299,7 @@ static int part_erase(struct mtd_info *m - void mtd_erase_callback(struct erase_info *instr) - { - if (instr->mtd->_erase == part_erase) { -- struct mtd_part *part = PART(instr->mtd); -+ struct mtd_part *part = mtd_to_part(instr->mtd); - size_t wrlen = 0; - - if (instr->mtd->flags & MTD_ERASE_PARTIAL) { -@@ -330,13 +330,13 @@ EXPORT_SYMBOL_GPL(mtd_erase_callback); - - static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_lock(part->master, ofs + part->offset, len); - } - - static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - - ofs += part->offset; - if (mtd->flags & MTD_ERASE_PARTIAL) { -@@ -349,45 +349,45 @@ static int part_unlock(struct mtd_info * - - static int part_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_is_locked(part->master, ofs + part->offset, len); - } - - static void part_sync(struct mtd_info *mtd) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - part->master->_sync(part->master); - } - - static int part_suspend(struct mtd_info *mtd) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return part->master->_suspend(part->master); - } - - static void part_resume(struct mtd_info *mtd) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - part->master->_resume(part->master); - } - - static int part_block_isreserved(struct mtd_info *mtd, loff_t ofs) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - ofs += part->offset; - return part->master->_block_isreserved(part->master, ofs); - } - - static int part_block_isbad(struct mtd_info *mtd, loff_t ofs) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - ofs += part->offset; - return part->master->_block_isbad(part->master, ofs); - } - - static int part_block_markbad(struct mtd_info *mtd, loff_t ofs) - { -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - int res; - - ofs += part->offset; -@@ -397,6 +397,27 @@ static int part_block_markbad(struct mtd - return res; - } - -+static int part_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct mtd_part *part = mtd_to_part(mtd); -+ -+ return mtd_ooblayout_ecc(part->master, section, oobregion); -+} -+ -+static int part_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct mtd_part *part = mtd_to_part(mtd); -+ -+ return mtd_ooblayout_free(part->master, section, oobregion); -+} -+ -+static const struct mtd_ooblayout_ops part_ooblayout_ops = { -+ .ecc = part_ooblayout_ecc, -+ .free = part_ooblayout_free, -+}; -+ - static inline void free_partition(struct mtd_part *p) - { - kfree(p->mtd.name); -@@ -614,7 +635,7 @@ static struct mtd_part *allocate_partiti - slave->mtd.erasesize = slave->mtd.size; - } - -- slave->mtd.ecclayout = master->ecclayout; -+ mtd_set_ooblayout(&slave->mtd, &part_ooblayout_ops); - slave->mtd.ecc_step_size = master->ecc_step_size; - slave->mtd.ecc_strength = master->ecc_strength; - slave->mtd.bitflip_threshold = master->bitflip_threshold; -@@ -639,7 +660,7 @@ static ssize_t mtd_partition_offset_show - struct device_attribute *attr, char *buf) - { - struct mtd_info *mtd = dev_get_drvdata(dev); -- struct mtd_part *part = PART(mtd); -+ struct mtd_part *part = mtd_to_part(mtd); - return snprintf(buf, PAGE_SIZE, "%lld\n", part->offset); - } - -@@ -677,11 +698,10 @@ int mtd_add_partition(struct mtd_info *m - if (length <= 0) - return -EINVAL; - -+ memset(&part, 0, sizeof(part)); - part.name = name; - part.size = length; - part.offset = offset; -- part.mask_flags = 0; -- part.ecclayout = NULL; - - new = allocate_partition(master, &part, -1, offset); - if (IS_ERR(new)) -@@ -845,7 +865,7 @@ int add_mtd_partitions(struct mtd_info * - static DEFINE_SPINLOCK(part_parser_lock); - static LIST_HEAD(part_parsers); - --static struct mtd_part_parser *get_partition_parser(const char *name) -+static struct mtd_part_parser *mtd_part_parser_get(const char *name) - { - struct mtd_part_parser *p, *ret = NULL; - -@@ -862,7 +882,20 @@ static struct mtd_part_parser *get_parti - return ret; - } - --#define put_partition_parser(p) do { module_put((p)->owner); } while (0) -+static inline void mtd_part_parser_put(const struct mtd_part_parser *p) -+{ -+ module_put(p->owner); -+} -+ -+/* -+ * Many partition parsers just expected the core to kfree() all their data in -+ * one chunk. Do that by default. -+ */ -+static void mtd_part_parser_cleanup_default(const struct mtd_partition *pparts, -+ int nr_parts) -+{ -+ kfree(pparts); -+} - - static struct mtd_part_parser * - get_partition_parser_by_type(enum mtd_parser_type type, -@@ -874,7 +907,7 @@ get_partition_parser_by_type(enum mtd_pa - - p = list_prepare_entry(start, &part_parsers, list); - if (start) -- put_partition_parser(start); -+ mtd_part_parser_put(start); - - list_for_each_entry_continue(p, &part_parsers, list) { - if (p->type == type && try_module_get(p->owner)) { -@@ -888,13 +921,19 @@ get_partition_parser_by_type(enum mtd_pa - return ret; - } - --void register_mtd_parser(struct mtd_part_parser *p) --{ -+int __register_mtd_parser(struct mtd_part_parser *p, struct module *owner) -+ { -+ p->owner = owner; -+ -+ if (!p->cleanup) -+ p->cleanup = &mtd_part_parser_cleanup_default; -+ - spin_lock(&part_parser_lock); - list_add(&p->list, &part_parsers); - spin_unlock(&part_parser_lock); -+ return 0; - } --EXPORT_SYMBOL_GPL(register_mtd_parser); -+EXPORT_SYMBOL_GPL(__register_mtd_parser); - - void deregister_mtd_parser(struct mtd_part_parser *p) - { -@@ -954,7 +993,7 @@ static const char * const default_mtd_pa - * parse_mtd_partitions - parse MTD partitions - * @master: the master partition (describes whole MTD device) - * @types: names of partition parsers to try or %NULL -- * @pparts: array of partitions found is returned here -+ * @pparts: info about partitions found is returned here - * @data: MTD partition parser-specific data - * - * This function tries to find partition on MTD device @master. It uses MTD -@@ -966,45 +1005,42 @@ static const char * const default_mtd_pa - * - * This function may return: - * o a negative error code in case of failure -- * o zero if no partitions were found -- * o a positive number of found partitions, in which case on exit @pparts will -- * point to an array containing this number of &struct mtd_info objects. -+ * o zero otherwise, and @pparts will describe the partitions, number of -+ * partitions, and the parser which parsed them. Caller must release -+ * resources with mtd_part_parser_cleanup() when finished with the returned -+ * data. - */ - int parse_mtd_partitions(struct mtd_info *master, const char *const *types, -- struct mtd_partition **pparts, -+ struct mtd_partitions *pparts, - struct mtd_part_parser_data *data) - { - struct mtd_part_parser *parser; - int ret, err = 0; - const char *const *types_of = NULL; - -- if (data && data->of_node) { -- types_of = of_get_probes(data->of_node); -- if (types_of != NULL) -- types = types_of; -- } -- - if (!types) - types = default_mtd_part_types; - - for ( ; *types; types++) { - pr_debug("%s: parsing partitions %s\n", master->name, *types); -- parser = get_partition_parser(*types); -+ parser = mtd_part_parser_get(*types); - if (!parser && !request_module("%s", *types)) -- parser = get_partition_parser(*types); -+ parser = mtd_part_parser_get(*types); - pr_debug("%s: got parser %s\n", master->name, - parser ? parser->name : NULL); - if (!parser) - continue; -- ret = (*parser->parse_fn)(master, pparts, data); -+ ret = (*parser->parse_fn)(master, &pparts->parts, data); - pr_debug("%s: parser %s: %i\n", - master->name, parser->name, ret); -- put_partition_parser(parser); - if (ret > 0) { - printk(KERN_NOTICE "%d %s partitions found on MTD device %s\n", - ret, parser->name, master->name); -- return ret; -+ pparts->nr_parts = ret; -+ pparts->parser = parser; -+ return 0; - } -+ mtd_part_parser_put(parser); - /* - * Stash the first error we see; only report it if no parser - * succeeds -@@ -1034,7 +1070,7 @@ int parse_mtd_partitions_by_type(struct - ret = (*parser->parse_fn)(master, pparts, data); - - if (ret > 0) { -- put_partition_parser(parser); -+ mtd_part_parser_put(parser); - printk(KERN_NOTICE - "%d %s partitions found on MTD device %s\n", - ret, parser->name, master->name); -@@ -1048,6 +1084,22 @@ int parse_mtd_partitions_by_type(struct - } - EXPORT_SYMBOL_GPL(parse_mtd_partitions_by_type); - -+void mtd_part_parser_cleanup(struct mtd_partitions *parts) -+{ -+ const struct mtd_part_parser *parser; -+ -+ if (!parts) -+ return; -+ -+ parser = parts->parser; -+ if (parser) { -+ if (parser->cleanup) -+ parser->cleanup(parts->parts, parts->nr_parts); -+ -+ mtd_part_parser_put(parser); -+ } -+} -+ - int mtd_is_partition(const struct mtd_info *mtd) - { - struct mtd_part *part; -@@ -1070,7 +1122,7 @@ struct mtd_info *mtdpart_get_master(cons - if (!mtd_is_partition(mtd)) - return (struct mtd_info *)mtd; - -- return PART(mtd)->master; -+ return mtd_to_part(mtd)->master; - } - EXPORT_SYMBOL_GPL(mtdpart_get_master); - -@@ -1079,7 +1131,7 @@ uint64_t mtdpart_get_offset(const struct - if (!mtd_is_partition(mtd)) - return 0; - -- return PART(mtd)->offset; -+ return mtd_to_part(mtd)->offset; - } - EXPORT_SYMBOL_GPL(mtdpart_get_offset); - -@@ -1089,6 +1141,6 @@ uint64_t mtd_get_device_size(const struc - if (!mtd_is_partition(mtd)) - return mtd->size; - -- return PART(mtd)->master->size; -+ return mtd_to_part(mtd)->master->size; - } - EXPORT_SYMBOL_GPL(mtd_get_device_size); ---- a/drivers/mtd/mtdswap.c -+++ b/drivers/mtd/mtdswap.c -@@ -346,7 +346,7 @@ static int mtdswap_read_markers(struct m - if (mtd_can_have_bb(d->mtd) && mtd_block_isbad(d->mtd, offset)) - return MTDSWAP_SCANNED_BAD; - -- ops.ooblen = 2 * d->mtd->ecclayout->oobavail; -+ ops.ooblen = 2 * d->mtd->oobavail; - ops.oobbuf = d->oob_buf; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -359,7 +359,7 @@ static int mtdswap_read_markers(struct m - - data = (struct mtdswap_oobdata *)d->oob_buf; - data2 = (struct mtdswap_oobdata *) -- (d->oob_buf + d->mtd->ecclayout->oobavail); -+ (d->oob_buf + d->mtd->oobavail); - - if (le16_to_cpu(data->magic) == MTDSWAP_MAGIC_CLEAN) { - eb->erase_count = le32_to_cpu(data->count); -@@ -933,7 +933,7 @@ static unsigned int mtdswap_eblk_passes( - - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = mtd->writesize; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.ooboffs = 0; - ops.datbuf = d->page_buf; - ops.oobbuf = d->oob_buf; -@@ -945,7 +945,7 @@ static unsigned int mtdswap_eblk_passes( - for (i = 0; i < mtd_pages; i++) { - patt = mtdswap_test_patt(test + i); - memset(d->page_buf, patt, mtd->writesize); -- memset(d->oob_buf, patt, mtd->ecclayout->oobavail); -+ memset(d->oob_buf, patt, mtd->oobavail); - ret = mtd_write_oob(mtd, pos, &ops); - if (ret) - goto error; -@@ -964,7 +964,7 @@ static unsigned int mtdswap_eblk_passes( - if (p1[j] != patt) - goto error; - -- for (j = 0; j < mtd->ecclayout->oobavail; j++) -+ for (j = 0; j < mtd->oobavail; j++) - if (p2[j] != (unsigned char)patt) - goto error; - -@@ -1387,7 +1387,7 @@ static int mtdswap_init(struct mtdswap_d - if (!d->page_buf) - goto page_buf_fail; - -- d->oob_buf = kmalloc(2 * mtd->ecclayout->oobavail, GFP_KERNEL); -+ d->oob_buf = kmalloc(2 * mtd->oobavail, GFP_KERNEL); - if (!d->oob_buf) - goto oob_buf_fail; - -@@ -1417,7 +1417,6 @@ static void mtdswap_add_mtd(struct mtd_b - unsigned long part; - unsigned int eblocks, eavailable, bad_blocks, spare_cnt; - uint64_t swap_size, use_size, size_limit; -- struct nand_ecclayout *oinfo; - int ret; - - parts = &partitions[0]; -@@ -1447,17 +1446,10 @@ static void mtdswap_add_mtd(struct mtd_b - return; - } - -- oinfo = mtd->ecclayout; -- if (!oinfo) { -- printk(KERN_ERR "%s: mtd%d does not have OOB\n", -- MTDSWAP_PREFIX, mtd->index); -- return; -- } -- -- if (!mtd->oobsize || oinfo->oobavail < MTDSWAP_OOBSIZE) { -+ if (!mtd->oobsize || mtd->oobavail < MTDSWAP_OOBSIZE) { - printk(KERN_ERR "%s: Not enough free bytes in OOB, " - "%d available, %zu needed.\n", -- MTDSWAP_PREFIX, oinfo->oobavail, MTDSWAP_OOBSIZE); -+ MTDSWAP_PREFIX, mtd->oobavail, MTDSWAP_OOBSIZE); - return; - } - ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -55,7 +55,7 @@ config MTD_NAND_DENALI_PCI - config MTD_NAND_DENALI_DT - tristate "Support Denali NAND controller as a DT device" - select MTD_NAND_DENALI -- depends on HAS_DMA && HAVE_CLK -+ depends on HAS_DMA && HAVE_CLK && OF - help - Enable the driver for NAND flash on platforms using a Denali NAND - controller as a DT device. -@@ -74,6 +74,7 @@ config MTD_NAND_DENALI_SCRATCH_REG_ADDR - config MTD_NAND_GPIO - tristate "GPIO assisted NAND Flash driver" - depends on GPIOLIB || COMPILE_TEST -+ depends on HAS_IOMEM - help - This enables a NAND flash driver where control signals are - connected to GPIO pins, and commands and data are communicated -@@ -310,6 +311,7 @@ config MTD_NAND_CAFE - config MTD_NAND_CS553X - tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)" - depends on X86_32 -+ depends on !UML && HAS_IOMEM - help - The CS553x companion chips for the AMD Geode processor - include NAND flash controllers with built-in hardware ECC -@@ -463,6 +465,7 @@ config MTD_NAND_MPC5121_NFC - config MTD_NAND_VF610_NFC - tristate "Support for Freescale NFC for VF610/MPC5125" - depends on (SOC_VF610 || COMPILE_TEST) -+ depends on HAS_IOMEM - help - Enables support for NAND Flash Controller on some Freescale - processors like the VF610, MPC5125, MCF54418 or Kinetis K70. -@@ -480,7 +483,7 @@ config MTD_NAND_MXC - - config MTD_NAND_SH_FLCTL - tristate "Support for NAND on Renesas SuperH FLCTL" -- depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST -+ depends on SUPERH || COMPILE_TEST - depends on HAS_IOMEM - depends on HAS_DMA - help -@@ -519,6 +522,13 @@ config MTD_NAND_JZ4740 - help - Enables support for NAND Flash on JZ4740 SoC based boards. - -+config MTD_NAND_JZ4780 -+ tristate "Support for NAND on JZ4780 SoC" -+ depends on MACH_JZ4780 && JZ4780_NEMC -+ help -+ Enables support for NAND Flash connected to the NEMC on JZ4780 SoC -+ based boards, using the BCH controller for hardware error correction. -+ - config MTD_NAND_FSMC - tristate "Support for NAND on ST Micros FSMC" - depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300 -@@ -546,4 +556,11 @@ config MTD_NAND_HISI504 - help - Enables support for NAND controller on Hisilicon SoC Hip04. - -+config MTD_NAND_QCOM -+ tristate "Support for NAND on QCOM SoCs" -+ depends on ARCH_QCOM -+ help -+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND -+ controller. This controller is found on IPQ806x SoC. -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -49,11 +49,13 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mp - obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o - obj-$(CONFIG_MTD_NAND_RICOH) += r852.o - obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o -+obj-$(CONFIG_MTD_NAND_JZ4780) += jz4780_nand.o jz4780_bch.o - obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ - obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o - obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/ - obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o - obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o - obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ -+obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o - - nand-objs := nand_base.o nand_bbt.o nand_timings.o ---- a/drivers/mtd/nand/nand_base.c -+++ b/drivers/mtd/nand/nand_base.c -@@ -48,50 +48,6 @@ - #include - #include - --/* Define default oob placement schemes for large and small page devices */ --static struct nand_ecclayout nand_oob_8 = { -- .eccbytes = 3, -- .eccpos = {0, 1, 2}, -- .oobfree = { -- {.offset = 3, -- .length = 2}, -- {.offset = 6, -- .length = 2} } --}; -- --static struct nand_ecclayout nand_oob_16 = { -- .eccbytes = 6, -- .eccpos = {0, 1, 2, 3, 6, 7}, -- .oobfree = { -- {.offset = 8, -- . length = 8} } --}; -- --static struct nand_ecclayout nand_oob_64 = { -- .eccbytes = 24, -- .eccpos = { -- 40, 41, 42, 43, 44, 45, 46, 47, -- 48, 49, 50, 51, 52, 53, 54, 55, -- 56, 57, 58, 59, 60, 61, 62, 63}, -- .oobfree = { -- {.offset = 2, -- .length = 38} } --}; -- --static struct nand_ecclayout nand_oob_128 = { -- .eccbytes = 48, -- .eccpos = { -- 80, 81, 82, 83, 84, 85, 86, 87, -- 88, 89, 90, 91, 92, 93, 94, 95, -- 96, 97, 98, 99, 100, 101, 102, 103, -- 104, 105, 106, 107, 108, 109, 110, 111, -- 112, 113, 114, 115, 116, 117, 118, 119, -- 120, 121, 122, 123, 124, 125, 126, 127}, -- .oobfree = { -- {.offset = 2, -- .length = 78} } --}; -- - static int nand_get_device(struct mtd_info *mtd, int new_state); - - static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, -@@ -103,10 +59,96 @@ static int nand_do_write_oob(struct mtd_ - */ - DEFINE_LED_TRIGGER(nand_led_trigger); - -+/* Define default oob placement schemes for large and small page devices */ -+static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nand_ecc_ctrl *ecc = &chip->ecc; -+ -+ if (section > 1) -+ return -ERANGE; -+ -+ if (!section) { -+ oobregion->offset = 0; -+ oobregion->length = 4; -+ } else { -+ oobregion->offset = 6; -+ oobregion->length = ecc->total - 4; -+ } -+ -+ return 0; -+} -+ -+static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ if (section > 1) -+ return -ERANGE; -+ -+ if (mtd->oobsize == 16) { -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = 8; -+ oobregion->offset = 8; -+ } else { -+ oobregion->length = 2; -+ if (!section) -+ oobregion->offset = 3; -+ else -+ oobregion->offset = 6; -+ } -+ -+ return 0; -+} -+ -+const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { -+ .ecc = nand_ooblayout_ecc_sp, -+ .free = nand_ooblayout_free_sp, -+}; -+EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); -+ -+static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nand_ecc_ctrl *ecc = &chip->ecc; -+ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = ecc->total; -+ oobregion->offset = mtd->oobsize - oobregion->length; -+ -+ return 0; -+} -+ -+static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobregion) -+{ -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nand_ecc_ctrl *ecc = &chip->ecc; -+ -+ if (section) -+ return -ERANGE; -+ -+ oobregion->length = mtd->oobsize - ecc->total - 2; -+ oobregion->offset = 2; -+ -+ return 0; -+} -+ -+const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { -+ .ecc = nand_ooblayout_ecc_lp, -+ .free = nand_ooblayout_free_lp, -+}; -+EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); -+ - static int check_offs_len(struct mtd_info *mtd, - loff_t ofs, uint64_t len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int ret = 0; - - /* Start address must align on block boundary */ -@@ -132,7 +174,7 @@ static int check_offs_len(struct mtd_inf - */ - static void nand_release_device(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - /* Release the controller and the chip */ - spin_lock(&chip->controller->lock); -@@ -150,7 +192,7 @@ static void nand_release_device(struct m - */ - static uint8_t nand_read_byte(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - return readb(chip->IO_ADDR_R); - } - -@@ -163,7 +205,7 @@ static uint8_t nand_read_byte(struct mtd - */ - static uint8_t nand_read_byte16(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); - } - -@@ -175,7 +217,7 @@ static uint8_t nand_read_byte16(struct m - */ - static u16 nand_read_word(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - return readw(chip->IO_ADDR_R); - } - -@@ -188,7 +230,7 @@ static u16 nand_read_word(struct mtd_inf - */ - static void nand_select_chip(struct mtd_info *mtd, int chipnr) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - switch (chipnr) { - case -1: -@@ -211,7 +253,7 @@ static void nand_select_chip(struct mtd_ - */ - static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - chip->write_buf(mtd, &byte, 1); - } -@@ -225,7 +267,7 @@ static void nand_write_byte(struct mtd_i - */ - static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - uint16_t word = byte; - - /* -@@ -257,7 +299,7 @@ static void nand_write_byte16(struct mtd - */ - static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - iowrite8_rep(chip->IO_ADDR_W, buf, len); - } -@@ -272,7 +314,7 @@ static void nand_write_buf(struct mtd_in - */ - static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - ioread8_rep(chip->IO_ADDR_R, buf, len); - } -@@ -287,7 +329,7 @@ static void nand_read_buf(struct mtd_inf - */ - static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - u16 *p = (u16 *) buf; - - iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); -@@ -303,7 +345,7 @@ static void nand_write_buf16(struct mtd_ - */ - static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - u16 *p = (u16 *) buf; - - ioread16_rep(chip->IO_ADDR_R, p, len >> 1); -@@ -313,14 +355,13 @@ static void nand_read_buf16(struct mtd_i - * nand_block_bad - [DEFAULT] Read bad block marker from the chip - * @mtd: MTD device structure - * @ofs: offset from device start -- * @getchip: 0, if the chip is already selected - * - * Check, if the block is bad. - */ --static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) -+static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) - { -- int page, chipnr, res = 0, i = 0; -- struct nand_chip *chip = mtd->priv; -+ int page, res = 0, i = 0; -+ struct nand_chip *chip = mtd_to_nand(mtd); - u16 bad; - - if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) -@@ -328,15 +369,6 @@ static int nand_block_bad(struct mtd_inf - - page = (int)(ofs >> chip->page_shift) & chip->pagemask; - -- if (getchip) { -- chipnr = (int)(ofs >> chip->chip_shift); -- -- nand_get_device(mtd, FL_READING); -- -- /* Select the NAND device */ -- chip->select_chip(mtd, chipnr); -- } -- - do { - if (chip->options & NAND_BUSWIDTH_16) { - chip->cmdfunc(mtd, NAND_CMD_READOOB, -@@ -361,11 +393,6 @@ static int nand_block_bad(struct mtd_inf - i++; - } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); - -- if (getchip) { -- chip->select_chip(mtd, -1); -- nand_release_device(mtd); -- } -- - return res; - } - -@@ -380,7 +407,7 @@ static int nand_block_bad(struct mtd_inf - */ - static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct mtd_oob_ops ops; - uint8_t buf[2] = { 0, 0 }; - int ret = 0, res, i = 0; -@@ -430,7 +457,7 @@ static int nand_default_block_markbad(st - */ - static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int res, ret = 0; - - if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { -@@ -471,7 +498,7 @@ static int nand_block_markbad_lowlevel(s - */ - static int nand_check_wp(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - /* Broken xD cards report WP despite being writable */ - if (chip->options & NAND_BROKEN_XD) -@@ -491,7 +518,7 @@ static int nand_check_wp(struct mtd_info - */ - static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (!chip->bbt) - return 0; -@@ -503,19 +530,17 @@ static int nand_block_isreserved(struct - * nand_block_checkbad - [GENERIC] Check if a block is marked bad - * @mtd: MTD device structure - * @ofs: offset from device start -- * @getchip: 0, if the chip is already selected - * @allowbbt: 1, if its allowed to access the bbt area - * - * Check, if the block is bad. Either by reading the bad block table or - * calling of the scan function. - */ --static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, -- int allowbbt) -+static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (!chip->bbt) -- return chip->block_bad(mtd, ofs, getchip); -+ return chip->block_bad(mtd, ofs); - - /* Return info from the table */ - return nand_isbad_bbt(mtd, ofs, allowbbt); -@@ -531,7 +556,7 @@ static int nand_block_checkbad(struct mt - */ - static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int i; - - /* Wait for the device to get ready */ -@@ -551,7 +576,7 @@ static void panic_nand_wait_ready(struct - */ - void nand_wait_ready(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - unsigned long timeo = 400; - - if (in_interrupt() || oops_in_progress) -@@ -566,8 +591,8 @@ void nand_wait_ready(struct mtd_info *mt - cond_resched(); - } while (time_before(jiffies, timeo)); - -- pr_warn_ratelimited( -- "timeout while waiting for chip to become ready\n"); -+ if (!chip->dev_ready(mtd)) -+ pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); - out: - led_trigger_event(nand_led_trigger, LED_OFF); - } -@@ -582,7 +607,7 @@ EXPORT_SYMBOL_GPL(nand_wait_ready); - */ - static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) - { -- register struct nand_chip *chip = mtd->priv; -+ register struct nand_chip *chip = mtd_to_nand(mtd); - - timeo = jiffies + msecs_to_jiffies(timeo); - do { -@@ -605,7 +630,7 @@ static void nand_wait_status_ready(struc - static void nand_command(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) - { -- register struct nand_chip *chip = mtd->priv; -+ register struct nand_chip *chip = mtd_to_nand(mtd); - int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; - - /* Write out the command to the device */ -@@ -708,7 +733,7 @@ static void nand_command(struct mtd_info - static void nand_command_lp(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) - { -- register struct nand_chip *chip = mtd->priv; -+ register struct nand_chip *chip = mtd_to_nand(mtd); - - /* Emulate NAND_CMD_READOOB */ - if (command == NAND_CMD_READOOB) { -@@ -832,7 +857,7 @@ static void panic_nand_get_device(struct - static int - nand_get_device(struct mtd_info *mtd, int new_state) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - spinlock_t *lock = &chip->controller->lock; - wait_queue_head_t *wq = &chip->controller->wq; - DECLARE_WAITQUEUE(wait, current); -@@ -952,7 +977,7 @@ static int __nand_unlock(struct mtd_info - { - int ret = 0; - int status, page; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - /* Submit address of first page to unlock */ - page = ofs >> chip->page_shift; -@@ -987,7 +1012,7 @@ int nand_unlock(struct mtd_info *mtd, lo - { - int ret = 0; - int chipnr; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("%s: start = 0x%012llx, len = %llu\n", - __func__, (unsigned long long)ofs, len); -@@ -1050,7 +1075,7 @@ int nand_lock(struct mtd_info *mtd, loff - { - int ret = 0; - int chipnr, status, page; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("%s: start = 0x%012llx, len = %llu\n", - __func__, (unsigned long long)ofs, len); -@@ -1309,13 +1334,12 @@ static int nand_read_page_raw_syndrome(s - static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - unsigned int max_bitflips = 0; - - chip->ecc.read_page_raw(mtd, chip, buf, 1, page); -@@ -1323,8 +1347,10 @@ static int nand_read_page_swecc(struct m - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - -- for (i = 0; i < chip->ecc.total; i++) -- ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - eccsteps = chip->ecc.steps; - p = buf; -@@ -1356,14 +1382,14 @@ static int nand_read_subpage(struct mtd_ - uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, - int page) - { -- int start_step, end_step, num_steps; -- uint32_t *eccpos = chip->ecc.layout->eccpos; -+ int start_step, end_step, num_steps, ret; - uint8_t *p; - int data_col_addr, i, gaps = 0; - int datafrag_len, eccfrag_len, aligned_len, aligned_pos; - int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; -- int index; -+ int index, section = 0; - unsigned int max_bitflips = 0; -+ struct mtd_oob_region oobregion = { }; - - /* Column address within the page aligned to ECC size (256bytes) */ - start_step = data_offs / chip->ecc.size; -@@ -1391,12 +1417,13 @@ static int nand_read_subpage(struct mtd_ - * The performance is faster if we position offsets according to - * ecc.pos. Let's make sure that there are no gaps in ECC positions. - */ -- for (i = 0; i < eccfrag_len - 1; i++) { -- if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { -- gaps = 1; -- break; -- } -- } -+ ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); -+ if (ret) -+ return ret; -+ -+ if (oobregion.length < eccfrag_len) -+ gaps = 1; -+ - if (gaps) { - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); -@@ -1405,20 +1432,23 @@ static int nand_read_subpage(struct mtd_ - * Send the command to read the particular ECC bytes take care - * about buswidth alignment in read_buf. - */ -- aligned_pos = eccpos[index] & ~(busw - 1); -+ aligned_pos = oobregion.offset & ~(busw - 1); - aligned_len = eccfrag_len; -- if (eccpos[index] & (busw - 1)) -+ if (oobregion.offset & (busw - 1)) - aligned_len++; -- if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) -+ if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & -+ (busw - 1)) - aligned_len++; - - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, -- mtd->writesize + aligned_pos, -1); -+ mtd->writesize + aligned_pos, -1); - chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); - } - -- for (i = 0; i < eccfrag_len; i++) -- chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode, -+ chip->oob_poi, index, eccfrag_len); -+ if (ret) -+ return ret; - - p = bufpoi + data_col_addr; - for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { -@@ -1426,6 +1456,16 @@ static int nand_read_subpage(struct mtd_ - - stat = chip->ecc.correct(mtd, p, - &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, -+ &chip->buffers->ecccode[i], -+ chip->ecc.bytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { -@@ -1449,13 +1489,12 @@ static int nand_read_subpage(struct mtd_ - static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - unsigned int max_bitflips = 0; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { -@@ -1465,8 +1504,10 @@ static int nand_read_page_hwecc(struct m - } - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - -- for (i = 0; i < chip->ecc.total; i++) -- ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - eccsteps = chip->ecc.steps; - p = buf; -@@ -1475,6 +1516,15 @@ static int nand_read_page_hwecc(struct m - int stat; - - stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, eccsize, -+ &ecc_code[i], eccbytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { -@@ -1502,12 +1552,11 @@ static int nand_read_page_hwecc(struct m - static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, - struct nand_chip *chip, uint8_t *buf, int oob_required, int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_code = chip->buffers->ecccode; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - uint8_t *ecc_calc = chip->buffers->ecccalc; - unsigned int max_bitflips = 0; - -@@ -1516,8 +1565,10 @@ static int nand_read_page_hwecc_oob_firs - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); - -- for (i = 0; i < chip->ecc.total; i++) -- ecc_code[i] = chip->oob_poi[eccpos[i]]; -+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - int stat; -@@ -1527,6 +1578,15 @@ static int nand_read_page_hwecc_oob_firs - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - - stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, eccsize, -+ &ecc_code[i], eccbytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ - if (stat < 0) { - mtd->ecc_stats.failed++; - } else { -@@ -1554,6 +1614,7 @@ static int nand_read_page_syndrome(struc - int i, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; -+ int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; - uint8_t *p = buf; - uint8_t *oob = chip->oob_poi; - unsigned int max_bitflips = 0; -@@ -1573,19 +1634,29 @@ static int nand_read_page_syndrome(struc - chip->read_buf(mtd, oob, eccbytes); - stat = chip->ecc.correct(mtd, p, oob, NULL); - -- if (stat < 0) { -- mtd->ecc_stats.failed++; -- } else { -- mtd->ecc_stats.corrected += stat; -- max_bitflips = max_t(unsigned int, max_bitflips, stat); -- } -- - oob += eccbytes; - - if (chip->ecc.postpad) { - chip->read_buf(mtd, oob, chip->ecc.postpad); - oob += chip->ecc.postpad; - } -+ -+ if (stat == -EBADMSG && -+ (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { -+ /* check for empty pages with bitflips */ -+ stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, -+ oob - eccpadbytes, -+ eccpadbytes, -+ NULL, 0, -+ chip->ecc.strength); -+ } -+ -+ if (stat < 0) { -+ mtd->ecc_stats.failed++; -+ } else { -+ mtd->ecc_stats.corrected += stat; -+ max_bitflips = max_t(unsigned int, max_bitflips, stat); -+ } - } - - /* Calculate remaining oob bytes */ -@@ -1598,14 +1669,17 @@ static int nand_read_page_syndrome(struc - - /** - * nand_transfer_oob - [INTERN] Transfer oob to client buffer -- * @chip: nand chip structure -+ * @mtd: mtd info structure - * @oob: oob destination address - * @ops: oob ops structure - * @len: size of oob to transfer - */ --static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, -+static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob, - struct mtd_oob_ops *ops, size_t len) - { -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ int ret; -+ - switch (ops->mode) { - - case MTD_OPS_PLACE_OOB: -@@ -1613,31 +1687,12 @@ static uint8_t *nand_transfer_oob(struct - memcpy(oob, chip->oob_poi + ops->ooboffs, len); - return oob + len; - -- case MTD_OPS_AUTO_OOB: { -- struct nand_oobfree *free = chip->ecc.layout->oobfree; -- uint32_t boffs = 0, roffs = ops->ooboffs; -- size_t bytes = 0; -- -- for (; free->length && len; free++, len -= bytes) { -- /* Read request not from offset 0? */ -- if (unlikely(roffs)) { -- if (roffs >= free->length) { -- roffs -= free->length; -- continue; -- } -- boffs = free->offset + roffs; -- bytes = min_t(size_t, len, -- (free->length - roffs)); -- roffs = 0; -- } else { -- bytes = min_t(size_t, len, free->length); -- boffs = free->offset; -- } -- memcpy(oob, chip->oob_poi + boffs, bytes); -- oob += bytes; -- } -- return oob; -- } -+ case MTD_OPS_AUTO_OOB: -+ ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, -+ ops->ooboffs, len); -+ BUG_ON(ret); -+ return oob + len; -+ - default: - BUG(); - } -@@ -1655,7 +1710,7 @@ static uint8_t *nand_transfer_oob(struct - */ - static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("setting READ RETRY mode %d\n", retry_mode); - -@@ -1680,12 +1735,11 @@ static int nand_do_read_ops(struct mtd_i - struct mtd_oob_ops *ops) - { - int chipnr, page, realpage, col, bytes, aligned, oob_required; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int ret = 0; - uint32_t readlen = ops->len; - uint32_t oobreadlen = ops->ooblen; -- uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? -- mtd->oobavail : mtd->oobsize; -+ uint32_t max_oobsize = mtd_oobavail(mtd, ops); - - uint8_t *bufpoi, *oob, *buf; - int use_bufpoi; -@@ -1772,7 +1826,7 @@ read_retry: - int toread = min(oobreadlen, max_oobsize); - - if (toread) { -- oob = nand_transfer_oob(chip, -+ oob = nand_transfer_oob(mtd, - oob, ops, toread); - oobreadlen -= toread; - } -@@ -2025,7 +2079,7 @@ static int nand_do_read_oob(struct mtd_i - { - unsigned int max_bitflips = 0; - int page, realpage, chipnr; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct mtd_ecc_stats stats; - int readlen = ops->ooblen; - int len; -@@ -2037,10 +2091,7 @@ static int nand_do_read_oob(struct mtd_i - - stats = mtd->ecc_stats; - -- if (ops->mode == MTD_OPS_AUTO_OOB) -- len = chip->ecc.layout->oobavail; -- else -- len = mtd->oobsize; -+ len = mtd_oobavail(mtd, ops); - - if (unlikely(ops->ooboffs >= len)) { - pr_debug("%s: attempt to start read outside oob\n", -@@ -2074,7 +2125,7 @@ static int nand_do_read_oob(struct mtd_i - break; - - len = min(len, readlen); -- buf = nand_transfer_oob(chip, buf, ops, len); -+ buf = nand_transfer_oob(mtd, buf, ops, len); - - if (chip->options & NAND_NEED_READRDY) { - /* Apply delay or wait for ready/busy pin */ -@@ -2235,19 +2286,20 @@ static int nand_write_page_swecc(struct - const uint8_t *buf, int oob_required, - int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *ecc_calc = chip->buffers->ecccalc; - const uint8_t *p = buf; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - - /* Software ECC calculation */ - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - -- for (i = 0; i < chip->ecc.total; i++) -- chip->oob_poi[eccpos[i]] = ecc_calc[i]; -+ ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); - } -@@ -2264,12 +2316,11 @@ static int nand_write_page_hwecc(struct - const uint8_t *buf, int oob_required, - int page) - { -- int i, eccsize = chip->ecc.size; -+ int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *ecc_calc = chip->buffers->ecccalc; - const uint8_t *p = buf; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - chip->ecc.hwctl(mtd, NAND_ECC_WRITE); -@@ -2277,8 +2328,10 @@ static int nand_write_page_hwecc(struct - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - } - -- for (i = 0; i < chip->ecc.total; i++) -- chip->oob_poi[eccpos[i]] = ecc_calc[i]; -+ ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); - -@@ -2306,11 +2359,10 @@ static int nand_write_subpage_hwecc(stru - int ecc_size = chip->ecc.size; - int ecc_bytes = chip->ecc.bytes; - int ecc_steps = chip->ecc.steps; -- uint32_t *eccpos = chip->ecc.layout->eccpos; - uint32_t start_step = offset / ecc_size; - uint32_t end_step = (offset + data_len - 1) / ecc_size; - int oob_bytes = mtd->oobsize / ecc_steps; -- int step, i; -+ int step, ret; - - for (step = 0; step < ecc_steps; step++) { - /* configure controller for WRITE access */ -@@ -2338,8 +2390,10 @@ static int nand_write_subpage_hwecc(stru - /* copy calculated ECC for whole page to chip->buffer->oob */ - /* this include masked-value(0xFF) for unwritten subpages */ - ecc_calc = chip->buffers->ecccalc; -- for (i = 0; i < chip->ecc.total; i++) -- chip->oob_poi[eccpos[i]] = ecc_calc[i]; -+ ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, -+ chip->ecc.total); -+ if (ret) -+ return ret; - - /* write OOB buffer to NAND device */ - chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); -@@ -2475,7 +2529,8 @@ static int nand_write_page(struct mtd_in - static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, - struct mtd_oob_ops *ops) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ int ret; - - /* - * Initialise to all 0xFF, to avoid the possibility of left over OOB -@@ -2490,31 +2545,12 @@ static uint8_t *nand_fill_oob(struct mtd - memcpy(chip->oob_poi + ops->ooboffs, oob, len); - return oob + len; - -- case MTD_OPS_AUTO_OOB: { -- struct nand_oobfree *free = chip->ecc.layout->oobfree; -- uint32_t boffs = 0, woffs = ops->ooboffs; -- size_t bytes = 0; -- -- for (; free->length && len; free++, len -= bytes) { -- /* Write request not from offset 0? */ -- if (unlikely(woffs)) { -- if (woffs >= free->length) { -- woffs -= free->length; -- continue; -- } -- boffs = free->offset + woffs; -- bytes = min_t(size_t, len, -- (free->length - woffs)); -- woffs = 0; -- } else { -- bytes = min_t(size_t, len, free->length); -- boffs = free->offset; -- } -- memcpy(chip->oob_poi + boffs, oob, bytes); -- oob += bytes; -- } -- return oob; -- } -+ case MTD_OPS_AUTO_OOB: -+ ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, -+ ops->ooboffs, len); -+ BUG_ON(ret); -+ return oob + len; -+ - default: - BUG(); - } -@@ -2535,12 +2571,11 @@ static int nand_do_write_ops(struct mtd_ - struct mtd_oob_ops *ops) - { - int chipnr, realpage, page, blockmask, column; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - uint32_t writelen = ops->len; - - uint32_t oobwritelen = ops->ooblen; -- uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? -- mtd->oobavail : mtd->oobsize; -+ uint32_t oobmaxlen = mtd_oobavail(mtd, ops); - - uint8_t *oob = ops->oobbuf; - uint8_t *buf = ops->datbuf; -@@ -2665,7 +2700,7 @@ err_out: - static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const uint8_t *buf) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - int chipnr = (int)(to >> chip->chip_shift); - struct mtd_oob_ops ops; - int ret; -@@ -2728,15 +2763,12 @@ static int nand_do_write_oob(struct mtd_ - struct mtd_oob_ops *ops) - { - int chipnr, page, status, len; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - pr_debug("%s: to = 0x%08x, len = %i\n", - __func__, (unsigned int)to, (int)ops->ooblen); - -- if (ops->mode == MTD_OPS_AUTO_OOB) -- len = chip->ecc.layout->oobavail; -- else -- len = mtd->oobsize; -+ len = mtd_oobavail(mtd, ops); - - /* Do not allow write past end of page */ - if ((ops->ooboffs + ops->ooblen) > len) { -@@ -2853,7 +2885,7 @@ out: - */ - static int single_erase(struct mtd_info *mtd, int page) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - /* Send commands to erase a block */ - chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); - chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); -@@ -2885,7 +2917,7 @@ int nand_erase_nand(struct mtd_info *mtd - int allowbbt) - { - int page, status, pages_per_block, ret, chipnr; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - loff_t len; - - pr_debug("%s: start = 0x%012llx, len = %llu\n", -@@ -2924,7 +2956,7 @@ int nand_erase_nand(struct mtd_info *mtd - while (len) { - /* Check if we have a bad block, we do not erase bad blocks! */ - if (nand_block_checkbad(mtd, ((loff_t) page) << -- chip->page_shift, 0, allowbbt)) { -+ chip->page_shift, allowbbt)) { - pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", - __func__, page); - instr->state = MTD_ERASE_FAILED; -@@ -3011,7 +3043,20 @@ static void nand_sync(struct mtd_info *m - */ - static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) - { -- return nand_block_checkbad(mtd, offs, 1, 0); -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ int chipnr = (int)(offs >> chip->chip_shift); -+ int ret; -+ -+ /* Select the NAND device */ -+ nand_get_device(mtd, FL_READING); -+ chip->select_chip(mtd, chipnr); -+ -+ ret = nand_block_checkbad(mtd, offs, 0); -+ -+ chip->select_chip(mtd, -1); -+ nand_release_device(mtd); -+ -+ return ret; - } - - /** -@@ -3100,7 +3145,7 @@ static int nand_suspend(struct mtd_info - */ - static void nand_resume(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->state == FL_PM_SUSPENDED) - nand_release_device(mtd); -@@ -3272,7 +3317,7 @@ ext_out: - - static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; - - return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, -@@ -3943,10 +3988,13 @@ ident_done: - return type; - } - --static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, -- struct device_node *dn) -+static int nand_dt_init(struct nand_chip *chip) - { -- int ecc_mode, ecc_strength, ecc_step; -+ struct device_node *dn = nand_get_flash_node(chip); -+ int ecc_mode, ecc_algo, ecc_strength, ecc_step; -+ -+ if (!dn) -+ return 0; - - if (of_get_nand_bus_width(dn) == 16) - chip->options |= NAND_BUSWIDTH_16; -@@ -3955,6 +4003,7 @@ static int nand_dt_init(struct mtd_info - chip->bbt_options |= NAND_BBT_USE_FLASH; - - ecc_mode = of_get_nand_ecc_mode(dn); -+ ecc_algo = of_get_nand_ecc_algo(dn); - ecc_strength = of_get_nand_ecc_strength(dn); - ecc_step = of_get_nand_ecc_step_size(dn); - -@@ -3967,6 +4016,9 @@ static int nand_dt_init(struct mtd_info - if (ecc_mode >= 0) - chip->ecc.mode = ecc_mode; - -+ if (ecc_algo >= 0) -+ chip->ecc.algo = ecc_algo; -+ - if (ecc_strength >= 0) - chip->ecc.strength = ecc_strength; - -@@ -3990,15 +4042,16 @@ int nand_scan_ident(struct mtd_info *mtd - struct nand_flash_dev *table) - { - int i, nand_maf_id, nand_dev_id; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_flash_dev *type; - int ret; - -- if (chip->flash_node) { -- ret = nand_dt_init(mtd, chip, chip->flash_node); -- if (ret) -- return ret; -- } -+ ret = nand_dt_init(chip); -+ if (ret) -+ return ret; -+ -+ if (!mtd->name && mtd->dev.parent) -+ mtd->name = dev_name(mtd->dev.parent); - - if (!mtd->name && mtd->dev.parent) - mtd->name = dev_name(mtd->dev.parent); -@@ -4061,7 +4114,7 @@ EXPORT_SYMBOL(nand_scan_ident); - */ - static bool nand_ecc_strength_good(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - int corr, ds_corr; - -@@ -4089,10 +4142,10 @@ static bool nand_ecc_strength_good(struc - */ - int nand_scan_tail(struct mtd_info *mtd) - { -- int i; -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - struct nand_buffers *nbuf; -+ int ret; - - /* New bad blocks should be marked in OOB, flash-based BBT, or both */ - BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && -@@ -4119,19 +4172,15 @@ int nand_scan_tail(struct mtd_info *mtd) - /* - * If no default placement scheme is given, select an appropriate one. - */ -- if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { -+ if (!mtd->ooblayout && (ecc->mode != NAND_ECC_SOFT_BCH)) { - switch (mtd->oobsize) { - case 8: -- ecc->layout = &nand_oob_8; -- break; - case 16: -- ecc->layout = &nand_oob_16; -+ mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); - break; - case 64: -- ecc->layout = &nand_oob_64; -- break; - case 128: -- ecc->layout = &nand_oob_128; -+ mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); - break; - default: - pr_warn("No oob scheme defined for oobsize %d\n", -@@ -4174,7 +4223,7 @@ int nand_scan_tail(struct mtd_info *mtd) - ecc->write_oob = nand_write_oob_std; - if (!ecc->read_subpage) - ecc->read_subpage = nand_read_subpage; -- if (!ecc->write_subpage) -+ if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) - ecc->write_subpage = nand_write_subpage_hwecc; - - case NAND_ECC_HW_SYNDROME: -@@ -4252,10 +4301,8 @@ int nand_scan_tail(struct mtd_info *mtd) - } - - /* See nand_bch_init() for details. */ -- ecc->bytes = DIV_ROUND_UP( -- ecc->strength * fls(8 * ecc->size), 8); -- ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, -- &ecc->layout); -+ ecc->bytes = 0; -+ ecc->priv = nand_bch_init(mtd); - if (!ecc->priv) { - pr_warn("BCH ECC initialization failed!\n"); - BUG(); -@@ -4286,20 +4333,9 @@ int nand_scan_tail(struct mtd_info *mtd) - if (!ecc->write_oob_raw) - ecc->write_oob_raw = ecc->write_oob; - -- /* -- * The number of bytes available for a client to place data into -- * the out of band area. -- */ -- ecc->layout->oobavail = 0; -- for (i = 0; ecc->layout->oobfree[i].length -- && i < ARRAY_SIZE(ecc->layout->oobfree); i++) -- ecc->layout->oobavail += ecc->layout->oobfree[i].length; -- mtd->oobavail = ecc->layout->oobavail; -- -- /* ECC sanity check: warn if it's too weak */ -- if (!nand_ecc_strength_good(mtd)) -- pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", -- mtd->name); -+ /* propagate ecc info to mtd_info */ -+ mtd->ecc_strength = ecc->strength; -+ mtd->ecc_step_size = ecc->size; - - /* - * Set the number of read / write steps for one page depending on ECC -@@ -4312,6 +4348,21 @@ int nand_scan_tail(struct mtd_info *mtd) - } - ecc->total = ecc->steps * ecc->bytes; - -+ /* -+ * The number of bytes available for a client to place data into -+ * the out of band area. -+ */ -+ ret = mtd_ooblayout_count_freebytes(mtd); -+ if (ret < 0) -+ ret = 0; -+ -+ mtd->oobavail = ret; -+ -+ /* ECC sanity check: warn if it's too weak */ -+ if (!nand_ecc_strength_good(mtd)) -+ pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", -+ mtd->name); -+ - /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ - if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { - switch (ecc->steps) { -@@ -4368,10 +4419,6 @@ int nand_scan_tail(struct mtd_info *mtd) - mtd->_block_markbad = nand_block_markbad; - mtd->writebufsize = mtd->writesize; - -- /* propagate ecc info to mtd_info */ -- mtd->ecclayout = ecc->layout; -- mtd->ecc_strength = ecc->strength; -- mtd->ecc_step_size = ecc->size; - /* - * Initialize bitflip_threshold to its default prior scan_bbt() call. - * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be -@@ -4427,7 +4474,7 @@ EXPORT_SYMBOL(nand_scan); - */ - void nand_release(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - if (chip->ecc.mode == NAND_ECC_SOFT_BCH) - nand_bch_free((struct nand_bch_control *)chip->ecc.priv); ---- a/drivers/mtd/nand/nand_bbt.c -+++ b/drivers/mtd/nand/nand_bbt.c -@@ -172,7 +172,7 @@ static int read_bbt(struct mtd_info *mtd - struct nand_bbt_descr *td, int offs) - { - int res, ret = 0, i, j, act = 0; -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - size_t retlen, len, totlen; - loff_t from; - int bits = td->options & NAND_BBT_NRBITS_MSK; -@@ -263,7 +263,7 @@ static int read_bbt(struct mtd_info *mtd - */ - static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int res = 0, i; - - if (td->options & NAND_BBT_PERCHIP) { -@@ -388,7 +388,7 @@ static u32 bbt_get_ver_offs(struct mtd_i - static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, - struct nand_bbt_descr *td, struct nand_bbt_descr *md) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - - /* Read the primary version, if available */ - if (td->options & NAND_BBT_VERSION) { -@@ -454,7 +454,7 @@ static int scan_block_fast(struct mtd_in - static int create_bbt(struct mtd_info *mtd, uint8_t *buf, - struct nand_bbt_descr *bd, int chip) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int i, numblocks, numpages; - int startblock; - loff_t from; -@@ -523,7 +523,7 @@ static int create_bbt(struct mtd_info *m - */ - static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int i, chips; - int startblock, block, dir; - int scanlen = mtd->writesize + mtd->oobsize; -@@ -618,7 +618,7 @@ static int write_bbt(struct mtd_info *mt - struct nand_bbt_descr *td, struct nand_bbt_descr *md, - int chipsel) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - struct erase_info einfo; - int i, res, chip = 0; - int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; -@@ -819,7 +819,7 @@ static int write_bbt(struct mtd_info *mt - */ - static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - - return create_bbt(mtd, this->buffers->databuf, bd, -1); - } -@@ -838,7 +838,7 @@ static inline int nand_memory_bbt(struct - static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) - { - int i, chips, writeops, create, chipsel, res, res2; -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - struct nand_bbt_descr *td = this->bbt_td; - struct nand_bbt_descr *md = this->bbt_md; - struct nand_bbt_descr *rd, *rd2; -@@ -962,7 +962,7 @@ static int check_create(struct mtd_info - */ - static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int i, j, chips, block, nrblocks, update; - uint8_t oldval; - -@@ -1022,7 +1022,7 @@ static void mark_bbt_region(struct mtd_i - */ - static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - u32 pattern_len; - u32 bits; - u32 table_size; -@@ -1074,7 +1074,7 @@ static void verify_bbt_descr(struct mtd_ - */ - static int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int len, res; - uint8_t *buf; - struct nand_bbt_descr *td = this->bbt_td; -@@ -1147,7 +1147,7 @@ err: - */ - static int nand_update_bbt(struct mtd_info *mtd, loff_t offs) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int len, res = 0; - int chip, chipsel; - uint8_t *buf; -@@ -1281,7 +1281,7 @@ static int nand_create_badblock_pattern( - */ - int nand_default_bbt(struct mtd_info *mtd) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int ret; - - /* Is a flash based bad block table requested? */ -@@ -1317,7 +1317,7 @@ int nand_default_bbt(struct mtd_info *mt - */ - int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int block; - - block = (int)(offs >> this->bbt_erase_shift); -@@ -1332,7 +1332,7 @@ int nand_isreserved_bbt(struct mtd_info - */ - int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int block, res; - - block = (int)(offs >> this->bbt_erase_shift); -@@ -1359,7 +1359,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, - */ - int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) - { -- struct nand_chip *this = mtd->priv; -+ struct nand_chip *this = mtd_to_nand(mtd); - int block, ret = 0; - - block = (int)(offs >> this->bbt_erase_shift); -@@ -1373,5 +1373,3 @@ int nand_markbad_bbt(struct mtd_info *mt - - return ret; - } -- --EXPORT_SYMBOL(nand_scan_bbt); ---- a/drivers/mtd/nand/nand_bch.c -+++ b/drivers/mtd/nand/nand_bch.c -@@ -32,13 +32,11 @@ - /** - * struct nand_bch_control - private NAND BCH control structure - * @bch: BCH control structure -- * @ecclayout: private ecc layout for this BCH configuration - * @errloc: error location array - * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid - */ - struct nand_bch_control { - struct bch_control *bch; -- struct nand_ecclayout ecclayout; - unsigned int *errloc; - unsigned char *eccmask; - }; -@@ -52,7 +50,7 @@ struct nand_bch_control { - int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf, - unsigned char *code) - { -- const struct nand_chip *chip = mtd->priv; -+ const struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_bch_control *nbc = chip->ecc.priv; - unsigned int i; - -@@ -79,7 +77,7 @@ EXPORT_SYMBOL(nand_bch_calculate_ecc); - int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, - unsigned char *read_ecc, unsigned char *calc_ecc) - { -- const struct nand_chip *chip = mtd->priv; -+ const struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_bch_control *nbc = chip->ecc.priv; - unsigned int *errloc = nbc->errloc; - int i, count; -@@ -98,7 +96,7 @@ int nand_bch_correct_data(struct mtd_inf - } - } else if (count < 0) { - printk(KERN_ERR "ecc unrecoverable error\n"); -- count = -1; -+ count = -EBADMSG; - } - return count; - } -@@ -107,9 +105,6 @@ EXPORT_SYMBOL(nand_bch_correct_data); - /** - * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction - * @mtd: MTD block structure -- * @eccsize: ecc block size in bytes -- * @eccbytes: ecc length in bytes -- * @ecclayout: output default layout - * - * Returns: - * a pointer to a new NAND BCH control structure, or NULL upon failure -@@ -123,14 +118,20 @@ EXPORT_SYMBOL(nand_bch_correct_data); - * @eccsize = 512 (thus, m=13 is the smallest integer such that 2^m-1 > 512*8) - * @eccbytes = 7 (7 bytes are required to store m*t = 13*4 = 52 bits) - */ --struct nand_bch_control * --nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes, -- struct nand_ecclayout **ecclayout) -+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd) - { -+ struct nand_chip *nand = mtd_to_nand(mtd); - unsigned int m, t, eccsteps, i; -- struct nand_ecclayout *layout; - struct nand_bch_control *nbc = NULL; - unsigned char *erased_page; -+ unsigned int eccsize = nand->ecc.size; -+ unsigned int eccbytes = nand->ecc.bytes; -+ unsigned int eccstrength = nand->ecc.strength; -+ -+ if (!eccbytes && eccstrength) { -+ eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8); -+ nand->ecc.bytes = eccbytes; -+ } - - if (!eccsize || !eccbytes) { - printk(KERN_WARNING "ecc parameters not supplied\n"); -@@ -158,7 +159,7 @@ nand_bch_init(struct mtd_info *mtd, unsi - eccsteps = mtd->writesize/eccsize; - - /* if no ecc placement scheme was provided, build one */ -- if (!*ecclayout) { -+ if (!mtd->ooblayout) { - - /* handle large page devices only */ - if (mtd->oobsize < 64) { -@@ -167,24 +168,7 @@ nand_bch_init(struct mtd_info *mtd, unsi - goto fail; - } - -- layout = &nbc->ecclayout; -- layout->eccbytes = eccsteps*eccbytes; -- -- /* reserve 2 bytes for bad block marker */ -- if (layout->eccbytes+2 > mtd->oobsize) { -- printk(KERN_WARNING "no suitable oob scheme available " -- "for oobsize %d eccbytes %u\n", mtd->oobsize, -- eccbytes); -- goto fail; -- } -- /* put ecc bytes at oob tail */ -- for (i = 0; i < layout->eccbytes; i++) -- layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i; -- -- layout->oobfree[0].offset = 2; -- layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes; -- -- *ecclayout = layout; -+ mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); - } - - /* sanity checks */ -@@ -192,7 +176,8 @@ nand_bch_init(struct mtd_info *mtd, unsi - printk(KERN_WARNING "eccsize %u is too large\n", eccsize); - goto fail; - } -- if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) { -+ -+ if (mtd_ooblayout_count_eccbytes(mtd) != (eccsteps*eccbytes)) { - printk(KERN_WARNING "invalid ecc layout\n"); - goto fail; - } -@@ -216,6 +201,9 @@ nand_bch_init(struct mtd_info *mtd, unsi - for (i = 0; i < eccbytes; i++) - nbc->eccmask[i] ^= 0xff; - -+ if (!eccstrength) -+ nand->ecc.strength = (eccbytes * 8) / fls(8 * eccsize); -+ - return nbc; - fail: - nand_bch_free(nbc); ---- a/drivers/mtd/nand/nand_ecc.c -+++ b/drivers/mtd/nand/nand_ecc.c -@@ -424,7 +424,7 @@ int nand_calculate_ecc(struct mtd_info * - unsigned char *code) - { - __nand_calculate_ecc(buf, -- ((struct nand_chip *)mtd->priv)->ecc.size, code); -+ mtd_to_nand(mtd)->ecc.size, code); - - return 0; - } -@@ -524,7 +524,7 @@ int nand_correct_data(struct mtd_info *m - unsigned char *read_ecc, unsigned char *calc_ecc) - { - return __nand_correct_data(buf, read_ecc, calc_ecc, -- ((struct nand_chip *)mtd->priv)->ecc.size); -+ mtd_to_nand(mtd)->ecc.size); - } - EXPORT_SYMBOL(nand_correct_data); - ---- a/drivers/mtd/nand/nand_ids.c -+++ b/drivers/mtd/nand/nand_ids.c -@@ -50,8 +50,8 @@ struct nand_flash_dev nand_flash_ids[] = - SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, - {"H27UCG8T2ATR-BC 64G 3.3V 8-bit", - { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, -- SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K), -- 4 }, -+ SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, -+ NAND_ECC_INFO(40, SZ_1K), 4 }, - - LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), ---- a/drivers/mtd/nand/nandsim.c -+++ b/drivers/mtd/nand/nandsim.c -@@ -666,8 +666,8 @@ static char *get_partition_name(int i) - */ - static int init_nandsim(struct mtd_info *mtd) - { -- struct nand_chip *chip = mtd->priv; -- struct nandsim *ns = chip->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - int i, ret = 0; - uint64_t remains; - uint64_t next_offset; -@@ -1908,7 +1908,8 @@ static void switch_state(struct nandsim - - static u_char ns_nand_read_byte(struct mtd_info *mtd) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - u_char outb = 0x00; - - /* Sanity and correctness checks */ -@@ -1969,7 +1970,8 @@ static u_char ns_nand_read_byte(struct m - - static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - /* Sanity and correctness checks */ - if (!ns->lines.ce) { -@@ -2123,7 +2125,8 @@ static void ns_nand_write_byte(struct mt - - static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - ns->lines.cle = bitmask & NAND_CLE ? 1 : 0; - ns->lines.ale = bitmask & NAND_ALE ? 1 : 0; -@@ -2141,7 +2144,7 @@ static int ns_device_ready(struct mtd_in - - static uint16_t ns_nand_read_word(struct mtd_info *mtd) - { -- struct nand_chip *chip = (struct nand_chip *)mtd->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); - - NS_DBG("read_word\n"); - -@@ -2150,7 +2153,8 @@ static uint16_t ns_nand_read_word(struct - - static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - /* Check that chip is expecting data input */ - if (!(ns->state & STATE_DATAIN_MASK)) { -@@ -2177,7 +2181,8 @@ static void ns_nand_write_buf(struct mtd - - static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) - { -- struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(mtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - - /* Sanity and correctness checks */ - if (!ns->lines.ce) { -@@ -2198,7 +2203,7 @@ static void ns_nand_read_buf(struct mtd_ - int i; - - for (i = 0; i < len; i++) -- buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd); -+ buf[i] = mtd_to_nand(mtd)->read_byte(mtd); - - return; - } -@@ -2236,16 +2241,15 @@ static int __init ns_init_module(void) - } - - /* Allocate and initialize mtd_info, nand_chip and nandsim structures */ -- nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip) -- + sizeof(struct nandsim), GFP_KERNEL); -- if (!nsmtd) { -+ chip = kzalloc(sizeof(struct nand_chip) + sizeof(struct nandsim), -+ GFP_KERNEL); -+ if (!chip) { - NS_ERR("unable to allocate core structures.\n"); - return -ENOMEM; - } -- chip = (struct nand_chip *)(nsmtd + 1); -- nsmtd->priv = (void *)chip; -+ nsmtd = nand_to_mtd(chip); - nand = (struct nandsim *)(chip + 1); -- chip->priv = (void *)nand; -+ nand_set_controller_data(chip, (void *)nand); - - /* - * Register simulator's callbacks. -@@ -2257,6 +2261,7 @@ static int __init ns_init_module(void) - chip->read_buf = ns_nand_read_buf; - chip->read_word = ns_nand_read_word; - chip->ecc.mode = NAND_ECC_SOFT; -+ chip->ecc.algo = NAND_ECC_HAMMING; - /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */ - /* and 'badblocks' parameters to work */ - chip->options |= NAND_SKIP_BBTSCAN; -@@ -2335,6 +2340,7 @@ static int __init ns_init_module(void) - goto error; - } - chip->ecc.mode = NAND_ECC_SOFT_BCH; -+ chip->ecc.algo = NAND_ECC_BCH; - chip->ecc.size = 512; - chip->ecc.strength = bch; - chip->ecc.bytes = eccbytes; -@@ -2392,7 +2398,7 @@ err_exit: - for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i) - kfree(nand->partitions[i].name); - error: -- kfree(nsmtd); -+ kfree(chip); - free_lists(); - - return retval; -@@ -2405,7 +2411,8 @@ module_init(ns_init_module); - */ - static void __exit ns_cleanup_module(void) - { -- struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv; -+ struct nand_chip *chip = mtd_to_nand(nsmtd); -+ struct nandsim *ns = nand_get_controller_data(chip); - int i; - - nandsim_debugfs_remove(ns); -@@ -2413,7 +2420,7 @@ static void __exit ns_cleanup_module(voi - nand_release(nsmtd); /* Unregister driver */ - for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i) - kfree(ns->partitions[i].name); -- kfree(nsmtd); /* Free other structures */ -+ kfree(mtd_to_nand(nsmtd)); /* Free other structures */ - free_lists(); - } - ---- a/drivers/mtd/ofpart.c -+++ b/drivers/mtd/ofpart.c -@@ -26,9 +26,10 @@ static bool node_has_compatible(struct d - } - - static int parse_ofpart_partitions(struct mtd_info *master, -- struct mtd_partition **pparts, -+ const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { -+ struct mtd_partition *parts; - struct device_node *mtd_node; - struct device_node *ofpart_node; - const char *partname; -@@ -37,10 +38,8 @@ static int parse_ofpart_partitions(struc - bool dedicated = true; - - -- if (!data) -- return 0; -- -- mtd_node = data->of_node; -+ /* Pull of_node from the master device node */ -+ mtd_node = mtd_get_of_node(master); - if (!mtd_node) - return 0; - -@@ -72,8 +71,8 @@ static int parse_ofpart_partitions(struc - if (nr_parts == 0) - return 0; - -- *pparts = kzalloc(nr_parts * sizeof(**pparts), GFP_KERNEL); -- if (!*pparts) -+ parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); -+ if (!parts) - return -ENOMEM; - - i = 0; -@@ -107,19 +106,19 @@ static int parse_ofpart_partitions(struc - goto ofpart_fail; - } - -- (*pparts)[i].offset = of_read_number(reg, a_cells); -- (*pparts)[i].size = of_read_number(reg + a_cells, s_cells); -+ parts[i].offset = of_read_number(reg, a_cells); -+ parts[i].size = of_read_number(reg + a_cells, s_cells); - - partname = of_get_property(pp, "label", &len); - if (!partname) - partname = of_get_property(pp, "name", &len); -- (*pparts)[i].name = partname; -+ parts[i].name = partname; - - if (of_get_property(pp, "read-only", &len)) -- (*pparts)[i].mask_flags |= MTD_WRITEABLE; -+ parts[i].mask_flags |= MTD_WRITEABLE; - - if (of_get_property(pp, "lock", &len)) -- (*pparts)[i].mask_flags |= MTD_POWERUP_LOCK; -+ parts[i].mask_flags |= MTD_POWERUP_LOCK; - - i++; - } -@@ -127,6 +126,7 @@ static int parse_ofpart_partitions(struc - if (!nr_parts) - goto ofpart_none; - -+ *pparts = parts; - return nr_parts; - - ofpart_fail: -@@ -135,21 +135,20 @@ ofpart_fail: - ret = -EINVAL; - ofpart_none: - of_node_put(pp); -- kfree(*pparts); -- *pparts = NULL; -+ kfree(parts); - return ret; - } - - static struct mtd_part_parser ofpart_parser = { -- .owner = THIS_MODULE, - .parse_fn = parse_ofpart_partitions, - .name = "ofpart", - }; - - static int parse_ofoldpart_partitions(struct mtd_info *master, -- struct mtd_partition **pparts, -+ const struct mtd_partition **pparts, - struct mtd_part_parser_data *data) - { -+ struct mtd_partition *parts; - struct device_node *dp; - int i, plen, nr_parts; - const struct { -@@ -157,10 +156,8 @@ static int parse_ofoldpart_partitions(st - } *part; - const char *names; - -- if (!data) -- return 0; -- -- dp = data->of_node; -+ /* Pull of_node from the master device node */ -+ dp = mtd_get_of_node(master); - if (!dp) - return 0; - -@@ -173,37 +170,37 @@ static int parse_ofoldpart_partitions(st - - nr_parts = plen / sizeof(part[0]); - -- *pparts = kzalloc(nr_parts * sizeof(*(*pparts)), GFP_KERNEL); -- if (!*pparts) -+ parts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL); -+ if (!parts) - return -ENOMEM; - - names = of_get_property(dp, "partition-names", &plen); - - for (i = 0; i < nr_parts; i++) { -- (*pparts)[i].offset = be32_to_cpu(part->offset); -- (*pparts)[i].size = be32_to_cpu(part->len) & ~1; -+ parts[i].offset = be32_to_cpu(part->offset); -+ parts[i].size = be32_to_cpu(part->len) & ~1; - /* bit 0 set signifies read only partition */ - if (be32_to_cpu(part->len) & 1) -- (*pparts)[i].mask_flags = MTD_WRITEABLE; -+ parts[i].mask_flags = MTD_WRITEABLE; - - if (names && (plen > 0)) { - int len = strlen(names) + 1; - -- (*pparts)[i].name = names; -+ parts[i].name = names; - plen -= len; - names += len; - } else { -- (*pparts)[i].name = "unnamed"; -+ parts[i].name = "unnamed"; - } - - part++; - } - -+ *pparts = parts; - return nr_parts; - } - - static struct mtd_part_parser ofoldpart_parser = { -- .owner = THIS_MODULE, - .parse_fn = parse_ofoldpart_partitions, - .name = "ofoldpart", - }; ---- a/drivers/mtd/spi-nor/Kconfig -+++ b/drivers/mtd/spi-nor/Kconfig -@@ -7,6 +7,14 @@ menuconfig MTD_SPI_NOR - - if MTD_SPI_NOR - -+config MTD_MT81xx_NOR -+ tristate "Mediatek MT81xx SPI NOR flash controller" -+ depends on HAS_IOMEM -+ help -+ This enables access to SPI NOR flash, using MT81xx SPI NOR flash -+ controller. This controller does not support generic SPI BUS, it only -+ supports SPI NOR Flash. -+ - config MTD_SPI_NOR_USE_4K_SECTORS - bool "Use small 4096 B erase sectors" - default y -@@ -23,7 +31,7 @@ config MTD_SPI_NOR_USE_4K_SECTORS - - config SPI_FSL_QUADSPI - tristate "Freescale Quad SPI controller" -- depends on ARCH_MXC || COMPILE_TEST -+ depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST - depends on HAS_IOMEM - help - This enables support for the Quad SPI controller in master mode. ---- a/drivers/mtd/spi-nor/Makefile -+++ b/drivers/mtd/spi-nor/Makefile -@@ -1,3 +1,4 @@ - obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o - obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o -+obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o - obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o ---- /dev/null -+++ b/drivers/mtd/spi-nor/mtk-quadspi.c -@@ -0,0 +1,485 @@ -+/* -+ * Copyright (c) 2015 MediaTek Inc. -+ * Author: Bayi Cheng -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_NOR_CMD_REG 0x00 -+#define MTK_NOR_CNT_REG 0x04 -+#define MTK_NOR_RDSR_REG 0x08 -+#define MTK_NOR_RDATA_REG 0x0c -+#define MTK_NOR_RADR0_REG 0x10 -+#define MTK_NOR_RADR1_REG 0x14 -+#define MTK_NOR_RADR2_REG 0x18 -+#define MTK_NOR_WDATA_REG 0x1c -+#define MTK_NOR_PRGDATA0_REG 0x20 -+#define MTK_NOR_PRGDATA1_REG 0x24 -+#define MTK_NOR_PRGDATA2_REG 0x28 -+#define MTK_NOR_PRGDATA3_REG 0x2c -+#define MTK_NOR_PRGDATA4_REG 0x30 -+#define MTK_NOR_PRGDATA5_REG 0x34 -+#define MTK_NOR_SHREG0_REG 0x38 -+#define MTK_NOR_SHREG1_REG 0x3c -+#define MTK_NOR_SHREG2_REG 0x40 -+#define MTK_NOR_SHREG3_REG 0x44 -+#define MTK_NOR_SHREG4_REG 0x48 -+#define MTK_NOR_SHREG5_REG 0x4c -+#define MTK_NOR_SHREG6_REG 0x50 -+#define MTK_NOR_SHREG7_REG 0x54 -+#define MTK_NOR_SHREG8_REG 0x58 -+#define MTK_NOR_SHREG9_REG 0x5c -+#define MTK_NOR_CFG1_REG 0x60 -+#define MTK_NOR_CFG2_REG 0x64 -+#define MTK_NOR_CFG3_REG 0x68 -+#define MTK_NOR_STATUS0_REG 0x70 -+#define MTK_NOR_STATUS1_REG 0x74 -+#define MTK_NOR_STATUS2_REG 0x78 -+#define MTK_NOR_STATUS3_REG 0x7c -+#define MTK_NOR_FLHCFG_REG 0x84 -+#define MTK_NOR_TIME_REG 0x94 -+#define MTK_NOR_PP_DATA_REG 0x98 -+#define MTK_NOR_PREBUF_STUS_REG 0x9c -+#define MTK_NOR_DELSEL0_REG 0xa0 -+#define MTK_NOR_DELSEL1_REG 0xa4 -+#define MTK_NOR_INTRSTUS_REG 0xa8 -+#define MTK_NOR_INTREN_REG 0xac -+#define MTK_NOR_CHKSUM_CTL_REG 0xb8 -+#define MTK_NOR_CHKSUM_REG 0xbc -+#define MTK_NOR_CMD2_REG 0xc0 -+#define MTK_NOR_WRPROT_REG 0xc4 -+#define MTK_NOR_RADR3_REG 0xc8 -+#define MTK_NOR_DUAL_REG 0xcc -+#define MTK_NOR_DELSEL2_REG 0xd0 -+#define MTK_NOR_DELSEL3_REG 0xd4 -+#define MTK_NOR_DELSEL4_REG 0xd8 -+ -+/* commands for mtk nor controller */ -+#define MTK_NOR_READ_CMD 0x0 -+#define MTK_NOR_RDSR_CMD 0x2 -+#define MTK_NOR_PRG_CMD 0x4 -+#define MTK_NOR_WR_CMD 0x10 -+#define MTK_NOR_PIO_WR_CMD 0x90 -+#define MTK_NOR_WRSR_CMD 0x20 -+#define MTK_NOR_PIO_READ_CMD 0x81 -+#define MTK_NOR_WR_BUF_ENABLE 0x1 -+#define MTK_NOR_WR_BUF_DISABLE 0x0 -+#define MTK_NOR_ENABLE_SF_CMD 0x30 -+#define MTK_NOR_DUAD_ADDR_EN 0x8 -+#define MTK_NOR_QUAD_READ_EN 0x4 -+#define MTK_NOR_DUAL_ADDR_EN 0x2 -+#define MTK_NOR_DUAL_READ_EN 0x1 -+#define MTK_NOR_DUAL_DISABLE 0x0 -+#define MTK_NOR_FAST_READ 0x1 -+ -+#define SFLASH_WRBUF_SIZE 128 -+ -+/* Can shift up to 48 bits (6 bytes) of TX/RX */ -+#define MTK_NOR_MAX_RX_TX_SHIFT 6 -+/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */ -+#define MTK_NOR_MAX_SHIFT 7 -+ -+/* Helpers for accessing the program data / shift data registers */ -+#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n)) -+#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n)) -+ -+struct mt8173_nor { -+ struct spi_nor nor; -+ struct device *dev; -+ void __iomem *base; /* nor flash base address */ -+ struct clk *spi_clk; -+ struct clk *nor_clk; -+}; -+ -+static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor) -+{ -+ struct spi_nor *nor = &mt8173_nor->nor; -+ -+ switch (nor->flash_read) { -+ case SPI_NOR_FAST: -+ writeb(nor->read_opcode, mt8173_nor->base + -+ MTK_NOR_PRGDATA3_REG); -+ writeb(MTK_NOR_FAST_READ, mt8173_nor->base + -+ MTK_NOR_CFG1_REG); -+ break; -+ case SPI_NOR_DUAL: -+ writeb(nor->read_opcode, mt8173_nor->base + -+ MTK_NOR_PRGDATA3_REG); -+ writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base + -+ MTK_NOR_DUAL_REG); -+ break; -+ case SPI_NOR_QUAD: -+ writeb(nor->read_opcode, mt8173_nor->base + -+ MTK_NOR_PRGDATA4_REG); -+ writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base + -+ MTK_NOR_DUAL_REG); -+ break; -+ default: -+ writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base + -+ MTK_NOR_DUAL_REG); -+ break; -+ } -+} -+ -+static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval) -+{ -+ int reg; -+ u8 val = cmdval & 0x1f; -+ -+ writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG); -+ return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg, -+ !(reg & val), 100, 10000); -+} -+ -+static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op, -+ u8 *tx, int txlen, u8 *rx, int rxlen) -+{ -+ int len = 1 + txlen + rxlen; -+ int i, ret, idx; -+ -+ if (len > MTK_NOR_MAX_SHIFT) -+ return -EINVAL; -+ -+ writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG); -+ -+ /* start at PRGDATA5, go down to PRGDATA0 */ -+ idx = MTK_NOR_MAX_RX_TX_SHIFT - 1; -+ -+ /* opcode */ -+ writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); -+ idx--; -+ -+ /* program TX data */ -+ for (i = 0; i < txlen; i++, idx--) -+ writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx)); -+ -+ /* clear out rest of TX registers */ -+ while (idx >= 0) { -+ writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx)); -+ idx--; -+ } -+ -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD); -+ if (ret) -+ return ret; -+ -+ /* restart at first RX byte */ -+ idx = rxlen - 1; -+ -+ /* read out RX data */ -+ for (i = 0; i < rxlen; i++, idx--) -+ rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx)); -+ -+ return 0; -+} -+ -+/* Do a WRSR (Write Status Register) command */ -+static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr) -+{ -+ writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG); -+ writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG); -+ return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD); -+} -+ -+static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor) -+{ -+ u8 reg; -+ -+ /* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer -+ * 0: pre-fetch buffer use for read -+ * 1: pre-fetch buffer use for page program -+ */ -+ writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); -+ return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, -+ 0x01 == (reg & 0x01), 100, 10000); -+} -+ -+static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor) -+{ -+ u8 reg; -+ -+ writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG); -+ return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg, -+ MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100, -+ 10000); -+} -+ -+static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr) -+{ -+ int i; -+ -+ for (i = 0; i < 3; i++) { -+ writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4); -+ addr >>= 8; -+ } -+ /* Last register is non-contiguous */ -+ writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG); -+} -+ -+static int mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length, -+ size_t *retlen, u_char *buffer) -+{ -+ int i, ret; -+ int addr = (int)from; -+ u8 *buf = (u8 *)buffer; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ /* set mode for fast read mode ,dual mode or quad mode */ -+ mt8173_nor_set_read_mode(mt8173_nor); -+ mt8173_nor_set_addr(mt8173_nor, addr); -+ -+ for (i = 0; i < length; i++, (*retlen)++) { -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD); -+ if (ret < 0) -+ return ret; -+ buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG); -+ } -+ return 0; -+} -+ -+static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor, -+ int addr, int length, u8 *data) -+{ -+ int i, ret; -+ -+ mt8173_nor_set_addr(mt8173_nor, addr); -+ -+ for (i = 0; i < length; i++) { -+ writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG); -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD); -+ if (ret < 0) -+ return ret; -+ } -+ return 0; -+} -+ -+static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr, -+ const u8 *buf) -+{ -+ int i, bufidx, data; -+ -+ mt8173_nor_set_addr(mt8173_nor, addr); -+ -+ bufidx = 0; -+ for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) { -+ data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 | -+ buf[bufidx + 1]<<8 | buf[bufidx]; -+ bufidx += 4; -+ writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG); -+ } -+ return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD); -+} -+ -+static void mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len, -+ size_t *retlen, const u_char *buf) -+{ -+ int ret; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ ret = mt8173_nor_write_buffer_enable(mt8173_nor); -+ if (ret < 0) -+ dev_warn(mt8173_nor->dev, "write buffer enable failed!\n"); -+ -+ while (len >= SFLASH_WRBUF_SIZE) { -+ ret = mt8173_nor_write_buffer(mt8173_nor, to, buf); -+ if (ret < 0) -+ dev_err(mt8173_nor->dev, "write buffer failed!\n"); -+ len -= SFLASH_WRBUF_SIZE; -+ to += SFLASH_WRBUF_SIZE; -+ buf += SFLASH_WRBUF_SIZE; -+ (*retlen) += SFLASH_WRBUF_SIZE; -+ } -+ ret = mt8173_nor_write_buffer_disable(mt8173_nor); -+ if (ret < 0) -+ dev_warn(mt8173_nor->dev, "write buffer disable failed!\n"); -+ -+ if (len) { -+ ret = mt8173_nor_write_single_byte(mt8173_nor, to, (int)len, -+ (u8 *)buf); -+ if (ret < 0) -+ dev_err(mt8173_nor->dev, "write single byte failed!\n"); -+ (*retlen) += len; -+ } -+} -+ -+static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) -+{ -+ int ret; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ switch (opcode) { -+ case SPINOR_OP_RDSR: -+ ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD); -+ if (ret < 0) -+ return ret; -+ if (len == 1) -+ *buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG); -+ else -+ dev_err(mt8173_nor->dev, "len should be 1 for read status!\n"); -+ break; -+ default: -+ ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len); -+ break; -+ } -+ return ret; -+} -+ -+static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, -+ int len) -+{ -+ int ret; -+ struct mt8173_nor *mt8173_nor = nor->priv; -+ -+ switch (opcode) { -+ case SPINOR_OP_WRSR: -+ /* We only handle 1 byte */ -+ ret = mt8173_nor_wr_sr(mt8173_nor, *buf); -+ break; -+ default: -+ ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0); -+ if (ret) -+ dev_warn(mt8173_nor->dev, "write reg failure!\n"); -+ break; -+ } -+ return ret; -+} -+ -+static int mtk_nor_init(struct mt8173_nor *mt8173_nor, -+ struct device_node *flash_node) -+{ -+ int ret; -+ struct spi_nor *nor; -+ -+ /* initialize controller to accept commands */ -+ writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG); -+ -+ nor = &mt8173_nor->nor; -+ nor->dev = mt8173_nor->dev; -+ nor->priv = mt8173_nor; -+ spi_nor_set_flash_node(nor, flash_node); -+ -+ /* fill the hooks to spi nor */ -+ nor->read = mt8173_nor_read; -+ nor->read_reg = mt8173_nor_read_reg; -+ nor->write = mt8173_nor_write; -+ nor->write_reg = mt8173_nor_write_reg; -+ nor->mtd.name = "mtk_nor"; -+ /* initialized with NULL */ -+ ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL); -+ if (ret) -+ return ret; -+ -+ return mtd_device_register(&nor->mtd, NULL, 0); -+} -+ -+static int mtk_nor_drv_probe(struct platform_device *pdev) -+{ -+ struct device_node *flash_np; -+ struct resource *res; -+ int ret; -+ struct mt8173_nor *mt8173_nor; -+ -+ if (!pdev->dev.of_node) { -+ dev_err(&pdev->dev, "No DT found\n"); -+ return -EINVAL; -+ } -+ -+ mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL); -+ if (!mt8173_nor) -+ return -ENOMEM; -+ platform_set_drvdata(pdev, mt8173_nor); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(mt8173_nor->base)) -+ return PTR_ERR(mt8173_nor->base); -+ -+ mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi"); -+ if (IS_ERR(mt8173_nor->spi_clk)) -+ return PTR_ERR(mt8173_nor->spi_clk); -+ -+ mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf"); -+ if (IS_ERR(mt8173_nor->nor_clk)) -+ return PTR_ERR(mt8173_nor->nor_clk); -+ -+ mt8173_nor->dev = &pdev->dev; -+ ret = clk_prepare_enable(mt8173_nor->spi_clk); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(mt8173_nor->nor_clk); -+ if (ret) { -+ clk_disable_unprepare(mt8173_nor->spi_clk); -+ return ret; -+ } -+ /* only support one attached flash */ -+ flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); -+ if (!flash_np) { -+ dev_err(&pdev->dev, "no SPI flash device to configure\n"); -+ ret = -ENODEV; -+ goto nor_free; -+ } -+ ret = mtk_nor_init(mt8173_nor, flash_np); -+ -+nor_free: -+ if (ret) { -+ clk_disable_unprepare(mt8173_nor->spi_clk); -+ clk_disable_unprepare(mt8173_nor->nor_clk); -+ } -+ return ret; -+} -+ -+static int mtk_nor_drv_remove(struct platform_device *pdev) -+{ -+ struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev); -+ -+ clk_disable_unprepare(mt8173_nor->spi_clk); -+ clk_disable_unprepare(mt8173_nor->nor_clk); -+ return 0; -+} -+ -+static const struct of_device_id mtk_nor_of_ids[] = { -+ { .compatible = "mediatek,mt8173-nor"}, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, mtk_nor_of_ids); -+ -+static struct platform_driver mtk_nor_driver = { -+ .probe = mtk_nor_drv_probe, -+ .remove = mtk_nor_drv_remove, -+ .driver = { -+ .name = "mtk-nor", -+ .of_match_table = mtk_nor_of_ids, -+ }, -+}; -+ -+module_platform_driver(mtk_nor_driver); -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver"); ---- a/drivers/mtd/spi-nor/spi-nor.c -+++ b/drivers/mtd/spi-nor/spi-nor.c -@@ -38,6 +38,7 @@ - #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) - - #define SPI_NOR_MAX_ID_LEN 6 -+#define SPI_NOR_MAX_ADDR_WIDTH 4 - - struct flash_info { - char *name; -@@ -60,15 +61,20 @@ struct flash_info { - u16 addr_width; - - u16 flags; --#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ --#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ --#define SST_WRITE 0x04 /* use SST byte programming */ --#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ --#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ --#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ --#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ --#define USE_FSR 0x80 /* use flag status register */ --#define SPI_NOR_HAS_LOCK 0x100 /* Flash supports lock/unlock via SR */ -+#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ -+#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ -+#define SST_WRITE BIT(2) /* use SST byte programming */ -+#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ -+#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ -+#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ -+#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ -+#define USE_FSR BIT(7) /* use flag status register */ -+#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ -+#define SPI_NOR_HAS_TB BIT(9) /* -+ * Flash SR has Top/Bottom (TB) protect -+ * bit. Must be used with -+ * SPI_NOR_HAS_LOCK. -+ */ - }; - - #define JEDEC_MFR(info) ((info)->id[0]) -@@ -314,6 +320,29 @@ static void spi_nor_unlock_and_unprep(st - } - - /* -+ * Initiate the erasure of a single sector -+ */ -+static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) -+{ -+ u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; -+ int i; -+ -+ if (nor->erase) -+ return nor->erase(nor, addr); -+ -+ /* -+ * Default implementation, if driver doesn't have a specialized HW -+ * control -+ */ -+ for (i = nor->addr_width - 1; i >= 0; i--) { -+ buf[i] = addr & 0xff; -+ addr >>= 8; -+ } -+ -+ return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); -+} -+ -+/* - * Erase an address range on the nor chip. The address range may extend - * one or more erase sectors. Return an error is there is a problem erasing. - */ -@@ -372,10 +401,9 @@ static int spi_nor_erase(struct mtd_info - while (len) { - write_enable(nor); - -- if (nor->erase(nor, addr)) { -- ret = -EIO; -+ ret = spi_nor_erase_sector(nor, addr); -+ if (ret) - goto erase_err; -- } - - addr += mtd->erasesize; - len -= mtd->erasesize; -@@ -388,17 +416,13 @@ static int spi_nor_erase(struct mtd_info - - write_disable(nor); - -+erase_err: - spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); - -- instr->state = MTD_ERASE_DONE; -+ instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; - mtd_erase_callback(instr); - - return ret; -- --erase_err: -- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); -- instr->state = MTD_ERASE_FAILED; -- return ret; - } - - static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, -@@ -416,32 +440,58 @@ static void stm_get_locked_range(struct - } else { - pow = ((sr & mask) ^ mask) >> shift; - *len = mtd->size >> pow; -- *ofs = mtd->size - *len; -+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) -+ *ofs = 0; -+ else -+ *ofs = mtd->size - *len; - } - } - - /* -- * Return 1 if the entire region is locked, 0 otherwise -+ * Return 1 if the entire region is locked (if @locked is true) or unlocked (if -+ * @locked is false); 0 otherwise - */ --static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -- u8 sr) -+static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr, bool locked) - { - loff_t lock_offs; - uint64_t lock_len; - -+ if (!len) -+ return 1; -+ - stm_get_locked_range(nor, sr, &lock_offs, &lock_len); - -- return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); -+ if (locked) -+ /* Requested range is a sub-range of locked range */ -+ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); -+ else -+ /* Requested range does not overlap with locked range */ -+ return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); -+} -+ -+static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr) -+{ -+ return stm_check_lock_status_sr(nor, ofs, len, sr, true); -+} -+ -+static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, -+ u8 sr) -+{ -+ return stm_check_lock_status_sr(nor, ofs, len, sr, false); - } - - /* - * Lock a region of the flash. Compatible with ST Micro and similar flash. -- * Supports only the block protection bits BP{0,1,2} in the status register -+ * Supports the block protection bits BP{0,1,2} in the status register - * (SR). Does not support these features found in newer SR bitfields: -- * - TB: top/bottom protect - only handle TB=0 (top protect) - * - SEC: sector/block protect - only handle SEC=0 (block protect) - * - CMP: complement protect - only support CMP=0 (range is not complemented) - * -+ * Support for the following is provided conditionally for some flash: -+ * - TB: top/bottom protect -+ * - * Sample table portion for 8MB flash (Winbond w25q64fw): - * - * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion -@@ -454,26 +504,55 @@ static int stm_is_locked_sr(struct spi_n - * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 - * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 - * X | X | 1 | 1 | 1 | 8 MB | ALL -+ * ------|-------|-------|-------|-------|---------------|------------------- -+ * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 -+ * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 -+ * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 -+ * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 -+ * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 -+ * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 - * - * Returns negative on errors, 0 on success. - */ - static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { - struct mtd_info *mtd = &nor->mtd; -- u8 status_old, status_new; -+ int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; -+ loff_t lock_len; -+ bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; -+ bool use_top; -+ int ret; - - status_old = read_sr(nor); -+ if (status_old < 0) -+ return status_old; - -- /* SPI NOR always locks to the end */ -- if (ofs + len != mtd->size) { -- /* Does combined region extend to end? */ -- if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len, -- status_old)) -- return -EINVAL; -- len = mtd->size - ofs; -- } -+ /* If nothing in our range is unlocked, we don't need to do anything */ -+ if (stm_is_locked_sr(nor, ofs, len, status_old)) -+ return 0; -+ -+ /* If anything below us is unlocked, we can't use 'bottom' protection */ -+ if (!stm_is_locked_sr(nor, 0, ofs, status_old)) -+ can_be_bottom = false; -+ -+ /* If anything above us is unlocked, we can't use 'top' protection */ -+ if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), -+ status_old)) -+ can_be_top = false; -+ -+ if (!can_be_bottom && !can_be_top) -+ return -EINVAL; -+ -+ /* Prefer top, if both are valid */ -+ use_top = can_be_top; -+ -+ /* lock_len: length of region that should end up locked */ -+ if (use_top) -+ lock_len = mtd->size - ofs; -+ else -+ lock_len = ofs + len; - - /* - * Need smallest pow such that: -@@ -484,7 +563,7 @@ static int stm_lock(struct spi_nor *nor, - * - * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) - */ -- pow = ilog2(mtd->size) - ilog2(len); -+ pow = ilog2(mtd->size) - ilog2(lock_len); - val = mask - (pow << shift); - if (val & ~mask) - return -EINVAL; -@@ -492,14 +571,27 @@ static int stm_lock(struct spi_nor *nor, - if (!(val & mask)) - return -EINVAL; - -- status_new = (status_old & ~mask) | val; -+ status_new = (status_old & ~mask & ~SR_TB) | val; -+ -+ /* Disallow further writes if WP pin is asserted */ -+ status_new |= SR_SRWD; -+ -+ if (!use_top) -+ status_new |= SR_TB; -+ -+ /* Don't bother if they're the same */ -+ if (status_new == status_old) -+ return 0; - - /* Only modify protection if it will not unlock other areas */ -- if ((status_new & mask) <= (status_old & mask)) -+ if ((status_new & mask) < (status_old & mask)) - return -EINVAL; - - write_enable(nor); -- return write_sr(nor, status_new); -+ ret = write_sr(nor, status_new); -+ if (ret) -+ return ret; -+ return spi_nor_wait_till_ready(nor); - } - - /* -@@ -510,17 +602,43 @@ static int stm_lock(struct spi_nor *nor, - static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) - { - struct mtd_info *mtd = &nor->mtd; -- uint8_t status_old, status_new; -+ int status_old, status_new; - u8 mask = SR_BP2 | SR_BP1 | SR_BP0; - u8 shift = ffs(mask) - 1, pow, val; -+ loff_t lock_len; -+ bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; -+ bool use_top; -+ int ret; - - status_old = read_sr(nor); -+ if (status_old < 0) -+ return status_old; -+ -+ /* If nothing in our range is locked, we don't need to do anything */ -+ if (stm_is_unlocked_sr(nor, ofs, len, status_old)) -+ return 0; -+ -+ /* If anything below us is locked, we can't use 'top' protection */ -+ if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) -+ can_be_top = false; -+ -+ /* If anything above us is locked, we can't use 'bottom' protection */ -+ if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), -+ status_old)) -+ can_be_bottom = false; - -- /* Cannot unlock; would unlock larger region than requested */ -- if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize, -- status_old)) -+ if (!can_be_bottom && !can_be_top) - return -EINVAL; - -+ /* Prefer top, if both are valid */ -+ use_top = can_be_top; -+ -+ /* lock_len: length of region that should remain locked */ -+ if (use_top) -+ lock_len = mtd->size - (ofs + len); -+ else -+ lock_len = ofs; -+ - /* - * Need largest pow such that: - * -@@ -530,8 +648,8 @@ static int stm_unlock(struct spi_nor *no - * - * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) - */ -- pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len)); -- if (ofs + len == mtd->size) { -+ pow = ilog2(mtd->size) - order_base_2(lock_len); -+ if (lock_len == 0) { - val = 0; /* fully unlocked */ - } else { - val = mask - (pow << shift); -@@ -540,14 +658,28 @@ static int stm_unlock(struct spi_nor *no - return -EINVAL; - } - -- status_new = (status_old & ~mask) | val; -+ status_new = (status_old & ~mask & ~SR_TB) | val; -+ -+ /* Don't protect status register if we're fully unlocked */ -+ if (lock_len == mtd->size) -+ status_new &= ~SR_SRWD; -+ -+ if (!use_top) -+ status_new |= SR_TB; -+ -+ /* Don't bother if they're the same */ -+ if (status_new == status_old) -+ return 0; - - /* Only modify protection if it will not lock other areas */ -- if ((status_new & mask) >= (status_old & mask)) -+ if ((status_new & mask) > (status_old & mask)) - return -EINVAL; - - write_enable(nor); -- return write_sr(nor, status_new); -+ ret = write_sr(nor, status_new); -+ if (ret) -+ return ret; -+ return spi_nor_wait_till_ready(nor); - } - - /* -@@ -737,8 +869,8 @@ static const struct flash_info spi_nor_i - { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, -- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, -- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, -+ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, -+ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, -@@ -772,6 +904,7 @@ static const struct flash_info spi_nor_i - { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, -+ { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, - { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, - { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, -@@ -835,11 +968,23 @@ static const struct flash_info spi_nor_i - { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, - { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, - { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, -- { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { -+ "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, - { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, -- { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -- { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { -+ "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, -+ { -+ "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, -+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) -+ }, - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, -@@ -862,7 +1007,7 @@ static const struct flash_info *spi_nor_ - - tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); - if (tmp < 0) { -- dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); -+ dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); - return ERR_PTR(tmp); - } - -@@ -873,7 +1018,7 @@ static const struct flash_info *spi_nor_ - return &spi_nor_ids[tmp]; - } - } -- dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n", -+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", - id[0], id[1], id[2]); - return ERR_PTR(-ENODEV); - } -@@ -1019,6 +1164,8 @@ static int macronix_quad_enable(struct s - int ret, val; - - val = read_sr(nor); -+ if (val < 0) -+ return val; - write_enable(nor); - - write_sr(nor, val | SR_QUAD_EN_MX); -@@ -1107,7 +1254,7 @@ static int set_quad_mode(struct spi_nor - static int spi_nor_check(struct spi_nor *nor) - { - if (!nor->dev || !nor->read || !nor->write || -- !nor->read_reg || !nor->write_reg || !nor->erase) { -+ !nor->read_reg || !nor->write_reg) { - pr_err("spi-nor: please fill all the necessary fields!\n"); - return -EINVAL; - } -@@ -1120,7 +1267,7 @@ int spi_nor_scan(struct spi_nor *nor, co - const struct flash_info *info = NULL; - struct device *dev = nor->dev; - struct mtd_info *mtd = &nor->mtd; -- struct device_node *np = nor->flash_node; -+ struct device_node *np = spi_nor_get_flash_node(nor); - int ret; - int i; - -@@ -1174,6 +1321,7 @@ int spi_nor_scan(struct spi_nor *nor, co - info->flags & SPI_NOR_HAS_LOCK) { - write_enable(nor); - write_sr(nor, 0); -+ spi_nor_wait_till_ready(nor); - } - - if (!mtd->name) -@@ -1208,6 +1356,8 @@ int spi_nor_scan(struct spi_nor *nor, co - - if (info->flags & USE_FSR) - nor->flags |= SNOR_F_USE_FSR; -+ if (info->flags & SPI_NOR_HAS_TB) -+ nor->flags |= SNOR_F_HAS_SR_TB; - - #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS - /* prefer "small sector" erase if possible */ -@@ -1310,6 +1460,12 @@ int spi_nor_scan(struct spi_nor *nor, co - nor->addr_width = 3; - } - -+ if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { -+ dev_err(dev, "address width is too large: %u\n", -+ nor->addr_width); -+ return -EINVAL; -+ } -+ - nor->read_dummy = spi_nor_read_dummy_cycles(nor); - - dev_info(dev, "%s (%lld Kbytes)\n", info->name, ---- a/drivers/mtd/tests/mtd_nandecctest.c -+++ b/drivers/mtd/tests/mtd_nandecctest.c -@@ -187,7 +187,7 @@ static int double_bit_error_detect(void - __nand_calculate_ecc(error_data, size, calc_ecc); - ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size); - -- return (ret == -1) ? 0 : -EINVAL; -+ return (ret == -EBADMSG) ? 0 : -EINVAL; - } - - static const struct nand_ecc_test nand_ecc_test[] = { ---- a/drivers/mtd/tests/oobtest.c -+++ b/drivers/mtd/tests/oobtest.c -@@ -215,19 +215,19 @@ static int verify_eraseblock(int ebnum) - pr_info("ignoring error as within bitflip_limit\n"); - } - -- if (use_offset != 0 || use_len < mtd->ecclayout->oobavail) { -+ if (use_offset != 0 || use_len < mtd->oobavail) { - int k; - - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; - ops.oobbuf = readbuf; - err = mtd_read_oob(mtd, addr, &ops); -- if (err || ops.oobretlen != mtd->ecclayout->oobavail) { -+ if (err || ops.oobretlen != mtd->oobavail) { - pr_err("error: readoob failed at %#llx\n", - (long long)addr); - errcnt += 1; -@@ -244,7 +244,7 @@ static int verify_eraseblock(int ebnum) - /* verify post-(use_offset + use_len) area for 0xff */ - k = use_offset + use_len; - bitflips += memffshow(addr, k, readbuf + k, -- mtd->ecclayout->oobavail - k); -+ mtd->oobavail - k); - - if (bitflips > bitflip_limit) { - pr_err("error: verify failed at %#llx\n", -@@ -269,8 +269,8 @@ static int verify_eraseblock_in_one_go(i - struct mtd_oob_ops ops; - int err = 0; - loff_t addr = (loff_t)ebnum * mtd->erasesize; -- size_t len = mtd->ecclayout->oobavail * pgcnt; -- size_t oobavail = mtd->ecclayout->oobavail; -+ size_t len = mtd->oobavail * pgcnt; -+ size_t oobavail = mtd->oobavail; - size_t bitflips; - int i; - -@@ -394,8 +394,8 @@ static int __init mtd_oobtest_init(void) - goto out; - - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 0; - - /* First test: write all OOB, read it back and verify */ -@@ -460,8 +460,8 @@ static int __init mtd_oobtest_init(void) - - /* Write all eraseblocks */ - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 1; - prandom_seed_state(&rnd_state, 5); - -@@ -471,8 +471,8 @@ static int __init mtd_oobtest_init(void) - - /* Check all eraseblocks */ - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 1; - prandom_seed_state(&rnd_state, 5); - err = verify_all_eraseblocks(); -@@ -480,8 +480,8 @@ static int __init mtd_oobtest_init(void) - goto out; - - use_offset = 0; -- use_len = mtd->ecclayout->oobavail; -- use_len_max = mtd->ecclayout->oobavail; -+ use_len = mtd->oobavail; -+ use_len_max = mtd->oobavail; - vary_offset = 0; - - /* Fourth test: try to write off end of device */ -@@ -501,7 +501,7 @@ static int __init mtd_oobtest_init(void) - ops.retlen = 0; - ops.ooblen = 1; - ops.oobretlen = 0; -- ops.ooboffs = mtd->ecclayout->oobavail; -+ ops.ooboffs = mtd->oobavail; - ops.datbuf = NULL; - ops.oobbuf = writebuf; - pr_info("attempting to start write past end of OOB\n"); -@@ -521,7 +521,7 @@ static int __init mtd_oobtest_init(void) - ops.retlen = 0; - ops.ooblen = 1; - ops.oobretlen = 0; -- ops.ooboffs = mtd->ecclayout->oobavail; -+ ops.ooboffs = mtd->oobavail; - ops.datbuf = NULL; - ops.oobbuf = readbuf; - pr_info("attempting to start read past end of OOB\n"); -@@ -543,7 +543,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail + 1; -+ ops.ooblen = mtd->oobavail + 1; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -563,7 +563,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail + 1; -+ ops.ooblen = mtd->oobavail + 1; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -587,7 +587,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.oobretlen = 0; - ops.ooboffs = 1; - ops.datbuf = NULL; -@@ -607,7 +607,7 @@ static int __init mtd_oobtest_init(void) - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail; -+ ops.ooblen = mtd->oobavail; - ops.oobretlen = 0; - ops.ooboffs = 1; - ops.datbuf = NULL; -@@ -638,7 +638,7 @@ static int __init mtd_oobtest_init(void) - for (i = 0; i < ebcnt - 1; ++i) { - int cnt = 2; - int pg; -- size_t sz = mtd->ecclayout->oobavail; -+ size_t sz = mtd->oobavail; - if (bbt[i] || bbt[i + 1]) - continue; - addr = (loff_t)(i + 1) * mtd->erasesize - mtd->writesize; -@@ -673,13 +673,12 @@ static int __init mtd_oobtest_init(void) - for (i = 0; i < ebcnt - 1; ++i) { - if (bbt[i] || bbt[i + 1]) - continue; -- prandom_bytes_state(&rnd_state, writebuf, -- mtd->ecclayout->oobavail * 2); -+ prandom_bytes_state(&rnd_state, writebuf, mtd->oobavail * 2); - addr = (loff_t)(i + 1) * mtd->erasesize - mtd->writesize; - ops.mode = MTD_OPS_AUTO_OOB; - ops.len = 0; - ops.retlen = 0; -- ops.ooblen = mtd->ecclayout->oobavail * 2; -+ ops.ooblen = mtd->oobavail * 2; - ops.oobretlen = 0; - ops.ooboffs = 0; - ops.datbuf = NULL; -@@ -688,7 +687,7 @@ static int __init mtd_oobtest_init(void) - if (err) - goto out; - if (memcmpshow(addr, readbuf, writebuf, -- mtd->ecclayout->oobavail * 2)) { -+ mtd->oobavail * 2)) { - pr_err("error: verify failed at %#llx\n", - (long long)addr); - errcnt += 1; ---- a/drivers/mtd/tests/pagetest.c -+++ b/drivers/mtd/tests/pagetest.c -@@ -127,13 +127,12 @@ static int crosstest(void) - unsigned char *pp1, *pp2, *pp3, *pp4; - - pr_info("crosstest\n"); -- pp1 = kmalloc(pgsize * 4, GFP_KERNEL); -+ pp1 = kzalloc(pgsize * 4, GFP_KERNEL); - if (!pp1) - return -ENOMEM; - pp2 = pp1 + pgsize; - pp3 = pp2 + pgsize; - pp4 = pp3 + pgsize; -- memset(pp1, 0, pgsize * 4); - - addr0 = 0; - for (i = 0; i < ebcnt && bbt[i]; ++i) ---- a/include/linux/mtd/bbm.h -+++ b/include/linux/mtd/bbm.h -@@ -166,7 +166,6 @@ struct bbm_info { - }; - - /* OneNAND BBT interface */ --extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); - extern int onenand_default_bbt(struct mtd_info *mtd); - - #endif /* __LINUX_MTD_BBM_H */ ---- a/include/linux/mtd/fsmc.h -+++ b/include/linux/mtd/fsmc.h -@@ -103,24 +103,6 @@ - - #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) - --/* -- * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 -- * and it has to be read consecutively and immediately after the 512 -- * byte data block for hardware to generate the error bit offsets -- * Managing the ecc bytes in the following way is easier. This way is -- * similar to oobfree structure maintained already in u-boot nand driver -- */ --#define MAX_ECCPLACE_ENTRIES 32 -- --struct fsmc_nand_eccplace { -- uint8_t offset; -- uint8_t length; --}; -- --struct fsmc_eccplace { -- struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; --}; -- - struct fsmc_nand_timings { - uint8_t tclr; - uint8_t tar; ---- a/include/linux/mtd/inftl.h -+++ b/include/linux/mtd/inftl.h -@@ -44,7 +44,6 @@ struct INFTLrecord { - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ - struct erase_info instr; -- struct nand_ecclayout oobinfo; - }; - - int INFTL_mount(struct INFTLrecord *s); ---- a/include/linux/mtd/map.h -+++ b/include/linux/mtd/map.h -@@ -137,7 +137,9 @@ - #endif - - #ifndef map_bankwidth -+#ifdef CONFIG_MTD - #warning "No CONFIG_MTD_MAP_BANK_WIDTH_xx selected. No NOR chip support can work" -+#endif - static inline int map_bankwidth(void *map) - { - BUG(); -@@ -233,8 +235,11 @@ struct map_info { - If there is no cache to care about this can be set to NULL. */ - void (*inval_cache)(struct map_info *, unsigned long, ssize_t); - -- /* set_vpp() must handle being reentered -- enable, enable, disable -- must leave it enabled. */ -+ /* This will be called with 1 as parameter when the first map user -+ * needs VPP, and called with 0 when the last user exits. The map -+ * core maintains a reference counter, and assumes that VPP is a -+ * global resource applying to all mapped flash chips on the system. -+ */ - void (*set_vpp)(struct map_info *, int); - - unsigned long pfow_base; ---- a/include/linux/mtd/mtd.h -+++ b/include/linux/mtd/mtd.h -@@ -100,17 +100,35 @@ struct mtd_oob_ops { - - #define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 - #define MTD_MAX_ECCPOS_ENTRIES_LARGE 640 -+/** -+ * struct mtd_oob_region - oob region definition -+ * @offset: region offset -+ * @length: region length -+ * -+ * This structure describes a region of the OOB area, and is used -+ * to retrieve ECC or free bytes sections. -+ * Each section is defined by an offset within the OOB area and a -+ * length. -+ */ -+struct mtd_oob_region { -+ u32 offset; -+ u32 length; -+}; -+ - /* -- * Internal ECC layout control structure. For historical reasons, there is a -- * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained -- * for export to user-space via the ECCGETLAYOUT ioctl. -- * nand_ecclayout should be expandable in the future simply by the above macros. -+ * struct mtd_ooblayout_ops - NAND OOB layout operations -+ * @ecc: function returning an ECC region in the OOB area. -+ * Should return -ERANGE if %section exceeds the total number of -+ * ECC sections. -+ * @free: function returning a free region in the OOB area. -+ * Should return -ERANGE if %section exceeds the total number of -+ * free sections. - */ --struct nand_ecclayout { -- __u32 eccbytes; -- __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; -- __u32 oobavail; -- struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; -+struct mtd_ooblayout_ops { -+ int (*ecc)(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc); -+ int (*free)(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree); - }; - - struct module; /* only needed for owner field in mtd_info */ -@@ -171,8 +189,8 @@ struct mtd_info { - const char *name; - int index; - -- /* ECC layout structure pointer - read only! */ -- struct nand_ecclayout *ecclayout; -+ /* OOB layout description */ -+ const struct mtd_ooblayout_ops *ooblayout; - - /* the ecc step size. */ - unsigned int ecc_step_size; -@@ -258,6 +276,46 @@ struct mtd_info { - int usecount; - }; - -+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobecc); -+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte, -+ int *section, -+ struct mtd_oob_region *oobregion); -+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf, -+ const u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf, -+ u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *oobfree); -+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf, -+ const u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf, -+ u8 *oobbuf, int start, int nbytes); -+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd); -+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd); -+ -+static inline void mtd_set_ooblayout(struct mtd_info *mtd, -+ const struct mtd_ooblayout_ops *ooblayout) -+{ -+ mtd->ooblayout = ooblayout; -+} -+ -+static inline void mtd_set_of_node(struct mtd_info *mtd, -+ struct device_node *np) -+{ -+ mtd->dev.of_node = np; -+} -+ -+static inline struct device_node *mtd_get_of_node(struct mtd_info *mtd) -+{ -+ return mtd->dev.of_node; -+} -+ -+static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops) -+{ -+ return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize; -+} -+ - int mtd_erase(struct mtd_info *mtd, struct erase_info *instr); - int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, - void **virt, resource_size_t *phys); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -119,6 +119,12 @@ typedef enum { - NAND_ECC_SOFT_BCH, - } nand_ecc_modes_t; - -+enum nand_ecc_algo { -+ NAND_ECC_UNKNOWN, -+ NAND_ECC_HAMMING, -+ NAND_ECC_BCH, -+}; -+ - /* - * Constants for Hardware ECC - */ -@@ -129,6 +135,14 @@ typedef enum { - /* Enable Hardware ECC before syndrome is read back from flash */ - #define NAND_ECC_READSYN 2 - -+/* -+ * Enable generic NAND 'page erased' check. This check is only done when -+ * ecc.correct() returns -EBADMSG. -+ * Set this flag if your implementation does not fix bitflips in erased -+ * pages and you want to rely on the default implementation. -+ */ -+#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) -+ - /* Bit mask for flags passed to do_nand_read_ecc */ - #define NAND_GET_DEVICE 0x80 - -@@ -160,6 +174,12 @@ typedef enum { - /* Device supports subpage reads */ - #define NAND_SUBPAGE_READ 0x00001000 - -+/* -+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated -+ * patterns. -+ */ -+#define NAND_NEED_SCRAMBLING 0x00002000 -+ - /* Options valid for Samsung large page devices */ - #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG - -@@ -276,15 +296,15 @@ struct nand_onfi_params { - __le16 t_r; - __le16 t_ccs; - __le16 src_sync_timing_mode; -- __le16 src_ssync_features; -+ u8 src_ssync_features; - __le16 clk_pin_capacitance_typ; - __le16 io_pin_capacitance_typ; - __le16 input_pin_capacitance_typ; - u8 input_pin_capacitance_max; - u8 driver_strength_support; - __le16 t_int_r; -- __le16 t_ald; -- u8 reserved4[7]; -+ __le16 t_adl; -+ u8 reserved4[8]; - - /* vendor */ - __le16 vendor_revision; -@@ -407,7 +427,7 @@ struct nand_jedec_params { - __le16 input_pin_capacitance_typ; - __le16 clk_pin_capacitance_typ; - u8 driver_strength_support; -- __le16 t_ald; -+ __le16 t_adl; - u8 reserved4[36]; - - /* ECC and endurance block */ -@@ -444,6 +464,7 @@ struct nand_hw_control { - /** - * struct nand_ecc_ctrl - Control structure for ECC - * @mode: ECC mode -+ * @algo: ECC algorithm - * @steps: number of ECC steps per page - * @size: data bytes per ECC step - * @bytes: ECC bytes per step -@@ -451,12 +472,18 @@ struct nand_hw_control { - * @total: total number of ECC bytes per page - * @prepad: padding information for syndrome based ECC generators - * @postpad: padding information for syndrome based ECC generators -- * @layout: ECC layout control struct pointer -+ * @options: ECC specific options (see NAND_ECC_XXX flags defined above) - * @priv: pointer to private ECC control data - * @hwctl: function to control hardware ECC generator. Must only - * be provided if an hardware ECC is available - * @calculate: function for ECC calculation or readback from ECC hardware -- * @correct: function for ECC correction, matching to ECC generator (sw/hw) -+ * @correct: function for ECC correction, matching to ECC generator (sw/hw). -+ * Should return a positive number representing the number of -+ * corrected bitflips, -EBADMSG if the number of bitflips exceed -+ * ECC strength, or any other error code if the error is not -+ * directly related to correction. -+ * If -EBADMSG is returned the input buffers should be left -+ * untouched. - * @read_page_raw: function to read a raw page without ECC. This function - * should hide the specific layout used by the ECC - * controller and always return contiguous in-band and -@@ -487,6 +514,7 @@ struct nand_hw_control { - */ - struct nand_ecc_ctrl { - nand_ecc_modes_t mode; -+ enum nand_ecc_algo algo; - int steps; - int size; - int bytes; -@@ -494,7 +522,7 @@ struct nand_ecc_ctrl { - int strength; - int prepad; - int postpad; -- struct nand_ecclayout *layout; -+ unsigned int options; - void *priv; - void (*hwctl)(struct mtd_info *mtd, int mode); - int (*calculate)(struct mtd_info *mtd, const uint8_t *dat, -@@ -540,11 +568,11 @@ struct nand_buffers { - - /** - * struct nand_chip - NAND Private Flash Chip Data -+ * @mtd: MTD device registered to the MTD framework - * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the - * flash device - * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the - * flash device. -- * @flash_node: [BOARDSPECIFIC] device node describing this instance - * @read_byte: [REPLACEABLE] read one byte from the chip - * @read_word: [REPLACEABLE] read one word from the chip - * @write_byte: [REPLACEABLE] write a single byte to the chip on the -@@ -640,18 +668,17 @@ struct nand_buffers { - */ - - struct nand_chip { -+ struct mtd_info mtd; - void __iomem *IO_ADDR_R; - void __iomem *IO_ADDR_W; - -- struct device_node *flash_node; -- - uint8_t (*read_byte)(struct mtd_info *mtd); - u16 (*read_word)(struct mtd_info *mtd); - void (*write_byte)(struct mtd_info *mtd, uint8_t byte); - void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); - void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); - void (*select_chip)(struct mtd_info *mtd, int chip); -- int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); -+ int (*block_bad)(struct mtd_info *mtd, loff_t ofs); - int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); - void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); - int (*dev_ready)(struct mtd_info *mtd); -@@ -719,6 +746,40 @@ struct nand_chip { - void *priv; - }; - -+extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; -+extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; -+ -+static inline void nand_set_flash_node(struct nand_chip *chip, -+ struct device_node *np) -+{ -+ mtd_set_of_node(&chip->mtd, np); -+} -+ -+static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) -+{ -+ return mtd_get_of_node(&chip->mtd); -+} -+ -+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) -+{ -+ return container_of(mtd, struct nand_chip, mtd); -+} -+ -+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) -+{ -+ return &chip->mtd; -+} -+ -+static inline void *nand_get_controller_data(struct nand_chip *chip) -+{ -+ return chip->priv; -+} -+ -+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) -+{ -+ chip->priv = priv; -+} -+ - /* - * NAND Flash Manufacturer ID Codes - */ -@@ -851,7 +912,6 @@ extern int nand_do_read(struct mtd_info - * @chip_delay: R/B delay value in us - * @options: Option flags, e.g. 16bit buswidth - * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH -- * @ecclayout: ECC layout info structure - * @part_probe_types: NULL-terminated array of probe types - */ - struct platform_nand_chip { -@@ -859,7 +919,6 @@ struct platform_nand_chip { - int chip_offset; - int nr_partitions; - struct mtd_partition *partitions; -- struct nand_ecclayout *ecclayout; - int chip_delay; - unsigned int options; - unsigned int bbt_options; -@@ -909,15 +968,6 @@ struct platform_nand_data { - struct platform_nand_ctrl ctrl; - }; - --/* Some helpers to access the data structures */ --static inline --struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) --{ -- struct nand_chip *chip = mtd->priv; -- -- return chip->priv; --} -- - /* return the supported features. */ - static inline int onfi_feature(struct nand_chip *chip) - { ---- a/include/linux/mtd/nand_bch.h -+++ b/include/linux/mtd/nand_bch.h -@@ -32,9 +32,7 @@ int nand_bch_correct_data(struct mtd_inf - /* - * Initialize BCH encoder/decoder - */ --struct nand_bch_control * --nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, -- unsigned int eccbytes, struct nand_ecclayout **ecclayout); -+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd); - /* - * Release BCH encoder/decoder resources - */ -@@ -55,12 +53,10 @@ static inline int - nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf, - unsigned char *read_ecc, unsigned char *calc_ecc) - { -- return -1; -+ return -ENOTSUPP; - } - --static inline struct nand_bch_control * --nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, -- unsigned int eccbytes, struct nand_ecclayout **ecclayout) -+static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd) - { - return NULL; - } ---- a/include/linux/mtd/nftl.h -+++ b/include/linux/mtd/nftl.h -@@ -50,7 +50,6 @@ struct NFTLrecord { - unsigned int nb_blocks; /* number of physical blocks */ - unsigned int nb_boot_blocks; /* number of blocks used by the bios */ - struct erase_info instr; -- struct nand_ecclayout oobinfo; - }; - - int NFTL_mount(struct NFTLrecord *s); ---- a/include/linux/mtd/onenand.h -+++ b/include/linux/mtd/onenand.h -@@ -80,7 +80,6 @@ struct onenand_bufferram { - * @page_buf: [INTERN] page main data buffer - * @oob_buf: [INTERN] page oob data buffer - * @subpagesize: [INTERN] holds the subpagesize -- * @ecclayout: [REPLACEABLE] the default ecc placement scheme - * @bbm: [REPLACEABLE] pointer to Bad Block Management - * @priv: [OPTIONAL] pointer to private chip date - */ -@@ -134,7 +133,6 @@ struct onenand_chip { - #endif - - int subpagesize; -- struct nand_ecclayout *ecclayout; - - void *bbm; - ---- a/include/linux/mtd/partitions.h -+++ b/include/linux/mtd/partitions.h -@@ -42,7 +42,6 @@ struct mtd_partition { - uint64_t size; /* partition size */ - uint64_t offset; /* offset within the master MTD space */ - uint32_t mask_flags; /* master MTD flags to mask out for this partition */ -- struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only) */ - }; - - #define MTDPART_OFS_RETAIN (-3) -@@ -56,11 +55,9 @@ struct device_node; - /** - * struct mtd_part_parser_data - used to pass data to MTD partition parsers. - * @origin: for RedBoot, start address of MTD device -- * @of_node: for OF parsers, device node containing partitioning information - */ - struct mtd_part_parser_data { - unsigned long origin; -- struct device_node *of_node; - }; - - -@@ -78,14 +75,34 @@ struct mtd_part_parser { - struct list_head list; - struct module *owner; - const char *name; -- int (*parse_fn)(struct mtd_info *, struct mtd_partition **, -+ int (*parse_fn)(struct mtd_info *, const struct mtd_partition **, - struct mtd_part_parser_data *); -+ void (*cleanup)(const struct mtd_partition *pparts, int nr_parts); - enum mtd_parser_type type; - }; - --extern void register_mtd_parser(struct mtd_part_parser *parser); -+/* Container for passing around a set of parsed partitions */ -+struct mtd_partitions { -+ const struct mtd_partition *parts; -+ int nr_parts; -+ const struct mtd_part_parser *parser; -+}; -+ -+extern int __register_mtd_parser(struct mtd_part_parser *parser, -+ struct module *owner); -+#define register_mtd_parser(parser) __register_mtd_parser(parser, THIS_MODULE) -+ - extern void deregister_mtd_parser(struct mtd_part_parser *parser); - -+/* -+ * module_mtd_part_parser() - Helper macro for MTD partition parsers that don't -+ * do anything special in module init/exit. Each driver may only use this macro -+ * once, and calling it replaces module_init() and module_exit(). -+ */ -+#define module_mtd_part_parser(__mtd_part_parser) \ -+ module_driver(__mtd_part_parser, register_mtd_parser, \ -+ deregister_mtd_parser) -+ - int mtd_is_partition(const struct mtd_info *mtd); - int mtd_add_partition(struct mtd_info *master, const char *name, - long long offset, long long length); ---- a/include/linux/mtd/sh_flctl.h -+++ b/include/linux/mtd/sh_flctl.h -@@ -143,7 +143,6 @@ enum flctl_ecc_res_t { - struct dma_chan; - - struct sh_flctl { -- struct mtd_info mtd; - struct nand_chip chip; - struct platform_device *pdev; - struct dev_pm_qos_request pm_qos; -@@ -187,7 +186,7 @@ struct sh_flctl_platform_data { - - static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo) - { -- return container_of(mtdinfo, struct sh_flctl, mtd); -+ return container_of(mtd_to_nand(mtdinfo), struct sh_flctl, chip); - } - - #endif /* __SH_FLCTL_H__ */ ---- a/include/linux/mtd/sharpsl.h -+++ b/include/linux/mtd/sharpsl.h -@@ -14,7 +14,7 @@ - - struct sharpsl_nand_platform_data { - struct nand_bbt_descr *badblock_pattern; -- struct nand_ecclayout *ecc_layout; -+ const struct mtd_ooblayout_ops *ecc_layout; - struct mtd_partition *partitions; - unsigned int nr_partitions; - }; ---- a/include/uapi/mtd/mtd-abi.h -+++ b/include/uapi/mtd/mtd-abi.h -@@ -228,7 +228,7 @@ struct nand_oobfree { - * complete set of ECC information. The ioctl truncates the larger internal - * structure to retain binary compatibility with the static declaration of the - * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of -- * the user struct, not the MAX size of the internal struct nand_ecclayout. -+ * the user struct, not the MAX size of the internal OOB layout representation. - */ - struct nand_ecclayout_user { - __u32 eccbytes; ---- a/fs/jffs2/wbuf.c -+++ b/fs/jffs2/wbuf.c -@@ -1153,7 +1153,7 @@ static struct jffs2_sb_info *work_to_sb( - { - struct delayed_work *dwork; - -- dwork = container_of(work, struct delayed_work, work); -+ dwork = to_delayed_work(work); - return container_of(dwork, struct jffs2_sb_info, wbuf_dwork); - } - -@@ -1183,22 +1183,20 @@ void jffs2_dirty_trigger(struct jffs2_sb - - int jffs2_nand_flash_setup(struct jffs2_sb_info *c) - { -- struct nand_ecclayout *oinfo = c->mtd->ecclayout; -- - if (!c->mtd->oobsize) - return 0; - - /* Cleanmarker is out-of-band, so inline size zero */ - c->cleanmarker_size = 0; - -- if (!oinfo || oinfo->oobavail == 0) { -+ if (c->mtd->oobavail == 0) { - pr_err("inconsistent device description\n"); - return -EINVAL; - } - - jffs2_dbg(1, "using OOB on NAND\n"); - -- c->oobavail = oinfo->oobavail; -+ c->oobavail = c->mtd->oobavail; - - /* Initialise write buffer */ - init_rwsem(&c->wbuf_sem); ---- a/include/linux/mtd/spi-nor.h -+++ b/include/linux/mtd/spi-nor.h -@@ -85,6 +85,7 @@ - #define SR_BP0 BIT(2) /* Block protect 0 */ - #define SR_BP1 BIT(3) /* Block protect 1 */ - #define SR_BP2 BIT(4) /* Block protect 2 */ -+#define SR_TB BIT(5) /* Top/Bottom protect */ - #define SR_SRWD BIT(7) /* SR write protect */ - - #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ -@@ -116,6 +117,7 @@ enum spi_nor_ops { - - enum spi_nor_option_flags { - SNOR_F_USE_FSR = BIT(0), -+ SNOR_F_HAS_SR_TB = BIT(1), - }; - - /** -@@ -123,7 +125,6 @@ enum spi_nor_option_flags { - * @mtd: point to a mtd_info structure - * @lock: the lock for the read/write/erase/lock/unlock operations - * @dev: point to a spi device, or a spi nor controller device. -- * @flash_node: point to a device node describing this flash instance. - * @page_size: the page size of the SPI NOR - * @addr_width: number of address bytes - * @erase_opcode: the opcode for erasing a sector -@@ -143,7 +144,8 @@ enum spi_nor_option_flags { - * @read: [DRIVER-SPECIFIC] read data from the SPI NOR - * @write: [DRIVER-SPECIFIC] write data to the SPI NOR - * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR -- * at the offset @offs -+ * at the offset @offs; if not provided by the driver, -+ * spi-nor will send the erase opcode via write_reg() - * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR - * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR - * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is -@@ -154,7 +156,6 @@ struct spi_nor { - struct mtd_info mtd; - struct mutex lock; - struct device *dev; -- struct device_node *flash_node; - u32 page_size; - u8 addr_width; - u8 erase_opcode; -@@ -184,6 +185,17 @@ struct spi_nor { - void *priv; - }; - -+static inline void spi_nor_set_flash_node(struct spi_nor *nor, -+ struct device_node *np) -+{ -+ mtd_set_of_node(&nor->mtd, np); -+} -+ -+static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor) -+{ -+ return mtd_get_of_node(&nor->mtd); -+} -+ - /** - * spi_nor_scan() - scan the SPI NOR - * @nor: the spi_nor structure diff --git a/target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch b/target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch deleted file mode 100644 index aa45441af..000000000 --- a/target/linux/oxnas/patches-4.4/0073-of-mtd-prepare-helper-reading-NAND-ECC-algo-from-DT.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 410a91f6efa1c4c3c4369d1dd2c31286749dff33 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Wed, 23 Mar 2016 11:19:01 +0100 -Subject: [PATCH 073/102] of: mtd: prepare helper reading NAND ECC algo from - DT -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -NAND subsystem is being slightly reworked to store ECC details in -separated fields. In future we'll want to add support for more DT -properties as specifying every possible setup with a single -"nand-ecc-mode" is a pretty bad idea. -To allow this let's add a helper that will support something like -"nand-ecc-algo" in future. Right now we use it for keeping backward -compatibility. - -Signed-off-by: Rafał Miłecki -Signed-off-by: Boris Brezillon ---- - drivers/of/of_mtd.c | 36 ++++++++++++++++++++++++++++++++++++ - include/linux/of_mtd.h | 6 ++++++ - 2 files changed, 42 insertions(+) - ---- a/drivers/of/of_mtd.c -+++ b/drivers/of/of_mtd.c -@@ -50,6 +50,42 @@ int of_get_nand_ecc_mode(struct device_n - EXPORT_SYMBOL_GPL(of_get_nand_ecc_mode); - - /** -+ * of_get_nand_ecc_algo - Get nand ecc algorithm for given device_node -+ * @np: Pointer to the given device_node -+ * -+ * The function gets ecc algorithm and returns its enum value, or errno in error -+ * case. -+ */ -+int of_get_nand_ecc_algo(struct device_node *np) -+{ -+ const char *pm; -+ int err; -+ -+ /* -+ * TODO: Read ECC algo OF property and map it to enum nand_ecc_algo. -+ * It's not implemented yet as currently NAND subsystem ignores -+ * algorithm explicitly set this way. Once it's handled we should -+ * document & support new property. -+ */ -+ -+ /* -+ * For backward compatibility we also read "nand-ecc-mode" checking -+ * for some obsoleted values that were specifying ECC algorithm. -+ */ -+ err = of_property_read_string(np, "nand-ecc-mode", &pm); -+ if (err < 0) -+ return err; -+ -+ if (!strcasecmp(pm, "soft")) -+ return NAND_ECC_HAMMING; -+ else if (!strcasecmp(pm, "soft_bch")) -+ return NAND_ECC_BCH; -+ -+ return -ENODEV; -+} -+EXPORT_SYMBOL_GPL(of_get_nand_ecc_algo); -+ -+/** - * of_get_nand_ecc_step_size - Get ECC step size associated to - * the required ECC strength (see below). - * @np: Pointer to the given device_node ---- a/include/linux/of_mtd.h -+++ b/include/linux/of_mtd.h -@@ -13,6 +13,7 @@ - - #include - int of_get_nand_ecc_mode(struct device_node *np); -+int of_get_nand_ecc_algo(struct device_node *np); - int of_get_nand_ecc_step_size(struct device_node *np); - int of_get_nand_ecc_strength(struct device_node *np); - int of_get_nand_bus_width(struct device_node *np); -@@ -24,6 +25,11 @@ static inline int of_get_nand_ecc_mode(s - { - return -ENOSYS; - } -+ -+static inline int of_get_nand_ecc_algo(struct device_node *np) -+{ -+ return -ENOSYS; -+} - - static inline int of_get_nand_ecc_step_size(struct device_node *np) - { diff --git a/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch b/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch deleted file mode 100644 index 8ff28b3bc..000000000 --- a/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch +++ /dev/null @@ -1,175 +0,0 @@ -From d45bc58dd3bdcaabc1d7d8d9b0b8dee826635cc6 Mon Sep 17 00:00:00 2001 -From: Marc Gonzalez -Date: Wed, 27 Jul 2016 11:23:52 +0200 -Subject: [PATCH] mtd: nand: import nand_hw_control_init() - -The code to initialize a struct nand_hw_control is duplicated across -several drivers. Factorize it using an inline function. - -Signed-off-by: Marc Gonzalez -Signed-off-by: Boris Brezillon ---- - drivers/mtd/nand/bf5xx_nand.c | 3 +-- - drivers/mtd/nand/brcmnand/brcmnand.c | 3 +-- - drivers/mtd/nand/docg4.c | 3 +-- - drivers/mtd/nand/fsl_elbc_nand.c | 3 +-- - drivers/mtd/nand/fsl_ifc_nand.c | 3 +-- - drivers/mtd/nand/jz4780_nand.c | 3 +-- - drivers/mtd/nand/nand_base.c | 3 +-- - drivers/mtd/nand/ndfc.c | 3 +-- - drivers/mtd/nand/pxa3xx_nand.c | 3 +-- - drivers/mtd/nand/qcom_nandc.c | 3 +-- - drivers/mtd/nand/s3c2410.c | 3 +-- - drivers/mtd/nand/sunxi_nand.c | 3 +-- - drivers/mtd/nand/txx9ndfmc.c | 3 +-- - include/linux/mtd/nand.h | 7 +++++++ - 14 files changed, 20 insertions(+), 26 deletions(-) - ---- a/drivers/mtd/nand/bf5xx_nand.c -+++ b/drivers/mtd/nand/bf5xx_nand.c -@@ -748,8 +748,7 @@ static int bf5xx_nand_probe(struct platf - - platform_set_drvdata(pdev, info); - -- spin_lock_init(&info->controller.lock); -- init_waitqueue_head(&info->controller.wq); -+ nand_hw_control_init(&info->controller); - - info->device = &pdev->dev; - info->platform = plat; ---- a/drivers/mtd/nand/brcmnand/brcmnand.c -+++ b/drivers/mtd/nand/brcmnand/brcmnand.c -@@ -2149,8 +2149,7 @@ int brcmnand_probe(struct platform_devic - - init_completion(&ctrl->done); - init_completion(&ctrl->dma_done); -- spin_lock_init(&ctrl->controller.lock); -- init_waitqueue_head(&ctrl->controller.wq); -+ nand_hw_control_init(&ctrl->controller); - INIT_LIST_HEAD(&ctrl->host_list); - - /* NAND register range */ ---- a/drivers/mtd/nand/docg4.c -+++ b/drivers/mtd/nand/docg4.c -@@ -1227,8 +1227,7 @@ static void __init init_mtd_structs(stru - nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE; - nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA; - nand->controller = &nand->hwcontrol; -- spin_lock_init(&nand->controller->lock); -- init_waitqueue_head(&nand->controller->wq); -+ nand_hw_control_init(nand->controller); - - /* methods */ - nand->cmdfunc = docg4_command; ---- a/drivers/mtd/nand/fsl_elbc_nand.c -+++ b/drivers/mtd/nand/fsl_elbc_nand.c -@@ -866,8 +866,7 @@ static int fsl_elbc_nand_probe(struct pl - } - elbc_fcm_ctrl->counter++; - -- spin_lock_init(&elbc_fcm_ctrl->controller.lock); -- init_waitqueue_head(&elbc_fcm_ctrl->controller.wq); -+ nand_hw_control_init(&elbc_fcm_ctrl->controller); - fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; - } else { - elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; ---- a/drivers/mtd/nand/fsl_ifc_nand.c -+++ b/drivers/mtd/nand/fsl_ifc_nand.c -@@ -1073,8 +1073,7 @@ static int fsl_ifc_nand_probe(struct pla - ifc_nand_ctrl->addr = NULL; - fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; - -- spin_lock_init(&ifc_nand_ctrl->controller.lock); -- init_waitqueue_head(&ifc_nand_ctrl->controller.wq); -+ nand_hw_control_init(&ifc_nand_ctrl->controller); - } else { - ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; - } ---- a/drivers/mtd/nand/nand_base.c -+++ b/drivers/mtd/nand/nand_base.c -@@ -3208,8 +3208,7 @@ static void nand_set_defaults(struct nan - - if (!chip->controller) { - chip->controller = &chip->hwcontrol; -- spin_lock_init(&chip->controller->lock); -- init_waitqueue_head(&chip->controller->wq); -+ nand_hw_control_init(chip->controller); - } - - } ---- a/drivers/mtd/nand/ndfc.c -+++ b/drivers/mtd/nand/ndfc.c -@@ -220,8 +220,7 @@ static int ndfc_probe(struct platform_de - ndfc = &ndfc_ctrl[cs]; - ndfc->chip_select = cs; - -- spin_lock_init(&ndfc->ndfc_control.lock); -- init_waitqueue_head(&ndfc->ndfc_control.wq); -+ nand_hw_control_init(&ndfc->ndfc_control); - ndfc->ofdev = ofdev; - dev_set_drvdata(&ofdev->dev, ndfc); - ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -1739,8 +1739,7 @@ static int alloc_nand_resource(struct pl - chip->cmdfunc = nand_cmdfunc; - } - -- spin_lock_init(&chip->controller->lock); -- init_waitqueue_head(&chip->controller->wq); -+ nand_hw_control_init(chip->controller); - info->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(info->clk)) { - dev_err(&pdev->dev, "failed to get nand clock\n"); ---- a/drivers/mtd/nand/s3c2410.c -+++ b/drivers/mtd/nand/s3c2410.c -@@ -955,8 +955,7 @@ static int s3c24xx_nand_probe(struct pla - - platform_set_drvdata(pdev, info); - -- spin_lock_init(&info->controller.lock); -- init_waitqueue_head(&info->controller.wq); -+ nand_hw_control_init(&info->controller); - - /* get the clock source and enable it */ - ---- a/drivers/mtd/nand/sunxi_nand.c -+++ b/drivers/mtd/nand/sunxi_nand.c -@@ -1432,8 +1432,7 @@ static int sunxi_nfc_probe(struct platfo - return -ENOMEM; - - nfc->dev = dev; -- spin_lock_init(&nfc->controller.lock); -- init_waitqueue_head(&nfc->controller.wq); -+ nand_hw_control_init(&nfc->controller); - INIT_LIST_HEAD(&nfc->chips); - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ---- a/drivers/mtd/nand/txx9ndfmc.c -+++ b/drivers/mtd/nand/txx9ndfmc.c -@@ -304,8 +304,7 @@ static int __init txx9ndfmc_probe(struct - dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", - (gbusclk + 500000) / 1000000, hold, spw); - -- spin_lock_init(&drvdata->hw_control.lock); -- init_waitqueue_head(&drvdata->hw_control.wq); -+ nand_hw_control_init(&drvdata->hw_control); - - platform_set_drvdata(dev, drvdata); - txx9ndfmc_initialize(dev); ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -461,6 +461,13 @@ struct nand_hw_control { - wait_queue_head_t wq; - }; - -+static inline void nand_hw_control_init(struct nand_hw_control *nfc) -+{ -+ nfc->active = NULL; -+ spin_lock_init(&nfc->lock); -+ init_waitqueue_head(&nfc->wq); -+} -+ - /** - * struct nand_ecc_ctrl - Control structure for ECC - * @mode: ECC mode diff --git a/target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch b/target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch deleted file mode 100644 index 024675e59..000000000 --- a/target/linux/oxnas/patches-4.4/010-arm_introduce-dma-fiq-irq-broadcast.patch +++ /dev/null @@ -1,80 +0,0 @@ ---- a/arch/arm/include/asm/glue-cache.h -+++ b/arch/arm/include/asm/glue-cache.h -@@ -156,9 +156,15 @@ static inline void nop_dma_unmap_area(co - #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) - #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) - #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) --#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) - --#define dmac_flush_range __glue(_CACHE,_dma_flush_range) -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+# define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) -+# define dmac_flush_range __glue(_CACHE,_dma_flush_range) -+#else -+# define __cpuc_flush_dcache_area __glue(fiq,_flush_kern_dcache_area) -+# define dmac_flush_range __glue(fiq,_dma_flush_range) -+#endif -+ - #endif - - #endif ---- a/arch/arm/mm/Kconfig -+++ b/arch/arm/mm/Kconfig -@@ -866,6 +866,17 @@ config DMA_CACHE_RWFO - in hardware, other workarounds are needed (e.g. cache - maintenance broadcasting in software via FIQ). - -+config DMA_CACHE_FIQ_BROADCAST -+ bool "Enable fiq broadcast DMA cache maintenance" -+ depends on CPU_V6K && SMP -+ select FIQ -+ help -+ The Snoop Control Unit on ARM11MPCore does not detect the -+ cache maintenance operations and the dma_{map,unmap}_area() -+ functions may leave stale cache entries on other CPUs. By -+ enabling this option, fiq broadcast in the ARMv6 -+ DMA cache maintenance functions is performed. -+ - config OUTER_CACHE - bool - ---- a/arch/arm/mm/flush.c -+++ b/arch/arm/mm/flush.c -@@ -319,6 +319,7 @@ void __sync_icache_dcache(pte_t pteval) - void flush_dcache_page(struct page *page) - { - struct address_space *mapping; -+ bool skip_broadcast = true; - - /* - * The zero page is never written to, so never has any dirty -@@ -329,7 +330,10 @@ void flush_dcache_page(struct page *page - - mapping = page_mapping(page); - -- if (!cache_ops_need_broadcast() && -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+ skip_broadcast = !cache_ops_need_broadcast(); -+#endif -+ if (skip_broadcast && - mapping && !page_mapped(page)) - clear_bit(PG_dcache_clean, &page->flags); - else { ---- a/arch/arm/mm/dma.h -+++ b/arch/arm/mm/dma.h -@@ -4,8 +4,13 @@ - #include - - #ifndef MULTI_CACHE --#define dmac_map_area __glue(_CACHE,_dma_map_area) --#define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -+#ifndef CONFIG_DMA_CACHE_FIQ_BROADCAST -+# define dmac_map_area __glue(_CACHE,_dma_map_area) -+# define dmac_unmap_area __glue(_CACHE,_dma_unmap_area) -+#else -+# define dmac_map_area __glue(fiq,_dma_map_area) -+# define dmac_unmap_area __glue(fiq,_dma_unmap_area) -+#endif - - /* - * These are private to the dma-mapping API. Do not use directly. diff --git a/target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch b/target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch deleted file mode 100644 index a94ac2277..000000000 --- a/target/linux/oxnas/patches-4.4/250-add-plxtech-vendor-prefix.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/Documentation/devicetree/bindings/vendor-prefixes.txt -+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt -@@ -175,6 +175,7 @@ picochip Picochip Ltd - plathome Plat'Home Co., Ltd. - plda PLDA - pixcir PIXCIR MICROELECTRONICS Co., Ltd -+plxtech PLX Technology, Inc. - pulsedlight PulsedLight, Inc - powervr PowerVR (deprecated, use img) - qca Qualcomm Atheros, Inc. diff --git a/target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch b/target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch deleted file mode 100644 index a88d5d94b..000000000 --- a/target/linux/oxnas/patches-4.4/300-introduce-oxnas-platform.patch +++ /dev/null @@ -1,71 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -603,6 +603,19 @@ config ARCH_LPC32XX - help - Support for the NXP LPC32XX family of processors - -+config ARCH_OXNAS -+ bool "Oxford Semiconductor 815/820/825 NAS SoC" -+ select ARM_GIC -+ select ARCH_REQUIRE_GPIOLIB -+ select CLKDEV_LOOKUP -+ select GENERIC_CLOCKEVENTS -+ select COMMON_CLK -+ select MIGHT_HAVE_PCI -+ select ARCH_HAS_RESET_CONTROLLER -+ help -+ This enables support for Oxford 815/820/825 NAS SoC -+ later renamed to PLXTECH NAS782x. -+ - config ARCH_PXA - bool "PXA2xx/PXA3xx-based" - depends on MMU -@@ -883,6 +896,8 @@ source "arch/arm/mach-omap2/Kconfig" - - source "arch/arm/mach-orion5x/Kconfig" - -+source "arch/arm/mach-oxnas/Kconfig" -+ - source "arch/arm/mach-picoxcell/Kconfig" - - source "arch/arm/mach-pxa/Kconfig" ---- a/arch/arm/Makefile -+++ b/arch/arm/Makefile -@@ -200,6 +200,7 @@ machine-$(CONFIG_ARCH_NSPIRE) += nspire - machine-$(CONFIG_ARCH_OMAP1) += omap1 - machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 - machine-$(CONFIG_ARCH_ORION5X) += orion5x -+machine-$(CONFIG_ARCH_OXNAS) += oxnas - machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell - machine-$(CONFIG_ARCH_PXA) += pxa - machine-$(CONFIG_ARCH_QCOM) += qcom ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -497,6 +497,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-rd88f5182-nas.dtb -+dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb - dtb-$(CONFIG_ARCH_PRIMA2) += \ - prima2-evb.dtb - dtb-$(CONFIG_ARCH_QCOM) += \ ---- a/arch/arm/tools/mach-types -+++ b/arch/arm/tools/mach-types -@@ -228,6 +228,7 @@ edb9302a MACH_EDB9302A EDB9302A 1127 - edb9307a MACH_EDB9307A EDB9307A 1128 - omap_3430sdp MACH_OMAP_3430SDP OMAP_3430SDP 1138 - vstms MACH_VSTMS VSTMS 1140 -+ox820 MACH_OX820 OX820 1152 - micro9m MACH_MICRO9M MICRO9M 1169 - bug MACH_BUG BUG 1179 - at91sam9263ek MACH_AT91SAM9263EK AT91SAM9263EK 1202 ---- a/drivers/clk/Makefile -+++ b/drivers/clk/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s - obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o - obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o - obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o -+obj-$(CONFIG_ARCH_OXNAS) += clk-oxnas.o - obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o - obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o - obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o diff --git a/target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch b/target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch deleted file mode 100644 index efb058dbb..000000000 --- a/target/linux/oxnas/patches-4.4/310-oxnas-clocksource.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/clocksource/Kconfig -+++ b/drivers/clocksource/Kconfig -@@ -222,6 +222,12 @@ config VF_PIT_TIMER - help - Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. - -+config CLKSRC_RPS_TIMER -+ def_bool y if ARCH_OXNAS -+ select CLKSRC_MMIO -+ help -+ This option enables support for the oxnas rps timers. -+ - config SYS_SUPPORTS_SH_CMT - bool - ---- a/drivers/clocksource/Makefile -+++ b/drivers/clocksource/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exyno - obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o - obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o - obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o -+obj-$(CONFIG_CLKSRC_RPS_TIMER) += oxnas_rps_timer.o - obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o - obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o - obj-$(CONFIG_MTK_TIMER) += mtk_timer.o diff --git a/target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch b/target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch deleted file mode 100644 index 37918d680..000000000 --- a/target/linux/oxnas/patches-4.4/320-oxnas-irqchip.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/irqchip/Kconfig -+++ b/drivers/irqchip/Kconfig -@@ -27,6 +27,11 @@ config ARM_GIC_V3_ITS - bool - select PCI_MSI_IRQ_DOMAIN - -+config PLXTECH_RPS -+ def_bool y if ARHC_OXNAS -+ depends on ARCH_OXNAS -+ select IRQ_DOMAIN -+ - config ARM_NVIC - bool - select IRQ_DOMAIN ---- a/drivers/irqchip/Makefile -+++ b/drivers/irqchip/Makefile -@@ -34,6 +34,7 @@ obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips- - obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o - obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o - obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o -+obj-$(CONFIG_PLXTECH_RPS) += irq-rps.o - obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o - obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o - obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o ---- a/drivers/irqchip/irq-gic.c -+++ b/drivers/irqchip/irq-gic.c -@@ -1253,6 +1253,7 @@ IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm, - IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); - IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); - IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); -+IRQCHIP_DECLARE(arm11_mpcore_gic, "arm,arm11mp-gic", gic_of_init); - IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); - IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); - IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); diff --git a/target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch b/target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch deleted file mode 100644 index 76a19267a..000000000 --- a/target/linux/oxnas/patches-4.4/330-oxnas-pinctrl.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/pinctrl/Kconfig -+++ b/drivers/pinctrl/Kconfig -@@ -228,6 +228,15 @@ config PINCTRL_COH901 - COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 - ports of 8 GPIO pins each. - -+config PINCTRL_OXNAS -+ bool "OXNAS pinctrl driver" -+ depends on OF -+ depends on ARCH_OXNAS -+ select PINMUX -+ select PINCONF -+ help -+ Say Y here to enable the oxnas pinctrl driver -+ - config PINCTRL_PALMAS - bool "Pinctrl driver for the PALMAS Series MFD devices" - depends on OF && MFD_PALMAS ---- a/drivers/pinctrl/Makefile -+++ b/drivers/pinctrl/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd - obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o - obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o - obj-$(CONFIG_PINCTRL_MESON) += meson/ -+obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o - obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o - obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o - obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o diff --git a/target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch b/target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch deleted file mode 100644 index edc23b70a..000000000 --- a/target/linux/oxnas/patches-4.4/340-oxnas-pcie.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/pci/host/Kconfig -+++ b/drivers/pci/host/Kconfig -@@ -173,4 +173,9 @@ config PCI_HISI - help - Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC - -+config PCI_OXNAS -+ bool "PLX Oxnas PCIe controller" -+ depends on ARCH_OXNAS -+ select PCIEPORTBUS -+ - endmenu ---- a/drivers/pci/host/Makefile -+++ b/drivers/pci/host/Makefile -@@ -3,6 +3,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o - obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o - obj-$(CONFIG_PCI_IMX6) += pci-imx6.o - obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o -+obj-$(CONFIG_PCI_OXNAS) += pcie-oxnas.o - obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o - obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o - obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o diff --git a/target/linux/oxnas/patches-4.4/350-oxnas-reset.patch b/target/linux/oxnas/patches-4.4/350-oxnas-reset.patch deleted file mode 100644 index e9aaf4b43..000000000 --- a/target/linux/oxnas/patches-4.4/350-oxnas-reset.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/reset/Kconfig -+++ b/drivers/reset/Kconfig -@@ -12,4 +12,9 @@ menuconfig RESET_CONTROLLER - - If unsure, say no. - -+config RESET_CONTROLLER_OXNAS -+ bool -+ select RESET_CONTROLLER -+ - source "drivers/reset/sti/Kconfig" -+ ---- a/drivers/reset/Makefile -+++ b/drivers/reset/Makefile -@@ -1,4 +1,5 @@ - obj-$(CONFIG_RESET_CONTROLLER) += core.o -+obj-$(CONFIG_RESET_CONTROLLER_OXNAS) += reset-ox820.o - obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o - obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o - obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o diff --git a/target/linux/oxnas/patches-4.4/400-oxnas-nand.patch b/target/linux/oxnas/patches-4.4/400-oxnas-nand.patch deleted file mode 100644 index fbc3edbbe..000000000 --- a/target/linux/oxnas/patches-4.4/400-oxnas-nand.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/mtd/nand/Kconfig -+++ b/drivers/mtd/nand/Kconfig -@@ -563,4 +563,11 @@ config MTD_NAND_QCOM - Enables support for NAND flash chips on SoCs containing the EBI2 NAND - controller. This controller is found on IPQ806x SoC. - -+config MTD_NAND_OXNAS -+ tristate "Support for NAND on Plxtech NAS782X SoC" -+ depends on ARCH_OXNAS -+ help -+ Enables support for NAND Flash chips on Plxtech NAS782X SoCs. NAND is attached -+ to the STATIC Unit. -+ - endif # MTD_NAND ---- a/drivers/mtd/nand/Makefile -+++ b/drivers/mtd/nand/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socr - obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o - obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o - obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o -+obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o - obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o - obj-$(CONFIG_MTD_NAND_RICOH) += r852.o - obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o diff --git a/target/linux/oxnas/patches-4.4/500-oxnas-sata.patch b/target/linux/oxnas/patches-4.4/500-oxnas-sata.patch deleted file mode 100644 index b833b635a..000000000 --- a/target/linux/oxnas/patches-4.4/500-oxnas-sata.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/ata/Kconfig -+++ b/drivers/ata/Kconfig -@@ -432,6 +432,13 @@ config SATA_VITESSE - - If unsure, say N. - -+config SATA_OXNAS -+ tristate "PLXTECH NAS782X SATA support" -+ help -+ This option enables support for Nas782x Serial ATA controller. -+ -+ If unsure, say N. -+ - comment "PATA SFF controllers with BMDMA" - - config PATA_ALI ---- a/drivers/ata/Makefile -+++ b/drivers/ata/Makefile -@@ -40,6 +40,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o - obj-$(CONFIG_SATA_ULI) += sata_uli.o - obj-$(CONFIG_SATA_VIA) += sata_via.o - obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o -+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o - - # SFF PATA w/ BMDMA - obj-$(CONFIG_PATA_ALI) += pata_ali.o diff --git a/target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch b/target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch deleted file mode 100644 index 5de25d2e8..000000000 --- a/target/linux/oxnas/patches-4.4/700-oxnas-dwmac.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -69,6 +69,16 @@ config DWMAC_MESON - the stmmac device driver. This driver is used for Meson6 and - Meson8 SoCs. - -+config DWMAC_OXNAS -+ tristate "Oxnas gmac support" -+ default ARCH_OXNAS -+ depends on OF && ARCH_OXNAS -+ help -+ Support for Ethernet controller on Oxnas SoCs. -+ -+ This selects the Oxford OX82x SoC glue layer support for -+ the stmmac device driver. -+ - config DWMAC_ROCKCHIP - tristate "Rockchip dwmac support" - default ARCH_ROCKCHIP ---- a/drivers/net/ethernet/stmicro/stmmac/Makefile -+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac- - obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o - obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o - obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o -+obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o - obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o - obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-socfpga.o - obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o diff --git a/target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch b/target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch deleted file mode 100644 index 7f26de6b1..000000000 --- a/target/linux/oxnas/patches-4.4/800-oxnas-ehci.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -315,6 +315,13 @@ config USB_OCTEON_EHCI - USB 2.0 device support. All CN6XXX based chips with USB are - supported. - -+config USB_EHCI_OXNAS -+ tristate "OXNAS EHCI Module" -+ depends on USB_EHCI_HCD && ARCH_OXNAS -+ select USB_EHCI_ROOT_HUB_TT -+ ---help--- -+ Enable support for the OX820 SOC's on-chip EHCI controller. -+ - endif # USB_EHCI_HCD - - config USB_OXU210HP_HCD ---- a/drivers/usb/host/Makefile -+++ b/drivers/usb/host/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci- - obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o - obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o - obj-$(CONFIG_USB_W90X900_EHCI) += ehci-w90x900.o -+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o - - obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o - obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o diff --git a/target/linux/oxnas/patches-4.4/900-more-boards.patch b/target/linux/oxnas/patches-4.4/900-more-boards.patch deleted file mode 100644 index f41fa8648..000000000 --- a/target/linux/oxnas/patches-4.4/900-more-boards.patch +++ /dev/null @@ -1,15 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -497,7 +497,11 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ - orion5x-lswsgl.dtb \ - orion5x-maxtor-shared-storage-2.dtb \ - orion5x-rd88f5182-nas.dtb --dtb-$(CONFIG_ARCH_OXNAS) += ox820-pogoplug-pro.dtb -+dtb-$(CONFIG_ARCH_OXNAS) += ox820-akitio.dtb \ -+ ox820-pogoplug-pro.dtb \ -+ ox820-pogoplug-v3.dtb \ -+ ox820-stg212.dtb \ -+ ox820-kd20.dtb - dtb-$(CONFIG_ARCH_PRIMA2) += \ - prima2-evb.dtb - dtb-$(CONFIG_ARCH_QCOM) += \ diff --git a/target/linux/sunxi/patches-4.9/0052-stmmac-form-4-12.patch b/target/linux/sunxi/patches-4.9/0052-stmmac-form-4-12.patch index a1b018186..1ed129469 100644 --- a/target/linux/sunxi/patches-4.9/0052-stmmac-form-4-12.patch +++ b/target/linux/sunxi/patches-4.9/0052-stmmac-form-4-12.patch @@ -3095,7 +3095,7 @@ if (priv->hw->mode->set_16kib_bfsize) bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); -@@ -1033,235 +1234,409 @@ static int init_dma_desc_rings(struct ne +@@ -1033,257 +1234,516 @@ static int init_dma_desc_rings(struct ne priv->dma_buf_sz = bfsize; @@ -3351,17 +3351,10 @@ - priv->tx_skbuff_dma[i].buf, - priv->tx_skbuff_dma[i].len, - DMA_TO_DEVICE); -- } + for (i = 0; i < DMA_TX_SIZE; i++) + stmmac_free_tx_buffer(priv, queue, i); +} - -- if (priv->tx_skbuff[i]) { -- dev_kfree_skb_any(priv->tx_skbuff[i]); -- priv->tx_skbuff[i] = NULL; -- priv->tx_skbuff_dma[i].buf = 0; -- priv->tx_skbuff_dma[i].map_as_page = false; -- } ++ +/** + * free_dma_rx_desc_resources - free RX dma desc resources + * @priv: private structure @@ -3390,11 +3383,10 @@ + + kfree(rx_q->rx_skbuff_dma); + kfree(rx_q->rx_skbuff); - } - } - - /** -- * alloc_dma_desc_resources - alloc TX/RX resources. ++ } ++} ++ ++/** + * free_dma_tx_desc_resources - free TX dma desc resources + * @priv: private structure + */ @@ -3427,90 +3419,36 @@ + +/** + * alloc_dma_rx_desc_resources - alloc RX resources. - * @priv: private structure - * Description: according to which descriptor can be used (extend or basic) - * this function allocates the resources for TX and RX paths. In case of - * reception, for example, it pre-allocated the RX socket buffer in order to - * allow zero-copy mechanism. - */ --static int alloc_dma_desc_resources(struct stmmac_priv *priv) ++ * @priv: private structure ++ * Description: according to which descriptor can be used (extend or basic) ++ * this function allocates the resources for TX and RX paths. In case of ++ * reception, for example, it pre-allocated the RX socket buffer in order to ++ * allow zero-copy mechanism. ++ */ +static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) - { ++{ + u32 rx_count = priv->plat->rx_queues_to_use; - int ret = -ENOMEM; ++ int ret = -ENOMEM; + u32 queue; - -- priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), -- GFP_KERNEL); -- if (!priv->rx_skbuff_dma) -- return -ENOMEM; ++ + /* RX queues buffers and DMA */ + for (queue = 0; queue < rx_count; queue++) { + struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - -- priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), -- GFP_KERNEL); -- if (!priv->rx_skbuff) -- goto err_rx_skbuff; -- -- priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, -- sizeof(*priv->tx_skbuff_dma), -- GFP_KERNEL); -- if (!priv->tx_skbuff_dma) -- goto err_tx_skbuff_dma; -- -- priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), -- GFP_KERNEL); -- if (!priv->tx_skbuff) -- goto err_tx_skbuff; -- -- if (priv->extend_desc) { -- priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * -- sizeof(struct -- dma_extended_desc), -- &priv->dma_rx_phy, -- GFP_KERNEL); -- if (!priv->dma_erx) -- goto err_dma; ++ + rx_q->queue_index = queue; + rx_q->priv_data = priv; - -- priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * -- sizeof(struct -- dma_extended_desc), -- &priv->dma_tx_phy, ++ + rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, + sizeof(dma_addr_t), - GFP_KERNEL); -- if (!priv->dma_etx) { -- dma_free_coherent(priv->device, DMA_RX_SIZE * -- sizeof(struct dma_extended_desc), -- priv->dma_erx, priv->dma_rx_phy); -- goto err_dma; -- } -- } else { -- priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * -- sizeof(struct dma_desc), -- &priv->dma_rx_phy, -- GFP_KERNEL); -- if (!priv->dma_rx) -- goto err_dma; ++ GFP_KERNEL); + if (!rx_q->rx_skbuff_dma) + return -ENOMEM; - -- priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * -- sizeof(struct dma_desc), -- &priv->dma_tx_phy, -- GFP_KERNEL); -- if (!priv->dma_tx) { -- dma_free_coherent(priv->device, DMA_RX_SIZE * -- sizeof(struct dma_desc), -- priv->dma_rx, priv->dma_rx_phy); ++ + rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE, + sizeof(struct sk_buff *), + GFP_KERNEL); + if (!rx_q->rx_skbuff) - goto err_dma; ++ goto err_dma; + + if (priv->extend_desc) { + rx_q->dma_erx = dma_zalloc_coherent(priv->device, @@ -3531,19 +3469,12 @@ + GFP_KERNEL); + if (!rx_q->dma_rx) + goto err_dma; - } - } - - return 0; - - err_dma: -- kfree(priv->tx_skbuff); --err_tx_skbuff: -- kfree(priv->tx_skbuff_dma); --err_tx_skbuff_dma: -- kfree(priv->rx_skbuff); --err_rx_skbuff: -- kfree(priv->rx_skbuff_dma); ++ } ++ } ++ ++ return 0; ++ ++err_dma: + free_dma_rx_desc_resources(priv); + + return ret; @@ -3600,7 +3531,7 @@ + GFP_KERNEL); + if (!tx_q->dma_tx) + goto err_dma_buffers; -+ } + } + } + + return 0; @@ -3629,14 +3560,183 @@ + + ret = alloc_dma_tx_desc_resources(priv); + - return ret; - } - ++ return ret; ++} ++ +/** + * free_dma_desc_resources - free dma desc resources + * @priv: private structure + */ - static void free_dma_desc_resources(struct stmmac_priv *priv) ++static void free_dma_desc_resources(struct stmmac_priv *priv) ++{ ++ /* Release the DMA RX socket buffers */ ++ free_dma_rx_desc_resources(priv); ++ ++ /* Release the DMA TX socket buffers */ ++ free_dma_tx_desc_resources(priv); ++} ++ ++/** ++ * stmmac_mac_enable_rx_queues - Enable MAC rx queues ++ * @priv: driver private structure ++ * Description: It is used for enabling the rx queues in the MAC ++ */ ++static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) ++{ ++ u32 rx_queues_count = priv->plat->rx_queues_to_use; ++ int queue; ++ u8 mode; + +- if (priv->tx_skbuff[i]) { +- dev_kfree_skb_any(priv->tx_skbuff[i]); +- priv->tx_skbuff[i] = NULL; +- priv->tx_skbuff_dma[i].buf = 0; +- priv->tx_skbuff_dma[i].map_as_page = false; +- } ++ for (queue = 0; queue < rx_queues_count; queue++) { ++ mode = priv->plat->rx_queues_cfg[queue].mode_to_use; ++ priv->hw->mac->rx_queue_enable(priv->hw, mode, queue); + } + } + + /** +- * alloc_dma_desc_resources - alloc TX/RX resources. +- * @priv: private structure +- * Description: according to which descriptor can be used (extend or basic) +- * this function allocates the resources for TX and RX paths. In case of +- * reception, for example, it pre-allocated the RX socket buffer in order to +- * allow zero-copy mechanism. ++ * stmmac_start_rx_dma - start RX DMA channel ++ * @priv: driver private structure ++ * @chan: RX channel index ++ * Description: ++ * This starts a RX DMA channel + */ +-static int alloc_dma_desc_resources(struct stmmac_priv *priv) ++static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) + { +- int ret = -ENOMEM; +- +- priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t), +- GFP_KERNEL); +- if (!priv->rx_skbuff_dma) +- return -ENOMEM; +- +- priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *), +- GFP_KERNEL); +- if (!priv->rx_skbuff) +- goto err_rx_skbuff; +- +- priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, +- sizeof(*priv->tx_skbuff_dma), +- GFP_KERNEL); +- if (!priv->tx_skbuff_dma) +- goto err_tx_skbuff_dma; +- +- priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *), +- GFP_KERNEL); +- if (!priv->tx_skbuff) +- goto err_tx_skbuff; +- +- if (priv->extend_desc) { +- priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * +- sizeof(struct +- dma_extended_desc), +- &priv->dma_rx_phy, +- GFP_KERNEL); +- if (!priv->dma_erx) +- goto err_dma; +- +- priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * +- sizeof(struct +- dma_extended_desc), +- &priv->dma_tx_phy, +- GFP_KERNEL); +- if (!priv->dma_etx) { +- dma_free_coherent(priv->device, DMA_RX_SIZE * +- sizeof(struct dma_extended_desc), +- priv->dma_erx, priv->dma_rx_phy); +- goto err_dma; +- } +- } else { +- priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE * +- sizeof(struct dma_desc), +- &priv->dma_rx_phy, +- GFP_KERNEL); +- if (!priv->dma_rx) +- goto err_dma; ++ netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); ++ priv->hw->dma->start_rx(priv->ioaddr, chan); ++} + +- priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE * +- sizeof(struct dma_desc), +- &priv->dma_tx_phy, +- GFP_KERNEL); +- if (!priv->dma_tx) { +- dma_free_coherent(priv->device, DMA_RX_SIZE * +- sizeof(struct dma_desc), +- priv->dma_rx, priv->dma_rx_phy); +- goto err_dma; +- } +- } ++/** ++ * stmmac_start_tx_dma - start TX DMA channel ++ * @priv: driver private structure ++ * @chan: TX channel index ++ * Description: ++ * This starts a TX DMA channel ++ */ ++static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) ++{ ++ netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); ++ priv->hw->dma->start_tx(priv->ioaddr, chan); ++} + +- return 0; ++/** ++ * stmmac_stop_rx_dma - stop RX DMA channel ++ * @priv: driver private structure ++ * @chan: RX channel index ++ * Description: ++ * This stops a RX DMA channel ++ */ ++static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) ++{ ++ netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); ++ priv->hw->dma->stop_rx(priv->ioaddr, chan); ++} + +-err_dma: +- kfree(priv->tx_skbuff); +-err_tx_skbuff: +- kfree(priv->tx_skbuff_dma); +-err_tx_skbuff_dma: +- kfree(priv->rx_skbuff); +-err_rx_skbuff: +- kfree(priv->rx_skbuff_dma); +- return ret; ++/** ++ * stmmac_stop_tx_dma - stop TX DMA channel ++ * @priv: driver private structure ++ * @chan: TX channel index ++ * Description: ++ * This stops a TX DMA channel ++ */ ++static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) ++{ ++ netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); ++ priv->hw->dma->stop_tx(priv->ioaddr, chan); + } + +-static void free_dma_desc_resources(struct stmmac_priv *priv) ++/** ++ * stmmac_start_all_dma - start all RX and TX DMA channels ++ * @priv: driver private structure ++ * Description: ++ * This starts all the RX and TX DMA channels ++ */ ++static void stmmac_start_all_dma(struct stmmac_priv *priv) { - /* Release the DMA TX/RX socket buffers */ - dma_free_rx_skbufs(priv); @@ -3662,99 +3762,6 @@ - kfree(priv->rx_skbuff); - kfree(priv->tx_skbuff_dma); - kfree(priv->tx_skbuff); -+ /* Release the DMA RX socket buffers */ -+ free_dma_rx_desc_resources(priv); -+ -+ /* Release the DMA TX socket buffers */ -+ free_dma_tx_desc_resources(priv); - } - - /** -@@ -1271,19 +1646,104 @@ static void free_dma_desc_resources(stru - */ - static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) - { -- int rx_count = priv->dma_cap.number_rx_queues; -- int queue = 0; -+ u32 rx_queues_count = priv->plat->rx_queues_to_use; -+ int queue; -+ u8 mode; - -- /* If GMAC does not have multiple queues, then this is not necessary*/ -- if (rx_count == 1) -- return; -+ for (queue = 0; queue < rx_queues_count; queue++) { -+ mode = priv->plat->rx_queues_cfg[queue].mode_to_use; -+ priv->hw->mac->rx_queue_enable(priv->hw, mode, queue); -+ } -+} - -- /** -- * If the core is synthesized with multiple rx queues / multiple -- * dma channels, then rx queues will be disabled by default. -- * For now only rx queue 0 is enabled. -- */ -- priv->hw->mac->rx_queue_enable(priv->hw, queue); -+/** -+ * stmmac_start_rx_dma - start RX DMA channel -+ * @priv: driver private structure -+ * @chan: RX channel index -+ * Description: -+ * This starts a RX DMA channel -+ */ -+static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) -+{ -+ netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); -+ priv->hw->dma->start_rx(priv->ioaddr, chan); -+} -+ -+/** -+ * stmmac_start_tx_dma - start TX DMA channel -+ * @priv: driver private structure -+ * @chan: TX channel index -+ * Description: -+ * This starts a TX DMA channel -+ */ -+static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) -+{ -+ netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); -+ priv->hw->dma->start_tx(priv->ioaddr, chan); -+} -+ -+/** -+ * stmmac_stop_rx_dma - stop RX DMA channel -+ * @priv: driver private structure -+ * @chan: RX channel index -+ * Description: -+ * This stops a RX DMA channel -+ */ -+static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) -+{ -+ netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); -+ priv->hw->dma->stop_rx(priv->ioaddr, chan); -+} -+ -+/** -+ * stmmac_stop_tx_dma - stop TX DMA channel -+ * @priv: driver private structure -+ * @chan: TX channel index -+ * Description: -+ * This stops a TX DMA channel -+ */ -+static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) -+{ -+ netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); -+ priv->hw->dma->stop_tx(priv->ioaddr, chan); -+} -+ -+/** -+ * stmmac_start_all_dma - start all RX and TX DMA channels -+ * @priv: driver private structure -+ * Description: -+ * This starts all the RX and TX DMA channels -+ */ -+static void stmmac_start_all_dma(struct stmmac_priv *priv) -+{ + u32 rx_channels_count = priv->plat->rx_queues_to_use; + u32 tx_channels_count = priv->plat->tx_queues_to_use; + u32 chan = 0; @@ -3764,23 +3771,38 @@ + + for (chan = 0; chan < tx_channels_count; chan++) + stmmac_start_tx_dma(priv, chan); -+} -+ -+/** + } + + /** +- * stmmac_mac_enable_rx_queues - Enable MAC rx queues +- * @priv: driver private structure +- * Description: It is used for enabling the rx queues in the MAC + * stmmac_stop_all_dma - stop all RX and TX DMA channels + * @priv: driver private structure + * Description: + * This stops the RX and TX DMA channels -+ */ + */ +-static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) +static void stmmac_stop_all_dma(struct stmmac_priv *priv) -+{ + { +- int rx_count = priv->dma_cap.number_rx_queues; +- int queue = 0; + u32 rx_channels_count = priv->plat->rx_queues_to_use; + u32 tx_channels_count = priv->plat->tx_queues_to_use; + u32 chan = 0; -+ + +- /* If GMAC does not have multiple queues, then this is not necessary*/ +- if (rx_count == 1) +- return; + for (chan = 0; chan < rx_channels_count; chan++) + stmmac_stop_rx_dma(priv, chan); -+ + +- /** +- * If the core is synthesized with multiple rx queues / multiple +- * dma channels, then rx queues will be disabled by default. +- * For now only rx queue 0 is enabled. +- */ +- priv->hw->mac->rx_queue_enable(priv->hw, queue); + for (chan = 0; chan < tx_channels_count; chan++) + stmmac_stop_tx_dma(priv, chan); } diff --git a/target/linux/x86/patches-4.9/200-pcengines-apu2-reboot.patch b/target/linux/x86/patches-4.9/200-pcengines-apu2-reboot.patch index 21a8eeff9..6c2b21d15 100644 --- a/target/linux/x86/patches-4.9/200-pcengines-apu2-reboot.patch +++ b/target/linux/x86/patches-4.9/200-pcengines-apu2-reboot.patch @@ -1,6 +1,6 @@ --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c -@@ -447,6 +447,16 @@ static struct dmi_system_id __initdata r +@@ -449,6 +449,16 @@ static struct dmi_system_id __initdata r }, },