From 3f938d01a6fd027e3e1d111ecc5061aba37e31c6 Mon Sep 17 00:00:00 2001 From: coolsnowwolf Date: Fri, 14 Mar 2025 15:15:25 +0800 Subject: [PATCH] kernel: bump all to latest HEAD --- include/kernel-5.10 | 4 +- include/kernel-5.15 | 4 +- include/kernel-5.4 | 4 +- include/kernel-6.1 | 4 +- include/kernel-6.12 | 4 +- include/kernel-6.6 | 4 +- ...mediatek-clk-mtk-Add-dummy-clock-ops.patch | 74 ------------------- ...ockchip-naneng-combphy-fix-phy-reset.patch | 14 ---- ...ockchip-naneng-combphy-fix-phy-reset.patch | 28 +++++++ 9 files changed, 40 insertions(+), 100 deletions(-) delete mode 100644 target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch create mode 100644 target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch diff --git a/include/kernel-5.10 b/include/kernel-5.10 index e03d1a90e..385314704 100644 --- a/include/kernel-5.10 +++ b/include/kernel-5.10 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.10 = .234 -LINUX_KERNEL_HASH-5.10.234 = 9597c4fee2f1ce452acfec516f4325ad342155872052fd5f0d9ce2ddcc26ebe5 +LINUX_VERSION-5.10 = .235 +LINUX_KERNEL_HASH-5.10.235 = 953be3931101a94a93a644c1283ca41a7e567447ca87d3069ed4dd712dc1f1cc diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 9631a45f3..463a4c227 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .178 -LINUX_KERNEL_HASH-5.15.178 = efe9f7eb5ea4d26cec6290689343e1804eb3b4a88ff5a60497a696fc08157c42 +LINUX_VERSION-5.15 = .179 +LINUX_KERNEL_HASH-5.15.179 = 9319a47b1e9b5d344ff6015431856d0c9640e4faedc527c87f9129061a27136f diff --git a/include/kernel-5.4 b/include/kernel-5.4 index e872c3a2f..6539daba9 100644 --- a/include/kernel-5.4 +++ b/include/kernel-5.4 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.4 = .290 -LINUX_KERNEL_HASH-5.4.290 = 6cc73cf2a7f50580f7d8c7e99d2f2e8ada8b7d2f4e76f5896f0daf691cc2a456 +LINUX_VERSION-5.4 = .291 +LINUX_KERNEL_HASH-5.4.291 = b3ad64a4476a7c5450b92eab9a888b84ecb64dc613fcb0128f653f58e958ef6e diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 3f823097b..11614ee23 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .130 -LINUX_KERNEL_HASH-6.1.130 = 9416b2c2d448ec7f54bb0ce5713fb34c32dae4a4edf1abd8cf7a8995cbac66fd +LINUX_VERSION-6.1 = .131 +LINUX_KERNEL_HASH-6.1.131 = 44caf510603b4cbbe78ef828620099d200536d666e909ddb73bb2938c7de5b16 diff --git a/include/kernel-6.12 b/include/kernel-6.12 index f10c62f87..c452ee214 100644 --- a/include/kernel-6.12 +++ b/include/kernel-6.12 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.12 = .18 - LINUX_KERNEL_HASH-6.12.18 = beb902a5f69d9e57710112203db38111dad6d30556ea8ce389284c8077fe944d +LINUX_VERSION-6.12 = .19 +LINUX_KERNEL_HASH-6.12.19 = d73bf057bec04434b169d1b61641936f7d0c97ceb923a281f32e35dd4dcc6531 diff --git a/include/kernel-6.6 b/include/kernel-6.6 index 7502edfd6..e6f3c97c6 100644 --- a/include/kernel-6.6 +++ b/include/kernel-6.6 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.6 = .82 -LINUX_KERNEL_HASH-6.6.82 = f3c2389b8c23cabe747f104a3e434201ca6e7725bbbfb3a8c59a063ac4820e41 +LINUX_VERSION-6.6 = .83 +LINUX_KERNEL_HASH-6.6.83 = 894bbbe63b7484a0bc576a1e11a8dbc090fbd476d6424431bdc8435e03c2c208 diff --git a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch b/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch deleted file mode 100644 index c7de44fcf..000000000 --- a/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch +++ /dev/null @@ -1,74 +0,0 @@ -From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:37 +0100 -Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops - -In order to migrate some (few) old clock drivers to the common -mtk_clk_simple_probe() function, add dummy clock ops to be able -to insert a dummy clock with ID 0 at the beginning of the list. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++ - drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ - 2 files changed, 35 insertions(+) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -21,6 +21,22 @@ - #include "clk-gate.h" - #include "clk-mux.h" - -+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; -+EXPORT_SYMBOL_GPL(cg_regs_dummy); -+ -+static int mtk_clk_dummy_enable(struct clk_hw *hw) -+{ -+ return 0; -+} -+ -+static void mtk_clk_dummy_disable(struct clk_hw *hw) { } -+ -+const struct clk_ops mtk_clk_dummy_ops = { -+ .enable = mtk_clk_dummy_enable, -+ .disable = mtk_clk_dummy_disable, -+}; -+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); -+ - static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, - unsigned int clk_num) - { ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -22,6 +22,25 @@ - - struct platform_device; - -+/* -+ * We need the clock IDs to start from zero but to maintain devicetree -+ * backwards compatibility we can't change bindings to start from zero. -+ * Only a few platforms are affected, so we solve issues given by the -+ * commonized MTK clocks probe function(s) by adding a dummy clock at -+ * the beginning where needed. -+ */ -+#define CLK_DUMMY 0 -+ -+extern const struct clk_ops mtk_clk_dummy_ops; -+extern const struct mtk_gate_regs cg_regs_dummy; -+ -+#define GATE_DUMMY(_id, _name) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .regs = &cg_regs_dummy, \ -+ .ops = &mtk_clk_dummy_ops, \ -+ } -+ - struct mtk_fixed_clk { - int id; - const char *name; diff --git a/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch b/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch index 0fc571bdb..622f7aea8 100644 --- a/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch +++ b/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch @@ -26,17 +26,3 @@ rockchip,pipe-grf = <&pipegrf>; rockchip,pipe-phy-grf = <&pipe_phy_grf2>; #phy-cells = <1>; ---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -299,7 +299,10 @@ static int rockchip_combphy_parse_dt(str - - priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); - -- priv->phy_rst = devm_reset_control_get(dev, "phy"); -+ priv->phy_rst = devm_reset_control_get_exclusive(dev, "phy"); -+ /* fallback to old behaviour */ -+ if (PTR_ERR(priv->phy_rst) == -ENOENT) -+ priv->phy_rst = devm_reset_control_array_get_exclusive(dev); - if (IS_ERR(priv->phy_rst)) - return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); - diff --git a/target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch b/target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch new file mode 100644 index 000000000..4025de518 --- /dev/null +++ b/target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch @@ -0,0 +1,28 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -225,6 +225,7 @@ + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1724,6 +1724,7 @@ + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; +@@ -1740,6 +1741,7 @@ + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>;