From 3d32cf17562a284b53ef710fb4e374f2e39ff5d9 Mon Sep 17 00:00:00 2001
From: aiamadeus <2789289348@qq.com>
Date: Thu, 21 Nov 2024 22:28:06 +0800
Subject: [PATCH] rockchip: fixes rk3588 usb3 init issue

---
 .../boot/dts/rockchip/rk3588-srcm3588-io.dts  |  9 +----
 ...ockchip-naneng-combphy-fix-phy-reset.patch | 39 +++++++++++++++++++
 ...ockchip-naneng-combphy-fix-phy-reset.patch | 39 +++++++++++++++++++
 3 files changed, 79 insertions(+), 8 deletions(-)
 create mode 100644 target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
 create mode 100644 target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch

diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-srcm3588-io.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-srcm3588-io.dts
index 63719f05e..6c1498498 100644
--- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-srcm3588-io.dts
+++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3588-srcm3588-io.dts
@@ -296,10 +296,6 @@
 	};
 };
 
-/*
- * fspi is unavailable
- * use i2c instead
- */
 &i2c8 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c8m1_xfer>;
@@ -840,9 +836,6 @@
 	status = "okay";
 };
 
-/*
- * Disabled due to driver bug.
- */
 &usb_host2_xhci {
-	status = "disabled";
+	status = "okay";
 };
diff --git a/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch b/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
new file mode 100644
index 000000000..a27240386
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
@@ -0,0 +1,39 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -225,6 +225,7 @@
+ 		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ 		assigned-clock-rates = <100000000>;
+ 		resets = <&cru SRST_PIPEPHY0>;
++		reset-names = "phy";
+ 		rockchip,pipe-grf = <&pipegrf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ 		#phy-cells = <1>;
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1686,6 +1686,7 @@
+ 		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+ 		assigned-clock-rates = <100000000>;
+ 		resets = <&cru SRST_PIPEPHY1>;
++		reset-names = "phy";
+ 		rockchip,pipe-grf = <&pipegrf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+ 		#phy-cells = <1>;
+@@ -1702,6 +1703,7 @@
+ 		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+ 		assigned-clock-rates = <100000000>;
+ 		resets = <&cru SRST_PIPEPHY2>;
++		reset-names = "phy";
+ 		rockchip,pipe-grf = <&pipegrf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+ 		#phy-cells = <1>;
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -299,7 +299,7 @@ static int rockchip_combphy_parse_dt(str
+ 
+ 	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+ 
+-	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
++	priv->phy_rst = devm_reset_control_get(dev, "phy");
+ 	if (IS_ERR(priv->phy_rst))
+ 		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
+ 
diff --git a/target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch b/target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
new file mode 100644
index 000000000..12101f397
--- /dev/null
+++ b/target/linux/rockchip/patches-6.6/220-phy-rockchip-naneng-combphy-fix-phy-reset.patch
@@ -0,0 +1,39 @@
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -225,6 +225,7 @@
+ 		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
+ 		assigned-clock-rates = <100000000>;
+ 		resets = <&cru SRST_PIPEPHY0>;
++		reset-names = "phy";
+ 		rockchip,pipe-grf = <&pipegrf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
+ 		#phy-cells = <1>;
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1719,6 +1719,7 @@
+ 		assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
+ 		assigned-clock-rates = <100000000>;
+ 		resets = <&cru SRST_PIPEPHY1>;
++		reset-names = "phy";
+ 		rockchip,pipe-grf = <&pipegrf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
+ 		#phy-cells = <1>;
+@@ -1735,6 +1736,7 @@
+ 		assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
+ 		assigned-clock-rates = <100000000>;
+ 		resets = <&cru SRST_PIPEPHY2>;
++		reset-names = "phy";
+ 		rockchip,pipe-grf = <&pipegrf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
+ 		#phy-cells = <1>;
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -324,7 +324,7 @@ static int rockchip_combphy_parse_dt(str
+ 
+ 	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
+ 
+-	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
++	priv->phy_rst = devm_reset_control_get(dev, "phy");
+ 	if (IS_ERR(priv->phy_rst))
+ 		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
+