From 37836e0c3db69dd64cd30e7a4a415365ee1f074e Mon Sep 17 00:00:00 2001 From: CN_SZTL <22235437+1715173329@users.noreply.github.com> Date: Sat, 12 Dec 2020 11:33:26 +0800 Subject: [PATCH] rockchip: enable hwRNG for rk3399 by default and remove R4S support (#5916) * Revert "rockchip: add support for NanoPi R4S" This reverts commit 6edffa84190641f0acd8e1ae5e73ecd99897d877. * rockchip: move hwRNG driver to files * rockchip: drop hwRNG support for NanoPi R2S * rockchip: enable hwRNG on rk3399 by default * rockchip: enable hwRNG crypto engine in Kconfig * rockchip: sync upstream patch Co-authored-by: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> --- package/boot/uboot-rockchip/Makefile | 30 +- ...kchip-add-support-for-NanoPi-R4S-v11.patch | 221 ----------- .../armv8/base-files/etc/board.d/01_leds | 3 +- .../armv8/base-files/etc/board.d/02_network | 6 +- .../etc/hotplug.d/net/40-net-smp-affinity | 4 - target/linux/rockchip/armv8/config-5.4 | 7 + .../drivers/char/hw_random/rockchip-rng.c | 340 +++++++++++++++++ target/linux/rockchip/image/armv8.mk | 9 - .../image/bootscript/nanopi-r4s.bootscript | 8 - ...-add-hwmon-support-for-SoCs-and-GPUs.patch | 26 +- ...-for-rockchip-hardware-random-number.patch | 343 ------------------ ...ip-add-hardware-random-number-genera.patch | 2 +- ...p-enable-hardware-rng-for-NanoPi-R2S.patch | 19 - ...-rockchip-add-support-for-NanoPi-R4S.patch | 156 -------- 14 files changed, 371 insertions(+), 803 deletions(-) delete mode 100644 package/boot/uboot-rockchip/patches/101-uboot-rockchip-add-support-for-NanoPi-R4S-v11.patch create mode 100644 target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c delete mode 100644 target/linux/rockchip/image/bootscript/nanopi-r4s.bootscript delete mode 100644 target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch delete mode 100644 target/linux/rockchip/patches-5.4/200-rockchip-add-support-for-NanoPi-R4S.patch diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 3309912cf..d460e3723 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2020.10 -PKG_RELEASE:=1 +PKG_VERSION:=2020.07 +PKG_RELEASE:=3 -PKG_HASH:=0d481bbdc05c0ee74908ec2f56a6daa53166cc6a78a0e4fac2ac5d025770a622 +PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a PKG_MAINTAINER:=Tobias Maedel @@ -38,26 +38,6 @@ endef # RK3399 boards -define U-Boot/nanopi-r4s-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R4S - BUILD_DEVICES:= \ - friendlyarm_nanopi-r4s - DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - -define U-Boot/rock-pi-4-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=Rock Pi 4 - BUILD_DEVICES:= \ - radxa_rock-pi-4 - DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - define U-Boot/rockpro64-rk3399 BUILD_SUBTARGET:=armv8 NAME:=RockPro64 @@ -69,9 +49,7 @@ define U-Boot/rockpro64-rk3399 endef UBOOT_TARGETS := \ - rock-pi-4-rk3399 \ rockpro64-rk3399 \ - nanopi-r4s-rk3399 \ nanopi-r2s-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes @@ -103,4 +81,4 @@ endef define Package/u-boot/install/default endef -$(eval $(call BuildPackage/U-Boot)) \ No newline at end of file +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-rockchip/patches/101-uboot-rockchip-add-support-for-NanoPi-R4S-v11.patch b/package/boot/uboot-rockchip/patches/101-uboot-rockchip-add-support-for-NanoPi-R4S-v11.patch deleted file mode 100644 index 6df188e11..000000000 --- a/package/boot/uboot-rockchip/patches/101-uboot-rockchip-add-support-for-NanoPi-R4S-v11.patch +++ /dev/null @@ -1,221 +0,0 @@ -From fb33ae31b89d6a1ecb277d10a2d42aa2a732a95d Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Fri, 4 Dec 2020 10:09:24 -0500 -Subject: [PATCH] uboot-rockchip: add support for NanoPi R4S v11 - -Signed-off-by: Marty Jones ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 8 ++ - arch/arm/dts/rk3399-nanopi-r4s.dts | 115 +++++++++++++++++++++ - configs/nanopi-r4s-rk3399_defconfig | 62 +++++++++++++ - 4 files changed, 186 insertions(+) - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts - create mode 100644 configs/nanopi-r4s-rk3399_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -130,6 +130,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-nanopi-m4.dtb \ - rk3399-nanopi-m4-2gb.dtb \ - rk3399-nanopi-neo4.dtb \ -+ rk3399-nanopi-r4s.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ - rk3399-puma-haikou.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2019 Jagan Teki -+ */ -+ -+#include "rk3399-nanopi4-u-boot.dtsi" -+#include "rk3399-sdram-ddr3-1866.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4s.dts -@@ -0,0 +1,115 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * FriendlyElec NanoPC-T4 board device tree source -+ * -+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2018 Collabora Ltd. -+ */ -+ -+/dts-v1/; -+#include "rk3399-nanopi4.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S"; -+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* FIXME: adjust leveles for the connected fan */ -+ cooling-levels = <0 12 18 255>; -+ #cooling-cells = <2>; -+ fan-supply = <&vdd_5v>; -+ pwms = <&pwm1 0 50000 0>; -+ }; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_warm: cpu_warm { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_hot: cpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map2 { -+ trip = <&cpu_warm>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map3 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&emmc_phy { -+ status = "disabled"; -+}; -+ -+&fusb0 { -+ status = "disabled"; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+}; -+ -+&sdhci { -+ status = "disabled"; -+}; -+ -+&sdio0 { -+ status = "disabled"; -+}; -+ -+&sdmmc { -+ host-index-min = <1>; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&u2phy1_host { -+ status = "disabled"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; -+ -+&leds { -+ led@2 { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "lan_led"; -+ }; -+ -+ led@3 { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "wan_led"; -+ }; -+}; ---- /dev/null -+++ b/configs/nanopi-r4s-rk3399_defconfig -@@ -0,0 +1,62 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y - diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index 77655d426..bba3e2aa5 100755 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -9,8 +9,7 @@ boardname="${board##*,}" board_config_update case $board in -friendlyarm,nanopi-r2s|\ -friendlyarm,nanopi-r4s) +friendlyarm,nanopi-r2s) ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0" ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1" ;; diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 75f43f2dc..e129fd6a6 100755 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -8,8 +8,7 @@ rockchip_setup_interfaces() local board="$1" case "$board" in - friendlyarm,nanopi-r2s|\ - friendlyarm,nanopi-r4s) + friendlyarm,nanopi-r2s) ucidef_set_interfaces_lan_wan 'eth1' 'eth0' ;; *) @@ -26,8 +25,7 @@ rockchip_setup_macs() local label_mac="" case "$board" in - friendlyarm,nanopi-r2s|\ - friendlyarm,nanopi-r4s) + friendlyarm,nanopi-r2s) wan_mac=$(macaddr_random) lan_mac=$(macaddr_add "$wan_mac" +1) ;; diff --git a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity index 1434d8935..ab3f95465 100644 --- a/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity +++ b/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity @@ -26,9 +26,5 @@ friendlyarm,nanopi-r2s) set_interface_core 2 "eth0" set_interface_core 4 "eth1" "xhci-hcd:usb3" ;; -friendlyarm,nanopi-r4s) - set_interface_core 2 "eth0" - set_interface_core 3 "eth1" - ;; esac diff --git a/target/linux/rockchip/armv8/config-5.4 b/target/linux/rockchip/armv8/config-5.4 index d1a3b1c94..e9a972338 100644 --- a/target/linux/rockchip/armv8/config-5.4 +++ b/target/linux/rockchip/armv8/config-5.4 @@ -117,6 +117,13 @@ CONFIG_CRC_T10DIF=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEVFREQ_GOV_PASSIVE is not set CONFIG_DEVFREQ_GOV_PERFORMANCE=y diff --git a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c new file mode 100644 index 000000000..718762f99 --- /dev/null +++ b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rockchip-rng.c Random Number Generator driver for the Rockchip + * + * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. + * Author: Lin Jinhan + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define _SBF(s, v) ((v) << (s)) +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define ROCKCHIP_AUTOSUSPEND_DELAY 100 +#define ROCKCHIP_POLL_PERIOD_US 100 +#define ROCKCHIP_POLL_TIMEOUT_US 10000 +#define RK_MAX_RNG_BYTE (32) + +/* start of CRYPTO V1 register define */ +#define CRYPTO_V1_CTRL 0x0008 +#define CRYPTO_V1_RNG_START BIT(8) +#define CRYPTO_V1_RNG_FLUSH BIT(9) + +#define CRYPTO_V1_TRNG_CTRL 0x0200 +#define CRYPTO_V1_OSC_ENABLE BIT(16) +#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) + +#define CRYPTO_V1_TRNG_DOUT_0 0x0204 +/* end of CRYPTO V1 register define */ + +/* start of CRYPTO V2 register define */ +#define CRYPTO_V2_RNG_CTL 0x0400 +#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) +#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) +#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) +#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) +#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) +#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) +#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) +#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) +#define CRYPTO_V2_RNG_ENABLE BIT(1) +#define CRYPTO_V2_RNG_START BIT(0) +#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 +#define CRYPTO_V2_RNG_DOUT_0 0x0410 +/* end of CRYPTO V2 register define */ + +struct rk_rng_soc_data { + const char * const *clks; + int clks_num; + int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); +}; + +struct rk_rng { + struct device *dev; + struct hwrng rng; + void __iomem *mem; + struct rk_rng_soc_data *soc_data; + u32 clk_num; + struct clk_bulk_data *clk_bulks; +}; + +static const char * const rk_rng_v1_clks[] = { + "hclk_crypto", + "clk_crypto", +}; + +static const char * const rk_rng_v2_clks[] = { + "hclk_crypto", + "aclk_crypto", + "clk_crypto", + "clk_crypto_apk", +}; + +static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) +{ + __raw_writel(val, rng->mem + offset); +} + +static u32 rk_rng_readl(struct rk_rng *rng, u32 offset) +{ + return __raw_readl(rng->mem + offset); +} + +static int rk_rng_init(struct hwrng *rng) +{ + int ret; + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + + dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n"); + + ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); + if (ret < 0) { + dev_err(rk_rng->dev, "failed to enable clks %d\n", ret); + return ret; + } + + return 0; +} + +static void rk_rng_cleanup(struct hwrng *rng) +{ + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + + dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n"); + clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); +} + +static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, + size_t size) +{ + u32 i; + + for (i = 0; i < size; i += 4) + *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); +} + +static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) +{ + int ret = 0; + u32 reg_ctrl = 0; + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + + ret = pm_runtime_get_sync(rk_rng->dev); + if (ret < 0) { + pm_runtime_put_noidle(rk_rng->dev); + return ret; + } + + /* enable osc_ring to get entropy, sample period is set as 100 */ + reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); + rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); + + reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0); + + rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL); + + ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl, + !(reg_ctrl & CRYPTO_V1_RNG_START), + ROCKCHIP_POLL_PERIOD_US, + ROCKCHIP_POLL_TIMEOUT_US); + if (ret < 0) + goto out; + + ret = min_t(size_t, max, RK_MAX_RNG_BYTE); + + rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret); + +out: + /* close TRNG */ + rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), + CRYPTO_V1_CTRL); + + pm_runtime_mark_last_busy(rk_rng->dev); + pm_runtime_put_sync_autosuspend(rk_rng->dev); + + return ret; +} + +static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) +{ + int ret = 0; + u32 reg_ctrl = 0; + struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); + + ret = pm_runtime_get_sync(rk_rng->dev); + if (ret < 0) { + pm_runtime_put_noidle(rk_rng->dev); + return ret; + } + + /* enable osc_ring to get entropy, sample period is set as 100 */ + rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); + + reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN; + reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; + reg_ctrl |= CRYPTO_V2_RNG_ENABLE; + reg_ctrl |= CRYPTO_V2_RNG_START; + + rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), + CRYPTO_V2_RNG_CTL); + + ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl, + !(reg_ctrl & CRYPTO_V2_RNG_START), + ROCKCHIP_POLL_PERIOD_US, + ROCKCHIP_POLL_TIMEOUT_US); + if (ret < 0) + goto out; + + ret = min_t(size_t, max, RK_MAX_RNG_BYTE); + + rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret); + +out: + /* close TRNG */ + rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); + + pm_runtime_mark_last_busy(rk_rng->dev); + pm_runtime_put_sync_autosuspend(rk_rng->dev); + + return ret; +} + +static const struct rk_rng_soc_data rk_rng_v1_soc_data = { + .clks_num = ARRAY_SIZE(rk_rng_v1_clks), + .clks = rk_rng_v1_clks, + .rk_rng_read = rk_rng_v1_read, +}; + +static const struct rk_rng_soc_data rk_rng_v2_soc_data = { + .clks_num = ARRAY_SIZE(rk_rng_v2_clks), + .clks = rk_rng_v2_clks, + .rk_rng_read = rk_rng_v2_read, +}; + +static const struct of_device_id rk_rng_dt_match[] = { + { + .compatible = "rockchip,cryptov1-rng", + .data = (void *)&rk_rng_v1_soc_data, + }, + { + .compatible = "rockchip,cryptov2-rng", + .data = (void *)&rk_rng_v2_soc_data, + }, + { }, +}; + +MODULE_DEVICE_TABLE(of, rk_rng_dt_match); + +static int rk_rng_probe(struct platform_device *pdev) +{ + int i; + int ret; + struct rk_rng *rk_rng; + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + + dev_dbg(&pdev->dev, "probing...\n"); + rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); + if (!rk_rng) + return -ENOMEM; + + match = of_match_node(rk_rng_dt_match, np); + rk_rng->soc_data = (struct rk_rng_soc_data *)match->data; + + rk_rng->dev = &pdev->dev; + rk_rng->rng.name = "rockchip"; +#ifndef CONFIG_PM + rk_rng->rng.init = rk_rng_init; + rk_rng->rng.cleanup = rk_rng_cleanup, +#endif + rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; + rk_rng->rng.quality = 999; + + rk_rng->clk_bulks = + devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) * + rk_rng->soc_data->clks_num, GFP_KERNEL); + + rk_rng->clk_num = rk_rng->soc_data->clks_num; + + for (i = 0; i < rk_rng->soc_data->clks_num; i++) + rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i]; + + rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); + if (IS_ERR(rk_rng->mem)) + return PTR_ERR(rk_rng->mem); + + ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num, + rk_rng->clk_bulks); + if (ret) { + dev_err(&pdev->dev, "failed to get clks property\n"); + return ret; + } + + platform_set_drvdata(pdev, rk_rng); + + pm_runtime_set_autosuspend_delay(&pdev->dev, + ROCKCHIP_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng); + if (ret) { + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_disable(&pdev->dev); + } + + return ret; +} + +#ifdef CONFIG_PM +static int rk_rng_runtime_suspend(struct device *dev) +{ + struct rk_rng *rk_rng = dev_get_drvdata(dev); + + rk_rng_cleanup(&rk_rng->rng); + + return 0; +} + +static int rk_rng_runtime_resume(struct device *dev) +{ + struct rk_rng *rk_rng = dev_get_drvdata(dev); + + return rk_rng_init(&rk_rng->rng); +} + +static const struct dev_pm_ops rk_rng_pm_ops = { + SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, + rk_rng_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + +#endif + +static struct platform_driver rk_rng_driver = { + .driver = { + .name = "rockchip-rng", +#ifdef CONFIG_PM + .pm = &rk_rng_pm_ops, +#endif + .of_match_table = rk_rng_dt_match, + }, + .probe = rk_rng_probe, +}; + +module_platform_driver(rk_rng_driver); + +MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver"); +MODULE_AUTHOR("Lin Jinhan "); +MODULE_LICENSE("GPL v2"); + diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk index 80161a54b..8e4ba07e0 100644 --- a/target/linux/rockchip/image/armv8.mk +++ b/target/linux/rockchip/image/armv8.mk @@ -15,15 +15,6 @@ define Device/friendlyarm_nanopi-r2s endef TARGET_DEVICES += friendlyarm_nanopi-r2s -define Device/friendlyarm_nanopi-r4s - DEVICE_VENDOR := FriendlyARM - DEVICE_MODEL := NanoPi R4S - SOC := rk3399 - UBOOT_DEVICE_NAME := nanopi-r4s-rk3399 - DEVICE_PACKAGES := kmod-r8169 -endef -TARGET_DEVICES += friendlyarm_nanopi-r4s - define Device/pine64_rockpro64 DEVICE_VENDOR := Pine64 DEVICE_MODEL := RockPro64 diff --git a/target/linux/rockchip/image/bootscript/nanopi-r4s.bootscript b/target/linux/rockchip/image/bootscript/nanopi-r4s.bootscript deleted file mode 100644 index abe9c24ee..000000000 --- a/target/linux/rockchip/image/bootscript/nanopi-r4s.bootscript +++ /dev/null @@ -1,8 +0,0 @@ -part uuid mmc ${devnum}:2 uuid - -setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait" - -load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb -load mmc ${devnum}:1 ${kernel_addr_r} kernel.img - -booti ${kernel_addr_r} - ${fdt_addr_r} diff --git a/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch b/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch index 9b21a9028..5d0d6b3a3 100644 --- a/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch +++ b/target/linux/rockchip/patches-5.4/002-rockchip-add-hwmon-support-for-SoCs-and-GPUs.patch @@ -1,31 +1,34 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From d27970b82a0f552f70e76fab154855b3192aac23 Mon Sep 17 00:00:00 2001 From: Stefan Schaeckeler Date: Wed, 11 Dec 2019 22:17:02 -0800 -Subject: [RESEND PATCH] thermal: rockchip: enable hwmon +Subject: thermal: rockchip: Enable hwmon By default, of-based thermal drivers do not enable hwmon. Explicitly enable hwmon for both, the soc and gpu temperature sensor. Signed-off-by: Stefan Schaeckeler +Tested-by: Daniel Lezcano +Signed-off-by: Daniel Lezcano +Link: https://lore.kernel.org/r/20191212061702.BFE2D6E85603@corona.crabdance.com --- drivers/thermal/rockchip_thermal.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c -index 343c2f5c5a25..e47c60010259 100644 +index 9ed8085bb7924..7c1a8bccdcba6 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c -@@ -19,6 +19,8 @@ - #include - #include +@@ -58,6 +58,8 @@ enum adc_sort_mode { + ADC_INCREMENT, + }; +#include "thermal_hwmon.h" + /** - * If the temperature over a period of time High, - * the resulting TSHUT gave CRU module,let it reset the entire chip, -@@ -1321,8 +1323,15 @@ static int rockchip_thermal_probe(struct platform_device *pdev) + * The max sensors is two in rockchip SoCs. + * Two sensors: CPU and GPU sensor. +@@ -1331,8 +1333,15 @@ static int rockchip_thermal_probe(struct platform_device *pdev) thermal->chip->control(thermal->regs, true); @@ -42,7 +45,7 @@ index 343c2f5c5a25..e47c60010259 100644 platform_set_drvdata(pdev, thermal); -@@ -1344,6 +1353,7 @@ static int rockchip_thermal_remove(struct platform_device *pdev) +@@ -1354,6 +1363,7 @@ static int rockchip_thermal_remove(struct platform_device *pdev) for (i = 0; i < thermal->chip->chn_num; i++) { struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; @@ -50,3 +53,6 @@ index 343c2f5c5a25..e47c60010259 100644 rockchip_thermal_toggle_sensor(sensor, false); } +-- +cgit 1.2.3-1.el7 + diff --git a/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch index 196cc00ae..85f14e61b 100644 --- a/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch +++ b/target/linux/rockchip/patches-5.4/105-char-add-support-for-rockchip-hardware-random-number.patch @@ -33,349 +33,6 @@ Signed-off-by: wevsty config HW_RANDOM_PIC32 tristate "Microchip PIC32 Random Number Generator support" depends on HW_RANDOM && MACH_PIC32 ---- /dev/null -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -0,0 +1,340 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * rockchip-rng.c Random Number Generator driver for the Rockchip -+ * -+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. -+ * Author: Lin Jinhan -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define _SBF(s, v) ((v) << (s)) -+#define HIWORD_UPDATE(val, mask, shift) \ -+ ((val) << (shift) | (mask) << ((shift) + 16)) -+ -+#define ROCKCHIP_AUTOSUSPEND_DELAY 100 -+#define ROCKCHIP_POLL_PERIOD_US 100 -+#define ROCKCHIP_POLL_TIMEOUT_US 10000 -+#define RK_MAX_RNG_BYTE (32) -+ -+/* start of CRYPTO V1 register define */ -+#define CRYPTO_V1_CTRL 0x0008 -+#define CRYPTO_V1_RNG_START BIT(8) -+#define CRYPTO_V1_RNG_FLUSH BIT(9) -+ -+#define CRYPTO_V1_TRNG_CTRL 0x0200 -+#define CRYPTO_V1_OSC_ENABLE BIT(16) -+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) -+ -+#define CRYPTO_V1_TRNG_DOUT_0 0x0204 -+/* end of CRYPTO V1 register define */ -+ -+/* start of CRYPTO V2 register define */ -+#define CRYPTO_V2_RNG_CTL 0x0400 -+#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) -+#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) -+#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) -+#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) -+#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) -+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) -+#define CRYPTO_V2_RNG_ENABLE BIT(1) -+#define CRYPTO_V2_RNG_START BIT(0) -+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 -+#define CRYPTO_V2_RNG_DOUT_0 0x0410 -+/* end of CRYPTO V2 register define */ -+ -+struct rk_rng_soc_data { -+ const char * const *clks; -+ int clks_num; -+ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); -+}; -+ -+struct rk_rng { -+ struct device *dev; -+ struct hwrng rng; -+ void __iomem *mem; -+ struct rk_rng_soc_data *soc_data; -+ u32 clk_num; -+ struct clk_bulk_data *clk_bulks; -+}; -+ -+static const char * const rk_rng_v1_clks[] = { -+ "hclk_crypto", -+ "clk_crypto", -+}; -+ -+static const char * const rk_rng_v2_clks[] = { -+ "hclk_crypto", -+ "aclk_crypto", -+ "clk_crypto", -+ "clk_crypto_apk", -+}; -+ -+static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) -+{ -+ __raw_writel(val, rng->mem + offset); -+} -+ -+static u32 rk_rng_readl(struct rk_rng *rng, u32 offset) -+{ -+ return __raw_readl(rng->mem + offset); -+} -+ -+static int rk_rng_init(struct hwrng *rng) -+{ -+ int ret; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n"); -+ -+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); -+ if (ret < 0) { -+ dev_err(rk_rng->dev, "failed to enable clks %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void rk_rng_cleanup(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n"); -+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); -+} -+ -+static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, -+ size_t size) -+{ -+ u32 i; -+ -+ for (i = 0; i < size; i += 4) -+ *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); -+} -+ -+static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ ret = pm_runtime_get_sync(rk_rng->dev); -+ if (ret < 0) { -+ pm_runtime_put_noidle(rk_rng->dev); -+ return ret; -+ } -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); -+ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); -+ -+ reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0); -+ -+ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL); -+ -+ ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl, -+ !(reg_ctrl & CRYPTO_V1_RNG_START), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US); -+ if (ret < 0) -+ goto out; -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret); -+ -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), -+ CRYPTO_V1_CTRL); -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ -+ return ret; -+} -+ -+static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ ret = pm_runtime_get_sync(rk_rng->dev); -+ if (ret < 0) { -+ pm_runtime_put_noidle(rk_rng->dev); -+ return ret; -+ } -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); -+ -+ reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN; -+ reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; -+ reg_ctrl |= CRYPTO_V2_RNG_ENABLE; -+ reg_ctrl |= CRYPTO_V2_RNG_START; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), -+ CRYPTO_V2_RNG_CTL); -+ -+ ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl, -+ !(reg_ctrl & CRYPTO_V2_RNG_START), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US); -+ if (ret < 0) -+ goto out; -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret); -+ -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ -+ return ret; -+} -+ -+static const struct rk_rng_soc_data rk_rng_v1_soc_data = { -+ .clks_num = ARRAY_SIZE(rk_rng_v1_clks), -+ .clks = rk_rng_v1_clks, -+ .rk_rng_read = rk_rng_v1_read, -+}; -+ -+static const struct rk_rng_soc_data rk_rng_v2_soc_data = { -+ .clks_num = ARRAY_SIZE(rk_rng_v2_clks), -+ .clks = rk_rng_v2_clks, -+ .rk_rng_read = rk_rng_v2_read, -+}; -+ -+static const struct of_device_id rk_rng_dt_match[] = { -+ { -+ .compatible = "rockchip,cryptov1-rng", -+ .data = (void *)&rk_rng_v1_soc_data, -+ }, -+ { -+ .compatible = "rockchip,cryptov2-rng", -+ .data = (void *)&rk_rng_v2_soc_data, -+ }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, rk_rng_dt_match); -+ -+static int rk_rng_probe(struct platform_device *pdev) -+{ -+ int i; -+ int ret; -+ struct rk_rng *rk_rng; -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *match; -+ -+ dev_dbg(&pdev->dev, "probing...\n"); -+ rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); -+ if (!rk_rng) -+ return -ENOMEM; -+ -+ match = of_match_node(rk_rng_dt_match, np); -+ rk_rng->soc_data = (struct rk_rng_soc_data *)match->data; -+ -+ rk_rng->dev = &pdev->dev; -+ rk_rng->rng.name = "rockchip"; -+#ifndef CONFIG_PM -+ rk_rng->rng.init = rk_rng_init; -+ rk_rng->rng.cleanup = rk_rng_cleanup, -+#endif -+ rk_rng->rng.read = rk_rng->soc_data->rk_rng_read; -+ rk_rng->rng.quality = 999; -+ -+ rk_rng->clk_bulks = -+ devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) * -+ rk_rng->soc_data->clks_num, GFP_KERNEL); -+ -+ rk_rng->clk_num = rk_rng->soc_data->clks_num; -+ -+ for (i = 0; i < rk_rng->soc_data->clks_num; i++) -+ rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i]; -+ -+ rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); -+ if (IS_ERR(rk_rng->mem)) -+ return PTR_ERR(rk_rng->mem); -+ -+ ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num, -+ rk_rng->clk_bulks); -+ if (ret) { -+ dev_err(&pdev->dev, "failed to get clks property\n"); -+ return ret; -+ } -+ -+ platform_set_drvdata(pdev, rk_rng); -+ -+ pm_runtime_set_autosuspend_delay(&pdev->dev, -+ ROCKCHIP_AUTOSUSPEND_DELAY); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ pm_runtime_enable(&pdev->dev); -+ -+ ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng); -+ if (ret) { -+ pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ } -+ -+ return ret; -+} -+ -+#ifdef CONFIG_PM -+static int rk_rng_runtime_suspend(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ rk_rng_cleanup(&rk_rng->rng); -+ -+ return 0; -+} -+ -+static int rk_rng_runtime_resume(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ return rk_rng_init(&rk_rng->rng); -+} -+ -+static const struct dev_pm_ops rk_rng_pm_ops = { -+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, -+ rk_rng_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+}; -+ -+#endif -+ -+static struct platform_driver rk_rng_driver = { -+ .driver = { -+ .name = "rockchip-rng", -+#ifdef CONFIG_PM -+ .pm = &rk_rng_pm_ops, -+#endif -+ .of_match_table = rk_rng_dt_match, -+ }, -+ .probe = rk_rng_probe, -+}; -+ -+module_platform_driver(rk_rng_driver); -+ -+MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver"); -+MODULE_AUTHOR("Lin Jinhan "); -+MODULE_LICENSE("GPL v2"); -+ --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += diff --git a/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch index aa7c5c39d..75e283ab3 100644 --- a/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-5.4/106-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -42,7 +42,7 @@ Signed-off-by: wevsty + clock-names = "clk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; + assigned-clock-rates = <150000000>, <100000000>; -+ status = "disabled"; ++ status = "okay"; + }; + gpu: gpu@ff9a0000 { diff --git a/target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch deleted file mode 100644 index cab0abedd..000000000 --- a/target/linux/rockchip/patches-5.4/107-rockchip-enable-hardware-rng-for-NanoPi-R2S.patch +++ /dev/null @@ -1,19 +0,0 @@ -From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001 -From: wevsty -Date: Mon, 24 Aug 2020 02:27:11 +0800 -Subject: [PATCH] rockchip: rk3328: enable hardware rng for NanoPi R2S - - -Signed-off-by: wevsty ---- - ---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts -@@ -411,3 +411,7 @@ - realtek,led-data = <0x87>; - }; - }; -+ -+&rng { -+ status = "okay"; -+}; diff --git a/target/linux/rockchip/patches-5.4/200-rockchip-add-support-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-5.4/200-rockchip-add-support-for-NanoPi-R4S.patch deleted file mode 100644 index c56045e86..000000000 --- a/target/linux/rockchip/patches-5.4/200-rockchip-add-support-for-NanoPi-R4S.patch +++ /dev/null @@ -1,156 +0,0 @@ -From 25ac972b2e00ad04ea371d91332496e72a4b0a0b Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sat, 5 Dec 2020 12:13:37 -0500 -Subject: [PATCH] rockchip: add support for NanoPi R4S - -Signed-off-by: Marty Jones ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 131 ++++++++++++++++++ - 2 files changed, 132 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts - ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts -@@ -0,0 +1,131 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * FriendlyElec NanoPC-T4 board device tree source -+ * -+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2018 Collabora Ltd. -+ */ -+ -+/dts-v1/; -+#include "rk3399-nanopi4.dtsi" -+#include "rk3399-op1-opp.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPi R4S"; -+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399"; -+ -+ aliases { -+ ethernet1 = &r8169; -+ }; -+ -+ vdd_5v: vdd-5v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vdd_5v"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ /* FIXME: adjust leveles for the connected fan */ -+ cooling-levels = <0 12 18 255>; -+ #cooling-cells = <2>; -+ fan-supply = <&vdd_5v>; -+ pwms = <&pwm1 0 50000 0>; -+ }; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_warm: cpu_warm { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_hot: cpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map2 { -+ trip = <&cpu_warm>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map3 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&emmc_phy { -+ status = "disabled"; -+}; -+ -+&fusb0 { -+ status = "disabled"; -+}; -+ -+&pcie0 { -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+ -+ pcie@0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ r8169: pcie@0,0 { -+ reg = <0x000000 0 0 0 0>; -+ local-mac-address = [ 00 00 00 00 00 00 ]; -+ }; -+ }; -+}; -+ -+&sdhci { -+ status = "disabled"; -+}; -+ -+&sdio0 { -+ status = "disabled"; -+}; -+ -+&sdmmc { -+ host-index-min = <1>; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vdd_5v>; -+}; -+ -+&u2phy1_host { -+ status = "disabled"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+}; -+ -+&vcc3v3_sys { -+ vin-supply = <&vcc5v0_sys>; -+}; -+ -+&leds { -+ led@2 { -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ label = "lan_led"; -+ }; -+ -+ led@3 { -+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+ label = "wan_led"; -+ }; -+}; \ No newline at end of file