From 35f20da58db0938efe839480648b4644f3561489 Mon Sep 17 00:00:00 2001
From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com>
Date: Tue, 27 Sep 2022 23:28:40 +0800
Subject: [PATCH] rockchip: rock3a: fixes pcie3 support

---
 .../boot/dts/rockchip/rk3568-rock-3a.dts      | 44 +++++++++++++++----
 1 file changed, 35 insertions(+), 9 deletions(-)

diff --git a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
index ee6855e03..14801aa27 100644
--- a/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/target/linux/rockchip/files-5.15/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -120,6 +120,37 @@
 		vin-supply = <&vcc5v0_usb>;
 	};
 
+	pcie30_avdd0v9: pcie30-avdd0v9 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v9";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc3v3_sys>;
+	};
+
+	/* pi6c pcie clock generator */
+	vcc3v3_pi6c_03: vcc3v3-pi6c-03 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pi6c_03";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc3v3_pcie: vcc3v3-pcie {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -450,22 +481,21 @@
 };
 
 &pcie2x1 {
-	/* M.2 slot */
 	pinctrl-names = "default";
-	pinctrl-0 = <&ngffpcie_reset_h>;
+	pinctrl-0 = <&pcie_reset_h>;
 	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };
 
 &pcie30phy {
+	phy-supply = <&vcc3v3_pi6c_03>;
 	status = "okay";
 };
 
 &pcie3x2 {
-	/* mPCIe slot */
 	pinctrl-names = "default";
-	pinctrl-0 = <&minipcie_reset_h>;
+	pinctrl-0 = <&pcie30x2m1_pins>;
 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
@@ -489,11 +519,7 @@
 			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
-		minipcie_reset_h: minipcie-reset-h {
-			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
-		ngffpcie_reset_h: ngffpcie-reset-h {
+		pcie_reset_h: pcie-reset-h {
 			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};