From 32aea04c4c5c36c19450047d6728b50c1aaf80ac Mon Sep 17 00:00:00 2001 From: AmadeusGhost <42570690+AmadeusGhost@users.noreply.github.com> Date: Thu, 15 Sep 2022 23:21:38 +0800 Subject: [PATCH] mediatek: sync upstream source code Fixes: #10156 --- target/linux/mediatek/Makefile | 3 +- .../dts/mt7622-elecom-wrc-2533gent.dts | 86 +- .../dts/mt7622-elecom-wrc-x3200gst3.dts | 436 ++++ .../mediatek/dts/mt7622-linksys-e8450.dtsi | 19 +- target/linux/mediatek/dts/mt7622-rfb1-ubi.dts | 88 +- .../dts/mt7622-ruijie-rg-ew3200gx-pro.dts | 4 +- .../mediatek/dts/mt7622-totolink-a8000ru.dts | 108 +- ...=> mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts} | 6 +- ...6-lr.dts => mt7622-ubnt-unifi-6-lr-v1.dts} | 6 +- .../dts/mt7622-ubnt-unifi-6-lr-v1.dtsi | 28 + .../mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts | 84 + .../dts/mt7622-ubnt-unifi-6-lr-v2.dts | 100 + .../dts/mt7622-ubnt-unifi-6-lr-v2.dtsi | 24 + .../mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi | 31 +- .../dts/mt7622-xiaomi-redmi-router-ax6s.dts | 158 +- .../mt7986a-xiaomi-redmi-router-ax6000.dts | 2 +- .../files/drivers/mtd/mtk-snand/Kconfig | 13 - .../files/drivers/mtd/mtk-snand/Makefile | 10 - .../drivers/mtd/mtk-snand/mtk-snand-def.h | 268 --- .../drivers/mtd/mtk-snand/mtk-snand-ecc.c | 379 ---- .../drivers/mtd/mtk-snand/mtk-snand-ids.c | 515 ----- .../drivers/mtd/mtk-snand/mtk-snand-mtd.c | 681 ------ .../drivers/mtd/mtk-snand/mtk-snand-os.c | 48 - .../drivers/mtd/mtk-snand/mtk-snand-os.h | 127 -- .../files/drivers/mtd/mtk-snand/mtk-snand.c | 1862 ----------------- .../files/drivers/mtd/mtk-snand/mtk-snand.h | 76 - .../filogic/base-files/etc/board.d/02_network | 2 +- target/linux/mediatek/filogic/config-5.15 | 1 + target/linux/mediatek/image/filogic.mk | 8 +- target/linux/mediatek/image/mt7622.mk | 66 +- .../mt7622/base-files/etc/board.d/02_network | 1 + .../mt7622/base-files/lib/upgrade/platform.sh | 12 +- target/linux/mediatek/mt7622/config-5.10 | 465 ---- target/linux/mediatek/mt7622/config-5.15 | 11 +- target/linux/mediatek/mt7623/config-5.10 | 633 ------ target/linux/mediatek/mt7623/config-5.15 | 59 +- target/linux/mediatek/mt7629/config-5.10 | 305 --- target/linux/mediatek/mt7629/config-5.15 | 35 +- .../100-dts-update-mt7622-rfb1.patch | 119 -- .../101-dts-update-mt7629-rfb.patch | 60 - .../105-dts-mt7622-enable-pstore.patch | 25 - .../110-dts-fix-bpi2-console.patch | 10 - .../111-dts-fix-bpi64-console.patch | 11 - .../112-dts-fix-bpi64-lan-names.patch | 37 - .../113-dts-fix-bpi64-leds-and-buttons.patch | 56 - .../114-dts-bpi64-disable-rtc.patch | 21 - .../115-dts-bpi64-add-snand-support.patch | 41 - .../130-dts-mt7629-add-snand-support.patch | 77 - .../131-dts-mt7622-add-snand-support.patch | 81 - ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 18 - ...s-mt7623-eip97-inside-secure-support.patch | 23 - .../160-dts-mt7623-bpi-r2-earlycon.patch | 11 - ...1-dts-mt7623-bpi-r2-mmc-device-order.patch | 11 - .../162-dts-mt7623-bpi-r2-led-aliases.patch | 29 - ...163-dts-mt7623-bpi-r2-ethernet-alias.patch | 10 - ...convert-mediatek-musb.txt-to-YAML-sc.patch | 195 -- ...-mediatek-musb-add-mt8516-compatbile.patch | 25 - ...s-usb-mtk-musb-add-MT7623-compatible.patch | 23 - ...arm-dts-mt7623-add-musb-device-nodes.patch | 69 - ...80-dts-mt7622-bpi-r64-add-mt7531-irq.patch | 13 - ...-phy-phy-mtk-tphy-Add-hifsys-support.patch | 66 - .../330-mtk-snand-bmt-support.patch | 36 - .../331-mt7622-rfb1-enable-bmt.patch | 11 - .../360-mtd-add-mtk-snand-driver.patch | 21 - ...ypto-add-eip97-inside-secure-support.patch | 27 - ...01-crypto-fix-eip97-cache-incoherent.patch | 26 - ...or-add-support-for-Winbond-W25Q512JV.patch | 28 - .../500-gsw-rtl8367s-mt7622-support.patch | 25 - ...ngs-PCI-Mediatek-Update-PCIe-binding.patch | 415 ---- ...e-regmap-to-get-shared-pcie-cfg-base.patch | 217 -- ...ek-Split-PCIe-node-for-MT2712-MT7622.patch | 417 ---- ...dts-mediatek-Update-mt7629-PCIe-node.patch | 203 -- ...diatek-fix-clearing-interrupt-status.patch | 24 - ..._eth_soc-fix-return-values-and-refac.patch | 128 -- ...pers-to-extract-clause-45-regad-and-.patch | 53 - ..._eth_soc-implement-Clause-45-MDIO-ac.patch | 128 -- ...ernet-mtk_eth_soc-announce-2500baseT.patch | 10 - ...ediatek-add-support-for-coherent-DMA.patch | 96 - .../721-dts-mt7622-mediatek-fix-300mhz.patch | 27 - .../patches-5.10/800-ubnt-ledbar-driver.patch | 29 - ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 65 - .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 31 - .../103-mt7623-enable-arch-timer.patch | 20 + .../104-mt7622-add-snor-irq.patch | 10 + .../105-dts-mt7622-enable-pstore.patch | 2 +- .../115-dts-bpi64-add-snand-support.patch | 61 +- ...-infrastructure-to-support-hardware-.patch | 214 ++ ...ew-helper-to-retrieve-the-ECC-contex.patch | 31 + ...vide-a-helper-to-retrieve-a-pileline.patch | 73 + ...mem-Introduce-a-capability-structure.patch | 71 + ...ck-the-controller-extra-capabilities.patch | 51 + ...l-the-spi_mem_dtr_supports_op-helper.patch | 111 + ...an-ecc-parameter-to-the-spi_mem_op-s.patch | 72 + ...lay-a-little-bit-the-dirmap-creation.patch | 50 + ...te-direct-mapping-descriptors-for-EC.patch | 98 + ...nd-make-mtk_ecc.c-a-separated-module.patch | 1383 ++++++++++++ ...ver-for-MTK-SPI-NAND-Flash-Interface.patch | 1537 ++++++++++++++ ...-also-parse-nand-ecc-engine-if-avail.patch | 30 + ...dts-mediatek-add-mtk-snfi-for-mt7622.patch | 35 + .../121-hack-spi-nand-1b-bbm.patch | 20 + .../130-dts-mt7629-add-snand-support.patch | 83 +- .../131-dts-mt7622-add-snand-support.patch | 103 +- ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 18 +- ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 106 + ...mt7622-specify-the-L2-cache-topology.patch | 132 ++ ...2-specify-the-number-of-DMA-requests.patch | 122 ++ ...spi-mediatek-add-mt7986-spi-support.patch} | 0 ...dblock-revert-warn-if-opened-on-NAND.patch | 26 + .../330-mtk-snand-bmt-support.patch | 36 - .../330-snand-mtk-bmt-support.patch | 34 + .../331-mt7622-rfb1-enable-bmt.patch | 15 +- ...Add-support-for-the-Fidelix-FM35X1GA.patch | 122 ++ .../360-mtd-add-mtk-snand-driver.patch | 21 - .../500-gsw-rtl8367s-mt7622-support.patch | 2 +- ...ek-Split-PCIe-node-for-MT2712-and-MT.patch | 4 +- ...s-mediatek-add-mt7622-pcie-slot-node.patch | 4 +- ...dts-mediatek-Update-mt7629-PCIe-node.patch | 4 +- ...ediatek-add-support-for-coherent-DMA.patch | 4 +- .../722-remove-300Hz-to-prevent-freeze.patch | 25 + ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 2 +- .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 2 +- 121 files changed, 5587 insertions(+), 8955 deletions(-) create mode 100644 target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts rename target/linux/mediatek/dts/{mt7622-ubnt-unifi-6-lr-ubootmod.dts => mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts} (89%) rename target/linux/mediatek/dts/{mt7622-ubnt-unifi-6-lr.dts => mt7622-ubnt-unifi-6-lr-v1.dts} (92%) create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts create mode 100644 target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c delete mode 100644 target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h delete mode 100644 target/linux/mediatek/mt7622/config-5.10 delete mode 100644 target/linux/mediatek/mt7623/config-5.10 delete mode 100644 target/linux/mediatek/mt7629/config-5.10 delete mode 100644 target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch delete mode 100644 target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch delete mode 100644 target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch delete mode 100644 target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch delete mode 100644 target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch delete mode 100644 target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch delete mode 100644 target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch delete mode 100644 target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch delete mode 100644 target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch delete mode 100644 target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch delete mode 100644 target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch delete mode 100644 target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch delete mode 100644 target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch delete mode 100644 target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch delete mode 100644 target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch delete mode 100644 target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch delete mode 100644 target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch delete mode 100644 target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch delete mode 100644 target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch delete mode 100644 target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch delete mode 100644 target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch delete mode 100644 target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch delete mode 100644 target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch delete mode 100644 target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch delete mode 100644 target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch delete mode 100644 target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch delete mode 100644 target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch delete mode 100644 target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch delete mode 100644 target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch delete mode 100644 target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch delete mode 100644 target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch delete mode 100644 target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch delete mode 100644 target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch delete mode 100644 target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch delete mode 100644 target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch delete mode 100644 target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch delete mode 100644 target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch create mode 100644 target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch create mode 100644 target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch create mode 100644 target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch create mode 100644 target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch create mode 100644 target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch create mode 100644 target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch create mode 100644 target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch create mode 100644 target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch create mode 100644 target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch create mode 100644 target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch create mode 100644 target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch create mode 100644 target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch create mode 100644 target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch create mode 100644 target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch create mode 100644 target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch create mode 100644 target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch create mode 100644 target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch create mode 100644 target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch create mode 100644 target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch rename target/linux/mediatek/patches-5.15/{213-spi-mediatek-add-mt7986-spi-support => 213-spi-mediatek-add-mt7986-spi-support.patch} (100%) create mode 100644 target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch delete mode 100644 target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch create mode 100644 target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch create mode 100644 target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch delete mode 100644 target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch create mode 100644 target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch diff --git a/target/linux/mediatek/Makefile b/target/linux/mediatek/Makefile index c5eaec2e1..73da79eaa 100644 --- a/target/linux/mediatek/Makefile +++ b/target/linux/mediatek/Makefile @@ -8,8 +8,7 @@ BOARDNAME:=MediaTek Ralink ARM SUBTARGETS:=mt7622 mt7623 mt7629 filogic FEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb -KERNEL_PATCHVER:=5.10 -KERNEL_TESTING_PATCHVER:=5.15 +KERNEL_PATCHVER:=5.15 include $(INCLUDE_DIR)/target.mk DEFAULT_PACKAGES += \ diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts index 867982b06..3e061ef94 100644 --- a/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts +++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts @@ -497,55 +497,65 @@ status = "okay"; }; -&snand { - mediatek,quad-spi; +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "Preloader"; - reg = <0x00000 0x0080000>; - read-only; - }; + partition@0 { + label = "Preloader"; + reg = <0x00000 0x0080000>; + read-only; + }; - partition@80000 { - label = "ATF"; - reg = <0x80000 0x0040000>; - read-only; - }; + partition@80000 { + label = "ATF"; + reg = <0x80000 0x0040000>; + read-only; + }; - partition@c0000 { - label = "uboot"; - reg = <0xc0000 0x0080000>; - read-only; - }; + partition@c0000 { + label = "uboot"; + reg = <0xc0000 0x0080000>; + read-only; + }; - partition@140000 { - label = "uboot-env"; - reg = <0x140000 0x0080000>; - read-only; - }; + partition@140000 { + label = "uboot-env"; + reg = <0x140000 0x0080000>; + read-only; + }; - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x0040000>; - read-only; - }; + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x0040000>; + read-only; + }; - partition@200000 { - label = "firmware"; - reg = <0x200000 0x2000000>; - }; + partition@200000 { + label = "firmware"; + reg = <0x200000 0x2000000>; + }; - partition@2200000 { - label = "reserved"; - reg = <0x2200000 0x4000000>; + partition@2200000 { + label = "reserved"; + reg = <0x2200000 0x4000000>; + }; }; }; }; diff --git a/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts new file mode 100644 index 000000000..fdbcbc18b --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-elecom-wrc-x3200gst3.dts @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include +#include +#include + +#include "mt7622.dtsi" +#include "mt6380.dtsi" + +/ { + model = "ELECOM WRC-X3200GST3"; + compatible = "elecom,wrc-x3200gst3", "mediatek,mt7622"; + + aliases { + serial0 = &uart0; + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_green; + label-mac-device = &wan; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512"; + }; + + memory { + reg = <0 0x40000000 0 0x1f000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "red:wps"; + gpios = <&pio 47 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WPS; + }; + + led_power_red: led-1 { + label = "red:power"; + gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_POWER; + function-enumerator = <1>; + }; + + led_power_green: led-2 { + label = "green:power"; + gpios = <&pio 49 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_POWER; + function-enumerator = <2>; + }; + + led-3 { + label = "blue:power"; + gpios = <&pio 50 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_POWER; + function-enumerator = <3>; + }; + + led-4 { + label = "white:wlan2g"; + gpios = <&pio 85 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <1>; + linux,default-trigger = "phy0tpt"; + }; + + led-5 { + label = "white:wlan5g"; + gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <2>; + linux,default-trigger = "phy1radio"; + }; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ap { + label = "ap"; + gpios = <&pio 42 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + router { + label = "router"; + gpios = <&pio 43 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + wps { + label = "wps"; + gpios = <&pio 102 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&cpu0 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&cpu1 { + proc-supply = <&mt6380_vcpu_reg>; + sram-supply = <&mt6380_vm_reg>; +}; + +&pio { + eth_pins: eth-pins { + mux { + function = "eth"; + groups = "mdc_mdio", "rgmii_via_gmac2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pad_perst", + "pcie0_1_waken", + "pcie0_1_clkreq"; + }; + }; + + pmic_bus_pins: pmic-bus-pins { + mux { + function = "pmic"; + groups = "pmic_bus"; + }; + }; + + pwm7_pins: pwm1-2-pins { + mux { + function = "pwm"; + groups = "pwm_ch7_2"; + }; + }; + + /* Serial NAND is shared pin with SPI-NOR */ + serial_nand_pins: serial-nand-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + + conf-cmd-data { + pins = "SPI_WP", "SPI_HOLD", "SPI_MOSI", + "SPI_MISO", "SPI_CS"; + drive-strength = <16>; + bias-pull-up; + }; + + conf-clk { + pins = "SPI_CLK"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0_0_tx_rx" ; + }; + }; + + watchdog_pins: watchdog-pins { + mux { + function = "watchdog"; + groups = "watchdog"; + }; + }; +}; + +ð { + pinctrl-names = "default"; + pinctrl-0 = <ð_pins>; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-connection-type = "2500base-x"; + + nvmem-cells = <&macaddr_factory_7fff4>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "mediatek,mt7531"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + wan: port@0 { + reg = <0>; + label = "wan"; + + nvmem-cells = <&macaddr_factory_7fffa>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan1"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&bch { + status = "okay"; +}; + +&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-remap-range = <0x0 0x8c0000>, + <0x1bc0000 0x30c0000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; + + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; + + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x80000>; + read-only; + }; + + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x100000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + + macaddr_factory_7fff4: macaddr@7fff4 { + reg = <0x7fff4 0x6>; + }; + + macaddr_factory_7fffa: macaddr@7fffa { + reg = <0x7fffa 0x6>; + }; + }; + + partition@2c0000 { + label = "kernel"; + reg = <0x2c0000 0x600000>; + }; + + partition@8c0000 { + label = "ubi"; + reg = <0x8c0000 0x1300000>; + }; + + partition@1bc0000 { + label = "tm_pattern"; + reg = <0x1bc0000 0x500000>; + read-only; + }; + + partition@20c0000 { + label = "tm_key"; + reg = <0x20c0000 0x100000>; + read-only; + }; + + partition@21c0000 { + label = "user_data"; + reg = <0x21c0000 0xf00000>; + read-only; + }; + + partition@30c0000 { + label = "reserved"; + reg = <0x30c0000 0x4f40000>; + read-only; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&slot0 { + status = "okay"; + + wifi@0,0 { + compatible = "mediatek,mt76"; + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x5000>; + ieee80211-freq-limit = <5000000 6000000>; + nvmem-cells = <&macaddr_factory_4>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + status = "okay"; +}; + +&pwrap { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_bus_pins>; + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; + status = "okay"; +}; + +&wmac { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; diff --git a/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi b/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi index 047a4a59e..1fe839575 100644 --- a/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi +++ b/target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi @@ -336,17 +336,30 @@ }; &slot0 { - wmac1: mt7915@0,0 { + wmac1: wifi@0,0 { + compatible = "mediatek,mt76"; reg = <0x0000 0 0 0 0>; ieee80211-freq-limit = <5000000 6000000>; + mediatek,disable-radar-background; }; }; -&snand { - mediatek,quad-spi; +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; + + snand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + }; }; &spi0 { diff --git a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts index 1a94446c7..0f6d9bbc5 100644 --- a/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts +++ b/target/linux/mediatek/dts/mt7622-rfb1-ubi.dts @@ -6,51 +6,53 @@ compatible = "mediatek,mt7622-rfb1-ubi"; }; -&snand { - mediatek,bmt-v2; - mediatek,bmt-remap-range = <0x0 0x6c0000>; +&snfi { + flash@0 { + mediatek,bmt-v2; + mediatek,bmt-remap-range = <0x0 0x6c0000>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "Preloader"; - reg = <0x00000 0x0080000>; - read-only; + partition@0 { + label = "Preloader"; + reg = <0x00000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "ATF"; + reg = <0x80000 0x0040000>; + }; + + partition@c0000 { + label = "Bootloader"; + reg = <0xc0000 0x0080000>; + }; + + partition@140000 { + label = "Config"; + reg = <0x140000 0x0080000>; + }; + + factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0100000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x2c0000 0x400000>; + }; + + partition@6c0000 { + label = "ubi"; + reg = <0x6c0000 0x6f00000>; + }; + + /delete-node/ partition@2200000; }; - - partition@80000 { - label = "ATF"; - reg = <0x80000 0x0040000>; - }; - - partition@c0000 { - label = "Bootloader"; - reg = <0xc0000 0x0080000>; - }; - - partition@140000 { - label = "Config"; - reg = <0x140000 0x0080000>; - }; - - factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; - - partition@200000 { - label = "kernel"; - reg = <0x2c0000 0x400000>; - }; - - partition@6c0000 { - label = "ubi"; - reg = <0x6c0000 0x6f00000>; - }; - - /delete-node/ partition@2200000; }; }; diff --git a/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts b/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts index df8f2a581..fba9a1b8f 100644 --- a/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts +++ b/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts @@ -164,10 +164,12 @@ }; &slot0 { - mt7915@0,0 { + wifi@0,0 { + compatible = "mediatek,mt76"; reg = <0x0000 0 0 0 0>; mediatek,mtd-eeprom = <&factory 0x5000>; ieee80211-freq-limit = <5000000 6000000>; + mediatek,disable-radar-background; }; }; diff --git a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts index 0386865cc..b634e2878 100644 --- a/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts +++ b/target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts @@ -80,6 +80,15 @@ regulator-always-on; }; + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + rtkgsw: rtkgsw@0 { compatible = "mediatek,rtk-gsw"; mediatek,ethsys = <ðsys>; @@ -226,62 +235,72 @@ status = "okay"; }; -&snand { - mediatek,quad-spi; +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; - mediatek,bmt-v2; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; + mediatek,bmt-v2; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "Preloader"; - reg = <0x0 0x80000>; - read-only; - }; + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; + }; - partition@80000 { - label = "ATF"; - reg = <0x80000 0x40000>; - read-only; - }; + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; - partition@c0000 { - label = "u-boot"; - reg = <0xc0000 0x80000>; - read-only; - }; + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; - partition@140000 { - label = "u-boot-env"; - reg = <0x140000 0x80000>; - read-only; - }; + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x80000>; + read-only; + }; - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x40000>; - read-only; - }; + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x40000>; + read-only; + }; - partition@200000 { - label = "ubi"; - reg = <0x200000 0x6400000>; - }; + partition@200000 { + label = "ubi"; + reg = <0x200000 0x6400000>; + }; - partition@6600000 { - label = "User_data"; - reg = <0x6600000 0x100000>; - }; + partition@6600000 { + label = "User_data"; + reg = <0x6600000 0x100000>; + }; - /* size of this partition varies due to BMT & bad blocks. */ - partition@6700000 { - label = "reserved"; - reg = <0x6700000 0>; + /* size of this partition varies due to BMT & bad blocks. */ + partition@6700000 { + label = "reserved"; + reg = <0x6700000 0>; + }; }; }; }; @@ -302,6 +321,7 @@ &ssusb { vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; status = "okay"; }; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts similarity index 89% rename from target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-ubootmod.dts rename to target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts index e573d3091..5b1fd1d9b 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-ubootmod.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1-ubootmod.dts @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "mt7622-ubnt-unifi-6-lr.dtsi" +#include "mt7622-ubnt-unifi-6-lr-v1.dtsi" / { - model = "Ubiquiti UniFi 6 LR (U-Boot mod)"; - compatible = "ubnt,unifi-6-lr-ubootmod", "mediatek,mt7622"; + model = "Ubiquiti UniFi 6 LR v1 (U-Boot mod)"; + compatible = "ubnt,unifi-6-lr-v1-ubootmod", "mediatek,mt7622"; }; &nor_partitions { diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts similarity index 92% rename from target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dts rename to target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts index 9b676b43c..95f19af4c 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dts +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dts @@ -1,10 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -#include "mt7622-ubnt-unifi-6-lr.dtsi" +#include "mt7622-ubnt-unifi-6-lr-v1.dtsi" / { - model = "Ubiquiti UniFi 6 LR"; - compatible = "ubnt,unifi-6-lr", "mediatek,mt7622"; + model = "Ubiquiti UniFi 6 LR v1"; + compatible = "ubnt,unifi-6-lr-v1", "mediatek,mt7622"; }; &nor_partitions { diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi new file mode 100644 index 000000000..b3299a988 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v1.dtsi @@ -0,0 +1,28 @@ +#include "mt7622-ubnt-unifi-6-lr.dtsi" + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + led-controller@30 { + compatible = "ubnt,ledbar"; + reg = <0x30>; + + enable-gpio = <&pio 59 GPIO_ACTIVE_LOW>; + reset-gpio = <&pio 60 GPIO_ACTIVE_LOW>; + + red { + label = "red"; + }; + + green { + label = "green"; + }; + + led_blue: blue { + label = "blue"; + }; + }; +}; + diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts new file mode 100644 index 000000000..6a7b6868c --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2-ubootmod.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7622-ubnt-unifi-6-lr-v2.dtsi" + +/ { + model = "Ubiquiti UniFi 6 LR v2 (U-Boot mod)"; + compatible = "ubnt,unifi-6-lr-v2-ubootmod", "mediatek,mt7622"; +}; + +&nor_partitions { + partition@0 { + label = "bl2"; + reg = <0x0 0x20000>; + }; + + partition@20000 { + label = "fip"; + reg = <0x20000 0xa0000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + factory: partition@d0000 { + label = "factory"; + reg = <0xd0000 0x40000>; + read-only; + }; + + eeprom: partition@110000 { + label = "eeprom"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "recovery"; + reg = <0x120000 0xee0000>; + }; + + partition@1000000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x1000000 0x3000000>; + }; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&slot0 { + wifi@0,0 { + reg = <0x0 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x20000>; + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts new file mode 100644 index 000000000..f40e8e632 --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "mt7622-ubnt-unifi-6-lr-v2.dtsi" + +/ { + model = "Ubiquiti UniFi 6 LR v2"; + compatible = "ubnt,unifi-6-lr-v2", "mediatek,mt7622"; +}; + +&nor_partitions { + partition@0 { + label = "preloader"; + reg = <0x0 0x40000>; + }; + + partition@40000 { + label = "atf"; + reg = <0x40000 0x20000>; + }; + + partition@60000 { + label = "u-boot"; + reg = <0x60000 0x60000>; + }; + + partition@c0000 { + label = "u-boot-env"; + reg = <0xc0000 0x10000>; + }; + + factory: partition@d0000 { + label = "factory"; + reg = <0xd0000 0x40000>; + read-only; + }; + + eeprom: partition@110000 { + label = "eeprom"; + reg = <0x110000 0x10000>; + read-only; + }; + + partition@120000 { + label = "bs"; + reg = <0x120000 0x10000>; + }; + + partition@130000 { + label = "cfg"; + reg = <0x130000 0x100000>; + read-only; + }; + + partition@230000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x230000 0x1ee0000>; + }; + + partition@2110000 { + label = "kernel1"; + reg = <0x2110000 0x1ee0000>; + }; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&slot0 { + wifi@0,0 { + reg = <0x0 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x20000>; + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&gmac0 { + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi new file mode 100644 index 000000000..4d278805d --- /dev/null +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-v2.dtsi @@ -0,0 +1,24 @@ +#include "mt7622-ubnt-unifi-6-lr.dtsi" + +/ { + aliases { + led-boot = &led_white; + led-failsafe = &led_white; + led-running = &led_blue; + led-upgrade = &led_blue; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led_white: dome_white { + label = "white:dome"; + gpios = <&pio 0x43 GPIO_ACTIVE_LOW>; + }; + + led_blue: dome_blue { + label = "blue:dome"; + gpios = <&pio 0x44 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi index ae587a11a..4231cc1f7 100644 --- a/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi +++ b/target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi @@ -203,6 +203,12 @@ }; }; +&rtc { + status = "disabled"; + + /* No RTC battery */ +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; @@ -217,31 +223,6 @@ /* MT7915 Bluetooth */ }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - led-controller@30 { - compatible = "ubnt,ledbar"; - reg = <0x30>; - - enable-gpio = <&pio 59 0>; - - red { - label = "red"; - }; - - green { - label = "green"; - }; - - led_blue: blue { - label = "blue"; - }; - }; -}; - &watchdog { pinctrl-names = "default"; pinctrl-0 = <&watchdog_pins>; diff --git a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts index 933d2c927..73ee41bb2 100644 --- a/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts +++ b/target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts @@ -211,94 +211,105 @@ }; }; -&snand { +&bch { + status = "okay"; +}; + +&snfi { pinctrl-names = "default"; pinctrl-0 = <&serial_nand_pins>; status = "okay"; - mediatek,bmt-v2; - mediatek,bmt-table-size = <0x1000>; - mediatek,bmt-remap-range = <0x0 0x6c0000>; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; + mediatek,bmt-v2; + mediatek,bmt-table-size = <0x1000>; + mediatek,bmt-remap-range = <0x0 0x6c0000>; - partition@0 { - label = "Preloader"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@80000 { - label = "ATF"; - reg = <0x80000 0x40000>; - read-only; - }; - - partition@c0000 { - label = "u-boot"; - reg = <0xc0000 0x80000>; - read-only; - }; - - partition@140000 { - label = "u-boot-env"; - reg = <0x140000 0x40000>; - }; - - partition@180000 { - label = "bdata"; - reg = <0x180000 0x40000>; - }; - - factory: partition@1c0000 { - label = "factory"; - reg = <0x1c0000 0x80000>; - read-only; - - compatible = "nvmem-cells"; + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - macaddr_factory_4: macaddr@4 { - reg = <0x4 0x6>; + partition@0 { + label = "Preloader"; + reg = <0x0 0x80000>; + read-only; }; - }; - partition@240000 { - label = "crash"; - reg = <0x240000 0x40000>; - read-only; - }; + partition@80000 { + label = "ATF"; + reg = <0x80000 0x40000>; + read-only; + }; - partition@280000 { - label = "crash_log"; - reg = <0x280000 0x40000>; - read-only; - }; + partition@c0000 { + label = "u-boot"; + reg = <0xc0000 0x80000>; + read-only; + }; - /* Shrunk and renamed from "firmware" - * as to not break luci size checks - */ - partition@2c0000 { - label = "kernel"; - compatible = "denx,fit"; - reg = <0x2c0000 0x400000>; - }; + partition@140000 { + label = "u-boot-env"; + reg = <0x140000 0x40000>; + }; + partition@180000 { + label = "bdata"; + reg = <0x180000 0x40000>; + }; - /* ubi partition is the result of squashing - * consecutive stock partitions: - * - firmware (partially) - * - firmware1 - * - overlay - * - obr - */ - partition@6c0000 { - label = "ubi"; - reg = <0x6C0000 0x6f00000>; + factory: partition@1c0000 { + label = "factory"; + reg = <0x1c0000 0x80000>; + read-only; + + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_4: macaddr@4 { + reg = <0x4 0x6>; + }; + }; + + partition@240000 { + label = "crash"; + reg = <0x240000 0x40000>; + read-only; + }; + + partition@280000 { + label = "crash_log"; + reg = <0x280000 0x40000>; + read-only; + }; + + /* Shrunk and renamed from "firmware" + * as to not break luci size checks + */ + partition@2c0000 { + label = "kernel"; + compatible = "denx,fit"; + reg = <0x2c0000 0x400000>; + }; + + /* ubi partition is the result of squashing + * consecutive stock partitions: + * - firmware (partially) + * - firmware1 + * - overlay + * - obr + */ + partition@6c0000 { + label = "ubi"; + reg = <0x6C0000 0x6f00000>; + }; }; }; }; @@ -317,6 +328,7 @@ reg = <0x0000 0 0 0 0>; mediatek,mtd-eeprom = <&factory 0x5000>; ieee80211-freq-limit = <5000000 6000000>; + mediatek,disable-radar-background; }; }; diff --git a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts index 86b887237..28855836a 100644 --- a/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts +++ b/target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts @@ -145,7 +145,7 @@ mediatek,nmbm; mediatek,bmt-max-ratio = <1>; mediatek,bmt-max-reserved-blocks = <64>; - mediatek,bmt-remap-range = <0x0000000 0xa00000>; + mediatek,bmt-remap-range = <0x0 0x600000>; spi-max-frequency = <20000000>; spi-tx-buswidth = <4>; diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig b/target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig deleted file mode 100644 index 58aa56383..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 MediaTek Inc. All rights reserved. -# Author: Weijie Gao -# - -config MTK_SPI_NAND - tristate "MediaTek SPI NAND flash controller driver" - depends on MTD - default n - help - This option enables access to SPI-NAND flashes through the - MTD interface of MediaTek SPI NAND Flash Controller diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile b/target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile deleted file mode 100644 index e6b371004..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2020 MediaTek Inc. All rights reserved. -# Author: Weijie Gao -# - -obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o \ - mtk-snand-mtd.o - -ccflags-y += -DPRIVATE_MTK_SNAND_HEADER diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h deleted file mode 100644 index 1a93d93dc..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-def.h +++ /dev/null @@ -1,268 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#ifndef _MTK_SNAND_DEF_H_ -#define _MTK_SNAND_DEF_H_ - -#include "mtk-snand-os.h" - -#ifdef PRIVATE_MTK_SNAND_HEADER -#include "mtk-snand.h" -#else -#include -#endif - -struct mtk_snand_plat_dev; - -enum snand_flash_io { - SNAND_IO_1_1_1, - SNAND_IO_1_1_2, - SNAND_IO_1_2_2, - SNAND_IO_1_1_4, - SNAND_IO_1_4_4, - - __SNAND_IO_MAX -}; - -#define SPI_IO_1_1_1 BIT(SNAND_IO_1_1_1) -#define SPI_IO_1_1_2 BIT(SNAND_IO_1_1_2) -#define SPI_IO_1_2_2 BIT(SNAND_IO_1_2_2) -#define SPI_IO_1_1_4 BIT(SNAND_IO_1_1_4) -#define SPI_IO_1_4_4 BIT(SNAND_IO_1_4_4) - -struct snand_opcode { - uint8_t opcode; - uint8_t dummy; -}; - -struct snand_io_cap { - uint8_t caps; - struct snand_opcode opcodes[__SNAND_IO_MAX]; -}; - -#define SNAND_OP(_io, _opcode, _dummy) [_io] = { .opcode = (_opcode), \ - .dummy = (_dummy) } - -#define SNAND_IO_CAP(_name, _caps, ...) \ - struct snand_io_cap _name = { .caps = (_caps), \ - .opcodes = { __VA_ARGS__ } } - -#define SNAND_MAX_ID_LEN 4 - -enum snand_id_type { - SNAND_ID_DYMMY, - SNAND_ID_ADDR = SNAND_ID_DYMMY, - SNAND_ID_DIRECT, - - __SNAND_ID_TYPE_MAX -}; - -struct snand_id { - uint8_t type; /* enum snand_id_type */ - uint8_t len; - uint8_t id[SNAND_MAX_ID_LEN]; -}; - -#define SNAND_ID(_type, ...) \ - { .type = (_type), .id = { __VA_ARGS__ }, \ - .len = sizeof((uint8_t[]) { __VA_ARGS__ }) } - -struct snand_mem_org { - uint16_t pagesize; - uint16_t sparesize; - uint16_t pages_per_block; - uint16_t blocks_per_die; - uint16_t planes_per_die; - uint16_t ndies; -}; - -#define SNAND_MEMORG(_ps, _ss, _ppb, _bpd, _ppd, _nd) \ - { .pagesize = (_ps), .sparesize = (_ss), .pages_per_block = (_ppb), \ - .blocks_per_die = (_bpd), .planes_per_die = (_ppd), .ndies = (_nd) } - -typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx); - -struct snand_flash_info { - const char *model; - struct snand_id id; - const struct snand_mem_org memorg; - const struct snand_io_cap *cap_rd; - const struct snand_io_cap *cap_pl; - snand_select_die_t select_die; -}; - -#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \ - { .model = (_model), .id = _id, .memorg = _memorg, \ - .cap_rd = (_cap_rd), .cap_pl = (_cap_pl), __VA_ARGS__ } - -const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type, - const uint8_t *id); - -struct mtk_snand_soc_data { - uint16_t sector_size; - uint16_t max_sectors; - uint16_t fdm_size; - uint16_t fdm_ecc_size; - uint16_t fifo_size; - - bool bbm_swap; - bool empty_page_check; - uint32_t mastersta_mask; - - const uint8_t *spare_sizes; - uint32_t num_spare_size; -}; - -enum mtk_ecc_regs { - ECC_DECDONE, -}; - -struct mtk_ecc_soc_data { - const uint8_t *ecc_caps; - uint32_t num_ecc_cap; - const uint32_t *regs; - uint16_t mode_shift; - uint8_t errnum_bits; - uint8_t errnum_shift; -}; - -struct mtk_snand { - struct mtk_snand_plat_dev *pdev; - - void __iomem *nfi_base; - void __iomem *ecc_base; - - enum mtk_snand_soc soc; - const struct mtk_snand_soc_data *nfi_soc; - const struct mtk_ecc_soc_data *ecc_soc; - bool snfi_quad_spi; - bool quad_spi_op; - - const char *model; - uint64_t size; - uint64_t die_size; - uint32_t erasesize; - uint32_t writesize; - uint32_t oobsize; - - uint32_t num_dies; - snand_select_die_t select_die; - - uint8_t opcode_rfc; - uint8_t opcode_pl; - uint8_t dummy_rfc; - uint8_t mode_rfc; - uint8_t mode_pl; - - uint32_t writesize_mask; - uint32_t writesize_shift; - uint32_t erasesize_mask; - uint32_t erasesize_shift; - uint64_t die_mask; - uint32_t die_shift; - - uint32_t spare_per_sector; - uint32_t raw_sector_size; - uint32_t ecc_strength; - uint32_t ecc_steps; - uint32_t ecc_bytes; - uint32_t ecc_parity_bits; - - uint8_t *page_cache; /* Used by read/write page */ - uint8_t *buf_cache; /* Used by block bad/markbad & auto_oob */ - int *sect_bf; /* Used by ECC correction */ -}; - -enum mtk_snand_log_category { - SNAND_LOG_NFI, - SNAND_LOG_SNFI, - SNAND_LOG_ECC, - SNAND_LOG_CHIP, - - __SNAND_LOG_CAT_MAX -}; - -int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes, - uint32_t msg_size); -int mtk_snand_ecc_encoder_start(struct mtk_snand *snf); -void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf); -int mtk_snand_ecc_decoder_start(struct mtk_snand *snf); -void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf); -int mtk_ecc_wait_decoder_done(struct mtk_snand *snf); -int mtk_ecc_check_decode_error(struct mtk_snand *snf); -int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect); - -int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen, - uint8_t *in, uint32_t inlen); -int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val); - -int mtk_snand_log(struct mtk_snand_plat_dev *pdev, - enum mtk_snand_log_category cat, const char *fmt, ...); - -#define snand_log_nfi(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_NFI, fmt, ##__VA_ARGS__) - -#define snand_log_snfi(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_SNFI, fmt, ##__VA_ARGS__) - -#define snand_log_ecc(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_ECC, fmt, ##__VA_ARGS__) - -#define snand_log_chip(pdev, fmt, ...) \ - mtk_snand_log(pdev, SNAND_LOG_CHIP, fmt, ##__VA_ARGS__) - -/* ffs64 */ -static inline int mtk_snand_ffs64(uint64_t x) -{ - if (!x) - return 0; - - if (!(x & 0xffffffff)) - return ffs((uint32_t)(x >> 32)) + 32; - - return ffs((uint32_t)(x & 0xffffffff)); -} - -/* NFI dummy commands */ -#define NFI_CMD_DUMMY_READ 0x00 -#define NFI_CMD_DUMMY_WRITE 0x80 - -/* SPI-NAND opcodes */ -#define SNAND_CMD_RESET 0xff -#define SNAND_CMD_BLOCK_ERASE 0xd8 -#define SNAND_CMD_READ_FROM_CACHE_QUAD 0xeb -#define SNAND_CMD_WINBOND_SELECT_DIE 0xc2 -#define SNAND_CMD_READ_FROM_CACHE_DUAL 0xbb -#define SNAND_CMD_READID 0x9f -#define SNAND_CMD_READ_FROM_CACHE_X4 0x6b -#define SNAND_CMD_READ_FROM_CACHE_X2 0x3b -#define SNAND_CMD_PROGRAM_LOAD_X4 0x32 -#define SNAND_CMD_SET_FEATURE 0x1f -#define SNAND_CMD_READ_TO_CACHE 0x13 -#define SNAND_CMD_PROGRAM_EXECUTE 0x10 -#define SNAND_CMD_GET_FEATURE 0x0f -#define SNAND_CMD_READ_FROM_CACHE 0x0b -#define SNAND_CMD_WRITE_ENABLE 0x06 -#define SNAND_CMD_PROGRAM_LOAD 0x02 - -/* SPI-NAND feature addresses */ -#define SNAND_FEATURE_MICRON_DIE_ADDR 0xd0 -#define SNAND_MICRON_DIE_SEL_1 BIT(6) - -#define SNAND_FEATURE_STATUS_ADDR 0xc0 -#define SNAND_STATUS_OIP BIT(0) -#define SNAND_STATUS_WEL BIT(1) -#define SNAND_STATUS_ERASE_FAIL BIT(2) -#define SNAND_STATUS_PROGRAM_FAIL BIT(3) - -#define SNAND_FEATURE_CONFIG_ADDR 0xb0 -#define SNAND_FEATURE_QUAD_ENABLE BIT(0) -#define SNAND_FEATURE_ECC_EN BIT(4) - -#define SNAND_FEATURE_PROTECT_ADDR 0xa0 - -#endif /* _MTK_SNAND_DEF_H_ */ diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c deleted file mode 100644 index 6dd0f346c..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ecc.c +++ /dev/null @@ -1,379 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -/* ECC registers */ -#define ECC_ENCCON 0x000 -#define ENC_EN BIT(0) - -#define ECC_ENCCNFG 0x004 -#define ENC_MS_S 16 -#define ENC_BURST_EN BIT(8) -#define ENC_TNUM_S 0 - -#define ECC_ENCIDLE 0x00c -#define ENC_IDLE BIT(0) - -#define ECC_DECCON 0x100 -#define DEC_EN BIT(0) - -#define ECC_DECCNFG 0x104 -#define DEC_EMPTY_EN BIT(31) -#define DEC_CS_S 16 -#define DEC_CON_S 12 -#define DEC_CON_CORRECT 3 -#define DEC_BURST_EN BIT(8) -#define DEC_TNUM_S 0 - -#define ECC_DECIDLE 0x10c -#define DEC_IDLE BIT(0) - -#define ECC_DECENUM0 0x114 -#define ECC_DECENUM(n) (ECC_DECENUM0 + (n) * 4) - -/* ECC_ENCIDLE & ECC_DECIDLE */ -#define ECC_IDLE BIT(0) - -/* ENC_MODE & DEC_MODE */ -#define ECC_MODE_NFI 1 - -#define ECC_TIMEOUT 500000 - -static const uint8_t mt7622_ecc_caps[] = { 4, 6, 8, 10, 12 }; - -static const uint32_t mt7622_ecc_regs[] = { - [ECC_DECDONE] = 0x11c, -}; - -static const struct mtk_ecc_soc_data mtk_ecc_socs[__SNAND_SOC_MAX] = { - [SNAND_SOC_MT7622] = { - .ecc_caps = mt7622_ecc_caps, - .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps), - .regs = mt7622_ecc_regs, - .mode_shift = 4, - .errnum_bits = 5, - .errnum_shift = 5, - }, - [SNAND_SOC_MT7629] = { - .ecc_caps = mt7622_ecc_caps, - .num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps), - .regs = mt7622_ecc_regs, - .mode_shift = 4, - .errnum_bits = 5, - .errnum_shift = 5, - }, -}; - -static inline uint32_t ecc_read32(struct mtk_snand *snf, uint32_t reg) -{ - return readl(snf->ecc_base + reg); -} - -static inline void ecc_write32(struct mtk_snand *snf, uint32_t reg, - uint32_t val) -{ - writel(val, snf->ecc_base + reg); -} - -static inline void ecc_write16(struct mtk_snand *snf, uint32_t reg, - uint16_t val) -{ - writew(val, snf->ecc_base + reg); -} - -static int mtk_ecc_poll(struct mtk_snand *snf, uint32_t reg, uint32_t bits) -{ - uint32_t val; - - return read16_poll_timeout(snf->ecc_base + reg, val, (val & bits), 0, - ECC_TIMEOUT); -} - -static int mtk_ecc_wait_idle(struct mtk_snand *snf, uint32_t reg) -{ - int ret; - - ret = mtk_ecc_poll(snf, reg, ECC_IDLE); - if (ret) { - snand_log_ecc(snf->pdev, "ECC engine is busy\n"); - return -EBUSY; - } - - return 0; -} - -int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes, - uint32_t msg_size) -{ - uint32_t i, val, ecc_msg_bits, ecc_strength; - int ret; - - snf->ecc_soc = &mtk_ecc_socs[snf->soc]; - - snf->ecc_parity_bits = fls(1 + 8 * msg_size); - ecc_strength = max_ecc_bytes * 8 / snf->ecc_parity_bits; - - for (i = snf->ecc_soc->num_ecc_cap - 1; i >= 0; i--) { - if (snf->ecc_soc->ecc_caps[i] <= ecc_strength) - break; - } - - if (unlikely(i < 0)) { - snand_log_ecc(snf->pdev, "Page size %u+%u is not supported\n", - snf->writesize, snf->oobsize); - return -ENOTSUPP; - } - - snf->ecc_strength = snf->ecc_soc->ecc_caps[i]; - snf->ecc_bytes = DIV_ROUND_UP(snf->ecc_strength * snf->ecc_parity_bits, - 8); - - /* Encoder config */ - ecc_write16(snf, ECC_ENCCON, 0); - ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - if (ret) - return ret; - - ecc_msg_bits = msg_size * 8; - val = (ecc_msg_bits << ENC_MS_S) | - (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i; - ecc_write32(snf, ECC_ENCCNFG, val); - - /* Decoder config */ - ecc_write16(snf, ECC_DECCON, 0); - ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE); - if (ret) - return ret; - - ecc_msg_bits += snf->ecc_strength * snf->ecc_parity_bits; - val = DEC_EMPTY_EN | (ecc_msg_bits << DEC_CS_S) | - (DEC_CON_CORRECT << DEC_CON_S) | - (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i; - ecc_write32(snf, ECC_DECCNFG, val); - - return 0; -} - -int mtk_snand_ecc_encoder_start(struct mtk_snand *snf) -{ - int ret; - - ret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - if (ret) { - ecc_write16(snf, ECC_ENCCON, 0); - mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - } - - ecc_write16(snf, ECC_ENCCON, ENC_EN); - - return 0; -} - -void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf) -{ - mtk_ecc_wait_idle(snf, ECC_ENCIDLE); - ecc_write16(snf, ECC_ENCCON, 0); -} - -int mtk_snand_ecc_decoder_start(struct mtk_snand *snf) -{ - int ret; - - ret = mtk_ecc_wait_idle(snf, ECC_DECIDLE); - if (ret) { - ecc_write16(snf, ECC_DECCON, 0); - mtk_ecc_wait_idle(snf, ECC_DECIDLE); - } - - ecc_write16(snf, ECC_DECCON, DEC_EN); - - return 0; -} - -void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf) -{ - mtk_ecc_wait_idle(snf, ECC_DECIDLE); - ecc_write16(snf, ECC_DECCON, 0); -} - -int mtk_ecc_wait_decoder_done(struct mtk_snand *snf) -{ - uint16_t val, step_mask = (1 << snf->ecc_steps) - 1; - uint32_t reg = snf->ecc_soc->regs[ECC_DECDONE]; - int ret; - - ret = read16_poll_timeout(snf->ecc_base + reg, val, - (val & step_mask) == step_mask, 0, - ECC_TIMEOUT); - if (ret) - snand_log_ecc(snf->pdev, "ECC decoder is busy\n"); - - return ret; -} - -int mtk_ecc_check_decode_error(struct mtk_snand *snf) -{ - uint32_t i, regi, fi, errnum; - uint32_t errnum_shift = snf->ecc_soc->errnum_shift; - uint32_t errnum_mask = (1 << snf->ecc_soc->errnum_bits) - 1; - int ret = 0; - - for (i = 0; i < snf->ecc_steps; i++) { - regi = i / 4; - fi = i % 4; - - errnum = ecc_read32(snf, ECC_DECENUM(regi)); - errnum = (errnum >> (fi * errnum_shift)) & errnum_mask; - - if (errnum <= snf->ecc_strength) { - snf->sect_bf[i] = errnum; - } else { - snf->sect_bf[i] = -1; - ret = -EBADMSG; - } - } - - return ret; -} - -static int mtk_ecc_check_buf_bitflips(struct mtk_snand *snf, const void *buf, - size_t len, uint32_t bitflips) -{ - const uint8_t *buf8 = buf; - const uint32_t *buf32; - uint32_t d, weight; - - while (len && ((uintptr_t)buf8) % sizeof(uint32_t)) { - weight = hweight8(*buf8); - bitflips += BITS_PER_BYTE - weight; - buf8++; - len--; - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - } - - buf32 = (const uint32_t *)buf8; - while (len >= sizeof(uint32_t)) { - d = *buf32; - - if (d != ~0) { - weight = hweight32(d); - bitflips += sizeof(uint32_t) * BITS_PER_BYTE - weight; - } - - buf32++; - len -= sizeof(uint32_t); - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - } - - buf8 = (const uint8_t *)buf32; - while (len) { - weight = hweight8(*buf8); - bitflips += BITS_PER_BYTE - weight; - buf8++; - len--; - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - } - - return bitflips; -} - -static int mtk_ecc_check_parity_bitflips(struct mtk_snand *snf, const void *buf, - uint32_t bits, uint32_t bitflips) -{ - uint32_t len, i; - uint8_t b; - int rc; - - len = bits >> 3; - bits &= 7; - - rc = mtk_ecc_check_buf_bitflips(snf, buf, len, bitflips); - if (!bits || rc < 0) - return rc; - - bitflips = rc; - - /* We want a precise count of bits */ - b = ((const uint8_t *)buf)[len]; - for (i = 0; i < bits; i++) { - if (!(b & BIT(i))) - bitflips++; - } - - if (bitflips > snf->ecc_strength) - return -EBADMSG; - - return bitflips; -} - -static void mtk_ecc_reset_parity(void *buf, uint32_t bits) -{ - uint32_t len; - - len = bits >> 3; - bits &= 7; - - memset(buf, 0xff, len); - - /* Only reset bits protected by ECC to 1 */ - if (bits) - ((uint8_t *)buf)[len] |= GENMASK(bits - 1, 0); -} - -int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect) -{ - uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - uint8_t *oob = snf->page_cache + snf->writesize; - uint8_t *data_ptr, *fdm_ptr, *ecc_ptr; - int bitflips = 0, ecc_bits, parity_bits; - - parity_bits = fls(snf->nfi_soc->sector_size * 8); - ecc_bits = snf->ecc_strength * parity_bits; - - data_ptr = snf->page_cache + sect * snf->nfi_soc->sector_size; - fdm_ptr = oob + sect * snf->nfi_soc->fdm_size; - ecc_ptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size + - sect * ecc_bytes; - - /* - * Check whether DATA + FDM + ECC of a sector contains correctable - * bitflips - */ - bitflips = mtk_ecc_check_buf_bitflips(snf, data_ptr, - snf->nfi_soc->sector_size, - bitflips); - if (bitflips < 0) - return -EBADMSG; - - bitflips = mtk_ecc_check_buf_bitflips(snf, fdm_ptr, - snf->nfi_soc->fdm_ecc_size, - bitflips); - if (bitflips < 0) - return -EBADMSG; - - bitflips = mtk_ecc_check_parity_bitflips(snf, ecc_ptr, ecc_bits, - bitflips); - if (bitflips < 0) - return -EBADMSG; - - if (!bitflips) - return 0; - - /* Reset the data of this sector to 0xff */ - memset(data_ptr, 0xff, snf->nfi_soc->sector_size); - memset(fdm_ptr, 0xff, snf->nfi_soc->fdm_ecc_size); - mtk_ecc_reset_parity(ecc_ptr, ecc_bits); - - return bitflips; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c deleted file mode 100644 index 89c72c10a..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-ids.c +++ /dev/null @@ -1,515 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx); -static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx); - -#define SNAND_MEMORG_512M_2K_64 SNAND_MEMORG(2048, 64, 64, 512, 1, 1) -#define SNAND_MEMORG_1G_2K_64 SNAND_MEMORG(2048, 64, 64, 1024, 1, 1) -#define SNAND_MEMORG_2G_2K_64 SNAND_MEMORG(2048, 64, 64, 2048, 1, 1) -#define SNAND_MEMORG_2G_2K_120 SNAND_MEMORG(2048, 120, 64, 2048, 1, 1) -#define SNAND_MEMORG_4G_2K_64 SNAND_MEMORG(2048, 64, 64, 4096, 1, 1) -#define SNAND_MEMORG_1G_2K_120 SNAND_MEMORG(2048, 120, 64, 1024, 1, 1) -#define SNAND_MEMORG_1G_2K_128 SNAND_MEMORG(2048, 128, 64, 1024, 1, 1) -#define SNAND_MEMORG_2G_2K_128 SNAND_MEMORG(2048, 128, 64, 2048, 1, 1) -#define SNAND_MEMORG_4G_2K_128 SNAND_MEMORG(2048, 128, 64, 4096, 1, 1) -#define SNAND_MEMORG_4G_4K_240 SNAND_MEMORG(4096, 240, 64, 2048, 1, 1) -#define SNAND_MEMORG_4G_4K_256 SNAND_MEMORG(4096, 256, 64, 2048, 1, 1) -#define SNAND_MEMORG_8G_4K_256 SNAND_MEMORG(4096, 256, 64, 4096, 1, 1) -#define SNAND_MEMORG_2G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 2048, 2, 1) -#define SNAND_MEMORG_2G_2K_64_2D SNAND_MEMORG(2048, 64, 64, 1024, 1, 2) -#define SNAND_MEMORG_2G_2K_128_2P SNAND_MEMORG(2048, 128, 64, 2048, 2, 1) -#define SNAND_MEMORG_4G_2K_64_2P SNAND_MEMORG(2048, 64, 64, 4096, 2, 1) -#define SNAND_MEMORG_4G_2K_128_2P_2D SNAND_MEMORG(2048, 128, 64, 2048, 2, 2) -#define SNAND_MEMORG_8G_4K_256_2D SNAND_MEMORG(4096, 256, 64, 2048, 1, 2) - -static const SNAND_IO_CAP(snand_cap_read_from_cache_quad, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 | - SPI_IO_1_4_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8), - SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 4)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_q2d, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 | - SPI_IO_1_4_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8), - SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 2)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_a8d, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 | - SPI_IO_1_4_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 8), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8), - SNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 8)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_x4, - SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_1_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8)); - -static const SNAND_IO_CAP(snand_cap_read_from_cache_x4_only, - SPI_IO_1_1_1 | SPI_IO_1_1_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8)); - -static const SNAND_IO_CAP(snand_cap_program_load_x1, - SPI_IO_1_1_1, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0)); - -static const SNAND_IO_CAP(snand_cap_program_load_x4, - SPI_IO_1_1_1 | SPI_IO_1_1_4, - SNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0), - SNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_PROGRAM_LOAD_X4, 0)); - -static const struct snand_flash_info snand_flash_ids[] = { - SNAND_INFO("W25N512GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20), - SNAND_MEMORG_512M_2K_64, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("W25N01GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("W25M02GV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21), - SNAND_MEMORG_2G_2K_64_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_winbond_select_die), - SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - - SNAND_INFO("GD5F1GQ4UAWxx", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ4UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ4UExIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ5UExxH", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_a8d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F4GQ4UBxIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F4GQ4xAYIG", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4), - SNAND_MEMORG_4G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F1GQ5xExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x51), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("MX35LF1GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF1G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x14), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MX31LF1GE4BC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x1e), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2GE4AB", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x22), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x24), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x26), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF2G14AC", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x20), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF4G24AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x35), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MX35LF4GE4AD", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x37), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("MT29F1G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x12), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("MT29F1G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x14), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MT29F2G01AAAED", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x9f), - SNAND_MEMORG_2G_2K_64_2P, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("MT29F2G01ABAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x24), - SNAND_MEMORG_2G_2K_128_2P, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MT29F4G01AAADD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x32), - SNAND_MEMORG_4G_2K_64_2P, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("MT29F4G01ABAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x34), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("MT29F4G01ADAGD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x36), - SNAND_MEMORG_4G_2K_128_2P_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_micron_select_die), - SNAND_INFO("MT29F8G01ADAFD", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x46), - SNAND_MEMORG_8G_4K_256_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_micron_select_die), - - SNAND_INFO("TC58CVG0S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xc2), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("TC58CVG1S3HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcb), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("TC58CVG2S0HRAIG", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcd), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x1), - SNAND_INFO("TC58CVG0S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe2), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("TC58CVG1S3HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xeb), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("TC58CVG2S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xed), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("TH58CVG3S0HRAIJ", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe4), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("F50L512M41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x20), - SNAND_MEMORG_512M_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("F50L1G41A", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - SNAND_INFO("F50L1G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x01), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4), - SNAND_INFO("F50L2G41LB", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x0a), - SNAND_MEMORG_2G_2K_64_2D, - &snand_cap_read_from_cache_quad, - &snand_cap_program_load_x4, - mtk_snand_winbond_select_die), - - SNAND_INFO("CS11G0T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x00), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G0G0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x10), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G0S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x20), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G1T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x01), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G1S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x21), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G2T0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x02), - SNAND_MEMORG_4G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("CS11G2S0A0AA", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x22), - SNAND_MEMORG_4G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("EM73B044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x01), - SNAND_MEMORG_512M_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x11), - SNAND_MEMORG_1G_2K_120, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x09), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x18), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x19), - SNAND_MEMORG(2048, 64, 128, 512, 1, 1), - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1c), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1e), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x22), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044VCF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x25), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x31), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNC", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0a), - SNAND_MEMORG_2G_2K_120, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x12), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNF", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x10), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x13), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x14), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCD", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x17), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCH", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1b), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCG", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1f), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCE", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x20), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCL", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2e), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x32), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x03), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SND", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0b), - SNAND_MEMORG_4G_4K_240, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SNB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x23), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2c), - SNAND_MEMORG_4G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044VCB", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2f), - SNAND_MEMORG_4G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73F044SNA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x24), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73F044VCA", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2d), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73E044SNE", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0e), - SNAND_MEMORG_8G_4K_256, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73C044SNG", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0c), - SNAND_MEMORG_1G_2K_120, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("EM73D044VCN", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0f), - SNAND_MEMORG_2G_2K_64, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("PN26G02A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe2), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - - SNAND_INFO("IS37SML01G1", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4, - &snand_cap_program_load_x4), - - SNAND_INFO("ATO25D1GA", SNAND_ID(SNAND_ID_DYMMY, 0x9b, 0x12), - SNAND_MEMORG_1G_2K_64, - &snand_cap_read_from_cache_x4_only, - &snand_cap_program_load_x4), - - SNAND_INFO("HYF1GQ4U", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x51), - SNAND_MEMORG_1G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), - SNAND_INFO("HYF2GQ4U", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x52), - SNAND_MEMORG_2G_2K_128, - &snand_cap_read_from_cache_quad_q2d, - &snand_cap_program_load_x4), -}; - -static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx) -{ - uint8_t op[2]; - - if (dieidx > 1) { - snand_log_chip(snf->pdev, "Invalid die index %u\n", dieidx); - return -EINVAL; - } - - op[0] = SNAND_CMD_WINBOND_SELECT_DIE; - op[1] = (uint8_t)dieidx; - - return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0); -} - -static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx) -{ - int ret; - - if (dieidx > 1) { - snand_log_chip(snf->pdev, "Invalid die index %u\n", dieidx); - return -EINVAL; - } - - ret = mtk_snand_set_feature(snf, SNAND_FEATURE_MICRON_DIE_ADDR, - SNAND_MICRON_DIE_SEL_1); - if (ret) { - snand_log_chip(snf->pdev, - "Failed to set die selection feature\n"); - return ret; - } - - return 0; -} - -const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type, - const uint8_t *id) -{ - const struct snand_id *fid; - uint32_t i; - - for (i = 0; i < ARRAY_SIZE(snand_flash_ids); i++) { - if (snand_flash_ids[i].id.type != type) - continue; - - fid = &snand_flash_ids[i].id; - if (memcmp(fid->id, id, fid->len)) - continue; - - return &snand_flash_ids[i]; - } - - return NULL; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c deleted file mode 100644 index 7e5baf036..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-mtd.c +++ /dev/null @@ -1,681 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mtk-snand.h" -#include "mtk-snand-os.h" - -struct mtk_snand_of_id { - enum mtk_snand_soc soc; -}; - -struct mtk_snand_mtd { - struct mtk_snand_plat_dev pdev; - - struct clk *nfi_clk; - struct clk *pad_clk; - struct clk *ecc_clk; - - void __iomem *nfi_regs; - void __iomem *ecc_regs; - - int irq; - - bool quad_spi; - enum mtk_snand_soc soc; - - struct mtd_info mtd; - struct mtk_snand *snf; - struct mtk_snand_chip_info cinfo; - uint8_t *page_cache; - struct mutex lock; -}; - -#define mtd_to_msm(mtd) container_of(mtd, struct mtk_snand_mtd, mtd) - -static int mtk_snand_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - u64 start_addr, end_addr; - int ret; - - /* Do not allow write past end of device */ - if ((instr->addr + instr->len) > msm->cinfo.chipsize) { - dev_err(msm->pdev.dev, - "attempt to erase beyond end of device\n"); - return -EINVAL; - } - - start_addr = instr->addr & (~mtd->erasesize_mask); - end_addr = instr->addr + instr->len; - if (end_addr & mtd->erasesize_mask) { - end_addr = (end_addr + mtd->erasesize_mask) & - (~mtd->erasesize_mask); - } - - mutex_lock(&msm->lock); - - while (start_addr < end_addr) { - if (mtk_snand_block_isbad(msm->snf, start_addr)) { - instr->fail_addr = start_addr; - ret = -EIO; - break; - } - - ret = mtk_snand_erase_block(msm->snf, start_addr); - if (ret) { - instr->fail_addr = start_addr; - break; - } - - start_addr += mtd->erasesize; - } - - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_read_data(struct mtk_snand_mtd *msm, uint64_t addr, - struct mtd_oob_ops *ops) -{ - struct mtd_info *mtd = &msm->mtd; - size_t len, ooblen, maxooblen, chklen; - uint32_t col, ooboffs; - uint8_t *datcache, *oobcache; - bool ecc_failed = false, raw = ops->mode == MTD_OPS_RAW ? true : false; - int ret, max_bitflips = 0; - - col = addr & mtd->writesize_mask; - addr &= ~mtd->writesize_mask; - maxooblen = mtd_oobavail(mtd, ops); - ooboffs = ops->ooboffs; - ooblen = ops->ooblen; - len = ops->len; - - datcache = len ? msm->page_cache : NULL; - oobcache = ooblen ? msm->page_cache + mtd->writesize : NULL; - - ops->oobretlen = 0; - ops->retlen = 0; - - while (len || ooblen) { - if (ops->mode == MTD_OPS_AUTO_OOB) - ret = mtk_snand_read_page_auto_oob(msm->snf, addr, - datcache, oobcache, maxooblen, NULL, raw); - else - ret = mtk_snand_read_page(msm->snf, addr, datcache, - oobcache, raw); - - if (ret < 0 && ret != -EBADMSG) - return ret; - - if (ret == -EBADMSG) { - mtd->ecc_stats.failed++; - ecc_failed = true; - } else { - mtd->ecc_stats.corrected += ret; - max_bitflips = max_t(int, ret, max_bitflips); - } - - if (len) { - /* Move data */ - chklen = mtd->writesize - col; - if (chklen > len) - chklen = len; - - memcpy(ops->datbuf + ops->retlen, datcache + col, - chklen); - len -= chklen; - col = 0; /* (col + chklen) % */ - ops->retlen += chklen; - } - - if (ooblen) { - /* Move oob */ - chklen = maxooblen - ooboffs; - if (chklen > ooblen) - chklen = ooblen; - - memcpy(ops->oobbuf + ops->oobretlen, oobcache + ooboffs, - chklen); - ooblen -= chklen; - ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */ - ops->oobretlen += chklen; - } - - addr += mtd->writesize; - } - - return ecc_failed ? -EBADMSG : max_bitflips; -} - -static int mtk_snand_mtd_read_oob(struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - uint32_t maxooblen; - int ret; - - if (!ops->oobbuf && !ops->datbuf) { - if (ops->ooblen || ops->len) - return -EINVAL; - - return 0; - } - - switch (ops->mode) { - case MTD_OPS_PLACE_OOB: - case MTD_OPS_AUTO_OOB: - case MTD_OPS_RAW: - break; - default: - dev_err(msm->pdev.dev, "unsupported oob mode: %u\n", ops->mode); - return -EINVAL; - } - - maxooblen = mtd_oobavail(mtd, ops); - - /* Do not allow read past end of device */ - if (ops->datbuf && (from + ops->len) > msm->cinfo.chipsize) { - dev_err(msm->pdev.dev, - "attempt to read beyond end of device\n"); - return -EINVAL; - } - - if (unlikely(ops->ooboffs >= maxooblen)) { - dev_err(msm->pdev.dev, "attempt to start read outside oob\n"); - return -EINVAL; - } - - if (unlikely(from >= msm->cinfo.chipsize || - ops->ooboffs + ops->ooblen > - ((msm->cinfo.chipsize >> mtd->writesize_shift) - - (from >> mtd->writesize_shift)) * - maxooblen)) { - dev_err(msm->pdev.dev, - "attempt to read beyond end of device\n"); - return -EINVAL; - } - - mutex_lock(&msm->lock); - ret = mtk_snand_mtd_read_data(msm, from, ops); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_write_data(struct mtk_snand_mtd *msm, uint64_t addr, - struct mtd_oob_ops *ops) -{ - struct mtd_info *mtd = &msm->mtd; - size_t len, ooblen, maxooblen, chklen, oobwrlen; - uint32_t col, ooboffs; - uint8_t *datcache, *oobcache; - bool raw = ops->mode == MTD_OPS_RAW ? true : false; - int ret; - - col = addr & mtd->writesize_mask; - addr &= ~mtd->writesize_mask; - maxooblen = mtd_oobavail(mtd, ops); - ooboffs = ops->ooboffs; - ooblen = ops->ooblen; - len = ops->len; - - datcache = len ? msm->page_cache : NULL; - oobcache = ooblen ? msm->page_cache + mtd->writesize : NULL; - - ops->oobretlen = 0; - ops->retlen = 0; - - while (len || ooblen) { - if (len) { - /* Move data */ - chklen = mtd->writesize - col; - if (chklen > len) - chklen = len; - - memset(datcache, 0xff, col); - memcpy(datcache + col, ops->datbuf + ops->retlen, - chklen); - memset(datcache + col + chklen, 0xff, - mtd->writesize - col - chklen); - len -= chklen; - col = 0; /* (col + chklen) % */ - ops->retlen += chklen; - } - - oobwrlen = 0; - if (ooblen) { - /* Move oob */ - chklen = maxooblen - ooboffs; - if (chklen > ooblen) - chklen = ooblen; - - memset(oobcache, 0xff, ooboffs); - memcpy(oobcache + ooboffs, - ops->oobbuf + ops->oobretlen, chklen); - memset(oobcache + ooboffs + chklen, 0xff, - mtd->oobsize - ooboffs - chklen); - oobwrlen = chklen + ooboffs; - ooblen -= chklen; - ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */ - ops->oobretlen += chklen; - } - - if (ops->mode == MTD_OPS_AUTO_OOB) - ret = mtk_snand_write_page_auto_oob(msm->snf, addr, - datcache, oobcache, oobwrlen, NULL, raw); - else - ret = mtk_snand_write_page(msm->snf, addr, datcache, - oobcache, raw); - - if (ret) - return ret; - - addr += mtd->writesize; - } - - return 0; -} - -static int mtk_snand_mtd_write_oob(struct mtd_info *mtd, loff_t to, - struct mtd_oob_ops *ops) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - uint32_t maxooblen; - int ret; - - if (!ops->oobbuf && !ops->datbuf) { - if (ops->ooblen || ops->len) - return -EINVAL; - - return 0; - } - - switch (ops->mode) { - case MTD_OPS_PLACE_OOB: - case MTD_OPS_AUTO_OOB: - case MTD_OPS_RAW: - break; - default: - dev_err(msm->pdev.dev, "unsupported oob mode: %u\n", ops->mode); - return -EINVAL; - } - - maxooblen = mtd_oobavail(mtd, ops); - - /* Do not allow write past end of device */ - if (ops->datbuf && (to + ops->len) > msm->cinfo.chipsize) { - dev_err(msm->pdev.dev, - "attempt to write beyond end of device\n"); - return -EINVAL; - } - - if (unlikely(ops->ooboffs >= maxooblen)) { - dev_err(msm->pdev.dev, - "attempt to start write outside oob\n"); - return -EINVAL; - } - - if (unlikely(to >= msm->cinfo.chipsize || - ops->ooboffs + ops->ooblen > - ((msm->cinfo.chipsize >> mtd->writesize_shift) - - (to >> mtd->writesize_shift)) * - maxooblen)) { - dev_err(msm->pdev.dev, - "attempt to write beyond end of device\n"); - return -EINVAL; - } - - mutex_lock(&msm->lock); - ret = mtk_snand_mtd_write_data(msm, to, ops); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - int ret; - - mutex_lock(&msm->lock); - ret = mtk_snand_block_isbad(msm->snf, offs); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - int ret; - - mutex_lock(&msm->lock); - ret = mtk_snand_block_markbad(msm->snf, offs); - mutex_unlock(&msm->lock); - - return ret; -} - -static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobecc) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - - if (section) - return -ERANGE; - - oobecc->offset = msm->cinfo.fdm_size * msm->cinfo.num_sectors; - oobecc->length = mtd->oobsize - oobecc->offset; - - return 0; -} - -static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobfree) -{ - struct mtk_snand_mtd *msm = mtd_to_msm(mtd); - - if (section >= msm->cinfo.num_sectors) - return -ERANGE; - - oobfree->length = msm->cinfo.fdm_size - 1; - oobfree->offset = section * msm->cinfo.fdm_size + 1; - - return 0; -} - -static irqreturn_t mtk_snand_irq(int irq, void *id) -{ - struct mtk_snand_mtd *msm = id; - int ret; - - ret = mtk_snand_irq_process(msm->snf); - if (ret > 0) - return IRQ_HANDLED; - - return IRQ_NONE; -} - -static int mtk_snand_enable_clk(struct mtk_snand_mtd *msm) -{ - int ret; - - ret = clk_prepare_enable(msm->nfi_clk); - if (ret) { - dev_err(msm->pdev.dev, "unable to enable nfi clk\n"); - return ret; - } - - ret = clk_prepare_enable(msm->pad_clk); - if (ret) { - dev_err(msm->pdev.dev, "unable to enable pad clk\n"); - clk_disable_unprepare(msm->nfi_clk); - return ret; - } - - ret = clk_prepare_enable(msm->ecc_clk); - if (ret) { - dev_err(msm->pdev.dev, "unable to enable ecc clk\n"); - clk_disable_unprepare(msm->nfi_clk); - clk_disable_unprepare(msm->pad_clk); - return ret; - } - - return 0; -} - -static void mtk_snand_disable_clk(struct mtk_snand_mtd *msm) -{ - clk_disable_unprepare(msm->nfi_clk); - clk_disable_unprepare(msm->pad_clk); - clk_disable_unprepare(msm->ecc_clk); -} - -static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { - .ecc = mtk_snand_ooblayout_ecc, - .free = mtk_snand_ooblayout_free, -}; - -static struct mtk_snand_of_id mt7622_soc_id = { .soc = SNAND_SOC_MT7622 }; -static struct mtk_snand_of_id mt7629_soc_id = { .soc = SNAND_SOC_MT7629 }; - -static const struct of_device_id mtk_snand_ids[] = { - { .compatible = "mediatek,mt7622-snand", .data = &mt7622_soc_id }, - { .compatible = "mediatek,mt7629-snand", .data = &mt7629_soc_id }, - { }, -}; - -MODULE_DEVICE_TABLE(of, mtk_snand_ids); - -static int mtk_snand_probe(struct platform_device *pdev) -{ - struct mtk_snand_platdata mtk_snand_pdata = {}; - struct device_node *np = pdev->dev.of_node; - const struct of_device_id *of_soc_id; - const struct mtk_snand_of_id *soc_id; - struct mtk_snand_mtd *msm; - struct mtd_info *mtd; - struct resource *r; - uint32_t size; - int ret; - - of_soc_id = of_match_node(mtk_snand_ids, np); - if (!of_soc_id) - return -EINVAL; - - soc_id = of_soc_id->data; - - msm = devm_kzalloc(&pdev->dev, sizeof(*msm), GFP_KERNEL); - if (!msm) - return -ENOMEM; - - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nfi"); - msm->nfi_regs = devm_ioremap_resource(&pdev->dev, r); - if (IS_ERR(msm->nfi_regs)) { - ret = PTR_ERR(msm->nfi_regs); - goto errout1; - } - - r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecc"); - msm->ecc_regs = devm_ioremap_resource(&pdev->dev, r); - if (IS_ERR(msm->ecc_regs)) { - ret = PTR_ERR(msm->ecc_regs); - goto errout1; - } - - msm->pdev.dev = &pdev->dev; - msm->quad_spi = of_property_read_bool(np, "mediatek,quad-spi"); - msm->soc = soc_id->soc; - - msm->nfi_clk = devm_clk_get(msm->pdev.dev, "nfi_clk"); - if (IS_ERR(msm->nfi_clk)) { - ret = PTR_ERR(msm->nfi_clk); - dev_err(msm->pdev.dev, "unable to get nfi_clk, err = %d\n", - ret); - goto errout1; - } - - msm->ecc_clk = devm_clk_get(msm->pdev.dev, "ecc_clk"); - if (IS_ERR(msm->ecc_clk)) { - ret = PTR_ERR(msm->ecc_clk); - dev_err(msm->pdev.dev, "unable to get ecc_clk, err = %d\n", - ret); - goto errout1; - } - - msm->pad_clk = devm_clk_get(msm->pdev.dev, "pad_clk"); - if (IS_ERR(msm->pad_clk)) { - ret = PTR_ERR(msm->pad_clk); - dev_err(msm->pdev.dev, "unable to get pad_clk, err = %d\n", - ret); - goto errout1; - } - - ret = mtk_snand_enable_clk(msm); - if (ret) - goto errout1; - - /* Probe SPI-NAND Flash */ - mtk_snand_pdata.soc = msm->soc; - mtk_snand_pdata.quad_spi = msm->quad_spi; - mtk_snand_pdata.nfi_base = msm->nfi_regs; - mtk_snand_pdata.ecc_base = msm->ecc_regs; - - ret = mtk_snand_init(&msm->pdev, &mtk_snand_pdata, &msm->snf); - if (ret) - goto errout1; - - msm->irq = platform_get_irq(pdev, 0); - if (msm->irq >= 0) { - ret = devm_request_irq(msm->pdev.dev, msm->irq, mtk_snand_irq, - 0x0, "mtk-snand", msm); - if (ret) { - dev_err(msm->pdev.dev, "failed to request snfi irq\n"); - goto errout2; - } - - ret = dma_set_mask(msm->pdev.dev, DMA_BIT_MASK(32)); - if (ret) { - dev_err(msm->pdev.dev, "failed to set dma mask\n"); - goto errout3; - } - } - - mtk_snand_get_chip_info(msm->snf, &msm->cinfo); - - size = msm->cinfo.pagesize + msm->cinfo.sparesize; - msm->page_cache = devm_kmalloc(msm->pdev.dev, size, GFP_KERNEL); - if (!msm->page_cache) { - dev_err(msm->pdev.dev, "failed to allocate page cache\n"); - ret = -ENOMEM; - goto errout3; - } - - mutex_init(&msm->lock); - - dev_info(msm->pdev.dev, - "chip is %s, size %lluMB, page size %u, oob size %u\n", - msm->cinfo.model, msm->cinfo.chipsize >> 20, - msm->cinfo.pagesize, msm->cinfo.sparesize); - - /* Initialize mtd for SPI-NAND */ - mtd = &msm->mtd; - - mtd->owner = THIS_MODULE; - mtd->dev.parent = &pdev->dev; - mtd->type = MTD_NANDFLASH; - mtd->flags = MTD_CAP_NANDFLASH; - - mtd_set_of_node(mtd, np); - - mtd->size = msm->cinfo.chipsize; - mtd->erasesize = msm->cinfo.blocksize; - mtd->writesize = msm->cinfo.pagesize; - mtd->writebufsize = mtd->writesize; - mtd->oobsize = msm->cinfo.sparesize; - mtd->oobavail = msm->cinfo.num_sectors * (msm->cinfo.fdm_size - 1); - - mtd->erasesize_shift = ffs(mtd->erasesize) - 1; - mtd->writesize_shift = ffs(mtd->writesize) - 1; - mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1; - mtd->writesize_mask = (1 << mtd->writesize_shift) - 1; - - mtd->ooblayout = &mtk_snand_ooblayout; - - mtd->ecc_strength = msm->cinfo.ecc_strength; - mtd->bitflip_threshold = (mtd->ecc_strength * 3) / 4; - mtd->ecc_step_size = msm->cinfo.sector_size; - - mtd->_erase = mtk_snand_mtd_erase; - mtd->_read_oob = mtk_snand_mtd_read_oob; - mtd->_write_oob = mtk_snand_mtd_write_oob; - mtd->_block_isbad = mtk_snand_mtd_block_isbad; - mtd->_block_markbad = mtk_snand_mtd_block_markbad; - - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(msm->pdev.dev, "failed to register mtd partition\n"); - goto errout4; - } - - platform_set_drvdata(pdev, msm); - - return 0; - -errout4: - devm_kfree(msm->pdev.dev, msm->page_cache); - -errout3: - if (msm->irq >= 0) - devm_free_irq(msm->pdev.dev, msm->irq, msm); - -errout2: - mtk_snand_cleanup(msm->snf); - -errout1: - devm_kfree(msm->pdev.dev, msm); - - platform_set_drvdata(pdev, NULL); - - return ret; -} - -static int mtk_snand_remove(struct platform_device *pdev) -{ - struct mtk_snand_mtd *msm = platform_get_drvdata(pdev); - struct mtd_info *mtd = &msm->mtd; - int ret; - - ret = mtd_device_unregister(mtd); - if (ret) - return ret; - - mtk_snand_cleanup(msm->snf); - - if (msm->irq >= 0) - devm_free_irq(msm->pdev.dev, msm->irq, msm); - - mtk_snand_disable_clk(msm); - - devm_kfree(msm->pdev.dev, msm->page_cache); - devm_kfree(msm->pdev.dev, msm); - - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static struct platform_driver mtk_snand_driver = { - .probe = mtk_snand_probe, - .remove = mtk_snand_remove, - .driver = { - .name = "mtk-snand", - .of_match_table = mtk_snand_ids, - }, -}; - -module_platform_driver(mtk_snand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Weijie Gao "); -MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c deleted file mode 100644 index 0c3ffec8b..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -int mtk_snand_log(struct mtk_snand_plat_dev *pdev, - enum mtk_snand_log_category cat, const char *fmt, ...) -{ - const char *catname = ""; - va_list ap; - char *msg; - - switch (cat) { - case SNAND_LOG_NFI: - catname = "NFI"; - break; - case SNAND_LOG_SNFI: - catname = "SNFI"; - break; - case SNAND_LOG_ECC: - catname = "ECC"; - break; - default: - break; - } - - va_start(ap, fmt); - msg = kvasprintf(GFP_KERNEL, fmt, ap); - va_end(ap); - - if (!msg) { - dev_warn(pdev->dev, "unable to print log\n"); - return -1; - } - - if (*catname) - dev_warn(pdev->dev, "%s: %s", catname, msg); - else - dev_warn(pdev->dev, "%s", msg); - - kfree(msg); - - return 0; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h deleted file mode 100644 index eeeb83b53..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand-os.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#ifndef _MTK_SNAND_OS_H_ -#define _MTK_SNAND_OS_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct mtk_snand_plat_dev { - struct device *dev; - struct completion done; -}; - -/* Polling helpers */ -#define read16_poll_timeout(addr, val, cond, sleep_us, timeout_us) \ - readw_poll_timeout((addr), (val), (cond), (sleep_us), (timeout_us)) - -#define read32_poll_timeout(addr, val, cond, sleep_us, timeout_us) \ - readl_poll_timeout((addr), (val), (cond), (sleep_us), (timeout_us)) - -/* Timer helpers */ -#define mtk_snand_time_t ktime_t - -static inline mtk_snand_time_t timer_get_ticks(void) -{ - return ktime_get(); -} - -static inline mtk_snand_time_t timer_time_to_tick(uint32_t timeout_us) -{ - return ktime_add_us(ktime_set(0, 0), timeout_us); -} - -static inline bool timer_is_timeout(mtk_snand_time_t start_tick, - mtk_snand_time_t timeout_tick) -{ - ktime_t tmo = ktime_add(start_tick, timeout_tick); - - return ktime_compare(ktime_get(), tmo) > 0; -} - -/* Memory helpers */ -static inline void *generic_mem_alloc(struct mtk_snand_plat_dev *pdev, - size_t size) -{ - return devm_kzalloc(pdev->dev, size, GFP_KERNEL); -} -static inline void generic_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr) -{ - devm_kfree(pdev->dev, ptr); -} - -static inline void *dma_mem_alloc(struct mtk_snand_plat_dev *pdev, size_t size) -{ - return kzalloc(size, GFP_KERNEL); -} -static inline void dma_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr) -{ - kfree(ptr); -} - -static inline int dma_mem_map(struct mtk_snand_plat_dev *pdev, void *vaddr, - uintptr_t *dma_addr, size_t size, bool to_device) -{ - dma_addr_t addr; - int ret; - - addr = dma_map_single(pdev->dev, vaddr, size, - to_device ? DMA_TO_DEVICE : DMA_FROM_DEVICE); - ret = dma_mapping_error(pdev->dev, addr); - if (ret) - return ret; - - *dma_addr = (uintptr_t)addr; - - return 0; -} - -static inline void dma_mem_unmap(struct mtk_snand_plat_dev *pdev, - uintptr_t dma_addr, size_t size, - bool to_device) -{ - dma_unmap_single(pdev->dev, dma_addr, size, - to_device ? DMA_TO_DEVICE : DMA_FROM_DEVICE); -} - -/* Interrupt helpers */ -static inline void irq_completion_done(struct mtk_snand_plat_dev *pdev) -{ - complete(&pdev->done); -} - -static inline void irq_completion_init(struct mtk_snand_plat_dev *pdev) -{ - init_completion(&pdev->done); -} - -static inline int irq_completion_wait(struct mtk_snand_plat_dev *pdev, - void __iomem *reg, uint32_t bit, - uint32_t timeout_us) -{ - int ret; - - ret = wait_for_completion_timeout(&pdev->done, - usecs_to_jiffies(timeout_us)); - if (!ret) - return -ETIMEDOUT; - - return 0; -} - -#endif /* _MTK_SNAND_OS_H_ */ diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c deleted file mode 100644 index 729fd82d3..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.c +++ /dev/null @@ -1,1862 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#include "mtk-snand-def.h" - -/* NFI registers */ -#define NFI_CNFG 0x000 -#define CNFG_OP_MODE_S 12 -#define CNFG_OP_MODE_CUST 6 -#define CNFG_OP_MODE_PROGRAM 3 -#define CNFG_AUTO_FMT_EN BIT(9) -#define CNFG_HW_ECC_EN BIT(8) -#define CNFG_DMA_BURST_EN BIT(2) -#define CNFG_READ_MODE BIT(1) -#define CNFG_DMA_MODE BIT(0) - -#define NFI_PAGEFMT 0x0004 -#define NFI_SPARE_SIZE_LS_S 16 -#define NFI_FDM_ECC_NUM_S 12 -#define NFI_FDM_NUM_S 8 -#define NFI_SPARE_SIZE_S 4 -#define NFI_SEC_SEL_512 BIT(2) -#define NFI_PAGE_SIZE_S 0 -#define NFI_PAGE_SIZE_512_2K 0 -#define NFI_PAGE_SIZE_2K_4K 1 -#define NFI_PAGE_SIZE_4K_8K 2 -#define NFI_PAGE_SIZE_8K_16K 3 - -#define NFI_CON 0x008 -#define CON_SEC_NUM_S 12 -#define CON_BWR BIT(9) -#define CON_BRD BIT(8) -#define CON_NFI_RST BIT(1) -#define CON_FIFO_FLUSH BIT(0) - -#define NFI_INTR_EN 0x010 -#define NFI_INTR_STA 0x014 -#define NFI_IRQ_INTR_EN BIT(31) -#define NFI_IRQ_CUS_READ BIT(8) -#define NFI_IRQ_CUS_PG BIT(7) - -#define NFI_CMD 0x020 - -#define NFI_STRDATA 0x040 -#define STR_DATA BIT(0) - -#define NFI_STA 0x060 -#define NFI_NAND_FSM GENMASK(28, 24) -#define NFI_FSM GENMASK(19, 16) -#define READ_EMPTY BIT(12) - -#define NFI_FIFOSTA 0x064 -#define FIFO_WR_REMAIN_S 8 -#define FIFO_RD_REMAIN_S 0 - -#define NFI_ADDRCNTR 0x070 -#define SEC_CNTR GENMASK(16, 12) -#define SEC_CNTR_S 12 -#define NFI_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S) - -#define NFI_STRADDR 0x080 - -#define NFI_BYTELEN 0x084 -#define BUS_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S) - -#define NFI_FDM0L 0x0a0 -#define NFI_FDM0M 0x0a4 -#define NFI_FDML(n) (NFI_FDM0L + (n) * 8) -#define NFI_FDMM(n) (NFI_FDM0M + (n) * 8) - -#define NFI_DEBUG_CON1 0x220 -#define WBUF_EN BIT(2) - -#define NFI_MASTERSTA 0x224 -#define MAS_ADDR GENMASK(11, 9) -#define MAS_RD GENMASK(8, 6) -#define MAS_WR GENMASK(5, 3) -#define MAS_RDDLY GENMASK(2, 0) -#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) - -/* SNFI registers */ -#define SNF_MAC_CTL 0x500 -#define MAC_XIO_SEL BIT(4) -#define SF_MAC_EN BIT(3) -#define SF_TRIG BIT(2) -#define WIP_READY BIT(1) -#define WIP BIT(0) - -#define SNF_MAC_OUTL 0x504 -#define SNF_MAC_INL 0x508 - -#define SNF_RD_CTL2 0x510 -#define DATA_READ_DUMMY_S 8 -#define DATA_READ_CMD_S 0 - -#define SNF_RD_CTL3 0x514 - -#define SNF_PG_CTL1 0x524 -#define PG_LOAD_CMD_S 8 - -#define SNF_PG_CTL2 0x528 - -#define SNF_MISC_CTL 0x538 -#define SW_RST BIT(28) -#define FIFO_RD_LTC_S 25 -#define PG_LOAD_X4_EN BIT(20) -#define DATA_READ_MODE_S 16 -#define DATA_READ_MODE GENMASK(18, 16) -#define DATA_READ_MODE_X1 0 -#define DATA_READ_MODE_X2 1 -#define DATA_READ_MODE_X4 2 -#define DATA_READ_MODE_DUAL 5 -#define DATA_READ_MODE_QUAD 6 -#define PG_LOAD_CUSTOM_EN BIT(7) -#define DATARD_CUSTOM_EN BIT(6) -#define CS_DESELECT_CYC_S 0 - -#define SNF_MISC_CTL2 0x53c -#define PROGRAM_LOAD_BYTE_NUM_S 16 -#define READ_DATA_BYTE_NUM_S 11 - -#define SNF_DLY_CTL3 0x548 -#define SFCK_SAM_DLY_S 0 - -#define SNF_STA_CTL1 0x550 -#define CUS_PG_DONE BIT(28) -#define CUS_READ_DONE BIT(27) -#define SPI_STATE_S 0 -#define SPI_STATE GENMASK(3, 0) - -#define SNF_CFG 0x55c -#define SPI_MODE BIT(0) - -#define SNF_GPRAM 0x800 -#define SNF_GPRAM_SIZE 0xa0 - -#define SNFI_POLL_INTERVAL 1000000 - -static const uint8_t mt7622_spare_sizes[] = { 16, 26, 27, 28 }; - -static const struct mtk_snand_soc_data mtk_snand_socs[__SNAND_SOC_MAX] = { - [SNAND_SOC_MT7622] = { - .sector_size = 512, - .max_sectors = 8, - .fdm_size = 8, - .fdm_ecc_size = 1, - .fifo_size = 32, - .bbm_swap = false, - .empty_page_check = false, - .mastersta_mask = NFI_MASTERSTA_MASK_7622, - .spare_sizes = mt7622_spare_sizes, - .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) - }, - [SNAND_SOC_MT7629] = { - .sector_size = 512, - .max_sectors = 8, - .fdm_size = 8, - .fdm_ecc_size = 1, - .fifo_size = 32, - .bbm_swap = true, - .empty_page_check = false, - .mastersta_mask = NFI_MASTERSTA_MASK_7622, - .spare_sizes = mt7622_spare_sizes, - .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) - }, -}; - -static inline uint32_t nfi_read32(struct mtk_snand *snf, uint32_t reg) -{ - return readl(snf->nfi_base + reg); -} - -static inline void nfi_write32(struct mtk_snand *snf, uint32_t reg, - uint32_t val) -{ - writel(val, snf->nfi_base + reg); -} - -static inline void nfi_write16(struct mtk_snand *snf, uint32_t reg, - uint16_t val) -{ - writew(val, snf->nfi_base + reg); -} - -static inline void nfi_rmw32(struct mtk_snand *snf, uint32_t reg, uint32_t clr, - uint32_t set) -{ - uint32_t val; - - val = readl(snf->nfi_base + reg); - val &= ~clr; - val |= set; - writel(val, snf->nfi_base + reg); -} - -static void nfi_write_data(struct mtk_snand *snf, uint32_t reg, - const uint8_t *data, uint32_t len) -{ - uint32_t i, val = 0, es = sizeof(uint32_t); - - for (i = reg; i < reg + len; i++) { - val |= ((uint32_t)*data++) << (8 * (i % es)); - - if (i % es == es - 1 || i == reg + len - 1) { - nfi_write32(snf, i & ~(es - 1), val); - val = 0; - } - } -} - -static void nfi_read_data(struct mtk_snand *snf, uint32_t reg, uint8_t *data, - uint32_t len) -{ - uint32_t i, val = 0, es = sizeof(uint32_t); - - for (i = reg; i < reg + len; i++) { - if (i == reg || i % es == 0) - val = nfi_read32(snf, i & ~(es - 1)); - - *data++ = (uint8_t)(val >> (8 * (i % es))); - } -} - -static inline void do_bm_swap(uint8_t *bm1, uint8_t *bm2) -{ - uint8_t tmp = *bm1; - *bm1 = *bm2; - *bm2 = tmp; -} - -static void mtk_snand_bm_swap_raw(struct mtk_snand *snf) -{ - uint32_t fdm_bbm_pos; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - fdm_bbm_pos = (snf->ecc_steps - 1) * snf->raw_sector_size + - snf->nfi_soc->sector_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos], - &snf->page_cache[snf->writesize]); -} - -static void mtk_snand_bm_swap(struct mtk_snand *snf) -{ - uint32_t buf_bbm_pos, fdm_bbm_pos; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - buf_bbm_pos = snf->writesize - - (snf->ecc_steps - 1) * snf->spare_per_sector; - fdm_bbm_pos = snf->writesize + - (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos], - &snf->page_cache[buf_bbm_pos]); -} - -static void mtk_snand_fdm_bm_swap_raw(struct mtk_snand *snf) -{ - uint32_t fdm_bbm_pos1, fdm_bbm_pos2; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - fdm_bbm_pos1 = snf->nfi_soc->sector_size; - fdm_bbm_pos2 = (snf->ecc_steps - 1) * snf->raw_sector_size + - snf->nfi_soc->sector_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos1], - &snf->page_cache[fdm_bbm_pos2]); -} - -static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) -{ - uint32_t fdm_bbm_pos1, fdm_bbm_pos2; - - if (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1) - return; - - fdm_bbm_pos1 = snf->writesize; - fdm_bbm_pos2 = snf->writesize + - (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size; - do_bm_swap(&snf->page_cache[fdm_bbm_pos1], - &snf->page_cache[fdm_bbm_pos2]); -} - -static int mtk_nfi_reset(struct mtk_snand *snf) -{ - uint32_t val, fifo_mask; - int ret; - - nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); - - ret = read16_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, - !(val & snf->nfi_soc->mastersta_mask), 0, - SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "NFI master is still busy after reset\n"); - return ret; - } - - ret = read32_poll_timeout(snf->nfi_base + NFI_STA, val, - !(val & (NFI_FSM | NFI_NAND_FSM)), 0, - SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, "Failed to reset NFI\n"); - return ret; - } - - fifo_mask = ((snf->nfi_soc->fifo_size - 1) << FIFO_RD_REMAIN_S) | - ((snf->nfi_soc->fifo_size - 1) << FIFO_WR_REMAIN_S); - ret = read16_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, - !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, "NFI FIFOs are not empty\n"); - return ret; - } - - return 0; -} - -static int mtk_snand_mac_reset(struct mtk_snand *snf) -{ - int ret; - uint32_t val; - - nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); - - ret = read32_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, - !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); - if (ret) - snand_log_snfi(snf->pdev, "Failed to reset SNFI MAC\n"); - - nfi_write32(snf, SNF_MISC_CTL, (2 << FIFO_RD_LTC_S) | - (10 << CS_DESELECT_CYC_S)); - - return ret; -} - -static int mtk_snand_mac_trigger(struct mtk_snand *snf, uint32_t outlen, - uint32_t inlen) -{ - int ret; - uint32_t val; - - nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); - nfi_write32(snf, SNF_MAC_OUTL, outlen); - nfi_write32(snf, SNF_MAC_INL, inlen); - - nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); - - ret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, - val & WIP_READY, 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_snfi(snf->pdev, "Timed out waiting for WIP_READY\n"); - goto cleanup; - } - - ret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, - !(val & WIP), 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_snfi(snf->pdev, - "Timed out waiting for WIP cleared\n"); - } - -cleanup: - nfi_write32(snf, SNF_MAC_CTL, 0); - - return ret; -} - -int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen, - uint8_t *in, uint32_t inlen) -{ - int ret; - - if (outlen + inlen > SNF_GPRAM_SIZE) - return -EINVAL; - - mtk_snand_mac_reset(snf); - - nfi_write_data(snf, SNF_GPRAM, out, outlen); - - ret = mtk_snand_mac_trigger(snf, outlen, inlen); - if (ret) - return ret; - - if (!inlen) - return 0; - - nfi_read_data(snf, SNF_GPRAM + outlen, in, inlen); - - return 0; -} - -static int mtk_snand_get_feature(struct mtk_snand *snf, uint32_t addr) -{ - uint8_t op[2], val; - int ret; - - op[0] = SNAND_CMD_GET_FEATURE; - op[1] = (uint8_t)addr; - - ret = mtk_snand_mac_io(snf, op, sizeof(op), &val, 1); - if (ret) - return ret; - - return val; -} - -int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val) -{ - uint8_t op[3]; - - op[0] = SNAND_CMD_SET_FEATURE; - op[1] = (uint8_t)addr; - op[2] = (uint8_t)val; - - return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0); -} - -static int mtk_snand_poll_status(struct mtk_snand *snf, uint32_t wait_us) -{ - int val; - mtk_snand_time_t time_start, tmo; - - time_start = timer_get_ticks(); - tmo = timer_time_to_tick(wait_us); - - do { - val = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR); - if (!(val & SNAND_STATUS_OIP)) - return val & (SNAND_STATUS_ERASE_FAIL | - SNAND_STATUS_PROGRAM_FAIL); - } while (!timer_is_timeout(time_start, tmo)); - - return -ETIMEDOUT; -} - -int mtk_snand_chip_reset(struct mtk_snand *snf) -{ - uint8_t op = SNAND_CMD_RESET; - int ret; - - ret = mtk_snand_mac_io(snf, &op, 1, NULL, 0); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) - return ret; - - return 0; -} - -static int mtk_snand_config_feature(struct mtk_snand *snf, uint8_t clr, - uint8_t set) -{ - int val, newval; - int ret; - - val = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR); - if (val < 0) { - snand_log_chip(snf->pdev, - "Failed to get configuration feature\n"); - return val; - } - - newval = (val & (~clr)) | set; - - if (newval == val) - return 0; - - ret = mtk_snand_set_feature(snf, SNAND_FEATURE_CONFIG_ADDR, - (uint8_t)newval); - if (val < 0) { - snand_log_chip(snf->pdev, - "Failed to set configuration feature\n"); - return ret; - } - - val = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR); - if (val < 0) { - snand_log_chip(snf->pdev, - "Failed to get configuration feature\n"); - return val; - } - - if (newval != val) - return -ENOTSUPP; - - return 0; -} - -static int mtk_snand_ondie_ecc_control(struct mtk_snand *snf, bool enable) -{ - int ret; - - if (enable) - ret = mtk_snand_config_feature(snf, 0, SNAND_FEATURE_ECC_EN); - else - ret = mtk_snand_config_feature(snf, SNAND_FEATURE_ECC_EN, 0); - - if (ret) { - snand_log_chip(snf->pdev, "Failed to %s On-Die ECC engine\n", - enable ? "enable" : "disable"); - } - - return ret; -} - -static int mtk_snand_qspi_control(struct mtk_snand *snf, bool enable) -{ - int ret; - - if (enable) { - ret = mtk_snand_config_feature(snf, 0, - SNAND_FEATURE_QUAD_ENABLE); - } else { - ret = mtk_snand_config_feature(snf, - SNAND_FEATURE_QUAD_ENABLE, 0); - } - - if (ret) { - snand_log_chip(snf->pdev, "Failed to %s quad spi\n", - enable ? "enable" : "disable"); - } - - return ret; -} - -static int mtk_snand_unlock(struct mtk_snand *snf) -{ - int ret; - - ret = mtk_snand_set_feature(snf, SNAND_FEATURE_PROTECT_ADDR, 0); - if (ret) { - snand_log_chip(snf->pdev, "Failed to set protection feature\n"); - return ret; - } - - return 0; -} - -static int mtk_snand_write_enable(struct mtk_snand *snf) -{ - uint8_t op = SNAND_CMD_WRITE_ENABLE; - int ret, val; - - ret = mtk_snand_mac_io(snf, &op, 1, NULL, 0); - if (ret) - return ret; - - val = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR); - if (val < 0) - return ret; - - if (val & SNAND_STATUS_WEL) - return 0; - - snand_log_chip(snf->pdev, "Failed to send write-enable command\n"); - - return -ENOTSUPP; -} - -static int mtk_snand_select_die(struct mtk_snand *snf, uint32_t dieidx) -{ - if (!snf->select_die) - return 0; - - return snf->select_die(snf, dieidx); -} - -static uint64_t mtk_snand_select_die_address(struct mtk_snand *snf, - uint64_t addr) -{ - uint32_t dieidx; - - if (!snf->select_die) - return addr; - - dieidx = addr >> snf->die_shift; - - mtk_snand_select_die(snf, dieidx); - - return addr & snf->die_mask; -} - -static uint32_t mtk_snand_get_plane_address(struct mtk_snand *snf, - uint32_t page) -{ - uint32_t pages_per_block; - - pages_per_block = 1 << (snf->erasesize_shift - snf->writesize_shift); - - if (page & pages_per_block) - return 1 << (snf->writesize_shift + 1); - - return 0; -} - -static int mtk_snand_page_op(struct mtk_snand *snf, uint32_t page, uint8_t cmd) -{ - uint8_t op[4]; - - op[0] = cmd; - op[1] = (page >> 16) & 0xff; - op[2] = (page >> 8) & 0xff; - op[3] = page & 0xff; - - return mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0); -} - -static void mtk_snand_read_fdm(struct mtk_snand *snf, uint8_t *buf) -{ - uint32_t vall, valm; - uint8_t *oobptr = buf; - int i, j; - - for (i = 0; i < snf->ecc_steps; i++) { - vall = nfi_read32(snf, NFI_FDML(i)); - valm = nfi_read32(snf, NFI_FDMM(i)); - - for (j = 0; j < snf->nfi_soc->fdm_size; j++) - oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); - - oobptr += snf->nfi_soc->fdm_size; - } -} - -static int mtk_snand_read_ecc_parity(struct mtk_snand *snf, uint32_t page, - uint32_t sect, uint8_t *oob) -{ - uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - uint32_t coladdr, raw_offs, offs; - uint8_t op[4]; - - if (sizeof(op) + ecc_bytes > SNF_GPRAM_SIZE) { - snand_log_snfi(snf->pdev, - "ECC parity size does not fit the GPRAM\n"); - return -ENOTSUPP; - } - - raw_offs = sect * snf->raw_sector_size + snf->nfi_soc->sector_size + - snf->nfi_soc->fdm_size; - offs = snf->ecc_steps * snf->nfi_soc->fdm_size + sect * ecc_bytes; - - /* Column address with plane bit */ - coladdr = raw_offs | mtk_snand_get_plane_address(snf, page); - - op[0] = SNAND_CMD_READ_FROM_CACHE; - op[1] = (coladdr >> 8) & 0xff; - op[2] = coladdr & 0xff; - op[3] = 0; - - return mtk_snand_mac_io(snf, op, sizeof(op), oob + offs, ecc_bytes); -} - -static int mtk_snand_check_ecc_result(struct mtk_snand *snf, uint32_t page) -{ - uint8_t *oob = snf->page_cache + snf->writesize; - int i, rc, ret = 0, max_bitflips = 0; - - for (i = 0; i < snf->ecc_steps; i++) { - if (snf->sect_bf[i] >= 0) { - if (snf->sect_bf[i] > max_bitflips) - max_bitflips = snf->sect_bf[i]; - continue; - } - - rc = mtk_snand_read_ecc_parity(snf, page, i, oob); - if (rc) - return rc; - - rc = mtk_ecc_fixup_empty_sector(snf, i); - if (rc < 0) { - ret = -EBADMSG; - - snand_log_ecc(snf->pdev, - "Uncorrectable bitflips in page %u sect %u\n", - page, i); - } else if (rc) { - snf->sect_bf[i] = rc; - - if (snf->sect_bf[i] > max_bitflips) - max_bitflips = snf->sect_bf[i]; - - snand_log_ecc(snf->pdev, - "%u bitflip%s corrected in page %u sect %u\n", - rc, rc > 1 ? "s" : "", page, i); - } else { - snf->sect_bf[i] = 0; - } - } - - return ret ? ret : max_bitflips; -} - -static int mtk_snand_read_cache(struct mtk_snand *snf, uint32_t page, bool raw) -{ - uint32_t coladdr, rwbytes, mode, len, val; - uintptr_t dma_addr; - int ret; - - /* Column address with plane bit */ - coladdr = mtk_snand_get_plane_address(snf, page); - - mtk_snand_mac_reset(snf); - mtk_nfi_reset(snf); - - /* Command and dummy cycles */ - nfi_write32(snf, SNF_RD_CTL2, - ((uint32_t)snf->dummy_rfc << DATA_READ_DUMMY_S) | - (snf->opcode_rfc << DATA_READ_CMD_S)); - - /* Column address */ - nfi_write32(snf, SNF_RD_CTL3, coladdr); - - /* Set read mode */ - mode = (uint32_t)snf->mode_rfc << DATA_READ_MODE_S; - nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, mode | DATARD_CUSTOM_EN); - - /* Set bytes to read */ - rwbytes = snf->ecc_steps * snf->raw_sector_size; - nfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) | - rwbytes); - - /* NFI read prepare */ - mode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN; - nfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | - CNFG_DMA_BURST_EN | CNFG_READ_MODE | CNFG_DMA_MODE | mode); - - nfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S)); - - /* Prepare for DMA read */ - len = snf->writesize + snf->oobsize; - ret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, false); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA map from device failed with %d\n", ret); - return ret; - } - - nfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr); - - if (!raw) - mtk_snand_ecc_decoder_start(snf); - - /* Prepare for custom read interrupt */ - nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); - irq_completion_init(snf->pdev); - - /* Trigger NFI into custom mode */ - nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); - - /* Start DMA read */ - nfi_rmw32(snf, NFI_CON, 0, CON_BRD); - nfi_write16(snf, NFI_STRDATA, STR_DATA); - - /* Wait for operation finished */ - ret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1, - CUS_READ_DONE, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA timed out for reading from cache\n"); - goto cleanup; - } - - /* Wait for BUS_SEC_CNTR returning expected value */ - ret = read32_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, - BUS_SEC_CNTR(val) >= snf->ecc_steps, - 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "Timed out waiting for BUS_SEC_CNTR\n"); - goto cleanup; - } - - /* Wait for bus becoming idle */ - ret = read32_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, - !(val & snf->nfi_soc->mastersta_mask), - 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "Timed out waiting for bus becoming idle\n"); - goto cleanup; - } - - if (!raw) { - ret = mtk_ecc_wait_decoder_done(snf); - if (ret) - goto cleanup; - - mtk_snand_read_fdm(snf, snf->page_cache + snf->writesize); - - mtk_ecc_check_decode_error(snf); - mtk_snand_ecc_decoder_stop(snf); - - ret = mtk_snand_check_ecc_result(snf, page); - } - -cleanup: - /* DMA cleanup */ - dma_mem_unmap(snf->pdev, dma_addr, len, false); - - /* Stop read */ - nfi_write32(snf, NFI_CON, 0); - nfi_write16(snf, NFI_CNFG, 0); - - /* Clear SNF done flag */ - nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); - nfi_write32(snf, SNF_STA_CTL1, 0); - - /* Disable interrupt */ - nfi_read32(snf, NFI_INTR_STA); - nfi_write32(snf, NFI_INTR_EN, 0); - - nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); - - return ret; -} - -static void mtk_snand_from_raw_page(struct mtk_snand *snf, void *buf, void *oob) -{ - uint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size; - uint8_t *bufptr = buf, *oobptr = oob, *raw_sector; - - for (i = 0; i < snf->ecc_steps; i++) { - raw_sector = snf->page_cache + i * snf->raw_sector_size; - - if (buf) { - memcpy(bufptr, raw_sector, snf->nfi_soc->sector_size); - bufptr += snf->nfi_soc->sector_size; - } - - raw_sector += snf->nfi_soc->sector_size; - - if (oob) { - memcpy(oobptr, raw_sector, snf->nfi_soc->fdm_size); - oobptr += snf->nfi_soc->fdm_size; - raw_sector += snf->nfi_soc->fdm_size; - - memcpy(eccptr, raw_sector, ecc_bytes); - eccptr += ecc_bytes; - } - } -} - -static int mtk_snand_do_read_page(struct mtk_snand *snf, uint64_t addr, - void *buf, void *oob, bool raw, bool format) -{ - uint64_t die_addr; - uint32_t page; - int ret; - - die_addr = mtk_snand_select_die_address(snf, addr); - page = die_addr >> snf->writesize_shift; - - ret = mtk_snand_page_op(snf, page, SNAND_CMD_READ_TO_CACHE); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) { - snand_log_chip(snf->pdev, "Read to cache command timed out\n"); - return ret; - } - - ret = mtk_snand_read_cache(snf, page, raw); - if (ret < 0 && ret != -EBADMSG) - return ret; - - if (raw) { - if (format) { - mtk_snand_bm_swap_raw(snf); - mtk_snand_fdm_bm_swap_raw(snf); - mtk_snand_from_raw_page(snf, buf, oob); - } else { - if (buf) - memcpy(buf, snf->page_cache, snf->writesize); - - if (oob) { - memset(oob, 0xff, snf->oobsize); - memcpy(oob, snf->page_cache + snf->writesize, - snf->ecc_steps * snf->spare_per_sector); - } - } - } else { - mtk_snand_bm_swap(snf); - mtk_snand_fdm_bm_swap(snf); - - if (buf) - memcpy(buf, snf->page_cache, snf->writesize); - - if (oob) { - memset(oob, 0xff, snf->oobsize); - memcpy(oob, snf->page_cache + snf->writesize, - snf->ecc_steps * snf->nfi_soc->fdm_size); - } - } - - return ret; -} - -int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf, - void *oob, bool raw) -{ - if (!snf || (!buf && !oob)) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - return mtk_snand_do_read_page(snf, addr, buf, oob, raw, true); -} - -static void mtk_snand_write_fdm(struct mtk_snand *snf, const uint8_t *buf) -{ - uint32_t vall, valm, fdm_size = snf->nfi_soc->fdm_size; - const uint8_t *oobptr = buf; - int i, j; - - for (i = 0; i < snf->ecc_steps; i++) { - vall = 0; - valm = 0; - - for (j = 0; j < 8; j++) { - if (j < 4) - vall |= (j < fdm_size ? oobptr[j] : 0xff) - << (j * 8); - else - valm |= (j < fdm_size ? oobptr[j] : 0xff) - << ((j - 4) * 8); - } - - nfi_write32(snf, NFI_FDML(i), vall); - nfi_write32(snf, NFI_FDMM(i), valm); - - oobptr += fdm_size; - } -} - -static int mtk_snand_program_load(struct mtk_snand *snf, uint32_t page, - bool raw) -{ - uint32_t coladdr, rwbytes, mode, len, val; - uintptr_t dma_addr; - int ret; - - /* Column address with plane bit */ - coladdr = mtk_snand_get_plane_address(snf, page); - - mtk_snand_mac_reset(snf); - mtk_nfi_reset(snf); - - /* Write FDM registers if necessary */ - if (!raw) - mtk_snand_write_fdm(snf, snf->page_cache + snf->writesize); - - /* Command */ - nfi_write32(snf, SNF_PG_CTL1, (snf->opcode_pl << PG_LOAD_CMD_S)); - - /* Column address */ - nfi_write32(snf, SNF_PG_CTL2, coladdr); - - /* Set write mode */ - mode = snf->mode_pl ? PG_LOAD_X4_EN : 0; - nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, mode | PG_LOAD_CUSTOM_EN); - - /* Set bytes to write */ - rwbytes = snf->ecc_steps * snf->raw_sector_size; - nfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) | - rwbytes); - - /* NFI write prepare */ - mode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN; - nfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | - CNFG_DMA_BURST_EN | CNFG_DMA_MODE | mode); - - nfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S)); - - /* Prepare for DMA write */ - len = snf->writesize + snf->oobsize; - ret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, true); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA map to device failed with %d\n", ret); - return ret; - } - - nfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr); - - if (!raw) - mtk_snand_ecc_encoder_start(snf); - - /* Prepare for custom write interrupt */ - nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); - irq_completion_init(snf->pdev); - - /* Trigger NFI into custom mode */ - nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); - - /* Start DMA write */ - nfi_rmw32(snf, NFI_CON, 0, CON_BWR); - nfi_write16(snf, NFI_STRDATA, STR_DATA); - - /* Wait for operation finished */ - ret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1, - CUS_PG_DONE, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "DMA timed out for program load\n"); - goto cleanup; - } - - /* Wait for NFI_SEC_CNTR returning expected value */ - ret = read32_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, - NFI_SEC_CNTR(val) >= snf->ecc_steps, - 0, SNFI_POLL_INTERVAL); - if (ret) { - snand_log_nfi(snf->pdev, - "Timed out waiting for NFI_SEC_CNTR\n"); - goto cleanup; - } - - if (!raw) - mtk_snand_ecc_encoder_stop(snf); - -cleanup: - /* DMA cleanup */ - dma_mem_unmap(snf->pdev, dma_addr, len, true); - - /* Stop write */ - nfi_write32(snf, NFI_CON, 0); - nfi_write16(snf, NFI_CNFG, 0); - - /* Clear SNF done flag */ - nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); - nfi_write32(snf, SNF_STA_CTL1, 0); - - /* Disable interrupt */ - nfi_read32(snf, NFI_INTR_STA); - nfi_write32(snf, NFI_INTR_EN, 0); - - nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); - - return ret; -} - -static void mtk_snand_to_raw_page(struct mtk_snand *snf, - const void *buf, const void *oob, - bool empty_ecc) -{ - uint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; - const uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size; - const uint8_t *bufptr = buf, *oobptr = oob; - uint8_t *raw_sector; - - memset(snf->page_cache, 0xff, snf->writesize + snf->oobsize); - for (i = 0; i < snf->ecc_steps; i++) { - raw_sector = snf->page_cache + i * snf->raw_sector_size; - - if (buf) { - memcpy(raw_sector, bufptr, snf->nfi_soc->sector_size); - bufptr += snf->nfi_soc->sector_size; - } - - raw_sector += snf->nfi_soc->sector_size; - - if (oob) { - memcpy(raw_sector, oobptr, snf->nfi_soc->fdm_size); - oobptr += snf->nfi_soc->fdm_size; - raw_sector += snf->nfi_soc->fdm_size; - - if (empty_ecc) - memset(raw_sector, 0xff, ecc_bytes); - else - memcpy(raw_sector, eccptr, ecc_bytes); - eccptr += ecc_bytes; - } - } -} - -static bool mtk_snand_is_empty_page(struct mtk_snand *snf, const void *buf, - const void *oob) -{ - const uint8_t *p = buf; - uint32_t i, j; - - if (buf) { - for (i = 0; i < snf->writesize; i++) { - if (p[i] != 0xff) - return false; - } - } - - if (oob) { - for (j = 0; j < snf->ecc_steps; j++) { - p = oob + j * snf->nfi_soc->fdm_size; - - for (i = 0; i < snf->nfi_soc->fdm_ecc_size; i++) { - if (p[i] != 0xff) - return false; - } - } - } - - return true; -} - -static int mtk_snand_do_write_page(struct mtk_snand *snf, uint64_t addr, - const void *buf, const void *oob, - bool raw, bool format) -{ - uint64_t die_addr; - bool empty_ecc = false; - uint32_t page; - int ret; - - die_addr = mtk_snand_select_die_address(snf, addr); - page = die_addr >> snf->writesize_shift; - - if (!raw && mtk_snand_is_empty_page(snf, buf, oob)) { - /* - * If the data in the page to be ecc-ed is full 0xff, - * change to raw write mode - */ - raw = true; - format = true; - - /* fill ecc parity code region with 0xff */ - empty_ecc = true; - } - - if (raw) { - if (format) { - mtk_snand_to_raw_page(snf, buf, oob, empty_ecc); - mtk_snand_fdm_bm_swap_raw(snf); - mtk_snand_bm_swap_raw(snf); - } else { - memset(snf->page_cache, 0xff, - snf->writesize + snf->oobsize); - - if (buf) - memcpy(snf->page_cache, buf, snf->writesize); - - if (oob) { - memcpy(snf->page_cache + snf->writesize, oob, - snf->ecc_steps * snf->spare_per_sector); - } - } - } else { - memset(snf->page_cache, 0xff, snf->writesize + snf->oobsize); - if (buf) - memcpy(snf->page_cache, buf, snf->writesize); - - if (oob) { - memcpy(snf->page_cache + snf->writesize, oob, - snf->ecc_steps * snf->nfi_soc->fdm_size); - } - - mtk_snand_fdm_bm_swap(snf); - mtk_snand_bm_swap(snf); - } - - ret = mtk_snand_write_enable(snf); - if (ret) - return ret; - - ret = mtk_snand_program_load(snf, page, raw); - if (ret) - return ret; - - ret = mtk_snand_page_op(snf, page, SNAND_CMD_PROGRAM_EXECUTE); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) { - snand_log_chip(snf->pdev, - "Page program command timed out on page %u\n", - page); - return ret; - } - - if (ret & SNAND_STATUS_PROGRAM_FAIL) { - snand_log_chip(snf->pdev, - "Page program failed on page %u\n", page); - return -EIO; - } - - return 0; -} - -int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf, - const void *oob, bool raw) -{ - if (!snf || (!buf && !oob)) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - return mtk_snand_do_write_page(snf, addr, buf, oob, raw, true); -} - -int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr) -{ - uint64_t die_addr; - uint32_t page, block; - int ret; - - if (!snf) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - die_addr = mtk_snand_select_die_address(snf, addr); - block = die_addr >> snf->erasesize_shift; - page = block << (snf->erasesize_shift - snf->writesize_shift); - - ret = mtk_snand_write_enable(snf); - if (ret) - return ret; - - ret = mtk_snand_page_op(snf, page, SNAND_CMD_BLOCK_ERASE); - if (ret) - return ret; - - ret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL); - if (ret < 0) { - snand_log_chip(snf->pdev, - "Block erase command timed out on block %u\n", - block); - return ret; - } - - if (ret & SNAND_STATUS_ERASE_FAIL) { - snand_log_chip(snf->pdev, - "Block erase failed on block %u\n", block); - return -EIO; - } - - return 0; -} - -static int mtk_snand_block_isbad_std(struct mtk_snand *snf, uint64_t addr) -{ - int ret; - - ret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true, - false); - if (ret && ret != -EBADMSG) - return ret; - - return snf->buf_cache[0] != 0xff; -} - -static int mtk_snand_block_isbad_mtk(struct mtk_snand *snf, uint64_t addr) -{ - int ret; - - ret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true, - true); - if (ret && ret != -EBADMSG) - return ret; - - return snf->buf_cache[0] != 0xff; -} - -int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr) -{ - if (!snf) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - addr &= ~snf->erasesize_mask; - - if (snf->nfi_soc->bbm_swap) - return mtk_snand_block_isbad_std(snf, addr); - - return mtk_snand_block_isbad_mtk(snf, addr); -} - -static int mtk_snand_block_markbad_std(struct mtk_snand *snf, uint64_t addr) -{ - /* Standard BBM position */ - memset(snf->buf_cache, 0xff, snf->oobsize); - snf->buf_cache[0] = 0; - - return mtk_snand_do_write_page(snf, addr, NULL, snf->buf_cache, true, - false); -} - -static int mtk_snand_block_markbad_mtk(struct mtk_snand *snf, uint64_t addr) -{ - /* Write the whole page with zeros */ - memset(snf->buf_cache, 0, snf->writesize + snf->oobsize); - - return mtk_snand_do_write_page(snf, addr, snf->buf_cache, - snf->buf_cache + snf->writesize, true, - true); -} - -int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr) -{ - if (!snf) - return -EINVAL; - - if (addr >= snf->size) - return -EINVAL; - - addr &= ~snf->erasesize_mask; - - if (snf->nfi_soc->bbm_swap) - return mtk_snand_block_markbad_std(snf, addr); - - return mtk_snand_block_markbad_mtk(snf, addr); -} - -int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw, - const uint8_t *oobbuf, size_t ooblen) -{ - size_t len = ooblen, sect_fdm_len; - const uint8_t *oob = oobbuf; - uint32_t step = 0; - - if (!snf || !oobraw || !oob) - return -EINVAL; - - while (len && step < snf->ecc_steps) { - sect_fdm_len = snf->nfi_soc->fdm_size - 1; - if (sect_fdm_len > len) - sect_fdm_len = len; - - memcpy(oobraw + step * snf->nfi_soc->fdm_size + 1, oob, - sect_fdm_len); - - len -= sect_fdm_len; - oob += sect_fdm_len; - step++; - } - - return len; -} - -int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf, - size_t ooblen, const uint8_t *oobraw) -{ - size_t len = ooblen, sect_fdm_len; - uint8_t *oob = oobbuf; - uint32_t step = 0; - - if (!snf || !oobraw || !oob) - return -EINVAL; - - while (len && step < snf->ecc_steps) { - sect_fdm_len = snf->nfi_soc->fdm_size - 1; - if (sect_fdm_len > len) - sect_fdm_len = len; - - memcpy(oob, oobraw + step * snf->nfi_soc->fdm_size + 1, - sect_fdm_len); - - len -= sect_fdm_len; - oob += sect_fdm_len; - step++; - } - - return len; -} - -int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - void *buf, void *oob, size_t ooblen, - size_t *actualooblen, bool raw) -{ - int ret, oobremain; - - if (!snf) - return -EINVAL; - - if (!oob) - return mtk_snand_read_page(snf, addr, buf, NULL, raw); - - ret = mtk_snand_read_page(snf, addr, buf, snf->buf_cache, raw); - if (ret && ret != -EBADMSG) { - if (actualooblen) - *actualooblen = 0; - return ret; - } - - oobremain = mtk_snand_transfer_oob(snf, oob, ooblen, snf->buf_cache); - if (actualooblen) - *actualooblen = ooblen - oobremain; - - return ret; -} - -int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - const void *buf, const void *oob, - size_t ooblen, size_t *actualooblen, bool raw) -{ - int oobremain; - - if (!snf) - return -EINVAL; - - if (!oob) - return mtk_snand_write_page(snf, addr, buf, NULL, raw); - - memset(snf->buf_cache, 0xff, snf->oobsize); - oobremain = mtk_snand_fill_oob(snf, snf->buf_cache, oob, ooblen); - if (actualooblen) - *actualooblen = ooblen - oobremain; - - return mtk_snand_write_page(snf, addr, buf, snf->buf_cache, raw); -} - -int mtk_snand_get_chip_info(struct mtk_snand *snf, - struct mtk_snand_chip_info *info) -{ - if (!snf || !info) - return -EINVAL; - - info->model = snf->model; - info->chipsize = snf->size; - info->blocksize = snf->erasesize; - info->pagesize = snf->writesize; - info->sparesize = snf->oobsize; - info->spare_per_sector = snf->spare_per_sector; - info->fdm_size = snf->nfi_soc->fdm_size; - info->fdm_ecc_size = snf->nfi_soc->fdm_ecc_size; - info->num_sectors = snf->ecc_steps; - info->sector_size = snf->nfi_soc->sector_size; - info->ecc_strength = snf->ecc_strength; - info->ecc_bytes = snf->ecc_bytes; - - return 0; -} - -int mtk_snand_irq_process(struct mtk_snand *snf) -{ - uint32_t sta, ien; - - if (!snf) - return -EINVAL; - - sta = nfi_read32(snf, NFI_INTR_STA); - ien = nfi_read32(snf, NFI_INTR_EN); - - if (!(sta & ien)) - return 0; - - nfi_write32(snf, NFI_INTR_EN, 0); - irq_completion_done(snf->pdev); - - return 1; -} - -static int mtk_snand_select_spare_per_sector(struct mtk_snand *snf) -{ - uint32_t spare_per_step = snf->oobsize / snf->ecc_steps; - int i, mul = 1; - - /* - * If we're using the 1KB sector size, HW will automatically - * double the spare size. So we should only use half of the value. - */ - if (snf->nfi_soc->sector_size == 1024) - mul = 2; - - spare_per_step /= mul; - - for (i = snf->nfi_soc->num_spare_size - 1; i >= 0; i--) { - if (snf->nfi_soc->spare_sizes[i] <= spare_per_step) { - snf->spare_per_sector = snf->nfi_soc->spare_sizes[i]; - snf->spare_per_sector *= mul; - return i; - } - } - - snand_log_nfi(snf->pdev, - "Page size %u+%u is not supported\n", snf->writesize, - snf->oobsize); - - return -1; -} - -static int mtk_snand_pagefmt_setup(struct mtk_snand *snf) -{ - uint32_t spare_size_idx, spare_size_shift, pagesize_idx; - uint32_t sector_size_512; - - if (snf->nfi_soc->sector_size == 512) { - sector_size_512 = NFI_SEC_SEL_512; - spare_size_shift = NFI_SPARE_SIZE_S; - } else { - sector_size_512 = 0; - spare_size_shift = NFI_SPARE_SIZE_LS_S; - } - - switch (snf->writesize) { - case SZ_512: - pagesize_idx = NFI_PAGE_SIZE_512_2K; - break; - case SZ_2K: - if (snf->nfi_soc->sector_size == 512) - pagesize_idx = NFI_PAGE_SIZE_2K_4K; - else - pagesize_idx = NFI_PAGE_SIZE_512_2K; - break; - case SZ_4K: - if (snf->nfi_soc->sector_size == 512) - pagesize_idx = NFI_PAGE_SIZE_4K_8K; - else - pagesize_idx = NFI_PAGE_SIZE_2K_4K; - break; - case SZ_8K: - if (snf->nfi_soc->sector_size == 512) - pagesize_idx = NFI_PAGE_SIZE_8K_16K; - else - pagesize_idx = NFI_PAGE_SIZE_4K_8K; - break; - case SZ_16K: - pagesize_idx = NFI_PAGE_SIZE_8K_16K; - break; - default: - snand_log_nfi(snf->pdev, "Page size %u is not supported\n", - snf->writesize); - return -ENOTSUPP; - } - - spare_size_idx = mtk_snand_select_spare_per_sector(snf); - if (unlikely(spare_size_idx < 0)) - return -ENOTSUPP; - - snf->raw_sector_size = snf->nfi_soc->sector_size + - snf->spare_per_sector; - - /* Setup page format */ - nfi_write32(snf, NFI_PAGEFMT, - (snf->nfi_soc->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | - (snf->nfi_soc->fdm_size << NFI_FDM_NUM_S) | - (spare_size_idx << spare_size_shift) | - (pagesize_idx << NFI_PAGE_SIZE_S) | - sector_size_512); - - return 0; -} - -static enum snand_flash_io mtk_snand_select_opcode(struct mtk_snand *snf, - uint32_t snfi_caps, uint8_t *opcode, - uint8_t *dummy, - const struct snand_io_cap *op_cap) -{ - uint32_t i, caps; - - caps = snfi_caps & op_cap->caps; - - i = fls(caps); - if (i > 0) { - *opcode = op_cap->opcodes[i - 1].opcode; - if (dummy) - *dummy = op_cap->opcodes[i - 1].dummy; - return i - 1; - } - - return __SNAND_IO_MAX; -} - -static int mtk_snand_select_opcode_rfc(struct mtk_snand *snf, - uint32_t snfi_caps, - const struct snand_io_cap *op_cap) -{ - enum snand_flash_io idx; - - static const uint8_t rfc_modes[__SNAND_IO_MAX] = { - [SNAND_IO_1_1_1] = DATA_READ_MODE_X1, - [SNAND_IO_1_1_2] = DATA_READ_MODE_X2, - [SNAND_IO_1_2_2] = DATA_READ_MODE_DUAL, - [SNAND_IO_1_1_4] = DATA_READ_MODE_X4, - [SNAND_IO_1_4_4] = DATA_READ_MODE_QUAD, - }; - - idx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_rfc, - &snf->dummy_rfc, op_cap); - if (idx >= __SNAND_IO_MAX) { - snand_log_snfi(snf->pdev, - "No capable opcode for read from cache\n"); - return -ENOTSUPP; - } - - snf->mode_rfc = rfc_modes[idx]; - - if (idx == SNAND_IO_1_1_4 || idx == SNAND_IO_1_4_4) - snf->quad_spi_op = true; - - return 0; -} - -static int mtk_snand_select_opcode_pl(struct mtk_snand *snf, uint32_t snfi_caps, - const struct snand_io_cap *op_cap) -{ - enum snand_flash_io idx; - - static const uint8_t pl_modes[__SNAND_IO_MAX] = { - [SNAND_IO_1_1_1] = 0, - [SNAND_IO_1_1_4] = 1, - }; - - idx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_pl, - NULL, op_cap); - if (idx >= __SNAND_IO_MAX) { - snand_log_snfi(snf->pdev, - "No capable opcode for program load\n"); - return -ENOTSUPP; - } - - snf->mode_pl = pl_modes[idx]; - - if (idx == SNAND_IO_1_1_4) - snf->quad_spi_op = true; - - return 0; -} - -static int mtk_snand_setup(struct mtk_snand *snf, - const struct snand_flash_info *snand_info) -{ - const struct snand_mem_org *memorg = &snand_info->memorg; - uint32_t i, msg_size, snfi_caps; - int ret; - - /* Calculate flash memory organization */ - snf->model = snand_info->model; - snf->writesize = memorg->pagesize; - snf->oobsize = memorg->sparesize; - snf->erasesize = snf->writesize * memorg->pages_per_block; - snf->die_size = (uint64_t)snf->erasesize * memorg->blocks_per_die; - snf->size = snf->die_size * memorg->ndies; - snf->num_dies = memorg->ndies; - - snf->writesize_mask = snf->writesize - 1; - snf->erasesize_mask = snf->erasesize - 1; - snf->die_mask = snf->die_size - 1; - - snf->writesize_shift = ffs(snf->writesize) - 1; - snf->erasesize_shift = ffs(snf->erasesize) - 1; - snf->die_shift = mtk_snand_ffs64(snf->die_size) - 1; - - snf->select_die = snand_info->select_die; - - /* Determine opcodes for read from cache/program load */ - snfi_caps = SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2; - if (snf->snfi_quad_spi) - snfi_caps |= SPI_IO_1_1_4 | SPI_IO_1_4_4; - - ret = mtk_snand_select_opcode_rfc(snf, snfi_caps, snand_info->cap_rd); - if (ret) - return ret; - - ret = mtk_snand_select_opcode_pl(snf, snfi_caps, snand_info->cap_pl); - if (ret) - return ret; - - /* ECC and page format */ - snf->ecc_steps = snf->writesize / snf->nfi_soc->sector_size; - if (snf->ecc_steps > snf->nfi_soc->max_sectors) { - snand_log_nfi(snf->pdev, "Page size %u is not supported\n", - snf->writesize); - return -ENOTSUPP; - } - - ret = mtk_snand_pagefmt_setup(snf); - if (ret) - return ret; - - msg_size = snf->nfi_soc->sector_size + snf->nfi_soc->fdm_ecc_size; - ret = mtk_ecc_setup(snf, snf->nfi_base + NFI_FDM0L, - snf->spare_per_sector - snf->nfi_soc->fdm_size, - msg_size); - if (ret) - return ret; - - nfi_write16(snf, NFI_CNFG, 0); - - /* Tuning options */ - nfi_write16(snf, NFI_DEBUG_CON1, WBUF_EN); - nfi_write32(snf, SNF_DLY_CTL3, (40 << SFCK_SAM_DLY_S)); - - /* Interrupts */ - nfi_read32(snf, NFI_INTR_STA); - nfi_write32(snf, NFI_INTR_EN, 0); - - /* Clear SNF done flag */ - nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE | CUS_PG_DONE); - nfi_write32(snf, SNF_STA_CTL1, 0); - - /* Initialization on all dies */ - for (i = 0; i < snf->num_dies; i++) { - mtk_snand_select_die(snf, i); - - /* Disable On-Die ECC engine */ - ret = mtk_snand_ondie_ecc_control(snf, false); - if (ret) - return ret; - - /* Disable block protection */ - mtk_snand_unlock(snf); - - /* Enable/disable quad-spi */ - mtk_snand_qspi_control(snf, snf->quad_spi_op); - } - - mtk_snand_select_die(snf, 0); - - return 0; -} - -static int mtk_snand_id_probe(struct mtk_snand *snf, - const struct snand_flash_info **snand_info) -{ - uint8_t id[4], op[2]; - int ret; - - /* Read SPI-NAND JEDEC ID, OP + dummy/addr + ID */ - op[0] = SNAND_CMD_READID; - op[1] = 0; - ret = mtk_snand_mac_io(snf, op, 2, id, sizeof(id)); - if (ret) - return ret; - - *snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id); - if (*snand_info) - return 0; - - /* Read SPI-NAND JEDEC ID, OP + ID */ - op[0] = SNAND_CMD_READID; - ret = mtk_snand_mac_io(snf, op, 1, id, sizeof(id)); - if (ret) - return ret; - - *snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id); - if (*snand_info) - return 0; - - snand_log_chip(snf->pdev, - "Unrecognized SPI-NAND ID: %02x %02x %02x %02x\n", - id[0], id[1], id[2], id[3]); - - return -EINVAL; -} - -int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata, - struct mtk_snand **psnf) -{ - const struct snand_flash_info *snand_info; - uint32_t rawpage_size, sect_bf_size; - struct mtk_snand tmpsnf, *snf; - int ret; - - if (!pdata || !psnf) - return -EINVAL; - - if (pdata->soc >= __SNAND_SOC_MAX) { - snand_log_chip(dev, "Invalid SOC %u for MTK-SNAND\n", - pdata->soc); - return -EINVAL; - } - - /* Dummy instance only for initial reset and id probe */ - tmpsnf.nfi_base = pdata->nfi_base; - tmpsnf.ecc_base = pdata->ecc_base; - tmpsnf.soc = pdata->soc; - tmpsnf.nfi_soc = &mtk_snand_socs[pdata->soc]; - tmpsnf.pdev = dev; - - /* Switch to SNFI mode */ - writel(SPI_MODE, tmpsnf.nfi_base + SNF_CFG); - - /* Reset SNFI & NFI */ - mtk_snand_mac_reset(&tmpsnf); - mtk_nfi_reset(&tmpsnf); - - /* Reset SPI-NAND chip */ - ret = mtk_snand_chip_reset(&tmpsnf); - if (ret) { - snand_log_chip(dev, "Failed to reset SPI-NAND chip\n"); - return ret; - } - - /* Probe SPI-NAND flash by JEDEC ID */ - ret = mtk_snand_id_probe(&tmpsnf, &snand_info); - if (ret) - return ret; - - rawpage_size = snand_info->memorg.pagesize + - snand_info->memorg.sparesize; - - sect_bf_size = mtk_snand_socs[pdata->soc].max_sectors * - sizeof(*snf->sect_bf); - - /* Allocate memory for instance and cache */ - snf = generic_mem_alloc(dev, - sizeof(*snf) + rawpage_size + sect_bf_size); - if (!snf) { - snand_log_chip(dev, "Failed to allocate memory for instance\n"); - return -ENOMEM; - } - - snf->sect_bf = (int *)((uintptr_t)snf + sizeof(*snf)); - snf->buf_cache = (uint8_t *)((uintptr_t)snf->sect_bf + sect_bf_size); - - /* Allocate memory for DMA buffer */ - snf->page_cache = dma_mem_alloc(dev, rawpage_size); - if (!snf->page_cache) { - generic_mem_free(dev, snf); - snand_log_chip(dev, - "Failed to allocate memory for DMA buffer\n"); - return -ENOMEM; - } - - /* Fill up instance */ - snf->pdev = dev; - snf->nfi_base = pdata->nfi_base; - snf->ecc_base = pdata->ecc_base; - snf->soc = pdata->soc; - snf->nfi_soc = &mtk_snand_socs[pdata->soc]; - snf->snfi_quad_spi = pdata->quad_spi; - - /* Initialize SNFI & ECC engine */ - ret = mtk_snand_setup(snf, snand_info); - if (ret) { - dma_mem_free(dev, snf->page_cache); - generic_mem_free(dev, snf); - return ret; - } - - *psnf = snf; - - return 0; -} - -int mtk_snand_cleanup(struct mtk_snand *snf) -{ - if (!snf) - return 0; - - dma_mem_free(snf->pdev, snf->page_cache); - generic_mem_free(snf->pdev, snf); - - return 0; -} diff --git a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h b/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h deleted file mode 100644 index 73c5cc60c..000000000 --- a/target/linux/mediatek/files/drivers/mtd/mtk-snand/mtk-snand.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. - * - * Author: Weijie Gao - */ - -#ifndef _MTK_SNAND_H_ -#define _MTK_SNAND_H_ - -#ifndef PRIVATE_MTK_SNAND_HEADER -#include -#include -#include -#endif - -enum mtk_snand_soc { - SNAND_SOC_MT7622, - SNAND_SOC_MT7629, - - __SNAND_SOC_MAX -}; - -struct mtk_snand_platdata { - void *nfi_base; - void *ecc_base; - enum mtk_snand_soc soc; - bool quad_spi; -}; - -struct mtk_snand_chip_info { - const char *model; - uint64_t chipsize; - uint32_t blocksize; - uint32_t pagesize; - uint32_t sparesize; - uint32_t spare_per_sector; - uint32_t fdm_size; - uint32_t fdm_ecc_size; - uint32_t num_sectors; - uint32_t sector_size; - uint32_t ecc_strength; - uint32_t ecc_bytes; -}; - -struct mtk_snand; -struct snand_flash_info; - -int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata, - struct mtk_snand **psnf); -int mtk_snand_cleanup(struct mtk_snand *snf); - -int mtk_snand_chip_reset(struct mtk_snand *snf); -int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf, - void *oob, bool raw); -int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf, - const void *oob, bool raw); -int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr); -int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr); -int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr); -int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw, - const uint8_t *oobbuf, size_t ooblen); -int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf, - size_t ooblen, const uint8_t *oobraw); -int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - void *buf, void *oob, size_t ooblen, - size_t *actualooblen, bool raw); -int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr, - const void *buf, const void *oob, - size_t ooblen, size_t *actualooblen, - bool raw); -int mtk_snand_get_chip_info(struct mtk_snand *snf, - struct mtk_snand_chip_info *info); -int mtk_snand_irq_process(struct mtk_snand *snf); - -#endif /* _MTK_SNAND_H_ */ diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 211c8f7ba..1f3dc57d7 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -10,7 +10,7 @@ mediatek_setup_interfaces() case $board in mediatek,mt7986a-rfb|\ mediatek,mt7986b-rfb) - ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1 ;; bananapi,bpi-r3) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan" diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15 index 3c73e003c..0c026e0e0 100644 --- a/target/linux/mediatek/filogic/config-5.15 +++ b/target/linux/mediatek/filogic/config-5.15 @@ -50,6 +50,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y +# CONFIG_CMDLINE_OVERRIDE is not set CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y # CONFIG_COMMON_CLK_MT2712 is not set diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 131d3f0a2..5df1d735b 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -1,6 +1,6 @@ DTS_DIR := $(DTS_DIR)/mediatek -KERNEL_LOADADDR := 0x44000000 +KERNEL_LOADADDR := 0x48000000 define Image/Prepare # For UBI we want only one extra block @@ -45,7 +45,7 @@ define Device/bananapi_bpi-r3 DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3 DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-emmc-nor mt7986a-bananapi-bpi-r3-emmc-snand mt7986a-bananapi-bpi-r3-snand DEVICE_DTS_DIR := ../dts - DEVICE_PACKAGES := kmod-btmtkuart kmod-usb3 kmod-i2c-gpio kmod-sfp e2fsprogs f2fsck mkf2fs + DEVICE_PACKAGES := kmod-usb3 kmod-i2c-gpio kmod-sfp e2fsprogs f2fsck mkf2fs IMAGES := sysupgrade.itb KERNEL_INITRAMFS_SUFFIX := -recovery.itb ARTIFACTS := \ @@ -89,7 +89,6 @@ define Device/mediatek_mt7986a-rfb DEVICE_MODEL := MTK7986 rfba AP DEVICE_DTS := mt7986a-rfb DEVICE_DTS_DIR := $(DTS_DIR)/ - KERNEL_LOADADDR := 0x48000000 DEVICE_DTS_OVERLAY := mt7986a-rfb-spim-nand mt7986a-rfb-spim-nor SUPPORTED_DEVICES := mediatek,mt7986a-rfb UBINIZE_OPTS := -E 5 @@ -113,7 +112,6 @@ define Device/mediatek_mt7986b-rfb DEVICE_MODEL := MTK7986 rfbb AP DEVICE_DTS := mt7986b-rfb DEVICE_DTS_DIR := $(DTS_DIR)/ - KERNEL_LOADADDR := 0x48000000 SUPPORTED_DEVICES := mediatek,mt7986b-rfb UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k @@ -131,12 +129,10 @@ define Device/xiaomi_redmi-router-ax6000 DEVICE_MODEL := Redmi Router AX6000 DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000 DEVICE_DTS_DIR := ../dts - KERNEL_LOADADDR := 0x48000000 UBINIZE_OPTS := -E 5 BLOCKSIZE := 128k PAGESIZE := 2048 KERNEL_IN_UBI := 1 - KERNEL_SIZE := 4096k IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata endef TARGET_DEVICES += xiaomi_redmi-router-ax6000 diff --git a/target/linux/mediatek/image/mt7622.mk b/target/linux/mediatek/image/mt7622.mk index 69b21bb1f..f9cd18fd4 100644 --- a/target/linux/mediatek/image/mt7622.mk +++ b/target/linux/mediatek/image/mt7622.mk @@ -142,6 +142,26 @@ define Device/elecom_wrc-2533gent endef TARGET_DEVICES += elecom_wrc-2533gent +define Device/elecom_wrc-x3200gst3 + DEVICE_VENDOR := ELECOM + DEVICE_MODEL := WRC-X3200GST3 + DEVICE_DTS := mt7622-elecom-wrc-x3200gst3 + DEVICE_DTS_DIR := ../dts + IMAGE_SIZE := 25600k + KERNEL_SIZE := 6144k + BLOCKSIZE := 128k + PAGESIZE := 2048 + UBINIZE_OPTS := -E 5 + IMAGES += factory.bin + IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | \ + append-ubi | check-size | \ + elecom-wrc-gs-factory WRC-X3200GST3 0.00 -N | \ + append-string MT7622_ELECOM_WRC-X3200GST3 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata + DEVICE_PACKAGES := kmod-mt7915e +endef +TARGET_DEVICES += elecom_wrc-x3200gst3 + define Device/linksys_e8450 DEVICE_VENDOR := Linksys DEVICE_MODEL := E8450 @@ -227,21 +247,53 @@ define Device/totolink_a8000ru endef TARGET_DEVICES += totolink_a8000ru -define Device/ubnt_unifi-6-lr +define Device/ubnt_unifi-6-lr-v1 DEVICE_VENDOR := Ubiquiti DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v1 DEVICE_DTS_CONFIG := config@1 - DEVICE_DTS := mt7622-ubnt-unifi-6-lr + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v1 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-leds-ubnt-ledbar + SUPPORTED_DEVICES += ubnt,unifi-6-lr +endef +TARGET_DEVICES += ubnt_unifi-6-lr-v1 + +define Device/ubnt_unifi-6-lr-v1-ubootmod + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v1 U-Boot mod + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v1-ubootmod + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7915e kmod-leds-ubnt-ledbar + KERNEL := kernel-bin | lzma + KERNEL_INITRAMFS_SUFFIX := -recovery.itb + KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k + IMAGES := sysupgrade.itb + IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata + ARTIFACTS := preloader.bin bl31-uboot.fip + ARTIFACT/preloader.bin := bl2 nor-2ddr + ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr + SUPPORTED_DEVICES += ubnt,unifi-6-lr-ubootmod +endef +TARGET_DEVICES += ubnt_unifi-6-lr-v1-ubootmod + +define Device/ubnt_unifi-6-lr-v2 + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi 6 LR + DEVICE_VARIANT := v2 + DEVICE_DTS_CONFIG := config@1 + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v2 DEVICE_DTS_DIR := ../dts DEVICE_PACKAGES := kmod-mt7915e endef -TARGET_DEVICES += ubnt_unifi-6-lr +TARGET_DEVICES += ubnt_unifi-6-lr-v2 -define Device/ubnt_unifi-6-lr-ubootmod +define Device/ubnt_unifi-6-lr-v2-ubootmod DEVICE_VENDOR := Ubiquiti DEVICE_MODEL := UniFi 6 LR - DEVICE_VARIANT := U-Boot mod - DEVICE_DTS := mt7622-ubnt-unifi-6-lr-ubootmod + DEVICE_VARIANT := v2 U-Boot mod + DEVICE_DTS := mt7622-ubnt-unifi-6-lr-v2-ubootmod DEVICE_DTS_DIR := ../dts DEVICE_PACKAGES := kmod-mt7915e KERNEL := kernel-bin | lzma @@ -253,7 +305,7 @@ define Device/ubnt_unifi-6-lr-ubootmod ARTIFACT/preloader.bin := bl2 nor-2ddr ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr endef -TARGET_DEVICES += ubnt_unifi-6-lr-ubootmod +TARGET_DEVICES += ubnt_unifi-6-lr-v2-ubootmod define Device/xiaomi_redmi-router-ax6s DEVICE_VENDOR := Xiaomi diff --git a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network index c55fcbee2..29f4b875f 100644 --- a/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/mt7622/base-files/etc/board.d/02_network @@ -9,6 +9,7 @@ mediatek_setup_interfaces() case $board in bananapi,bpi-r64|\ + elecom,wrc-x3200gst3|\ linksys,e8450|\ linksys,e8450-ubi|\ mediatek,mt7622-rfb1|\ diff --git a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh index f54665dfa..103679314 100755 --- a/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh @@ -32,6 +32,12 @@ platform_do_upgrade() { nand_do_upgrade "$1" fi ;; + elecom,wrc-x3200gst3|\ + mediatek,mt7622-rfb1-ubi|\ + totolink,a8000ru|\ + xiaomi,redmi-router-ax6s) + nand_do_upgrade "$1" + ;; linksys,e8450-ubi) CI_KERNPART="fit" nand_do_upgrade "$1" @@ -44,11 +50,6 @@ platform_do_upgrade() { fi default_do_upgrade "$1" ;; - mediatek,mt7622-rfb1-ubi|\ - totolink,a8000ru|\ - xiaomi,redmi-router-ax6s) - nand_do_upgrade "$1" - ;; *) default_do_upgrade "$1" ;; @@ -67,6 +68,7 @@ platform_check_image() { buffalo,wsr-2533dhp2) buffalo_check_image "$board" "$magic" "$1" || return 1 ;; + elecom,wrc-x3200gst3|\ mediatek,mt7622-rfb1-ubi|\ totolink,a8000ru|\ xiaomi,redmi-router-ax6s) diff --git a/target/linux/mediatek/mt7622/config-5.10 b/target/linux/mediatek/mt7622/config-5.10 deleted file mode 100644 index 89ebc6157..000000000 --- a/target/linux/mediatek/mt7622/config-5.10 +++ /dev/null @@ -1,465 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_CNP is not set -CONFIG_ARM64_CRYPTO=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_PTR_AUTH is not set -# CONFIG_ARM64_SVE is not set -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8183=y -# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set -# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set -# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set -# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set -# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set -# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set -# CONFIG_COMMON_CLK_MT8183_MMSYS is not set -# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set -# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_KPP=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SIMD=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMATEST=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ENGINE_RAID=y -CONFIG_DMA_OF=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -# CONFIG_FLATMEM_MANUAL is not set -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIOLIB=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HOLES_IN_ZONE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -# CONFIG_KEYBOARD_MTK_PMIC is not set -CONFIG_LEDS_UBNT_LEDBAR=y -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_EFUSE=y -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SPI_NAND=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_CONFIGFS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_OVERLAY=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_BLK is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZO_COMPRESS is not set -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -# CONFIG_SND_SOC_MT6359 is not set -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_VMAP_STACK=y -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index 886e8d7f8..8717e799e 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -54,6 +54,7 @@ CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y +# CONFIG_CMDLINE_OVERRIDE is not set CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y CONFIG_COMMON_CLK_MT2712=y @@ -113,6 +114,7 @@ CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CMAC=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y @@ -128,6 +130,7 @@ CONFIG_CRYPTO_GHASH_ARM64_CE=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG=y @@ -194,7 +197,6 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GLOB=y -CONFIG_GPIOLIB=y CONFIG_GPIO_CDEV=y CONFIG_GRO_CELLS=y CONFIG_HANDLE_DOMAIN_IRQ=y @@ -223,7 +225,6 @@ CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y CONFIG_JUMP_LABEL=y -CONFIG_LEDS_UBNT_LEDBAR=y CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y @@ -248,6 +249,7 @@ CONFIG_MODULES_TREE_LOOKUP=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_MTD_NAND_CORE=y CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_MTK=y CONFIG_MTD_NAND_MTK_BMT=y @@ -255,6 +257,7 @@ CONFIG_MTD_PARSER_TRX=y CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_FIT_FW=y CONFIG_MTD_UBI=y @@ -269,7 +272,6 @@ CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SPI_NAND=y CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set @@ -351,7 +353,6 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_SUPPLY=y CONFIG_PRINTK_TIME=y CONFIG_PSTORE=y -# CONFIG_PSTORE_BLK is not set CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y @@ -387,6 +388,7 @@ CONFIG_RTC_DRV_MT7622=y CONFIG_RTC_I2C_AND_SPI=y CONFIG_RTL8367S_GSW=y CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCHED_MC=y CONFIG_SCSI=y CONFIG_SCSI_COMMON=y # CONFIG_SECTION_MISMATCH_WARN_ONLY is not set @@ -413,6 +415,7 @@ CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_MT65XX=y CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y CONFIG_SRCU=y CONFIG_SWCONFIG=y CONFIG_SWIOTLB=y diff --git a/target/linux/mediatek/mt7623/config-5.10 b/target/linux/mediatek/mt7623/config-5.10 deleted file mode 100644 index 3d017400a..000000000 --- a/target/linux/mediatek/mt7623/config-5.10 +++ /dev/null @@ -1,633 +0,0 @@ -# CONFIG_AIO is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_CMDLINE_PARSER=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CLEANCACHE=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DEV_MEDIATEK=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_PREEMPT=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -CONFIG_DEBUG_UNCOMPRESS=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_PANEL=y -# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set -# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set -# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -CONFIG_DRM_PANEL_BRIDGE=y -# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set -# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set -# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set -# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set -# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB=y -CONFIG_GRO_CELLS=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_CONSOLE=y -CONFIG_HWMON=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HID=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADC is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_AS5011 is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_DB9 is not set -# CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_GAMECON is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_PSXPAD_SPI is not set -# CONFIG_JOYSTICK_PXRC is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_TURBOGRAFX is not set -# CONFIG_JOYSTICK_WALKERA0701 is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_XPAD is not set -# CONFIG_JOYSTICK_ZHENHUA is not set -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_UBNT_LEDBAR is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_MTK_BMT is not set -# CONFIG_MTD_PARSER_TRX is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CQDMA=y -CONFIG_MTK_EFUSE=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -CONFIG_MTK_MMSYS=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SMI=y -# CONFIG_MTK_SPI_NAND is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_SWITCHDEV=y -# CONFIG_NET_VENDOR_AURORA is not set -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_CONFIGFS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OF_OVERLAY=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_MTK_HDMI=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -CONFIG_PINCTRL_MT6397=y -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -# CONFIG_SND_SOC_MT6359 is not set -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TABLET_SERIAL_WACOM4 is not set -# CONFIG_TABLET_USB_ACECAD is not set -# CONFIG_TABLET_USB_AIPTEK is not set -# CONFIG_TABLET_USB_GTCO is not set -# CONFIG_TABLET_USB_HANWANG is not set -# CONFIG_TABLET_USB_KBTAB is not set -# CONFIG_TABLET_USB_PEGASUS is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TOUCHSCREEN_PROPERTIES=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -# CONFIG_USB_MUSB_GADGET is not set -CONFIG_USB_MUSB_HDRC=y -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 index 1569b7a2e..d28b051c8 100644 --- a/target/linux/mediatek/mt7623/config-5.15 +++ b/target/linux/mediatek/mt7623/config-5.15 @@ -16,6 +16,8 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_ARM_ATAG_DTB_COMPAT is not set CONFIG_ARM_CPU_SUSPEND=y # CONFIG_ARM_CPU_TOPOLOGY is not set @@ -52,6 +54,7 @@ CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" CONFIG_CMDLINE_FROM_BOOTLOADER=y CONFIG_CMDLINE_PARTITION=y +# CONFIG_CMDLINE_OVERRIDE is not set CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y CONFIG_COMMON_CLK_MT2701=y @@ -105,6 +108,7 @@ CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_BLAKE2S=y CONFIG_CRYPTO_CRC32=y CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_DEFLATE=y @@ -115,6 +119,7 @@ CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG=y @@ -129,7 +134,6 @@ CONFIG_DCACHE_WORD_ACCESS=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y CONFIG_DEBUG_LL=y CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" CONFIG_DEBUG_MISC=y @@ -238,7 +242,6 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB=y CONFIG_GPIO_CDEV=y CONFIG_GRO_CELLS=y CONFIG_HANDLE_DOMAIN_IRQ=y @@ -268,14 +271,7 @@ CONFIG_IIO=y CONFIG_INITRAMFS_SOURCE="" CONFIG_INPUT=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_MOUSE=y -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_TABLET=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_IOMMU_API=y # CONFIG_IOMMU_DEBUGFS is not set @@ -294,37 +290,6 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_WORK=y CONFIG_JBD2=y -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADC is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_AS5011 is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_DB9 is not set -# CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_GAMECON is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_PSXPAD_SPI is not set -# CONFIG_JOYSTICK_PXRC is not set -# CONFIG_JOYSTICK_QWIIC is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_TURBOGRAFX is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_WALKERA0701 is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_XPAD is not set -# CONFIG_JOYSTICK_ZHENHUA is not set CONFIG_KALLSYMS=y CONFIG_KCMP=y CONFIG_KEYBOARD_MTK_PMIC=y @@ -333,7 +298,6 @@ CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_UBNT_LEDBAR is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y @@ -377,12 +341,8 @@ CONFIG_MMC_SDHCI=y # CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MODULES_USE_ELF_REL=y -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_NAND_ECC_MEDIATEK is not set CONFIG_MTD_SPI_NOR=y CONFIG_MTD_SPLIT_FIRMWARE=y CONFIG_MTD_SPLIT_UIMAGE_FW=y @@ -403,7 +363,6 @@ CONFIG_MTK_PMIC_WRAP=y CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y CONFIG_MTK_SMI=y -# CONFIG_MTK_SPI_NAND is not set CONFIG_MTK_THERMAL=y CONFIG_MTK_TIMER=y # CONFIG_MTK_UART_APDMA is not set @@ -553,12 +512,6 @@ CONFIG_SWPHY=y CONFIG_SWP_EMULATE=y CONFIG_SYNC_FILE=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -# CONFIG_TABLET_SERIAL_WACOM4 is not set -# CONFIG_TABLET_USB_ACECAD is not set -# CONFIG_TABLET_USB_AIPTEK is not set -# CONFIG_TABLET_USB_HANWANG is not set -# CONFIG_TABLET_USB_KBTAB is not set -# CONFIG_TABLET_USB_PEGASUS is not set CONFIG_THERMAL=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 diff --git a/target/linux/mediatek/mt7629/config-5.10 b/target/linux/mediatek/mt7629/config-5.10 deleted file mode 100644 index 5cd53b113..000000000 --- a/target/linux/mediatek/mt7629/config-5.10 +++ /dev/null @@ -1,305 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -CONFIG_COMMON_CLK_MT8516=y -# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DIMLIB=y -CONFIG_DMA_OPS=y -CONFIG_DMA_REMAP=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB=y -CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_HARDENED_USERCOPY is not set -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IO_URING=y -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -# CONFIG_LEDS_UBNT_LEDBAR is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_MT6577_AUXADC is not set -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -# CONFIG_MTD_PARSER_TRX is not set -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_EFUSE is not set -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SPI_NAND=y -# CONFIG_MTK_THERMAL is not set -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_NET=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15 index a42a62ed0..39596717a 100644 --- a/target/linux/mediatek/mt7629/config-5.15 +++ b/target/linux/mediatek/mt7629/config-5.15 @@ -1,3 +1,4 @@ +CONFIG_AF_UNIX_OOB=y CONFIG_ALIGNMENT_TRAP=y CONFIG_ARCH_32BIT_OFF_T=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y @@ -14,6 +15,8 @@ CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARM=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y CONFIG_ARM_GIC=y CONFIG_ARM_HAS_SG_CHAIN=y CONFIG_ARM_HEAVY_MB=y @@ -26,22 +29,22 @@ CONFIG_ARM_UNWIND=y CONFIG_ARM_VIRT_EXT=y CONFIG_ATAGS=y CONFIG_AUTO_ZRELADDR=y +CONFIG_BINARY_PRINTF=y CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_MQ_PCI=y CONFIG_BLK_PM=y -CONFIG_BLK_SCSI_REQUEST=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_CACHE_L2X0=y # CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_CHR_DEV_SCH=y -CONFIG_CLKDEV_LOOKUP=y CONFIG_CLKSRC_MMIO=y CONFIG_CLONE_BACKWARDS=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CMDLINE_OVERRIDE=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_MEDIATEK=y # CONFIG_COMMON_CLK_MT2701 is not set @@ -74,8 +77,10 @@ CONFIG_CPU_THUMB_CAPABLE=y CONFIG_CPU_TLB_V7=y CONFIG_CPU_V7=y CONFIG_CRC16=y +CONFIG_CRYPTO_BLAKE2S_ARM=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_ZSTD=y @@ -92,6 +97,7 @@ CONFIG_EDAC_SUPPORT=y CONFIG_EINT_MTK=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_GENERIC_ARCH_TOPOLOGY=y @@ -99,6 +105,7 @@ CONFIG_GENERIC_BUG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_IDLE_POLL_SETUP=y @@ -107,6 +114,7 @@ CONFIG_GENERIC_IRQ_MIGRATION=y CONFIG_GENERIC_IRQ_MULTI_HANDLER=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_GENERIC_PCI_IOMAP=y @@ -120,7 +128,7 @@ CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIOLIB=y +CONFIG_GPIO_CDEV=y CONFIG_HANDLE_DOMAIN_IRQ=y # CONFIG_HARDENED_USERCOPY is not set CONFIG_HARDEN_BRANCH_PREDICTOR=y @@ -142,10 +150,10 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_IRQ_WORK=y # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -# CONFIG_LEDS_UBNT_LEDBAR is not set CONFIG_LIBFDT=y CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LTO_NONE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y # CONFIG_MACH_MT2701 is not set @@ -158,7 +166,6 @@ CONFIG_MACH_MT7629=y CONFIG_MDIO_BUS=y CONFIG_MDIO_DEVICE=y CONFIG_MDIO_DEVRES=y -# CONFIG_MEDIATEK_MT6577_AUXADC is not set CONFIG_MEDIATEK_WATCHDOG=y CONFIG_MEMFD_CREATE=y CONFIG_MFD_SYSCON=y @@ -167,10 +174,9 @@ CONFIG_MIGRATION=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_MTD_NAND_CORE=y CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_MEDIATEK=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y CONFIG_MTD_NAND_MTK_BMT=y -# CONFIG_MTD_PARSER_TRX is not set CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NAND=y CONFIG_MTD_SPI_NOR=y @@ -186,14 +192,20 @@ CONFIG_MTK_INFRACFG=y # CONFIG_MTK_PMIC_WRAP is not set CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SPI_NAND=y -# CONFIG_MTK_THERMAL is not set CONFIG_MTK_TIMER=y CONFIG_MUTEX_SPIN_ON_OWNER=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NETFILTER=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_MT7530=y +CONFIG_NET_DSA_TAG_MTK=y CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_MEDIATEK_SOC=y +CONFIG_NET_MEDIATEK_SOC_WED=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_SWITCHDEV=y CONFIG_NET_VENDOR_MEDIATEK=y CONFIG_NLS=y CONFIG_NO_HZ_COMMON=y @@ -209,7 +221,6 @@ CONFIG_OF_GPIO=y CONFIG_OF_IRQ=y CONFIG_OF_KOBJ=y CONFIG_OF_MDIO=y -CONFIG_OF_NET=y CONFIG_OLD_SIGACTION=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OUTER_CACHE=y @@ -241,6 +252,7 @@ CONFIG_PM=y CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y CONFIG_PWM=y CONFIG_PWM_MEDIATEK=y # CONFIG_PWM_MTK_DISP is not set @@ -255,6 +267,7 @@ CONFIG_RPS=y # CONFIG_RTL8367S_GSW is not set CONFIG_RWSEM_SPIN_ON_OWNER=y CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_8250_NR_UARTS=3 @@ -265,12 +278,14 @@ CONFIG_SGL_ALLOC=y CONFIG_SG_POOL=y CONFIG_SMP=y CONFIG_SMP_ON_UP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_SPARSE_IRQ=y CONFIG_SPI=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y CONFIG_SPI_MT65XX=y CONFIG_SPI_MTK_NOR=y +CONFIG_SPI_MTK_SNFI=y CONFIG_SRCU=y CONFIG_STACKTRACE=y # CONFIG_SWAP is not set diff --git a/target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index f4e77cf69..000000000 --- a/target/linux/mediatek/patches-5.10/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,119 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -23,7 +22,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -40,23 +39,22 @@ - - gpio-keys { - compatible = "gpio-keys"; -- poll-interval = <100>; - - factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { -@@ -132,22 +130,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -236,15 +234,28 @@ - - &pcie { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>; -+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; - status = "okay"; - - pcie@0,0 { - status = "okay"; - }; -+ -+ pcie@1,0 { -+ status = "okay"; -+ }; - }; - - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -511,11 +522,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch b/target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index 254b5f9eb..000000000 --- a/target/linux/mediatek/patches-5.10/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -272,3 +281,17 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+}; diff --git a/target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index 6ef56f858..000000000 --- a/target/linux/mediatek/patches-5.10/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -111,7 +111,7 @@ - }; - - psci { -- compatible = "arm,psci-0.2"; -+ compatible = "arm,psci-1.0"; - method = "smc"; - }; - -@@ -127,6 +127,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@0x42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch b/target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 8dc53d298..000000000 --- a/target/linux/mediatek/patches-5.10/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch b/target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch deleted file mode 100644 index 07a2eae24..000000000 --- a/target/linux/mediatek/patches-5.10/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -22,7 +22,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch b/target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index 6ce85efde..000000000 --- a/target/linux/mediatek/patches-5.10/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -18,6 +18,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -160,22 +161,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@6 { diff --git a/target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index f88dbc719..000000000 --- a/target/linux/mediatek/patches-5.10/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -19,6 +19,10 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -42,8 +46,8 @@ - compatible = "gpio-keys"; - - factory { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -57,17 +61,25 @@ - leds { - compatible = "gpio-leds"; - -- green { -- label = "bpi-r64:pio:green"; -- gpios = <&pio 89 GPIO_ACTIVE_HIGH>; -+ led_system_blue: blue { -+ label = "bpi-r64:pio:blue"; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- red { -- label = "bpi-r64:pio:red"; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_green: green { -+ label = "bpi-r64:pio:green"; -+ gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; -+ -+/* -+ * red { -+ * label = "bpi-r64:pio:red"; -+ * gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ * default-state = "off"; -+ * }; -+ */ - }; - - memory { diff --git a/target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch b/target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index 261579bf3..000000000 --- a/target/linux/mediatek/patches-5.10/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -559,12 +559,16 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { -- status = "disable"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "disable"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch deleted file mode 100644 index 39d81bd5d..000000000 --- a/target/linux/mediatek/patches-5.10/115-dts-bpi64-add-snand-support.patch +++ /dev/null @@ -1,41 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -259,14 +259,32 @@ - status = "disabled"; - }; - --&nor_flash { -+&snand { - pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+ pinctrl-0 = <&serial_nand_pins>; -+ mediatek,quad-spi; -+ status = "okay"; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; - -- flash@0 { -- compatible = "jedec,spi-nor"; -- reg = <0>; -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; - }; - }; - diff --git a/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index e7c5d9b16..000000000 --- a/target/linux/mediatek/patches-5.10/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,77 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,22 @@ - status = "disabled"; - }; - -+ snand: snfi@1100d000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>, <0x1100e000 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,38 @@ - }; - }; - -+&snand { -+ status = "okay"; -+ mediatek,quad-spi; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index fe136c247..000000000 --- a/target/linux/mediatek/patches-5.10/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,81 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -561,6 +561,20 @@ - status = "disabled"; - }; - -+ snand: snfi@1100d000 { -+ compatible = "mediatek,mt7622-snand"; -+ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - nor_flash: spi@11014000 { - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -529,6 +529,55 @@ - status = "disabled"; - }; - -+&snand { -+ mediatek,quad-spi; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index e1e43ce75..000000000 --- a/target/linux/mediatek/patches-5.10/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -561,7 +561,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -619,5 +619,6 @@ - }; - - &wmac { -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 38947a3a9..000000000 --- a/target/linux/mediatek/patches-5.10/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -949,17 +949,14 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; - }; - - bdpsys: syscon@1c000000 { diff --git a/target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch b/target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 091cffc3c..000000000 --- a/target/linux/mediatek/patches-5.10/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index d1bafc152..000000000 --- a/target/linux/mediatek/patches-5.10/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch b/target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index f6745add5..000000000 --- a/target/linux/mediatek/patches-5.10/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index b1dd75a41..000000000 --- a/target/linux/mediatek/patches-5.10/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch b/target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch deleted file mode 100644 index bcdc31a2d..000000000 --- a/target/linux/mediatek/patches-5.10/171-dt-bindings-usb-convert-mediatek-musb.txt-to-YAML-sc.patch +++ /dev/null @@ -1,195 +0,0 @@ -From f9924caf5d952594b2d912e2ec318189ce64cf04 Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun -Date: Fri, 25 Dec 2020 15:52:55 +0800 -Subject: [PATCH] dt-bindings: usb: convert mediatek, musb.txt to YAML schema - -Convert mediatek,musb.txt to YAML schema mediatek,musb.yaml - -Cc: Min Guo -Reviewed-by: Rob Herring -Signed-off-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20201225075258.33352-8-chunfeng.yun@mediatek.com -Signed-off-by: Greg Kroah-Hartman ---- - .../devicetree/bindings/usb/mediatek,musb.txt | 57 --------- - .../bindings/usb/mediatek,musb.yaml | 113 ++++++++++++++++++ - 2 files changed, 113 insertions(+), 57 deletions(-) - delete mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt - create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.yaml - ---- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt -+++ /dev/null -@@ -1,57 +0,0 @@ --MediaTek musb DRD/OTG controller --------------------------------------------- -- --Required properties: -- - compatible : should be one of: -- "mediatek,mt2701-musb" -- ... -- followed by "mediatek,mtk-musb" -- - reg : specifies physical base address and size of -- the registers -- - interrupts : interrupt used by musb controller -- - interrupt-names : must be "mc" -- - phys : PHY specifier for the OTG phy -- - dr_mode : should be one of "host", "peripheral" or "otg", -- refer to usb/generic.txt -- - clocks : a list of phandle + clock-specifier pairs, one for -- each entry in clock-names -- - clock-names : must contain "main", "mcu", "univpll" -- for clocks of controller -- --Optional properties: -- - power-domains : a phandle to USB power domain node to control USB's -- MTCMOS -- --Required child nodes: -- usb connector node as defined in bindings/connector/usb-connector.yaml --Optional properties: -- - id-gpios : input GPIO for USB ID pin. -- - vbus-gpios : input GPIO for USB VBUS pin. -- - vbus-supply : reference to the VBUS regulator, needed when supports -- dual-role mode -- - usb-role-switch : use USB Role Switch to support dual-role switch, see -- usb/generic.txt. -- --Example: -- --usb2: usb@11200000 { -- compatible = "mediatek,mt2701-musb", -- "mediatek,mtk-musb"; -- reg = <0 0x11200000 0 0x1000>; -- interrupts = ; -- interrupt-names = "mc"; -- phys = <&u2port2 PHY_TYPE_USB2>; -- dr_mode = "otg"; -- clocks = <&pericfg CLK_PERI_USB0>, -- <&pericfg CLK_PERI_USB0_MCU>, -- <&pericfg CLK_PERI_USB_SLV>; -- clock-names = "main","mcu","univpll"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -- usb-role-switch; -- connector{ -- compatible = "gpio-usb-b-connector", "usb-b-connector"; -- type = "micro"; -- id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; -- vbus-supply = <&usb_vbus>; -- }; --}; ---- /dev/null -+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -@@ -0,0 +1,113 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+# Copyright (c) 2020 MediaTek -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/usb/mediatek,musb.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MediaTek MUSB DRD/OTG Controller Device Tree Bindings -+ -+maintainers: -+ - Min Guo -+ -+properties: -+ $nodename: -+ pattern: '^usb@[0-9a-f]+$' -+ -+ compatible: -+ items: -+ - enum: -+ - mediatek,mt2701-musb -+ - const: mediatek,mtk-musb -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts: -+ maxItems: 1 -+ -+ interrupt-names: -+ items: -+ - const: mc -+ -+ clocks: -+ items: -+ - description: The main/core clock -+ - description: The system bus clock -+ - description: The 48Mhz clock -+ -+ clock-names: -+ items: -+ - const: main -+ - const: mcu -+ - const: univpll -+ -+ phys: -+ maxItems: 1 -+ -+ usb-role-switch: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: Support role switch. See usb/generic.txt -+ type: boolean -+ -+ dr_mode: -+ enum: -+ - host -+ - otg -+ - peripheral -+ -+ power-domains: -+ description: A phandle to USB power domain node to control USB's MTCMOS -+ maxItems: 1 -+ -+ connector: -+ $ref: /connector/usb-connector.yaml# -+ description: Connector for dual role switch -+ type: object -+ -+dependencies: -+ usb-role-switch: [ 'connector' ] -+ connector: [ 'usb-role-switch' ] -+ -+required: -+ - compatible -+ - reg -+ - interrupts -+ - interrupt-names -+ - phys -+ - clocks -+ - clock-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ #include -+ #include -+ -+ usb@11200000 { -+ compatible = "mediatek,mt2701-musb", "mediatek,mtk-musb"; -+ reg = <0x11200000 0x1000>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&u2port2 PHY_TYPE_USB2>; -+ dr_mode = "otg"; -+ clocks = <&pericfg CLK_PERI_USB0>, -+ <&pericfg CLK_PERI_USB0_MCU>, -+ <&pericfg CLK_PERI_USB_SLV>; -+ clock-names = "main","mcu","univpll"; -+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -+ usb-role-switch; -+ -+ connector { -+ compatible = "gpio-usb-b-connector", "usb-b-connector"; -+ type = "micro"; -+ id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; -+ vbus-supply = <&usb_vbus>; -+ }; -+ }; -+... diff --git a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch b/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch deleted file mode 100644 index 3e97d4a0a..000000000 --- a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mediatek-musb-add-mt8516-compatbile.patch +++ /dev/null @@ -1,25 +0,0 @@ -From b5a12546e779d4f5586f58e60e0ef5070a833a64 Mon Sep 17 00:00:00 2001 -From: Chunfeng Yun -Date: Mon, 1 Feb 2021 15:00:08 +0800 -Subject: [PATCH] dt-bindings: usb: mediatek: musb: add mt8516 compatbile - -Add support mt8516 compatbile - -Reviewed-by: Rob Herring -Signed-off-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20210201070016.41721-8-chunfeng.yun@mediatek.com -Signed-off-by: Greg Kroah-Hartman ---- - Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -@@ -17,6 +17,7 @@ properties: - compatible: - items: - - enum: -+ - mediatek,mt8516-musb - - mediatek,mt2701-musb - - const: mediatek,mtk-musb - diff --git a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch b/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch deleted file mode 100644 index 44415db5d..000000000 --- a/target/linux/mediatek/patches-5.10/172-dt-bindings-usb-mtk-musb-add-MT7623-compatible.patch +++ /dev/null @@ -1,23 +0,0 @@ -From b7e4218ece0b7a1b9142491056ae0c4f1af80041 Mon Sep 17 00:00:00 2001 -From: Sungbo Eo -Date: Sun, 8 Aug 2021 21:38:39 +0900 -Subject: [PATCH 1/2] dt-bindings: usb: mtk-musb: add MT7623 compatible - -Document MT7623 compatible for mtk-musb. - -Signed-off-by: Sungbo Eo -Reviewed-by: Matthias Brugger ---- - Documentation/devicetree/bindings/usb/mediatek,musb.yaml | 1 + - 1 file changed, 1 insertion(+) - ---- a/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.yaml -@@ -19,6 +19,7 @@ properties: - - enum: - - mediatek,mt8516-musb - - mediatek,mt2701-musb -+ - mediatek,mt7623-musb - - const: mediatek,mtk-musb - - reg: diff --git a/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch b/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch deleted file mode 100644 index ba1d1fe20..000000000 --- a/target/linux/mediatek/patches-5.10/173-arm-dts-mt7623-add-musb-device-nodes.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001 -From: Sungbo Eo -Date: Sun, 8 Aug 2021 21:38:40 +0900 -Subject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes - -MT7623 has an musb controller that is compatible with the one from MT2701. - -Signed-off-by: Sungbo Eo ---- - arch/arm/boot/dts/mt7623.dtsi | 34 ++++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7623a.dtsi | 4 ++++ - 2 files changed, 38 insertions(+) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -585,6 +585,40 @@ - status = "disabled"; - }; - -+ usb0: usb@11200000 { -+ compatible = "mediatek,mt7623-musb", -+ "mediatek,mtk-musb"; -+ reg = <0 0x11200000 0 0x1000>; -+ interrupts = ; -+ interrupt-names = "mc"; -+ phys = <&u2port2 PHY_TYPE_USB2>; -+ dr_mode = "otg"; -+ clocks = <&pericfg CLK_PERI_USB0>, -+ <&pericfg CLK_PERI_USB0_MCU>, -+ <&pericfg CLK_PERI_USB_SLV>; -+ clock-names = "main","mcu","univpll"; -+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; -+ status = "disabled"; -+ }; -+ -+ u2phy1: t-phy@11210000 { -+ compatible = "mediatek,mt7623-tphy", -+ "mediatek,generic-tphy-v1"; -+ reg = <0 0x11210000 0 0x0800>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ u2port2: usb-phy@11210800 { -+ reg = <0 0x11210800 0 0x0100>; -+ clocks = <&topckgen CLK_TOP_USB_PHY48M>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ status = "okay"; -+ }; -+ }; -+ - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7623-audsys", - "mediatek,mt2701-audsys", ---- a/arch/arm/boot/dts/mt7623a.dtsi -+++ b/arch/arm/boot/dts/mt7623a.dtsi -@@ -35,6 +35,10 @@ - clock-names = "ethif"; - }; - -+&usb0 { -+ power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>; -+}; -+ - &usb1 { - power-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>; - }; diff --git a/target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch deleted file mode 100644 index 80ceb490d..000000000 --- a/target/linux/mediatek/patches-5.10/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -160,6 +160,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index 95f4be177..000000000 --- a/target/linux/mediatek/patches-5.10/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -15,6 +15,8 @@ - #include - #include - #include -+#include -+#include - - /* version V1 sub-banks offset base address */ - /* banks shared by multiple phys */ -@@ -267,6 +269,9 @@ - #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) - #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x)) - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -315,6 +320,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -634,6 +640,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); - tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H); - tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2); -@@ -1136,6 +1146,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_ref_clk); - device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef); - -+ if (of_find_property(np, "mediatek,phy-switch", NULL)) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch b/target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch deleted file mode 100644 index 318c8b287..000000000 --- a/target/linux/mediatek/patches-5.10/330-mtk-snand-bmt-support.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- a/drivers/mtd/mtk-snand/mtk-snand-mtd.c -+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -612,6 +613,8 @@ static int mtk_snand_probe(struct platfo - mtd->_block_isbad = mtk_snand_mtd_block_isbad; - mtd->_block_markbad = mtk_snand_mtd_block_markbad; - -+ mtk_bmt_attach(mtd); -+ - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(msm->pdev.dev, "failed to register mtd partition\n"); -@@ -623,6 +626,7 @@ static int mtk_snand_probe(struct platfo - return 0; - - errout4: -+ mtk_bmt_detach(mtd); - devm_kfree(msm->pdev.dev, msm->page_cache); - - errout3: -@@ -650,6 +654,8 @@ static int mtk_snand_remove(struct platf - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); -+ - mtk_snand_cleanup(msm->snf); - - if (msm->irq >= 0) diff --git a/target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index a79bd8fcd..000000000 --- a/target/linux/mediatek/patches-5.10/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -535,6 +535,8 @@ - pinctrl-0 = <&serial_nand_pins>; - status = "okay"; - -+ mediatek,bmt-v2; -+ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; diff --git a/target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch b/target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch deleted file mode 100644 index ebba6ffaa..000000000 --- a/target/linux/mediatek/patches-5.10/360-mtd-add-mtk-snand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -238,6 +238,8 @@ source "drivers/mtd/ubi/Kconfig" - - source "drivers/mtd/hyperbus/Kconfig" - -+source "drivers/mtd/mtk-snand/Kconfig" -+ - source "drivers/mtd/composite/Kconfig" - - endif # MTD ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -34,5 +34,7 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ - obj-$(CONFIG_MTD_UBI) += ubi/ - obj-$(CONFIG_MTD_HYPERBUS) += hyperbus/ - -+obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ -+ - # Composite drivers must be loaded last - obj-y += composite/ diff --git a/target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch b/target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index e0941a955..000000000 --- a/target/linux/mediatek/patches-5.10/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -314,6 +314,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch b/target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index be2bffb74..000000000 --- a/target/linux/mediatek/patches-5.10/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -736,6 +736,9 @@ enum safexcel_eip_version { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -53,9 +53,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch b/target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch deleted file mode 100644 index f8527ba42..000000000 --- a/target/linux/mediatek/patches-5.10/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch +++ /dev/null @@ -1,28 +0,0 @@ -From: David Bauer -To: linux-mtd@lists.infradead.org -Subject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV -Date: Sat, 13 Feb 2021 16:10:47 +0100 - -The Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K -sectors as well as block protection and Dual-/Quad-read. - -Tested on: Ubiquiti UniFi 6 LR - -Signed-off-by: David Bauer ---- - drivers/mtd/spi-nor/winbond.c | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/drivers/mtd/spi-nor/winbond.c -+++ b/drivers/mtd/spi-nor/winbond.c -@@ -95,6 +95,10 @@ static const struct flash_info winbond_p - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024, -+ SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | -+ SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 | -+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) }, - { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, - }; diff --git a/target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index c7e65456b..000000000 --- a/target/linux/mediatek/patches-5.10/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -340,6 +340,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -89,6 +89,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch b/target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch deleted file mode 100644 index 02e4c130e..000000000 --- a/target/linux/mediatek/patches-5.10/600-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch +++ /dev/null @@ -1,415 +0,0 @@ -From patchwork Thu May 28 06:16:45 2020 -Content-Type: text/plain; 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-+ reg = <0 0x1a140000 0 0x1000>; -+ }; -+... ---- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt -+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt -@@ -8,7 +8,7 @@ Required properties: - "mediatek,mt7623-pcie" - "mediatek,mt7629-pcie" - - device_type: Must be "pci" --- reg: Base addresses and lengths of the PCIe subsys and root ports. -+- reg: Base addresses and lengths of the root ports. - - reg-names: Names of the above areas to use during resource lookup. - - #address-cells: Address representation for root ports (must be 3) - - #size-cells: Size representation for root ports (must be 2) -@@ -19,10 +19,10 @@ Required properties: - - sys_ckN :transaction layer and data link layer clock - Required entries for MT2701/MT7623: - - free_ck :for reference clock of PCIe subsys -- Required entries for MT2712/MT7622: -+ Required entries for MT2712/MT7622/MT7629: - - ahb_ckN :AHB slave interface operating clock for CSR access and RC - initiated MMIO access -- Required entries for MT7622: -+ Required entries for MT7622/MT7629: - - axi_ckN :application layer MMIO channel operating clock - - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when - pcie_mac_ck/pcie_pipe_ck is turned off -@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701: - - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the - number of root ports. - --Required properties for MT2712/MT7622: -+Required properties for MT2712/MT7622/MT7629: - -interrupts: A list of interrupt outputs of the controller, must have one - entry for each PCIe port - -+Required properties for MT7622/MT7629: -+- mediatek,pcie-subsys: Should be a phandle of the pciecfg node. -+ - In addition, the device tree node must have sub-nodes describing each - PCIe port interface, having the following mandatory properties: - -@@ -143,56 +146,73 @@ Examples for MT7623: - - Examples for MT2712: - -- pcie: pcie@11700000 { -+ pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; -- reg = <0 0x11700000 0 0x1000>, -- <0 0x112ff000 0 0x1000>; -- reg-names = "port0", "port1"; -+ reg = <0 0x112ff000 0 0x1000>; -+ reg-names = "port1"; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, -- <&pericfg CLK_PERI_PCIE0>, -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; -- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ clock-names = "sys_ck1", "ahb_ck1"; -+ phys = <&u3port1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -- reg = <0x0000 0 0 0 0>; -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; -+ }; - -- pcie1: pcie@1,0 { -- reg = <0x0800 0 0 0 0>; -+ pcie0: pcie@11700000 { -+ compatible = "mediatek,mt2712-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11700000 0 0x1000>; -+ reg-names = "port0"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -+ <&pericfg CLK_PERI_PCIE0>; -+ clock-names = "sys_ck0", "ahb_ck0"; -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ status = "disabled"; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; -@@ -202,39 +222,31 @@ Examples for MT2712: - - Examples for MT7622: - -- pcie: pcie@1a140000 { -+ pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; -- reg = <0 0x1a140000 0 0x1000>, -- <0 0x1a143000 0 0x1000>, -- <0 0x1a145000 0 0x1000>; -- reg-names = "subsys", "port0", "port1"; -+ reg = <0 0x1a143000 0 0x1000>; -+ reg-names = "port0"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, -- <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, -- <&pciesys CLK_PCIE_P1_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, -- <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, -- <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, -- <&pciesys CLK_PCIE_P1_OBFF_EN>, -- <&pciesys CLK_PCIE_P0_PIPE_EN>, -- <&pciesys CLK_PCIE_P1_PIPE_EN>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", -- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", -- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; -- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ <&pciesys CLK_PCIE_P0_PIPE_EN>; -+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", -+ "axi_ck0", "obff_ck0", "pipe_ck0"; -+ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -+ slot0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; -@@ -251,8 +263,34 @@ Examples for MT7622: - #interrupt-cells = <1>; - }; - }; -+ }; -+ -+ pcie1: pcie@1a145000 { -+ compatible = "mediatek,mt7622-pcie"; -+ device_type = "pci"; -+ reg = <0 0x1a145000 0 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, -+ /* designer has connect RC1 with p0_ahb clock */ -+ <&pciesys CLK_PCIE_P0_AHB_EN>, -+ <&pciesys CLK_PCIE_P1_AUX_EN>, -+ <&pciesys CLK_PCIE_P1_AXI_EN>, -+ <&pciesys CLK_PCIE_P1_OBFF_EN>, -+ <&pciesys CLK_PCIE_P1_PIPE_EN>; -+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", -+ "axi_ck1", "obff_ck1", "pipe_ck1"; -+ -+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; diff --git a/target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch b/target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch deleted file mode 100644 index fea9486d3..000000000 --- a/target/linux/mediatek/patches-5.10/601-PCI-mediatek-Use-regmap-to-get-shared-pcie-cfg-base.patch +++ /dev/null @@ -1,217 +0,0 @@ -From patchwork Thu May 28 06:16:46 2020 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Chuanjia Liu -X-Patchwork-Id: 11574781 -Return-Path: - -Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org - [172.30.200.123]) - by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A99B60D - for ; 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- void __iomem *base; -+ struct regmap *cfg; - struct clk *free_ck; - - struct list_head ports; -@@ -650,7 +654,7 @@ static int mtk_pcie_setup_irq(struct mtk - return err; - } - -- port->irq = platform_get_irq(pdev, port->slot); -+ port->irq = platform_get_irq_byname(pdev, "pcie_irq"); - if (port->irq < 0) - return port->irq; - -@@ -676,12 +680,11 @@ static int mtk_pcie_startup_port_v2(stru - if (!mem) - return -EINVAL; - -- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ -- if (pcie->base) { -- val = readl(pcie->base + PCIE_SYS_CFG_V2); -- val |= PCIE_CSR_LTSSM_EN(port->slot) | -- PCIE_CSR_ASPM_L1_EN(port->slot); -- writel(val, pcie->base + PCIE_SYS_CFG_V2); -+ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */ -+ if (pcie->cfg) { -+ val = PCIE_CSR_LTSSM_EN(port->slot) | -+ PCIE_CSR_ASPM_L1_EN(port->slot); -+ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); - } - - /* Assert all reset signals */ -@@ -985,6 +988,7 @@ static int mtk_pcie_subsys_powerup(struc - struct device *dev = pcie->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *regs; -+ struct device_node *cfg_node; - int err; - - /* get shared registers, which are optional */ -@@ -997,6 +1001,13 @@ static int mtk_pcie_subsys_powerup(struc - } - } - -+ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0); -+ if (cfg_node) { -+ pcie->cfg = syscon_node_to_regmap(cfg_node); -+ if (IS_ERR(pcie->cfg)) -+ return PTR_ERR(pcie->cfg); -+ } -+ - pcie->free_ck = devm_clk_get(dev, "free_ck"); - if (IS_ERR(pcie->free_ck)) { - if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) diff --git a/target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch b/target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch deleted file mode 100644 index 197be4bf7..000000000 --- a/target/linux/mediatek/patches-5.10/602-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch +++ /dev/null @@ -1,417 +0,0 @@ -From patchwork Thu May 28 06:16:47 2020 -Content-Type: text/plain; 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- }; - -- pcie: pcie@11700000 { -+ pcie1: pcie@112ff000 { - compatible = "mediatek,mt2712-pcie"; - device_type = "pci"; -- reg = <0 0x11700000 0 0x1000>, -- <0 0x112ff000 0 0x1000>; -- reg-names = "port0", "port1"; -+ reg = <0 0x112ff000 0 0x1000>; -+ reg-names = "port1"; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, -- <&pericfg CLK_PERI_PCIE0>, -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, - <&pericfg CLK_PERI_PCIE1>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; -- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; -- phy-names = "pcie-phy0", "pcie-phy1"; -+ clock-names = "sys_ck1", "ahb_ck1"; -+ phys = <&u3port1 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy1"; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; -+ status = "disabled"; - -- pcie0: pcie@0,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0000 0 0 0 0>; -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc0 0>, -- <0 0 0 2 &pcie_intc0 1>, -- <0 0 0 3 &pcie_intc0 2>, -- <0 0 0 4 &pcie_intc0 3>; -- pcie_intc0: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc1 0>, -+ <0 0 0 2 &pcie_intc1 1>, -+ <0 0 0 3 &pcie_intc1 2>, -+ <0 0 0 4 &pcie_intc1 3>; -+ pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; -+ }; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -- status = "disabled"; -- reg = <0x0800 0 0 0 0>; -+ pcie0: pcie@11700000 { -+ compatible = "mediatek,mt2712-pcie"; -+ device_type = "pci"; -+ reg = <0 0x11700000 0 0x1000>; -+ reg-names = "port0"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, -+ <&pericfg CLK_PERI_PCIE0>; -+ clock-names = "sys_ck0", "ahb_ck0"; -+ phys = <&u3port0 PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy0"; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ status = "disabled"; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; - interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0 0 0 1 &pcie_intc1 0>, -- <0 0 0 2 &pcie_intc1 1>, -- <0 0 0 3 &pcie_intc1 2>, -- <0 0 0 4 &pcie_intc1 3>; -- pcie_intc1: interrupt-controller { -+ interrupt-map = <0 0 0 1 &pcie_intc0 0>, -+ <0 0 0 2 &pcie_intc0 1>, -+ <0 0 0 3 &pcie_intc0 2>, -+ <0 0 0 4 &pcie_intc0 3>; -+ pcie_intc0: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -292,18 +292,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -802,45 +802,41 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7622-pciecfg", "syscon"; -+ reg = <0 0x1a140000 0 0x1000>; -+ }; -+ -+ pcie0: pcie@1a143000 { - compatible = "mediatek,mt7622-pcie"; - device_type = "pci"; -- reg = <0 0x1a140000 0 0x1000>, -- <0 0x1a143000 0 0x1000>, -- <0 0x1a145000 0 0x1000>; -- reg-names = "subsys", "port0", "port1"; -+ reg = <0 0x1a143000 0 0x1000>; -+ reg-names = "port0"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, -- <&pciesys CLK_PCIE_P1_MAC_EN>, -- <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P0_AUX_EN>, -- <&pciesys CLK_PCIE_P1_AUX_EN>, - <&pciesys CLK_PCIE_P0_AXI_EN>, -- <&pciesys CLK_PCIE_P1_AXI_EN>, - <&pciesys CLK_PCIE_P0_OBFF_EN>, -- <&pciesys CLK_PCIE_P1_OBFF_EN>, -- <&pciesys CLK_PCIE_P0_PIPE_EN>, -- <&pciesys CLK_PCIE_P1_PIPE_EN>; -- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1", -- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1", -- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1"; -+ <&pciesys CLK_PCIE_P0_PIPE_EN>; -+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", -+ "axi_ck0", "obff_ck0", "pipe_ck0"; -+ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; -- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; -+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; - -- pcie0: pcie@0,0 { -+ slot0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- status = "disabled"; -- - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, -@@ -852,15 +848,39 @@ - #interrupt-cells = <1>; - }; - }; -+ }; - -- pcie1: pcie@1,0 { -+ pcie1: pcie@1a145000 { -+ compatible = "mediatek,mt7622-pcie"; -+ device_type = "pci"; -+ reg = <0 0x1a145000 0 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; -+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, -+ /* designer has connect RC1 with p0_ahb clock */ -+ <&pciesys CLK_PCIE_P0_AHB_EN>, -+ <&pciesys CLK_PCIE_P1_AUX_EN>, -+ <&pciesys CLK_PCIE_P1_AXI_EN>, -+ <&pciesys CLK_PCIE_P1_OBFF_EN>, -+ <&pciesys CLK_PCIE_P1_PIPE_EN>; -+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", -+ "axi_ck1", "obff_ck1", "pipe_ck1"; -+ -+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; -+ status = "disabled"; -+ -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- status = "disabled"; -- - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -232,18 +232,16 @@ - }; - }; - --&pcie { -+&pcie0 { - pinctrl-names = "default"; -- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; -+ pinctrl-0 = <&pcie0_pins>; - status = "okay"; -+}; - -- pcie@0,0 { -- status = "okay"; -- }; -- -- pcie@1,0 { -- status = "okay"; -- }; -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; - }; - - &pio { diff --git a/target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch deleted file mode 100644 index ce72ad659..000000000 --- a/target/linux/mediatek/patches-5.10/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch +++ /dev/null @@ -1,203 +0,0 @@ -From patchwork Thu May 28 06:16:48 2020 -Content-Type: text/plain; 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- }; - --&pcie { -+&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; -+ status = "okay"; - }; - - &pciephy1 { ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -376,16 +376,21 @@ - #reset-cells = <1>; - }; - -- pcie: pcie@1a140000 { -+ pciecfg: pciecfg@1a140000 { -+ compatible = "mediatek,mt7629-pciecfg", "syscon"; -+ reg = <0x1a140000 0x1000>; -+ }; -+ -+ pcie1: pcie@1a145000 { - compatible = "mediatek,mt7629-pcie"; - device_type = "pci"; -- reg = <0x1a140000 0x1000>, -- <0x1a145000 0x1000>; -- reg-names = "subsys","port1"; -+ reg = <0x1a145000 0x1000>; -+ reg-names = "port1"; -+ mediatek,pcie-cfg = <&pciecfg>; - #address-cells = <3>; - #size-cells = <2>; -- interrupts = , -- ; -+ interrupts = ; -+ interrupt-names = "pcie_irq"; - clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, - <&pciesys CLK_PCIE_P0_AHB_EN>, - <&pciesys CLK_PCIE_P1_AUX_EN>, -@@ -406,21 +411,19 @@ - power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; -+ status = "disabled"; - -- pcie1: pcie@1,0 { -- device_type = "pci"; -+ slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges; -- num-lanes = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; -- - pcie_intc1: interrupt-controller { - interrupt-controller; - #address-cells = <0>; diff --git a/target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index 031582a78..000000000 --- a/target/linux/mediatek/patches-5.10/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,24 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -615,10 +615,10 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - virq = irq_find_mapping(port->irq_domain, - bit - INTX_SHIFT); - generic_handle_irq(virq); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch b/target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch deleted file mode 100644 index be9dcfc3e..000000000 --- a/target/linux/mediatek/patches-5.10/701-v5.17-net-ethernet-mtk_eth_soc-fix-return-values-and-refac.patch +++ /dev/null @@ -1,128 +0,0 @@ -From eda80b249df7bbc7b3dd13907343a3e59bfc57fd Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 4 Jan 2022 12:06:22 +0000 -Subject: [PATCH 1/3] net: ethernet: mtk_eth_soc: fix return values and - refactor MDIO ops - -Instead of returning -1 (-EPERM) when MDIO bus is stuck busy -while writing or 0xffff if it happens while reading, return the -appropriate -ETIMEDOUT. Also fix return type to int instead of u32. -Refactor functions to use bitfield helpers instead of having various -masking and shifting constants in the code, which also results in the -register definitions in the header file being more obviously related -to what is stated in the MediaTek's Reference Manual. - -Fixes: 656e705243fd0 ("net-next: mediatek: add support for MT7623 ethernet") -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 53 ++++++++++++--------- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 16 +++++-- - 2 files changed, 41 insertions(+), 28 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -94,46 +94,53 @@ static int mtk_mdio_busy_wait(struct mtk - } - - dev_err(eth->dev, "mdio: MDIO timeout\n"); -- return -1; -+ return -ETIMEDOUT; - } - --static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, -- u32 phy_register, u32 write_data) -+static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, -+ u32 write_data) - { -- if (mtk_mdio_busy_wait(eth)) -- return -1; -+ int ret; - -- write_data &= 0xffff; -- -- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | -- (phy_register << PHY_IAC_REG_SHIFT) | -- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), - MTK_PHY_IAC); - -- if (mtk_mdio_busy_wait(eth)) -- return -1; -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; - - return 0; - } - --static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) -+static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) - { -- u32 d; -- -- if (mtk_mdio_busy_wait(eth)) -- return 0xffff; -+ int ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | -- (phy_reg << PHY_IAC_REG_SHIFT) | -- (phy_addr << PHY_IAC_ADDR_SHIFT), -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_C22_READ | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr), - MTK_PHY_IAC); - -- if (mtk_mdio_busy_wait(eth)) -- return 0xffff; -- -- d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; - -- return d; -+ return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; - } - - static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -344,11 +344,17 @@ - /* PHY Indirect Access Control registers */ - #define MTK_PHY_IAC 0x10004 - #define PHY_IAC_ACCESS BIT(31) --#define PHY_IAC_READ BIT(19) --#define PHY_IAC_WRITE BIT(18) --#define PHY_IAC_START BIT(16) --#define PHY_IAC_ADDR_SHIFT 20 --#define PHY_IAC_REG_SHIFT 25 -+#define PHY_IAC_REG_MASK GENMASK(29, 25) -+#define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x)) -+#define PHY_IAC_ADDR_MASK GENMASK(24, 20) -+#define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) -+#define PHY_IAC_CMD_MASK GENMASK(19, 18) -+#define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) -+#define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) -+#define PHY_IAC_START_MASK GENMASK(17, 16) -+#define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) -+#define PHY_IAC_DATA_MASK GENMASK(15, 0) -+#define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) - #define PHY_IAC_TIMEOUT HZ - - #define MTK_MAC_MISC 0x1000c diff --git a/target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch b/target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch deleted file mode 100644 index ef2e22571..000000000 --- a/target/linux/mediatek/patches-5.10/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch +++ /dev/null @@ -1,53 +0,0 @@ -From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001 -From: "Russell King (Oracle)" -Date: Tue, 4 Jan 2022 12:07:00 +0000 -Subject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and - devad fields - -Add a couple of helpers and definitions to extract the clause 45 regad -and devad fields from the regnum passed into MDIO drivers. - -Tested-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: Russell King (Oracle) -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - include/linux/mdio.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/include/linux/mdio.h -+++ b/include/linux/mdio.h -@@ -7,6 +7,7 @@ - #define __LINUX_MDIO_H__ - - #include -+#include - #include - - /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit -@@ -14,6 +15,7 @@ - */ - #define MII_ADDR_C45 (1<<30) - #define MII_DEVADDR_C45_SHIFT 16 -+#define MII_DEVADDR_C45_MASK GENMASK(20, 16) - #define MII_REGADDR_C45_MASK GENMASK(15, 0) - - struct gpio_desc; -@@ -342,6 +344,16 @@ static inline u32 mdiobus_c45_addr(int d - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; - } - -+static inline u16 mdiobus_c45_regad(u32 regnum) -+{ -+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum); -+} -+ -+static inline u16 mdiobus_c45_devad(u32 regnum) -+{ -+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); -+} -+ - static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad, - u16 regnum) - { diff --git a/target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch b/target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch deleted file mode 100644 index 289398ce3..000000000 --- a/target/linux/mediatek/patches-5.10/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch +++ /dev/null @@ -1,128 +0,0 @@ -From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 4 Jan 2022 12:07:46 +0000 -Subject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO - access - -Implement read and write access to IEEE 802.3 Clause 45 Ethernet -phy registers while making use of new mdiobus_c45_regad and -mdiobus_c45_devad helpers. - -Tested on the Ubiquiti UniFi 6 LR access point featuring -MediaTek MT7622BV WiSoC with Aquantia AQR112C. - -Signed-off-by: Daniel Golle -Signed-off-by: David S. Miller ---- - drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 + - 2 files changed, 60 insertions(+), 13 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -106,13 +106,35 @@ static int _mtk_mdio_write(struct mtk_et - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_WRITE | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr) | -- PHY_IAC_DATA(write_data), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_WRITE | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(write_data), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -129,12 +151,33 @@ static int _mtk_mdio_read(struct mtk_eth - if (ret < 0) - return ret; - -- mtk_w32(eth, PHY_IAC_ACCESS | -- PHY_IAC_START_C22 | -- PHY_IAC_CMD_C22_READ | -- PHY_IAC_REG(phy_reg) | -- PHY_IAC_ADDR(phy_addr), -- MTK_PHY_IAC); -+ if (phy_reg & MII_ADDR_C45) { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_ADDR | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr) | -+ PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), -+ MTK_PHY_IAC); -+ -+ ret = mtk_mdio_busy_wait(eth); -+ if (ret < 0) -+ return ret; -+ -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C45 | -+ PHY_IAC_CMD_C45_READ | -+ PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } else { -+ mtk_w32(eth, PHY_IAC_ACCESS | -+ PHY_IAC_START_C22 | -+ PHY_IAC_CMD_C22_READ | -+ PHY_IAC_REG(phy_reg) | -+ PHY_IAC_ADDR(phy_addr), -+ MTK_PHY_IAC); -+ } - - ret = mtk_mdio_busy_wait(eth); - if (ret < 0) -@@ -593,6 +636,7 @@ static int mtk_mdio_init(struct mtk_eth - eth->mii_bus->name = "mdio"; - eth->mii_bus->read = mtk_mdio_read; - eth->mii_bus->write = mtk_mdio_write; -+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; - eth->mii_bus->priv = eth; - eth->mii_bus->parent = eth->dev; - ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -@@ -349,9 +349,12 @@ - #define PHY_IAC_ADDR_MASK GENMASK(24, 20) - #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x)) - #define PHY_IAC_CMD_MASK GENMASK(19, 18) -+#define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0) - #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1) - #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2) -+#define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3) - #define PHY_IAC_START_MASK GENMASK(17, 16) -+#define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0) - #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1) - #define PHY_IAC_DATA_MASK GENMASK(15, 0) - #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x)) diff --git a/target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch b/target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch deleted file mode 100644 index e9d4188a4..000000000 --- a/target/linux/mediatek/patches-5.10/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c -+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -577,6 +577,7 @@ static void mtk_validate(struct phylink_ - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { - phylink_set(mask, 1000baseT_Full); - phylink_set(mask, 1000baseX_Full); -+ phylink_set(mask, 2500baseT_Full); - phylink_set(mask, 2500baseX_Full); - } - if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { diff --git a/target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index 32fc0a9ad..000000000 --- a/target/linux/mediatek/patches-5.10/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,96 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -813,6 +813,8 @@ - reg = <0 0x1a143000 0 0x1000>; - reg-names = "port0"; - mediatek,pcie-cfg = <&pciecfg>; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; -@@ -830,6 +832,7 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; - - slot0: pcie@0,0 { - reg = <0x0000 0 0 0 0>; -@@ -856,6 +859,8 @@ - reg = <0 0x1a145000 0 0x1000>; - reg-names = "port1"; - mediatek,pcie-cfg = <&pciecfg>; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; -@@ -874,6 +879,7 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; - - slot1: pcie@1,0 { - reg = <0x0800 0 0 0 0>; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1042,6 +1048,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - for_each_available_child_of_node(node, child) { - int slot; - diff --git a/target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch b/target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd0..000000000 --- a/target/linux/mediatek/patches-5.10/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch b/target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch deleted file mode 100644 index 92264eedf..000000000 --- a/target/linux/mediatek/patches-5.10/800-ubnt-ledbar-driver.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/drivers/leds/Kconfig -+++ b/drivers/leds/Kconfig -@@ -929,6 +929,16 @@ config LEDS_ACER_A500 - This option enables support for the Power Button LED of - Acer Iconia Tab A500. - -+config LEDS_UBNT_LEDBAR -+ tristate "LED support for Ubiquiti UniFi 6 LR" -+ depends on LEDS_CLASS && I2C && OF -+ help -+ This option enables support for the Ubiquiti LEDBAR -+ LED driver. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called leds-ubnt-ledbar. -+ - comment "LED Triggers" - source "drivers/leds/trigger/Kconfig" - ---- a/drivers/leds/Makefile -+++ b/drivers/leds/Makefile -@@ -93,6 +93,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA) += leds - obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o -+obj-$(CONFIG_LEDS_UBNT_LEDBAR) += leds-ubnt-ledbar.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff --git a/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index 987513eb4..000000000 --- a/target/linux/mediatek/patches-5.10/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,65 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -308,7 +308,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dts -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dts -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index 21fb98c19..000000000 --- a/target/linux/mediatek/patches-5.10/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -632,5 +632,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; diff --git a/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch new file mode 100644 index 000000000..04df7b927 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch @@ -0,0 +1,20 @@ +From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Fri, 29 Apr 2022 10:40:56 +0800 +Subject: [PATCH] arm: mediatek: select arch timer for mt7623 + +Signed-off-by: Chuanhong Guo +--- + arch/arm/mach-mediatek/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -26,6 +26,7 @@ config MACH_MT6592 + config MACH_MT7623 + bool "MediaTek MT7623 SoCs support" + default ARCH_MEDIATEK ++ select HAVE_ARM_ARCH_TIMER + + config MACH_MT7629 + bool "MediaTek MT7629 SoCs support" diff --git a/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch new file mode 100644 index 000000000..fa2cd96f9 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch @@ -0,0 +1,10 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -558,6 +558,7 @@ + compatible = "mediatek,mt7622-nor", + "mediatek,mt8173-nor"; + reg = <0 0x11014000 0 0xe0>; ++ interrupts = ; + clocks = <&pericfg CLK_PERI_FLASH_PD>, + <&topckgen CLK_TOP_FLASH_SEL>; + clock-names = "spi", "sf"; diff --git a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch b/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch index 6ef56f858..da42c0772 100644 --- a/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch +++ b/target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch @@ -14,7 +14,7 @@ ranges; + /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@0x42ff0000 { ++ ramoops@42ff0000 { + compatible = "ramoops"; + reg = <0 0x42ff0000 0 0x10000>; + record-size = <0x1000>; diff --git a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch index 39d81bd5d..34539a5d1 100644 --- a/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch @@ -1,40 +1,49 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -259,14 +259,32 @@ +@@ -259,14 +259,42 @@ status = "disabled"; }; -&nor_flash { -+&snand { - pinctrl-names = "default"; +- pinctrl-names = "default"; - pinctrl-0 = <&spi_nor_pins>; - status = "disabled"; -+ pinctrl-0 = <&serial_nand_pins>; -+ mediatek,quad-spi; ++&bch { + status = "okay"; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; ++}; -- flash@0 { ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; + flash@0 { - compatible = "jedec,spi-nor"; -- reg = <0>; -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; ++ compatible = "spi-nand"; + reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ read-only; ++ }; ++ ++ partition@80000 { ++ label = "fip"; ++ reg = <0x80000 0x200000>; ++ read-only; ++ }; ++ ++ partition@280000 { ++ label = "ubi"; ++ reg = <0x280000 0x7d80000>; ++ }; + }; }; }; diff --git a/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch new file mode 100644 index 000000000..7fb62e740 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch @@ -0,0 +1,214 @@ +From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:38 +0100 +Subject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware + engines + +Add the necessary helpers to register/unregister hardware ECC engines +that will be called from ECC engine drivers. + +Also add helpers to get the right engine from the user +perspective. Keep a reference of the in use ECC engine in order to +prevent modules to be unloaded. Put the reference when the engine gets +retired. + +A static list of hardware (only) ECC engines is setup to keep track of +the registered engines. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com +(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152) +--- + drivers/mtd/nand/core.c | 10 +++-- + drivers/mtd/nand/ecc.c | 88 ++++++++++++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 28 +++++++++++++ + 3 files changed, 123 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/nand/core.c ++++ b/drivers/mtd/nand/core.c +@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct + nand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand); + break; + case NAND_ECC_ENGINE_TYPE_ON_HOST: +- pr_err("On-host hardware ECC engines not supported yet\n"); ++ nand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand); ++ if (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; + break; + default: + pr_err("Missing ECC engine type\n"); +@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct + { + switch (nand->ecc.ctx.conf.engine_type) { + case NAND_ECC_ENGINE_TYPE_ON_HOST: +- pr_err("On-host hardware ECC engines not supported yet\n"); ++ nand_ecc_put_on_host_hw_engine(nand); + break; + case NAND_ECC_ENGINE_TYPE_NONE: + case NAND_ECC_ENGINE_TYPE_SOFT: +@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_ + /* Look for the ECC engine to use */ + ret = nanddev_get_ecc_engine(nand); + if (ret) { +- pr_err("No ECC engine found\n"); ++ if (ret != -EPROBE_DEFER) ++ pr_err("No ECC engine found\n"); ++ + return ret; + } + +--- a/drivers/mtd/nand/ecc.c ++++ b/drivers/mtd/nand/ecc.c +@@ -96,6 +96,12 @@ + #include + #include + #include ++#include ++#include ++#include ++ ++static LIST_HEAD(on_host_hw_engines); ++static DEFINE_MUTEX(on_host_hw_engines_mutex); + + /** + * nand_ecc_init_ctx - Init the ECC engine context +@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_ + } + EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine); + ++int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine) ++{ ++ struct nand_ecc_engine *item; ++ ++ if (!engine) ++ return -EINVAL; ++ ++ /* Prevent multiple registrations of one engine */ ++ list_for_each_entry(item, &on_host_hw_engines, node) ++ if (item == engine) ++ return 0; ++ ++ mutex_lock(&on_host_hw_engines_mutex); ++ list_add_tail(&engine->node, &on_host_hw_engines); ++ mutex_unlock(&on_host_hw_engines_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine); ++ ++int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine) ++{ ++ if (!engine) ++ return -EINVAL; ++ ++ mutex_lock(&on_host_hw_engines_mutex); ++ list_del(&engine->node); ++ mutex_unlock(&on_host_hw_engines_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine); ++ ++static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev) ++{ ++ struct nand_ecc_engine *item; ++ ++ list_for_each_entry(item, &on_host_hw_engines, node) ++ if (item->dev == dev) ++ return item; ++ ++ return NULL; ++} ++ ++struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *engine = NULL; ++ struct device *dev = &nand->mtd.dev; ++ struct platform_device *pdev; ++ struct device_node *np; ++ ++ if (list_empty(&on_host_hw_engines)) ++ return NULL; ++ ++ /* Check for an explicit nand-ecc-engine property */ ++ np = of_parse_phandle(dev->of_node, "nand-ecc-engine", 0); ++ if (np) { ++ pdev = of_find_device_by_node(np); ++ if (!pdev) ++ return ERR_PTR(-EPROBE_DEFER); ++ ++ engine = nand_ecc_match_on_host_hw_engine(&pdev->dev); ++ platform_device_put(pdev); ++ of_node_put(np); ++ ++ if (!engine) ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ if (engine) ++ get_device(engine->dev); ++ ++ return engine; ++} ++EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine); ++ ++void nand_ecc_put_on_host_hw_engine(struct nand_device *nand) ++{ ++ put_device(nand->ecc.engine->dev); ++} ++EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); ++ + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Miquel Raynal "); + MODULE_DESCRIPTION("Generic ECC engine"); +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops { + }; + + /** ++ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated ++ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value ++ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly ++ * correction, does not need to copy ++ * data around ++ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the ++ * data into its own area before use ++ */ ++enum nand_ecc_engine_integration { ++ NAND_ECC_ENGINE_INTEGRATION_INVALID, ++ NAND_ECC_ENGINE_INTEGRATION_PIPELINED, ++ NAND_ECC_ENGINE_INTEGRATION_EXTERNAL, ++}; ++ ++/** + * struct nand_ecc_engine - ECC engine abstraction for NAND devices ++ * @dev: Host device ++ * @node: Private field for registration time + * @ops: ECC engine operations ++ * @integration: How the engine is integrated with the host ++ * (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines) ++ * @priv: Private data + */ + struct nand_ecc_engine { ++ struct device *dev; ++ struct list_head node; + struct nand_ecc_engine_ops *ops; ++ enum nand_ecc_engine_integration integration; ++ void *priv; + }; + + void of_get_nand_ecc_user_config(struct nand_device *nand); +@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_ + int nand_ecc_finish_io_req(struct nand_device *nand, + struct nand_page_io_req *req); + bool nand_ecc_is_strong_enough(struct nand_device *nand); ++int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine); ++int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine); + struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); ++struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); ++void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); + + #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) + struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch new file mode 100644 index 000000000..61a39ee0e --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch @@ -0,0 +1,31 @@ +From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:39 +0100 +Subject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context + +Introduce nand_to_ecc_ctx() which will allow to easily jump to the +private pointer of an ECC context given a NAND device. This is very +handy, from the prepare or finish ECC hook, to get the internal context +out of the NAND device object. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com +(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4) +--- + include/linux/mtd/nand.h | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device * + int nanddev_ecc_engine_init(struct nand_device *nand); + void nanddev_ecc_engine_cleanup(struct nand_device *nand); + ++static inline void *nand_to_ecc_ctx(struct nand_device *nand) ++{ ++ return nand->ecc.ctx.priv; ++} ++ + /* BBT related functions */ + enum nand_bbt_block_status { + NAND_BBT_BLOCK_STATUS_UNKNOWN, diff --git a/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch new file mode 100644 index 000000000..29b62880a --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch @@ -0,0 +1,73 @@ +From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 16 Dec 2021 12:16:41 +0100 +Subject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a + pilelined engine device + +In a pipelined engine situation, we might either have the host which +internally has support for error correction, or have it using an +external hardware block for this purpose. In the former case, the host +is also the ECC engine. In the latter case, it is not. In order to get +the right pointers on the right devices (for example: in order to devm_* +allocate variables), let's introduce this helper which can safely be +called by pipelined ECC engines in order to retrieve the right device +structure. + +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com +(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309) +--- + drivers/mtd/nand/ecc.c | 31 +++++++++++++++++++++++++++++++ + include/linux/mtd/nand.h | 1 + + 2 files changed, 32 insertions(+) + +--- a/drivers/mtd/nand/ecc.c ++++ b/drivers/mtd/nand/ecc.c +@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru + } + EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine); + ++/* ++ * In the case of a pipelined engine, the device registering the ECC ++ * engine is not necessarily the ECC engine itself but may be a host controller. ++ * It is then useful to provide a helper to retrieve the right device object ++ * which actually represents the ECC engine. ++ */ ++struct device *nand_ecc_get_engine_dev(struct device *host) ++{ ++ struct platform_device *ecc_pdev; ++ struct device_node *np; ++ ++ /* ++ * If the device node contains this property, it means we need to follow ++ * it in order to get the right ECC engine device we are looking for. ++ */ ++ np = of_parse_phandle(host->of_node, "nand-ecc-engine", 0); ++ if (!np) ++ return host; ++ ++ ecc_pdev = of_find_device_by_node(np); ++ if (!ecc_pdev) { ++ of_node_put(np); ++ return NULL; ++ } ++ ++ platform_device_put(ecc_pdev); ++ of_node_put(np); ++ ++ return &ecc_pdev->dev; ++} ++ + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Miquel Raynal "); + MODULE_DESCRIPTION("Generic ECC engine"); +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_ + struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand); + struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand); + void nand_ecc_put_on_host_hw_engine(struct nand_device *nand); ++struct device *nand_ecc_get_engine_dev(struct device *host); + + #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING) + struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void); diff --git a/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch new file mode 100644 index 000000000..1e7f572dd --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch @@ -0,0 +1,71 @@ +From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:17:56 +0100 +Subject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure + +Create a spi_controller_mem_caps structure and put it within the +spi_controller structure close to the spi_controller_mem_ops +strucure. So far the only field in this structure is the support for dtr +operations, but soon we will add another parameter. + +Also create a helper to parse the capabilities and check if the +requested capability has been set or not. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Reviewed-by: Mark Brown +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com +(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20) +--- + include/linux/spi/spi-mem.h | 11 +++++++++++ + include/linux/spi/spi.h | 3 +++ + 2 files changed, 14 insertions(+) + +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -286,6 +286,17 @@ struct spi_controller_mem_ops { + }; + + /** ++ * struct spi_controller_mem_caps - SPI memory controller capabilities ++ * @dtr: Supports DTR operations ++ */ ++struct spi_controller_mem_caps { ++ bool dtr; ++}; ++ ++#define spi_mem_controller_is_capable(ctlr, cap) \ ++ ((ctlr)->mem_caps && (ctlr)->mem_caps->cap) ++ ++/** + * struct spi_mem_driver - SPI memory driver + * @spidrv: inherit from a SPI driver + * @probe: probe a SPI memory. Usually where detection/initialization takes +--- a/include/linux/spi/spi.h ++++ b/include/linux/spi/spi.h +@@ -23,6 +23,7 @@ struct software_node; + struct spi_controller; + struct spi_transfer; + struct spi_controller_mem_ops; ++struct spi_controller_mem_caps; + + /* + * INTERFACES between SPI master-side drivers and SPI slave protocol handlers, +@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill + * @mem_ops: optimized/dedicated operations for interactions with SPI memory. + * This field is optional and should only be implemented if the + * controller has native support for memory like operations. ++ * @mem_caps: controller capabilities for the handling of memory operations. + * @unprepare_message: undo any work done by prepare_message(). + * @slave_abort: abort the ongoing transfer request on an SPI slave controller + * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per +@@ -643,6 +645,7 @@ struct spi_controller { + + /* Optimized handlers for SPI memory-like operations. */ + const struct spi_controller_mem_ops *mem_ops; ++ const struct spi_controller_mem_caps *mem_caps; + + /* gpio chip select */ + int *cs_gpios; diff --git a/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch new file mode 100644 index 000000000..9f01fdb83 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch @@ -0,0 +1,51 @@ +From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:17:57 +0100 +Subject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities + +Controllers can now provide a spi-mem capabilities structure. Let's make +use of it in spi_mem_controller_default_supports_op(). As we want to +check for DTR operations as well as normal operations in a single +helper, let's pull the necessary checks from spi_mem_dtr_supports_op() +for now. + +However, because no controller provide these extra capabilities, this +change has no effect so far. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com +(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37) +--- + drivers/spi/spi-mem.c | 17 +++++++++++++---- + 1 file changed, 13 insertions(+), 4 deletions(-) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) +- return false; ++ struct spi_controller *ctlr = mem->spi->controller; ++ bool op_is_dtr = ++ op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr; + +- if (op->cmd.nbytes != 1) +- return false; ++ if (op_is_dtr) { ++ if (!spi_mem_controller_is_capable(ctlr, dtr)) ++ return false; ++ ++ if (op->cmd.nbytes != 2) ++ return false; ++ } else { ++ if (op->cmd.nbytes != 1) ++ return false; ++ } + + return spi_mem_check_buswidth(mem, op); + } diff --git a/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch new file mode 100644 index 000000000..c313a455b --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch @@ -0,0 +1,111 @@ +From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:00 +0100 +Subject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper + +Now that spi_mem_default_supports_op() has access to the static +controller capabilities (relating to memory operations), and now that +these capabilities have been filled by the relevant controllers, there +is no need for a specific helper checking only DTR operations, so let's +just kill spi_mem_dtr_supports_op() and simply use +spi_mem_default_supports_op() instead. + +Signed-off-by: Miquel Raynal +Reviewed-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com +(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20) +--- + drivers/spi/spi-cadence-quadspi.c | 5 +---- + drivers/spi/spi-mem.c | 10 ---------- + drivers/spi/spi-mxic.c | 10 +--------- + include/linux/spi/spi-mem.h | 11 ----------- + 4 files changed, 2 insertions(+), 34 deletions(-) + +--- a/drivers/spi/spi-cadence-quadspi.c ++++ b/drivers/spi/spi-cadence-quadspi.c +@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct + return false; + } + +- if (all_true) +- return spi_mem_dtr_supports_op(mem, op); +- else +- return spi_mem_default_supports_op(mem, op); ++ return spi_mem_default_supports_op(mem, op); + } + + static int cqspi_of_get_flash_pdata(struct platform_device *pdev, +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc + return true; + } + +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op) +-{ +- if (op->cmd.nbytes != 2) +- return false; +- +- return spi_mem_check_buswidth(mem, op); +-} +-EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); +- + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +--- a/drivers/spi/spi-mxic.c ++++ b/drivers/spi/spi-mxic.c +@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi + static bool mxic_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { +- bool all_false; +- + if (op->data.buswidth > 8 || op->addr.buswidth > 8 || + op->dummy.buswidth > 8 || op->cmd.buswidth > 8) + return false; +@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str + if (op->addr.nbytes > 7) + return false; + +- all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && +- !op->data.dtr; +- +- if (all_false) +- return spi_mem_default_supports_op(mem, op); +- else +- return spi_mem_dtr_supports_op(mem, op); ++ return spi_mem_default_supports_op(mem, op); + } + + static int mxic_spi_mem_exec_op(struct spi_mem *mem, +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat + + bool spi_mem_default_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op); +- +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op); +- + #else + static inline int + spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr, +@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct + { + return false; + } +- +-static inline +-bool spi_mem_dtr_supports_op(struct spi_mem *mem, +- const struct spi_mem_op *op) +-{ +- return false; +-} + #endif /* CONFIG_SPI_MEM */ + + int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op); diff --git a/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch new file mode 100644 index 000000000..6d7e47650 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch @@ -0,0 +1,72 @@ +From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:01 +0100 +Subject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op + structure + +Soon the SPI-NAND core will need a way to request a SPI controller to +enable ECC support for a given operation. This is because of the +pipelined integration of certain ECC engines, which are directly managed +by the SPI controller itself. + +Introduce a spi_mem_op additional field for this purpose: ecc. + +So far this field is left unset and checked to be false by all +the SPI controller drivers in their ->supports_op() hook, as they all +call spi_mem_default_supports_op(). + +Signed-off-by: Miquel Raynal +Acked-by: Pratyush Yadav +Reviewed-by: Boris Brezillon +Reviewed-by: Tudor Ambarus +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com +(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7) +--- + drivers/spi/spi-mem.c | 5 +++++ + include/linux/spi/spi-mem.h | 4 ++++ + 2 files changed, 9 insertions(+) + +--- a/drivers/spi/spi-mem.c ++++ b/drivers/spi/spi-mem.c +@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct + return false; + } + ++ if (op->data.ecc) { ++ if (!spi_mem_controller_is_capable(ctlr, ecc)) ++ return false; ++ } ++ + return spi_mem_check_buswidth(mem, op); + } + EXPORT_SYMBOL_GPL(spi_mem_default_supports_op); +--- a/include/linux/spi/spi-mem.h ++++ b/include/linux/spi/spi-mem.h +@@ -89,6 +89,7 @@ enum spi_mem_data_dir { + * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not + * @data.buswidth: number of IO lanes used to send/receive the data + * @data.dtr: whether the data should be sent in DTR mode or not ++ * @data.ecc: whether error correction is required or not + * @data.dir: direction of the transfer + * @data.nbytes: number of data bytes to send/receive. Can be zero if the + * operation does not involve transferring data +@@ -119,6 +120,7 @@ struct spi_mem_op { + struct { + u8 buswidth; + u8 dtr : 1; ++ u8 ecc : 1; + enum spi_mem_data_dir dir; + unsigned int nbytes; + union { +@@ -288,9 +290,11 @@ struct spi_controller_mem_ops { + /** + * struct spi_controller_mem_caps - SPI memory controller capabilities + * @dtr: Supports DTR operations ++ * @ecc: Supports operations with error correction + */ + struct spi_controller_mem_caps { + bool dtr; ++ bool ecc; + }; + + #define spi_mem_controller_is_capable(ctlr, cap) \ diff --git a/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch new file mode 100644 index 000000000..0f69b30e9 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch @@ -0,0 +1,50 @@ +From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:02 +0100 +Subject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation + +As we will soon tweak the dirmap creation to act a little bit +differently depending on the picked ECC engine, we need to initialize +dirmaps after ECC engines. This should not have any effect as dirmaps +are not yet used at this point. + +Signed-off-by: Miquel Raynal +Reviewed-by: Boris Brezillon +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com +(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949) +--- + drivers/mtd/nand/spi/core.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -1211,14 +1211,6 @@ static int spinand_init(struct spinand_d + if (ret) + goto err_free_bufs; + +- ret = spinand_create_dirmaps(spinand); +- if (ret) { +- dev_err(dev, +- "Failed to create direct mappings for read/write operations (err = %d)\n", +- ret); +- goto err_manuf_cleanup; +- } +- + ret = nanddev_init(nand, &spinand_ops, THIS_MODULE); + if (ret) + goto err_manuf_cleanup; +@@ -1253,6 +1245,14 @@ static int spinand_init(struct spinand_d + mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; + mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; + ++ ret = spinand_create_dirmaps(spinand); ++ if (ret) { ++ dev_err(dev, ++ "Failed to create direct mappings for read/write operations (err = %d)\n", ++ ret); ++ goto err_cleanup_ecc_engine; ++ } ++ + return 0; + + err_cleanup_ecc_engine: diff --git a/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch new file mode 100644 index 000000000..1188872bd --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch @@ -0,0 +1,98 @@ +From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001 +From: Miquel Raynal +Date: Thu, 27 Jan 2022 10:18:03 +0100 +Subject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC + operations + +In order for pipelined ECC engines to be able to enable/disable the ECC +engine only when needed and avoid races when future parallel-operations +will be supported, we need to provide the information about the use of +the ECC engine in the direct mapping hooks. As direct mapping +configurations are meant to be static, it is best to create two new +mappings: one for regular 'raw' accesses and one for accesses involving +correction. It is up to the driver to use or not the new ECC enable +boolean contained in the spi-mem operation. + +As dirmaps are not free (they consume a few pages of MMIO address space) +and because these extra entries are only meant to be used by pipelined +engines, let's limit their use to this specific type of engine and save +a bit of memory with all the other setups. + +Signed-off-by: Miquel Raynal +Reviewed-by: Boris Brezillon +Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com +(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2) +--- + drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++-- + include/linux/mtd/spinand.h | 2 ++ + 2 files changed, 35 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st + } + } + +- rdesc = spinand->dirmaps[req->pos.plane].rdesc; ++ if (req->mode == MTD_OPS_RAW) ++ rdesc = spinand->dirmaps[req->pos.plane].rdesc; ++ else ++ rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc; + + while (nbytes) { + ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf); +@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str + req->ooblen); + } + +- wdesc = spinand->dirmaps[req->pos.plane].wdesc; ++ if (req->mode == MTD_OPS_RAW) ++ wdesc = spinand->dirmaps[req->pos.plane].wdesc; ++ else ++ wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc; + + while (nbytes) { + ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf); +@@ -865,6 +871,31 @@ static int spinand_create_dirmap(struct + + spinand->dirmaps[plane].rdesc = desc; + ++ if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) { ++ spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc; ++ spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc; ++ ++ return 0; ++ } ++ ++ info.op_tmpl = *spinand->op_templates.update_cache; ++ info.op_tmpl.data.ecc = true; ++ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, ++ spinand->spimem, &info); ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ ++ spinand->dirmaps[plane].wdesc_ecc = desc; ++ ++ info.op_tmpl = *spinand->op_templates.read_cache; ++ info.op_tmpl.data.ecc = true; ++ desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev, ++ spinand->spimem, &info); ++ if (IS_ERR(desc)) ++ return PTR_ERR(desc); ++ ++ spinand->dirmaps[plane].rdesc_ecc = desc; ++ + return 0; + } + +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -392,6 +392,8 @@ struct spinand_info { + struct spinand_dirmap { + struct spi_mem_dirmap_desc *wdesc; + struct spi_mem_dirmap_desc *rdesc; ++ struct spi_mem_dirmap_desc *wdesc_ecc; ++ struct spi_mem_dirmap_desc *rdesc_ecc; + }; + + /** diff --git a/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch b/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch new file mode 100644 index 000000000..fd9098eae --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-11-v5.19-mtd-nand-make-mtk_ecc.c-a-separated-module.patch @@ -0,0 +1,1383 @@ +From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Tue, 22 Mar 2022 18:44:21 +0800 +Subject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module + +this code will be used in mediatek snfi spi-mem controller with +pipelined ECC engine. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d) +--- + drivers/mtd/nand/Kconfig | 7 +++++++ + drivers/mtd/nand/Makefile | 1 + + drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} | 3 +-- + drivers/mtd/nand/raw/Kconfig | 1 + + drivers/mtd/nand/raw/Makefile | 2 +- + drivers/mtd/nand/raw/mtk_nand.c | 2 +- + .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0 + 7 files changed, 12 insertions(+), 4 deletions(-) + rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%) + rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%) + +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT + bool "Support MediaTek NAND Bad-block Management Table" + default n + ++config MTD_NAND_ECC_MEDIATEK ++ tristate "Mediatek hardware ECC engine" ++ depends on HAS_IOMEM ++ select MTD_NAND_ECC ++ help ++ This enables support for the hardware ECC engine from Mediatek. ++ + endmenu + + endmenu +--- a/drivers/mtd/nand/Makefile ++++ b/drivers/mtd/nand/Makefile +@@ -3,6 +3,7 @@ + nandcore-objs := core.o bbt.o + obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o + obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o ++obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o + + obj-y += onenand/ + obj-y += raw/ +--- a/drivers/mtd/nand/raw/mtk_ecc.c ++++ /dev/null +@@ -1,599 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 OR MIT +-/* +- * MTK ECC controller driver. +- * Copyright (C) 2016 MediaTek Inc. +- * Authors: Xiaolei Li +- * Jorge Ramirez-Ortiz +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "mtk_ecc.h" +- +-#define ECC_IDLE_MASK BIT(0) +-#define ECC_IRQ_EN BIT(0) +-#define ECC_PG_IRQ_SEL BIT(1) +-#define ECC_OP_ENABLE (1) +-#define ECC_OP_DISABLE (0) +- +-#define ECC_ENCCON (0x00) +-#define ECC_ENCCNFG (0x04) +-#define ECC_MS_SHIFT (16) +-#define ECC_ENCDIADDR (0x08) +-#define ECC_ENCIDLE (0x0C) +-#define ECC_DECCON (0x100) +-#define ECC_DECCNFG (0x104) +-#define DEC_EMPTY_EN BIT(31) +-#define DEC_CNFG_CORRECT (0x3 << 12) +-#define ECC_DECIDLE (0x10C) +-#define ECC_DECENUM0 (0x114) +- +-#define ECC_TIMEOUT (500000) +- +-#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) +-#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) +- +-struct mtk_ecc_caps { +- u32 err_mask; +- u32 err_shift; +- const u8 *ecc_strength; +- const u32 *ecc_regs; +- u8 num_ecc_strength; +- u8 ecc_mode_shift; +- u32 parity_bits; +- int pg_irq_sel; +-}; +- +-struct mtk_ecc { +- struct device *dev; +- const struct mtk_ecc_caps *caps; +- void __iomem *regs; +- struct clk *clk; +- +- struct completion done; +- struct mutex lock; +- u32 sectors; +- +- u8 *eccdata; +-}; +- +-/* ecc strength that each IP supports */ +-static const u8 ecc_strength_mt2701[] = { +- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, +- 40, 44, 48, 52, 56, 60 +-}; +- +-static const u8 ecc_strength_mt2712[] = { +- 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, +- 40, 44, 48, 52, 56, 60, 68, 72, 80 +-}; +- +-static const u8 ecc_strength_mt7622[] = { +- 4, 6, 8, 10, 12 +-}; +- +-enum mtk_ecc_regs { +- ECC_ENCPAR00, +- ECC_ENCIRQ_EN, +- ECC_ENCIRQ_STA, +- ECC_DECDONE, +- ECC_DECIRQ_EN, +- ECC_DECIRQ_STA, +-}; +- +-static int mt2701_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x10, +- [ECC_ENCIRQ_EN] = 0x80, +- [ECC_ENCIRQ_STA] = 0x84, +- [ECC_DECDONE] = 0x124, +- [ECC_DECIRQ_EN] = 0x200, +- [ECC_DECIRQ_STA] = 0x204, +-}; +- +-static int mt2712_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x300, +- [ECC_ENCIRQ_EN] = 0x80, +- [ECC_ENCIRQ_STA] = 0x84, +- [ECC_DECDONE] = 0x124, +- [ECC_DECIRQ_EN] = 0x200, +- [ECC_DECIRQ_STA] = 0x204, +-}; +- +-static int mt7622_ecc_regs[] = { +- [ECC_ENCPAR00] = 0x10, +- [ECC_ENCIRQ_EN] = 0x30, +- [ECC_ENCIRQ_STA] = 0x34, +- [ECC_DECDONE] = 0x11c, +- [ECC_DECIRQ_EN] = 0x140, +- [ECC_DECIRQ_STA] = 0x144, +-}; +- +-static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, +- enum mtk_ecc_operation op) +-{ +- struct device *dev = ecc->dev; +- u32 val; +- int ret; +- +- ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, +- val & ECC_IDLE_MASK, +- 10, ECC_TIMEOUT); +- if (ret) +- dev_warn(dev, "%s NOT idle\n", +- op == ECC_ENCODE ? "encoder" : "decoder"); +-} +- +-static irqreturn_t mtk_ecc_irq(int irq, void *id) +-{ +- struct mtk_ecc *ecc = id; +- u32 dec, enc; +- +- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) +- & ECC_IRQ_EN; +- if (dec) { +- dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); +- if (dec & ecc->sectors) { +- /* +- * Clear decode IRQ status once again to ensure that +- * there will be no extra IRQ. +- */ +- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); +- ecc->sectors = 0; +- complete(&ecc->done); +- } else { +- return IRQ_HANDLED; +- } +- } else { +- enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) +- & ECC_IRQ_EN; +- if (enc) +- complete(&ecc->done); +- else +- return IRQ_NONE; +- } +- +- return IRQ_HANDLED; +-} +- +-static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) +-{ +- u32 ecc_bit, dec_sz, enc_sz; +- u32 reg, i; +- +- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { +- if (ecc->caps->ecc_strength[i] == config->strength) +- break; +- } +- +- if (i == ecc->caps->num_ecc_strength) { +- dev_err(ecc->dev, "invalid ecc strength %d\n", +- config->strength); +- return -EINVAL; +- } +- +- ecc_bit = i; +- +- if (config->op == ECC_ENCODE) { +- /* configure ECC encoder (in bits) */ +- enc_sz = config->len << 3; +- +- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); +- reg |= (enc_sz << ECC_MS_SHIFT); +- writel(reg, ecc->regs + ECC_ENCCNFG); +- +- if (config->mode != ECC_NFI_MODE) +- writel(lower_32_bits(config->addr), +- ecc->regs + ECC_ENCDIADDR); +- +- } else { +- /* configure ECC decoder (in bits) */ +- dec_sz = (config->len << 3) + +- config->strength * ecc->caps->parity_bits; +- +- reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); +- reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; +- reg |= DEC_EMPTY_EN; +- writel(reg, ecc->regs + ECC_DECCNFG); +- +- if (config->sectors) +- ecc->sectors = 1 << (config->sectors - 1); +- } +- +- return 0; +-} +- +-void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, +- int sectors) +-{ +- u32 offset, i, err; +- u32 bitflips = 0; +- +- stats->corrected = 0; +- stats->failed = 0; +- +- for (i = 0; i < sectors; i++) { +- offset = (i >> 2) << 2; +- err = readl(ecc->regs + ECC_DECENUM0 + offset); +- err = err >> ((i % 4) * ecc->caps->err_shift); +- err &= ecc->caps->err_mask; +- if (err == ecc->caps->err_mask) { +- /* uncorrectable errors */ +- stats->failed++; +- continue; +- } +- +- stats->corrected += err; +- bitflips = max_t(u32, bitflips, err); +- } +- +- stats->bitflips = bitflips; +-} +-EXPORT_SYMBOL(mtk_ecc_get_stats); +- +-void mtk_ecc_release(struct mtk_ecc *ecc) +-{ +- clk_disable_unprepare(ecc->clk); +- put_device(ecc->dev); +-} +-EXPORT_SYMBOL(mtk_ecc_release); +- +-static void mtk_ecc_hw_init(struct mtk_ecc *ecc) +-{ +- mtk_ecc_wait_idle(ecc, ECC_ENCODE); +- writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); +- +- mtk_ecc_wait_idle(ecc, ECC_DECODE); +- writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); +-} +- +-static struct mtk_ecc *mtk_ecc_get(struct device_node *np) +-{ +- struct platform_device *pdev; +- struct mtk_ecc *ecc; +- +- pdev = of_find_device_by_node(np); +- if (!pdev) +- return ERR_PTR(-EPROBE_DEFER); +- +- ecc = platform_get_drvdata(pdev); +- if (!ecc) { +- put_device(&pdev->dev); +- return ERR_PTR(-EPROBE_DEFER); +- } +- +- clk_prepare_enable(ecc->clk); +- mtk_ecc_hw_init(ecc); +- +- return ecc; +-} +- +-struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) +-{ +- struct mtk_ecc *ecc = NULL; +- struct device_node *np; +- +- np = of_parse_phandle(of_node, "ecc-engine", 0); +- if (np) { +- ecc = mtk_ecc_get(np); +- of_node_put(np); +- } +- +- return ecc; +-} +-EXPORT_SYMBOL(of_mtk_ecc_get); +- +-int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) +-{ +- enum mtk_ecc_operation op = config->op; +- u16 reg_val; +- int ret; +- +- ret = mutex_lock_interruptible(&ecc->lock); +- if (ret) { +- dev_err(ecc->dev, "interrupted when attempting to lock\n"); +- return ret; +- } +- +- mtk_ecc_wait_idle(ecc, op); +- +- ret = mtk_ecc_config(ecc, config); +- if (ret) { +- mutex_unlock(&ecc->lock); +- return ret; +- } +- +- if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { +- init_completion(&ecc->done); +- reg_val = ECC_IRQ_EN; +- /* +- * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it +- * means this chip can only generate one ecc irq during page +- * read / write. If is 0, generate one ecc irq each ecc step. +- */ +- if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) +- reg_val |= ECC_PG_IRQ_SEL; +- if (op == ECC_ENCODE) +- writew(reg_val, ecc->regs + +- ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); +- else +- writew(reg_val, ecc->regs + +- ecc->caps->ecc_regs[ECC_DECIRQ_EN]); +- } +- +- writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); +- +- return 0; +-} +-EXPORT_SYMBOL(mtk_ecc_enable); +- +-void mtk_ecc_disable(struct mtk_ecc *ecc) +-{ +- enum mtk_ecc_operation op = ECC_ENCODE; +- +- /* find out the running operation */ +- if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) +- op = ECC_DECODE; +- +- /* disable it */ +- mtk_ecc_wait_idle(ecc, op); +- if (op == ECC_DECODE) { +- /* +- * Clear decode IRQ status in case there is a timeout to wait +- * decode IRQ. +- */ +- readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); +- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); +- } else { +- writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); +- } +- +- writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); +- +- mutex_unlock(&ecc->lock); +-} +-EXPORT_SYMBOL(mtk_ecc_disable); +- +-int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) +-{ +- int ret; +- +- ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); +- if (!ret) { +- dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", +- (op == ECC_ENCODE) ? "encoder" : "decoder"); +- return -ETIMEDOUT; +- } +- +- return 0; +-} +-EXPORT_SYMBOL(mtk_ecc_wait_done); +- +-int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, +- u8 *data, u32 bytes) +-{ +- dma_addr_t addr; +- u32 len; +- int ret; +- +- addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); +- ret = dma_mapping_error(ecc->dev, addr); +- if (ret) { +- dev_err(ecc->dev, "dma mapping error\n"); +- return -EINVAL; +- } +- +- config->op = ECC_ENCODE; +- config->addr = addr; +- ret = mtk_ecc_enable(ecc, config); +- if (ret) { +- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); +- return ret; +- } +- +- ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); +- if (ret) +- goto timeout; +- +- mtk_ecc_wait_idle(ecc, ECC_ENCODE); +- +- /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ +- len = (config->strength * ecc->caps->parity_bits + 7) >> 3; +- +- /* write the parity bytes generated by the ECC back to temp buffer */ +- __ioread32_copy(ecc->eccdata, +- ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], +- round_up(len, 4)); +- +- /* copy into possibly unaligned OOB region with actual length */ +- memcpy(data + bytes, ecc->eccdata, len); +-timeout: +- +- dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); +- mtk_ecc_disable(ecc); +- +- return ret; +-} +-EXPORT_SYMBOL(mtk_ecc_encode); +- +-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) +-{ +- const u8 *ecc_strength = ecc->caps->ecc_strength; +- int i; +- +- for (i = 0; i < ecc->caps->num_ecc_strength; i++) { +- if (*p <= ecc_strength[i]) { +- if (!i) +- *p = ecc_strength[i]; +- else if (*p != ecc_strength[i]) +- *p = ecc_strength[i - 1]; +- return; +- } +- } +- +- *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; +-} +-EXPORT_SYMBOL(mtk_ecc_adjust_strength); +- +-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) +-{ +- return ecc->caps->parity_bits; +-} +-EXPORT_SYMBOL(mtk_ecc_get_parity_bits); +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { +- .err_mask = 0x3f, +- .err_shift = 8, +- .ecc_strength = ecc_strength_mt2701, +- .ecc_regs = mt2701_ecc_regs, +- .num_ecc_strength = 20, +- .ecc_mode_shift = 5, +- .parity_bits = 14, +- .pg_irq_sel = 0, +-}; +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { +- .err_mask = 0x7f, +- .err_shift = 8, +- .ecc_strength = ecc_strength_mt2712, +- .ecc_regs = mt2712_ecc_regs, +- .num_ecc_strength = 23, +- .ecc_mode_shift = 5, +- .parity_bits = 14, +- .pg_irq_sel = 1, +-}; +- +-static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { +- .err_mask = 0x1f, +- .err_shift = 5, +- .ecc_strength = ecc_strength_mt7622, +- .ecc_regs = mt7622_ecc_regs, +- .num_ecc_strength = 5, +- .ecc_mode_shift = 4, +- .parity_bits = 13, +- .pg_irq_sel = 0, +-}; +- +-static const struct of_device_id mtk_ecc_dt_match[] = { +- { +- .compatible = "mediatek,mt2701-ecc", +- .data = &mtk_ecc_caps_mt2701, +- }, { +- .compatible = "mediatek,mt2712-ecc", +- .data = &mtk_ecc_caps_mt2712, +- }, { +- .compatible = "mediatek,mt7622-ecc", +- .data = &mtk_ecc_caps_mt7622, +- }, +- {}, +-}; +- +-static int mtk_ecc_probe(struct platform_device *pdev) +-{ +- struct device *dev = &pdev->dev; +- struct mtk_ecc *ecc; +- struct resource *res; +- u32 max_eccdata_size; +- int irq, ret; +- +- ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); +- if (!ecc) +- return -ENOMEM; +- +- ecc->caps = of_device_get_match_data(dev); +- +- max_eccdata_size = ecc->caps->num_ecc_strength - 1; +- max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; +- max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; +- max_eccdata_size = round_up(max_eccdata_size, 4); +- ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); +- if (!ecc->eccdata) +- return -ENOMEM; +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- ecc->regs = devm_ioremap_resource(dev, res); +- if (IS_ERR(ecc->regs)) +- return PTR_ERR(ecc->regs); +- +- ecc->clk = devm_clk_get(dev, NULL); +- if (IS_ERR(ecc->clk)) { +- dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); +- return PTR_ERR(ecc->clk); +- } +- +- irq = platform_get_irq(pdev, 0); +- if (irq < 0) +- return irq; +- +- ret = dma_set_mask(dev, DMA_BIT_MASK(32)); +- if (ret) { +- dev_err(dev, "failed to set DMA mask\n"); +- return ret; +- } +- +- ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); +- if (ret) { +- dev_err(dev, "failed to request irq\n"); +- return -EINVAL; +- } +- +- ecc->dev = dev; +- mutex_init(&ecc->lock); +- platform_set_drvdata(pdev, ecc); +- dev_info(dev, "probed\n"); +- +- return 0; +-} +- +-#ifdef CONFIG_PM_SLEEP +-static int mtk_ecc_suspend(struct device *dev) +-{ +- struct mtk_ecc *ecc = dev_get_drvdata(dev); +- +- clk_disable_unprepare(ecc->clk); +- +- return 0; +-} +- +-static int mtk_ecc_resume(struct device *dev) +-{ +- struct mtk_ecc *ecc = dev_get_drvdata(dev); +- int ret; +- +- ret = clk_prepare_enable(ecc->clk); +- if (ret) { +- dev_err(dev, "failed to enable clk\n"); +- return ret; +- } +- +- return 0; +-} +- +-static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); +-#endif +- +-MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); +- +-static struct platform_driver mtk_ecc_driver = { +- .probe = mtk_ecc_probe, +- .driver = { +- .name = "mtk-ecc", +- .of_match_table = of_match_ptr(mtk_ecc_dt_match), +-#ifdef CONFIG_PM_SLEEP +- .pm = &mtk_ecc_pm_ops, +-#endif +- }, +-}; +- +-module_platform_driver(mtk_ecc_driver); +- +-MODULE_AUTHOR("Xiaolei Li "); +-MODULE_DESCRIPTION("MTK Nand ECC Driver"); +-MODULE_LICENSE("Dual MIT/GPL"); +--- /dev/null ++++ b/drivers/mtd/nand/ecc-mtk.c +@@ -0,0 +1,598 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * MTK ECC controller driver. ++ * Copyright (C) 2016 MediaTek Inc. ++ * Authors: Xiaolei Li ++ * Jorge Ramirez-Ortiz ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define ECC_IDLE_MASK BIT(0) ++#define ECC_IRQ_EN BIT(0) ++#define ECC_PG_IRQ_SEL BIT(1) ++#define ECC_OP_ENABLE (1) ++#define ECC_OP_DISABLE (0) ++ ++#define ECC_ENCCON (0x00) ++#define ECC_ENCCNFG (0x04) ++#define ECC_MS_SHIFT (16) ++#define ECC_ENCDIADDR (0x08) ++#define ECC_ENCIDLE (0x0C) ++#define ECC_DECCON (0x100) ++#define ECC_DECCNFG (0x104) ++#define DEC_EMPTY_EN BIT(31) ++#define DEC_CNFG_CORRECT (0x3 << 12) ++#define ECC_DECIDLE (0x10C) ++#define ECC_DECENUM0 (0x114) ++ ++#define ECC_TIMEOUT (500000) ++ ++#define ECC_IDLE_REG(op) ((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE) ++#define ECC_CTL_REG(op) ((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON) ++ ++struct mtk_ecc_caps { ++ u32 err_mask; ++ u32 err_shift; ++ const u8 *ecc_strength; ++ const u32 *ecc_regs; ++ u8 num_ecc_strength; ++ u8 ecc_mode_shift; ++ u32 parity_bits; ++ int pg_irq_sel; ++}; ++ ++struct mtk_ecc { ++ struct device *dev; ++ const struct mtk_ecc_caps *caps; ++ void __iomem *regs; ++ struct clk *clk; ++ ++ struct completion done; ++ struct mutex lock; ++ u32 sectors; ++ ++ u8 *eccdata; ++}; ++ ++/* ecc strength that each IP supports */ ++static const u8 ecc_strength_mt2701[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, ++ 40, 44, 48, 52, 56, 60 ++}; ++ ++static const u8 ecc_strength_mt2712[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, ++ 40, 44, 48, 52, 56, 60, 68, 72, 80 ++}; ++ ++static const u8 ecc_strength_mt7622[] = { ++ 4, 6, 8, 10, 12 ++}; ++ ++enum mtk_ecc_regs { ++ ECC_ENCPAR00, ++ ECC_ENCIRQ_EN, ++ ECC_ENCIRQ_STA, ++ ECC_DECDONE, ++ ECC_DECIRQ_EN, ++ ECC_DECIRQ_STA, ++}; ++ ++static int mt2701_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt2712_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x300, ++ [ECC_ENCIRQ_EN] = 0x80, ++ [ECC_ENCIRQ_STA] = 0x84, ++ [ECC_DECDONE] = 0x124, ++ [ECC_DECIRQ_EN] = 0x200, ++ [ECC_DECIRQ_STA] = 0x204, ++}; ++ ++static int mt7622_ecc_regs[] = { ++ [ECC_ENCPAR00] = 0x10, ++ [ECC_ENCIRQ_EN] = 0x30, ++ [ECC_ENCIRQ_STA] = 0x34, ++ [ECC_DECDONE] = 0x11c, ++ [ECC_DECIRQ_EN] = 0x140, ++ [ECC_DECIRQ_STA] = 0x144, ++}; ++ ++static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, ++ enum mtk_ecc_operation op) ++{ ++ struct device *dev = ecc->dev; ++ u32 val; ++ int ret; ++ ++ ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, ++ val & ECC_IDLE_MASK, ++ 10, ECC_TIMEOUT); ++ if (ret) ++ dev_warn(dev, "%s NOT idle\n", ++ op == ECC_ENCODE ? "encoder" : "decoder"); ++} ++ ++static irqreturn_t mtk_ecc_irq(int irq, void *id) ++{ ++ struct mtk_ecc *ecc = id; ++ u32 dec, enc; ++ ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (dec) { ++ dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ if (dec & ecc->sectors) { ++ /* ++ * Clear decode IRQ status once again to ensure that ++ * there will be no extra IRQ. ++ */ ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); ++ ecc->sectors = 0; ++ complete(&ecc->done); ++ } else { ++ return IRQ_HANDLED; ++ } ++ } else { ++ enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) ++ & ECC_IRQ_EN; ++ if (enc) ++ complete(&ecc->done); ++ else ++ return IRQ_NONE; ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config) ++{ ++ u32 ecc_bit, dec_sz, enc_sz; ++ u32 reg, i; ++ ++ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { ++ if (ecc->caps->ecc_strength[i] == config->strength) ++ break; ++ } ++ ++ if (i == ecc->caps->num_ecc_strength) { ++ dev_err(ecc->dev, "invalid ecc strength %d\n", ++ config->strength); ++ return -EINVAL; ++ } ++ ++ ecc_bit = i; ++ ++ if (config->op == ECC_ENCODE) { ++ /* configure ECC encoder (in bits) */ ++ enc_sz = config->len << 3; ++ ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); ++ reg |= (enc_sz << ECC_MS_SHIFT); ++ writel(reg, ecc->regs + ECC_ENCCNFG); ++ ++ if (config->mode != ECC_NFI_MODE) ++ writel(lower_32_bits(config->addr), ++ ecc->regs + ECC_ENCDIADDR); ++ ++ } else { ++ /* configure ECC decoder (in bits) */ ++ dec_sz = (config->len << 3) + ++ config->strength * ecc->caps->parity_bits; ++ ++ reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); ++ reg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT; ++ reg |= DEC_EMPTY_EN; ++ writel(reg, ecc->regs + ECC_DECCNFG); ++ ++ if (config->sectors) ++ ecc->sectors = 1 << (config->sectors - 1); ++ } ++ ++ return 0; ++} ++ ++void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, ++ int sectors) ++{ ++ u32 offset, i, err; ++ u32 bitflips = 0; ++ ++ stats->corrected = 0; ++ stats->failed = 0; ++ ++ for (i = 0; i < sectors; i++) { ++ offset = (i >> 2) << 2; ++ err = readl(ecc->regs + ECC_DECENUM0 + offset); ++ err = err >> ((i % 4) * ecc->caps->err_shift); ++ err &= ecc->caps->err_mask; ++ if (err == ecc->caps->err_mask) { ++ /* uncorrectable errors */ ++ stats->failed++; ++ continue; ++ } ++ ++ stats->corrected += err; ++ bitflips = max_t(u32, bitflips, err); ++ } ++ ++ stats->bitflips = bitflips; ++} ++EXPORT_SYMBOL(mtk_ecc_get_stats); ++ ++void mtk_ecc_release(struct mtk_ecc *ecc) ++{ ++ clk_disable_unprepare(ecc->clk); ++ put_device(ecc->dev); ++} ++EXPORT_SYMBOL(mtk_ecc_release); ++ ++static void mtk_ecc_hw_init(struct mtk_ecc *ecc) ++{ ++ mtk_ecc_wait_idle(ecc, ECC_ENCODE); ++ writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON); ++ ++ mtk_ecc_wait_idle(ecc, ECC_DECODE); ++ writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON); ++} ++ ++static struct mtk_ecc *mtk_ecc_get(struct device_node *np) ++{ ++ struct platform_device *pdev; ++ struct mtk_ecc *ecc; ++ ++ pdev = of_find_device_by_node(np); ++ if (!pdev) ++ return ERR_PTR(-EPROBE_DEFER); ++ ++ ecc = platform_get_drvdata(pdev); ++ if (!ecc) { ++ put_device(&pdev->dev); ++ return ERR_PTR(-EPROBE_DEFER); ++ } ++ ++ clk_prepare_enable(ecc->clk); ++ mtk_ecc_hw_init(ecc); ++ ++ return ecc; ++} ++ ++struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node) ++{ ++ struct mtk_ecc *ecc = NULL; ++ struct device_node *np; ++ ++ np = of_parse_phandle(of_node, "ecc-engine", 0); ++ if (np) { ++ ecc = mtk_ecc_get(np); ++ of_node_put(np); ++ } ++ ++ return ecc; ++} ++EXPORT_SYMBOL(of_mtk_ecc_get); ++ ++int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) ++{ ++ enum mtk_ecc_operation op = config->op; ++ u16 reg_val; ++ int ret; ++ ++ ret = mutex_lock_interruptible(&ecc->lock); ++ if (ret) { ++ dev_err(ecc->dev, "interrupted when attempting to lock\n"); ++ return ret; ++ } ++ ++ mtk_ecc_wait_idle(ecc, op); ++ ++ ret = mtk_ecc_config(ecc, config); ++ if (ret) { ++ mutex_unlock(&ecc->lock); ++ return ret; ++ } ++ ++ if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { ++ init_completion(&ecc->done); ++ reg_val = ECC_IRQ_EN; ++ /* ++ * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it ++ * means this chip can only generate one ecc irq during page ++ * read / write. If is 0, generate one ecc irq each ecc step. ++ */ ++ if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) ++ reg_val |= ECC_PG_IRQ_SEL; ++ if (op == ECC_ENCODE) ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ else ++ writew(reg_val, ecc->regs + ++ ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } ++ ++ writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(mtk_ecc_enable); ++ ++void mtk_ecc_disable(struct mtk_ecc *ecc) ++{ ++ enum mtk_ecc_operation op = ECC_ENCODE; ++ ++ /* find out the running operation */ ++ if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE) ++ op = ECC_DECODE; ++ ++ /* disable it */ ++ mtk_ecc_wait_idle(ecc, op); ++ if (op == ECC_DECODE) { ++ /* ++ * Clear decode IRQ status in case there is a timeout to wait ++ * decode IRQ. ++ */ ++ readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]); ++ } else { ++ writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]); ++ } ++ ++ writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op)); ++ ++ mutex_unlock(&ecc->lock); ++} ++EXPORT_SYMBOL(mtk_ecc_disable); ++ ++int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op) ++{ ++ int ret; ++ ++ ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500)); ++ if (!ret) { ++ dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n", ++ (op == ECC_ENCODE) ? "encoder" : "decoder"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(mtk_ecc_wait_done); ++ ++int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config, ++ u8 *data, u32 bytes) ++{ ++ dma_addr_t addr; ++ u32 len; ++ int ret; ++ ++ addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE); ++ ret = dma_mapping_error(ecc->dev, addr); ++ if (ret) { ++ dev_err(ecc->dev, "dma mapping error\n"); ++ return -EINVAL; ++ } ++ ++ config->op = ECC_ENCODE; ++ config->addr = addr; ++ ret = mtk_ecc_enable(ecc, config); ++ if (ret) { ++ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); ++ return ret; ++ } ++ ++ ret = mtk_ecc_wait_done(ecc, ECC_ENCODE); ++ if (ret) ++ goto timeout; ++ ++ mtk_ecc_wait_idle(ecc, ECC_ENCODE); ++ ++ /* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */ ++ len = (config->strength * ecc->caps->parity_bits + 7) >> 3; ++ ++ /* write the parity bytes generated by the ECC back to temp buffer */ ++ __ioread32_copy(ecc->eccdata, ++ ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00], ++ round_up(len, 4)); ++ ++ /* copy into possibly unaligned OOB region with actual length */ ++ memcpy(data + bytes, ecc->eccdata, len); ++timeout: ++ ++ dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE); ++ mtk_ecc_disable(ecc); ++ ++ return ret; ++} ++EXPORT_SYMBOL(mtk_ecc_encode); ++ ++void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p) ++{ ++ const u8 *ecc_strength = ecc->caps->ecc_strength; ++ int i; ++ ++ for (i = 0; i < ecc->caps->num_ecc_strength; i++) { ++ if (*p <= ecc_strength[i]) { ++ if (!i) ++ *p = ecc_strength[i]; ++ else if (*p != ecc_strength[i]) ++ *p = ecc_strength[i - 1]; ++ return; ++ } ++ } ++ ++ *p = ecc_strength[ecc->caps->num_ecc_strength - 1]; ++} ++EXPORT_SYMBOL(mtk_ecc_adjust_strength); ++ ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc) ++{ ++ return ecc->caps->parity_bits; ++} ++EXPORT_SYMBOL(mtk_ecc_get_parity_bits); ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { ++ .err_mask = 0x3f, ++ .err_shift = 8, ++ .ecc_strength = ecc_strength_mt2701, ++ .ecc_regs = mt2701_ecc_regs, ++ .num_ecc_strength = 20, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, ++ .pg_irq_sel = 0, ++}; ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { ++ .err_mask = 0x7f, ++ .err_shift = 8, ++ .ecc_strength = ecc_strength_mt2712, ++ .ecc_regs = mt2712_ecc_regs, ++ .num_ecc_strength = 23, ++ .ecc_mode_shift = 5, ++ .parity_bits = 14, ++ .pg_irq_sel = 1, ++}; ++ ++static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { ++ .err_mask = 0x1f, ++ .err_shift = 5, ++ .ecc_strength = ecc_strength_mt7622, ++ .ecc_regs = mt7622_ecc_regs, ++ .num_ecc_strength = 5, ++ .ecc_mode_shift = 4, ++ .parity_bits = 13, ++ .pg_irq_sel = 0, ++}; ++ ++static const struct of_device_id mtk_ecc_dt_match[] = { ++ { ++ .compatible = "mediatek,mt2701-ecc", ++ .data = &mtk_ecc_caps_mt2701, ++ }, { ++ .compatible = "mediatek,mt2712-ecc", ++ .data = &mtk_ecc_caps_mt2712, ++ }, { ++ .compatible = "mediatek,mt7622-ecc", ++ .data = &mtk_ecc_caps_mt7622, ++ }, ++ {}, ++}; ++ ++static int mtk_ecc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct mtk_ecc *ecc; ++ struct resource *res; ++ u32 max_eccdata_size; ++ int irq, ret; ++ ++ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); ++ if (!ecc) ++ return -ENOMEM; ++ ++ ecc->caps = of_device_get_match_data(dev); ++ ++ max_eccdata_size = ecc->caps->num_ecc_strength - 1; ++ max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size]; ++ max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3; ++ max_eccdata_size = round_up(max_eccdata_size, 4); ++ ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL); ++ if (!ecc->eccdata) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ecc->regs = devm_ioremap_resource(dev, res); ++ if (IS_ERR(ecc->regs)) ++ return PTR_ERR(ecc->regs); ++ ++ ecc->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(ecc->clk)) { ++ dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk)); ++ return PTR_ERR(ecc->clk); ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = dma_set_mask(dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(dev, "failed to set DMA mask\n"); ++ return ret; ++ } ++ ++ ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc); ++ if (ret) { ++ dev_err(dev, "failed to request irq\n"); ++ return -EINVAL; ++ } ++ ++ ecc->dev = dev; ++ mutex_init(&ecc->lock); ++ platform_set_drvdata(pdev, ecc); ++ dev_info(dev, "probed\n"); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int mtk_ecc_suspend(struct device *dev) ++{ ++ struct mtk_ecc *ecc = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(ecc->clk); ++ ++ return 0; ++} ++ ++static int mtk_ecc_resume(struct device *dev) ++{ ++ struct mtk_ecc *ecc = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_prepare_enable(ecc->clk); ++ if (ret) { ++ dev_err(dev, "failed to enable clk\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume); ++#endif ++ ++MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match); ++ ++static struct platform_driver mtk_ecc_driver = { ++ .probe = mtk_ecc_probe, ++ .driver = { ++ .name = "mtk-ecc", ++ .of_match_table = of_match_ptr(mtk_ecc_dt_match), ++#ifdef CONFIG_PM_SLEEP ++ .pm = &mtk_ecc_pm_ops, ++#endif ++ }, ++}; ++ ++module_platform_driver(mtk_ecc_driver); ++ ++MODULE_AUTHOR("Xiaolei Li "); ++MODULE_DESCRIPTION("MTK Nand ECC Driver"); ++MODULE_LICENSE("Dual MIT/GPL"); +--- a/drivers/mtd/nand/raw/Kconfig ++++ b/drivers/mtd/nand/raw/Kconfig +@@ -360,6 +360,7 @@ config MTD_NAND_QCOM + + config MTD_NAND_MTK + tristate "MTK NAND controller" ++ depends on MTD_NAND_ECC_MEDIATEK + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on HAS_IOMEM + help +--- a/drivers/mtd/nand/raw/Makefile ++++ b/drivers/mtd/nand/raw/Makefile +@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n + obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o + obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ + obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o +-obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o ++obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o + obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o + obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o + obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o +--- a/drivers/mtd/nand/raw/mtk_nand.c ++++ b/drivers/mtd/nand/raw/mtk_nand.c +@@ -17,7 +17,7 @@ + #include + #include + #include +-#include "mtk_ecc.h" ++#include + + /* NAND controller register definition */ + #define NFI_CNFG (0x00) +--- a/drivers/mtd/nand/raw/mtk_ecc.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +-/* +- * MTK SDG1 ECC controller +- * +- * Copyright (c) 2016 Mediatek +- * Authors: Xiaolei Li +- * Jorge Ramirez-Ortiz +- */ +- +-#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ +-#define __DRIVERS_MTD_NAND_MTK_ECC_H__ +- +-#include +- +-enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; +-enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; +- +-struct device_node; +-struct mtk_ecc; +- +-struct mtk_ecc_stats { +- u32 corrected; +- u32 bitflips; +- u32 failed; +-}; +- +-struct mtk_ecc_config { +- enum mtk_ecc_operation op; +- enum mtk_ecc_mode mode; +- dma_addr_t addr; +- u32 strength; +- u32 sectors; +- u32 len; +-}; +- +-int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); +-void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); +-int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); +-int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); +-void mtk_ecc_disable(struct mtk_ecc *); +-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); +-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); +- +-struct mtk_ecc *of_mtk_ecc_get(struct device_node *); +-void mtk_ecc_release(struct mtk_ecc *); +- +-#endif +--- /dev/null ++++ b/include/linux/mtd/nand-ecc-mtk.h +@@ -0,0 +1,47 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * MTK SDG1 ECC controller ++ * ++ * Copyright (c) 2016 Mediatek ++ * Authors: Xiaolei Li ++ * Jorge Ramirez-Ortiz ++ */ ++ ++#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ ++#define __DRIVERS_MTD_NAND_MTK_ECC_H__ ++ ++#include ++ ++enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; ++enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; ++ ++struct device_node; ++struct mtk_ecc; ++ ++struct mtk_ecc_stats { ++ u32 corrected; ++ u32 bitflips; ++ u32 failed; ++}; ++ ++struct mtk_ecc_config { ++ enum mtk_ecc_operation op; ++ enum mtk_ecc_mode mode; ++ dma_addr_t addr; ++ u32 strength; ++ u32 sectors; ++ u32 len; ++}; ++ ++int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); ++void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); ++int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); ++int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); ++void mtk_ecc_disable(struct mtk_ecc *); ++void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p); ++unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc); ++ ++struct mtk_ecc *of_mtk_ecc_get(struct device_node *); ++void mtk_ecc_release(struct mtk_ecc *); ++ ++#endif diff --git a/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch b/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch new file mode 100644 index 000000000..b77b4ad4c --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-12-v5.19-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch @@ -0,0 +1,1537 @@ +From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sat, 2 Apr 2022 10:16:11 +0800 +Subject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface + +This driver implements support for the SPI-NAND mode of MTK NAND Flash +Interface as a SPI-MEM controller with pipelined ECC capability. + +Signed-off-by: Chuanhong Guo +Tested-by: Daniel Golle +--- +Change since v1: + fix CI warnings + +Changes since v2: + use streamed DMA api to avoid an extra memory copy during read + make ECC engine config a per-nand context + take user-requested ECC strength into account + +Change since v3: none +Changes since v4: + fix missing OOB write + print page format with dev_dbg + replace uint*_t copied from vendor driver with u* + +Changes since v5: + add missing nfi mode register configuration in probe + fix an off-by-one bug in mtk_snand_mac_io + + drivers/spi/Kconfig | 10 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 1481 insertions(+) + create mode 100644 drivers/spi/spi-mtk-snfi.c + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -530,6 +530,16 @@ config SPI_MTK_NOR + SPI interface as well as several SPI NOR specific instructions + via SPI MEM interface. + ++config SPI_MTK_SNFI ++ tristate "MediaTek SPI NAND Flash Interface" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ depends on MTD_NAND_ECC_MEDIATEK ++ help ++ This enables support for SPI-NAND mode on the MediaTek NAND ++ Flash Interface found on MediaTek ARM SoCs. This controller ++ is implemented as a SPI-MEM controller with pipelined ECC ++ capcability. ++ + config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52x + obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o + obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o + obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o ++obj-$(CONFIG_SPI_MTK_SNFI) += spi-mtk-snfi.o + obj-$(CONFIG_SPI_MXIC) += spi-mxic.o + obj-$(CONFIG_SPI_MXS) += spi-mxs.o + obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o +--- /dev/null ++++ b/drivers/spi/spi-mtk-snfi.c +@@ -0,0 +1,1470 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// ++// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface ++// ++// Copyright (c) 2022 Chuanhong Guo ++// ++// This driver is based on the SPI-NAND mtd driver from Mediatek SDK: ++// ++// Copyright (C) 2020 MediaTek Inc. ++// Author: Weijie Gao ++// ++// This controller organize the page data as several interleaved sectors ++// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size) ++// +---------+------+------+---------+------+------+-----+ ++// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... | ++// +---------+------+------+---------+------+------+-----+ ++// With auto-format turned on, DMA only returns this part: ++// +---------+---------+-----+ ++// | Sector1 | Sector2 | ... | ++// +---------+---------+-----+ ++// The FDM data will be filled to the registers, and ECC parity data isn't ++// accessible. ++// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA ++// in it's original order shown in the first table. ECC can't be turned on when ++// auto-format is off. ++// ++// However, Linux SPI-NAND driver expects the data returned as: ++// +------+-----+ ++// | Page | OOB | ++// +------+-----+ ++// where the page data is continuously stored instead of interleaved. ++// So we assume all instructions matching the page_op template between ECC ++// prepare_io_req and finish_io_req are for page cache r/w. ++// Here's how this spi-mem driver operates when reading: ++// 1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off). ++// 2. Perform page ops and let the controller fill the DMA bounce buffer with ++// de-interleaved sector data and set FDM registers. ++// 3. Return the data as: ++// +---------+---------+-----+------+------+-----+ ++// | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... | ++// +---------+---------+-----+------+------+-----+ ++// 4. For other matching spi_mem ops outside a prepare/finish_io_req pair, ++// read the data with auto-format off into the bounce buffer and copy ++// needed data to the buffer specified in the request. ++// ++// Write requests operates in a similar manner. ++// As a limitation of this strategy, we won't be able to access any ECC parity ++// data at all in Linux. ++// ++// Here's the bad block mark situation on MTK chips: ++// In older chips like mt7622, MTK uses the first FDM byte in the first sector ++// as the bad block mark. After de-interleaving, this byte appears at [pagesize] ++// in the returned data, which is the BBM position expected by kernel. However, ++// the conventional bad block mark is the first byte of the OOB, which is part ++// of the last sector data in the interleaved layout. Instead of fixing their ++// hardware, MTK decided to address this inconsistency in software. On these ++// later chips, the BootROM expects the following: ++// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at ++// (page_size - (nsectors - 1) * spare_size) in the DMA buffer. ++// 2. The original byte stored at that position in the DMA buffer will be stored ++// as the first byte of the FDM section in the last sector. ++// We can't disagree with the BootROM, so after de-interleaving, we need to ++// perform the following swaps in read: ++// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size], ++// which is the expected BBM position by kernel. ++// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to ++// [page_size - (nsectors - 1) * spare_size] ++// Similarly, when writing, we need to perform swaps in the other direction. ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// NFI registers ++#define NFI_CNFG 0x000 ++#define CNFG_OP_MODE_S 12 ++#define CNFG_OP_MODE_CUST 6 ++#define CNFG_OP_MODE_PROGRAM 3 ++#define CNFG_AUTO_FMT_EN BIT(9) ++#define CNFG_HW_ECC_EN BIT(8) ++#define CNFG_DMA_BURST_EN BIT(2) ++#define CNFG_READ_MODE BIT(1) ++#define CNFG_DMA_MODE BIT(0) ++ ++#define NFI_PAGEFMT 0x0004 ++#define NFI_SPARE_SIZE_LS_S 16 ++#define NFI_FDM_ECC_NUM_S 12 ++#define NFI_FDM_NUM_S 8 ++#define NFI_SPARE_SIZE_S 4 ++#define NFI_SEC_SEL_512 BIT(2) ++#define NFI_PAGE_SIZE_S 0 ++#define NFI_PAGE_SIZE_512_2K 0 ++#define NFI_PAGE_SIZE_2K_4K 1 ++#define NFI_PAGE_SIZE_4K_8K 2 ++#define NFI_PAGE_SIZE_8K_16K 3 ++ ++#define NFI_CON 0x008 ++#define CON_SEC_NUM_S 12 ++#define CON_BWR BIT(9) ++#define CON_BRD BIT(8) ++#define CON_NFI_RST BIT(1) ++#define CON_FIFO_FLUSH BIT(0) ++ ++#define NFI_INTR_EN 0x010 ++#define NFI_INTR_STA 0x014 ++#define NFI_IRQ_INTR_EN BIT(31) ++#define NFI_IRQ_CUS_READ BIT(8) ++#define NFI_IRQ_CUS_PG BIT(7) ++ ++#define NFI_CMD 0x020 ++#define NFI_CMD_DUMMY_READ 0x00 ++#define NFI_CMD_DUMMY_WRITE 0x80 ++ ++#define NFI_STRDATA 0x040 ++#define STR_DATA BIT(0) ++ ++#define NFI_STA 0x060 ++#define NFI_NAND_FSM GENMASK(28, 24) ++#define NFI_FSM GENMASK(19, 16) ++#define READ_EMPTY BIT(12) ++ ++#define NFI_FIFOSTA 0x064 ++#define FIFO_WR_REMAIN_S 8 ++#define FIFO_RD_REMAIN_S 0 ++ ++#define NFI_ADDRCNTR 0x070 ++#define SEC_CNTR GENMASK(16, 12) ++#define SEC_CNTR_S 12 ++#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) ++ ++#define NFI_STRADDR 0x080 ++ ++#define NFI_BYTELEN 0x084 ++#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S) ++ ++#define NFI_FDM0L 0x0a0 ++#define NFI_FDM0M 0x0a4 ++#define NFI_FDML(n) (NFI_FDM0L + (n)*8) ++#define NFI_FDMM(n) (NFI_FDM0M + (n)*8) ++ ++#define NFI_DEBUG_CON1 0x220 ++#define WBUF_EN BIT(2) ++ ++#define NFI_MASTERSTA 0x224 ++#define MAS_ADDR GENMASK(11, 9) ++#define MAS_RD GENMASK(8, 6) ++#define MAS_WR GENMASK(5, 3) ++#define MAS_RDDLY GENMASK(2, 0) ++#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) ++ ++// SNFI registers ++#define SNF_MAC_CTL 0x500 ++#define MAC_XIO_SEL BIT(4) ++#define SF_MAC_EN BIT(3) ++#define SF_TRIG BIT(2) ++#define WIP_READY BIT(1) ++#define WIP BIT(0) ++ ++#define SNF_MAC_OUTL 0x504 ++#define SNF_MAC_INL 0x508 ++ ++#define SNF_RD_CTL2 0x510 ++#define DATA_READ_DUMMY_S 8 ++#define DATA_READ_MAX_DUMMY 0xf ++#define DATA_READ_CMD_S 0 ++ ++#define SNF_RD_CTL3 0x514 ++ ++#define SNF_PG_CTL1 0x524 ++#define PG_LOAD_CMD_S 8 ++ ++#define SNF_PG_CTL2 0x528 ++ ++#define SNF_MISC_CTL 0x538 ++#define SW_RST BIT(28) ++#define FIFO_RD_LTC_S 25 ++#define PG_LOAD_X4_EN BIT(20) ++#define DATA_READ_MODE_S 16 ++#define DATA_READ_MODE GENMASK(18, 16) ++#define DATA_READ_MODE_X1 0 ++#define DATA_READ_MODE_X2 1 ++#define DATA_READ_MODE_X4 2 ++#define DATA_READ_MODE_DUAL 5 ++#define DATA_READ_MODE_QUAD 6 ++#define PG_LOAD_CUSTOM_EN BIT(7) ++#define DATARD_CUSTOM_EN BIT(6) ++#define CS_DESELECT_CYC_S 0 ++ ++#define SNF_MISC_CTL2 0x53c ++#define PROGRAM_LOAD_BYTE_NUM_S 16 ++#define READ_DATA_BYTE_NUM_S 11 ++ ++#define SNF_DLY_CTL3 0x548 ++#define SFCK_SAM_DLY_S 0 ++ ++#define SNF_STA_CTL1 0x550 ++#define CUS_PG_DONE BIT(28) ++#define CUS_READ_DONE BIT(27) ++#define SPI_STATE_S 0 ++#define SPI_STATE GENMASK(3, 0) ++ ++#define SNF_CFG 0x55c ++#define SPI_MODE BIT(0) ++ ++#define SNF_GPRAM 0x800 ++#define SNF_GPRAM_SIZE 0xa0 ++ ++#define SNFI_POLL_INTERVAL 1000000 ++ ++static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 }; ++ ++struct mtk_snand_caps { ++ u16 sector_size; ++ u16 max_sectors; ++ u16 fdm_size; ++ u16 fdm_ecc_size; ++ u16 fifo_size; ++ ++ bool bbm_swap; ++ bool empty_page_check; ++ u32 mastersta_mask; ++ ++ const u8 *spare_sizes; ++ u32 num_spare_size; ++}; ++ ++static const struct mtk_snand_caps mt7622_snand_caps = { ++ .sector_size = 512, ++ .max_sectors = 8, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 32, ++ .bbm_swap = false, ++ .empty_page_check = false, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7622, ++ .spare_sizes = mt7622_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++}; ++ ++static const struct mtk_snand_caps mt7629_snand_caps = { ++ .sector_size = 512, ++ .max_sectors = 8, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 32, ++ .bbm_swap = true, ++ .empty_page_check = false, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7622, ++ .spare_sizes = mt7622_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++}; ++ ++struct mtk_snand_conf { ++ size_t page_size; ++ size_t oob_size; ++ u8 nsectors; ++ u8 spare_size; ++}; ++ ++struct mtk_snand { ++ struct spi_controller *ctlr; ++ struct device *dev; ++ struct clk *nfi_clk; ++ struct clk *pad_clk; ++ void __iomem *nfi_base; ++ int irq; ++ struct completion op_done; ++ const struct mtk_snand_caps *caps; ++ struct mtk_ecc_config *ecc_cfg; ++ struct mtk_ecc *ecc; ++ struct mtk_snand_conf nfi_cfg; ++ struct mtk_ecc_stats ecc_stats; ++ struct nand_ecc_engine ecc_eng; ++ bool autofmt; ++ u8 *buf; ++ size_t buf_len; ++}; ++ ++static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand) ++{ ++ struct nand_ecc_engine *eng = nand->ecc.engine; ++ ++ return container_of(eng, struct mtk_snand, ecc_eng); ++} ++ ++static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size) ++{ ++ if (snf->buf_len >= size) ++ return 0; ++ kfree(snf->buf); ++ snf->buf = kmalloc(size, GFP_KERNEL); ++ if (!snf->buf) ++ return -ENOMEM; ++ snf->buf_len = size; ++ memset(snf->buf, 0xff, snf->buf_len); ++ return 0; ++} ++ ++static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg) ++{ ++ return readl(snf->nfi_base + reg); ++} ++ ++static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val) ++{ ++ writel(val, snf->nfi_base + reg); ++} ++ ++static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val) ++{ ++ writew(val, snf->nfi_base + reg); ++} ++ ++static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set) ++{ ++ u32 val; ++ ++ val = readl(snf->nfi_base + reg); ++ val &= ~clr; ++ val |= set; ++ writel(val, snf->nfi_base + reg); ++} ++ ++static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len) ++{ ++ u32 i, val = 0, es = sizeof(u32); ++ ++ for (i = reg; i < reg + len; i++) { ++ if (i == reg || i % es == 0) ++ val = nfi_read32(snf, i & ~(es - 1)); ++ ++ *data++ = (u8)(val >> (8 * (i % es))); ++ } ++} ++ ++static int mtk_nfi_reset(struct mtk_snand *snf) ++{ ++ u32 val, fifo_mask; ++ int ret; ++ ++ nfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST); ++ ++ ret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->caps->mastersta_mask), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "NFI master is still busy after reset\n"); ++ return ret; ++ } ++ ++ ret = readl_poll_timeout(snf->nfi_base + NFI_STA, val, ++ !(val & (NFI_FSM | NFI_NAND_FSM)), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Failed to reset NFI\n"); ++ return ret; ++ } ++ ++ fifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) | ++ ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S); ++ ret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val, ++ !(val & fifo_mask), 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "NFI FIFOs are not empty\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int mtk_snand_mac_reset(struct mtk_snand *snf) ++{ ++ int ret; ++ u32 val; ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST); ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val, ++ !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Failed to reset SNFI MAC\n"); ++ ++ nfi_write32(snf, SNF_MISC_CTL, ++ (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S)); ++ ++ return ret; ++} ++ ++static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen) ++{ ++ int ret; ++ u32 val; ++ ++ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN); ++ nfi_write32(snf, SNF_MAC_OUTL, outlen); ++ nfi_write32(snf, SNF_MAC_INL, inlen); ++ ++ nfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG); ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, ++ val & WIP_READY, 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for WIP_READY\n"); ++ goto cleanup; ++ } ++ ++ ret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP), ++ 0, SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Timed out waiting for WIP cleared\n"); ++ ++cleanup: ++ nfi_write32(snf, SNF_MAC_CTL, 0); ++ ++ return ret; ++} ++ ++static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op) ++{ ++ u32 rx_len = 0; ++ u32 reg_offs = 0; ++ u32 val = 0; ++ const u8 *tx_buf = NULL; ++ u8 *rx_buf = NULL; ++ int i, ret; ++ u8 b; ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ rx_len = op->data.nbytes; ++ rx_buf = op->data.buf.in; ++ } else { ++ tx_buf = op->data.buf.out; ++ } ++ ++ mtk_snand_mac_reset(snf); ++ ++ for (i = 0; i < op->cmd.nbytes; i++, reg_offs++) { ++ b = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff; ++ val |= b << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ for (i = 0; i < op->addr.nbytes; i++, reg_offs++) { ++ b = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff; ++ val |= b << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ for (i = 0; i < op->dummy.nbytes; i++, reg_offs++) { ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) { ++ for (i = 0; i < op->data.nbytes; i++, reg_offs++) { ++ val |= tx_buf[i] << (8 * (reg_offs % 4)); ++ if (reg_offs % 4 == 3) { ++ nfi_write32(snf, SNF_GPRAM + reg_offs - 3, val); ++ val = 0; ++ } ++ } ++ } ++ ++ if (reg_offs % 4) ++ nfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val); ++ ++ for (i = 0; i < reg_offs; i += 4) ++ dev_dbg(snf->dev, "%d: %08X", i, ++ nfi_read32(snf, SNF_GPRAM + i)); ++ ++ dev_dbg(snf->dev, "SNF TX: %u RX: %u", reg_offs, rx_len); ++ ++ ret = mtk_snand_mac_trigger(snf, reg_offs, rx_len); ++ if (ret) ++ return ret; ++ ++ if (!rx_len) ++ return 0; ++ ++ nfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len); ++ return 0; ++} ++ ++static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size, ++ u32 oob_size) ++{ ++ int spare_idx = -1; ++ u32 spare_size, spare_size_shift, pagesize_idx; ++ u32 sector_size_512; ++ u8 nsectors; ++ int i; ++ ++ // skip if it's already configured as required. ++ if (snf->nfi_cfg.page_size == page_size && ++ snf->nfi_cfg.oob_size == oob_size) ++ return 0; ++ ++ nsectors = page_size / snf->caps->sector_size; ++ if (nsectors > snf->caps->max_sectors) { ++ dev_err(snf->dev, "too many sectors required.\n"); ++ goto err; ++ } ++ ++ if (snf->caps->sector_size == 512) { ++ sector_size_512 = NFI_SEC_SEL_512; ++ spare_size_shift = NFI_SPARE_SIZE_S; ++ } else { ++ sector_size_512 = 0; ++ spare_size_shift = NFI_SPARE_SIZE_LS_S; ++ } ++ ++ switch (page_size) { ++ case SZ_512: ++ pagesize_idx = NFI_PAGE_SIZE_512_2K; ++ break; ++ case SZ_2K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_2K_4K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_512_2K; ++ break; ++ case SZ_4K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_4K_8K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_2K_4K; ++ break; ++ case SZ_8K: ++ if (snf->caps->sector_size == 512) ++ pagesize_idx = NFI_PAGE_SIZE_8K_16K; ++ else ++ pagesize_idx = NFI_PAGE_SIZE_4K_8K; ++ break; ++ case SZ_16K: ++ pagesize_idx = NFI_PAGE_SIZE_8K_16K; ++ break; ++ default: ++ dev_err(snf->dev, "unsupported page size.\n"); ++ goto err; ++ } ++ ++ spare_size = oob_size / nsectors; ++ // If we're using the 1KB sector size, HW will automatically double the ++ // spare size. We should only use half of the value in this case. ++ if (snf->caps->sector_size == 1024) ++ spare_size /= 2; ++ ++ for (i = snf->caps->num_spare_size - 1; i >= 0; i--) { ++ if (snf->caps->spare_sizes[i] <= spare_size) { ++ spare_size = snf->caps->spare_sizes[i]; ++ if (snf->caps->sector_size == 1024) ++ spare_size *= 2; ++ spare_idx = i; ++ break; ++ } ++ } ++ ++ if (spare_idx < 0) { ++ dev_err(snf->dev, "unsupported spare size: %u\n", spare_size); ++ goto err; ++ } ++ ++ nfi_write32(snf, NFI_PAGEFMT, ++ (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) | ++ (snf->caps->fdm_size << NFI_FDM_NUM_S) | ++ (spare_idx << spare_size_shift) | ++ (pagesize_idx << NFI_PAGE_SIZE_S) | ++ sector_size_512); ++ ++ snf->nfi_cfg.page_size = page_size; ++ snf->nfi_cfg.oob_size = oob_size; ++ snf->nfi_cfg.nsectors = nsectors; ++ snf->nfi_cfg.spare_size = spare_size; ++ ++ dev_dbg(snf->dev, "page format: (%u + %u) * %u\n", ++ snf->caps->sector_size, spare_size, nsectors); ++ return snand_prepare_bouncebuf(snf, page_size + oob_size); ++err: ++ dev_err(snf->dev, "page size %u + %u is not supported\n", page_size, ++ oob_size); ++ return -EOPNOTSUPP; ++} ++ ++static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobecc) ++{ ++ // ECC area is not accessible ++ return -ERANGE; ++} ++ ++static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *oobfree) ++{ ++ struct nand_device *nand = mtd_to_nanddev(mtd); ++ struct mtk_snand *ms = nand_to_mtk_snand(nand); ++ ++ if (section >= ms->nfi_cfg.nsectors) ++ return -ERANGE; ++ ++ oobfree->length = ms->caps->fdm_size - 1; ++ oobfree->offset = section * ms->caps->fdm_size + 1; ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops mtk_snand_ooblayout = { ++ .ecc = mtk_snand_ooblayout_ecc, ++ .free = mtk_snand_ooblayout_free, ++}; ++ ++static int mtk_snand_ecc_init_ctx(struct nand_device *nand) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct nand_ecc_props *conf = &nand->ecc.ctx.conf; ++ struct nand_ecc_props *reqs = &nand->ecc.requirements; ++ struct nand_ecc_props *user = &nand->ecc.user_conf; ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ int step_size = 0, strength = 0, desired_correction = 0, steps; ++ bool ecc_user = false; ++ int ret; ++ u32 parity_bits, max_ecc_bytes; ++ struct mtk_ecc_config *ecc_cfg; ++ ++ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, ++ nand->memorg.oobsize); ++ if (ret) ++ return ret; ++ ++ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); ++ if (!ecc_cfg) ++ return -ENOMEM; ++ ++ nand->ecc.ctx.priv = ecc_cfg; ++ ++ if (user->step_size && user->strength) { ++ step_size = user->step_size; ++ strength = user->strength; ++ ecc_user = true; ++ } else if (reqs->step_size && reqs->strength) { ++ step_size = reqs->step_size; ++ strength = reqs->strength; ++ } ++ ++ if (step_size && strength) { ++ steps = mtd->writesize / step_size; ++ desired_correction = steps * strength; ++ strength = desired_correction / snf->nfi_cfg.nsectors; ++ } ++ ++ ecc_cfg->mode = ECC_NFI_MODE; ++ ecc_cfg->sectors = snf->nfi_cfg.nsectors; ++ ecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size; ++ ++ // calculate the max possible strength under current page format ++ parity_bits = mtk_ecc_get_parity_bits(snf->ecc); ++ max_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size; ++ ecc_cfg->strength = max_ecc_bytes * 8 / parity_bits; ++ mtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength); ++ ++ // if there's a user requested strength, find the minimum strength that ++ // meets the requirement. Otherwise use the maximum strength which is ++ // expected by BootROM. ++ if (ecc_user && strength) { ++ u32 s_next = ecc_cfg->strength - 1; ++ ++ while (1) { ++ mtk_ecc_adjust_strength(snf->ecc, &s_next); ++ if (s_next >= ecc_cfg->strength) ++ break; ++ if (s_next < strength) ++ break; ++ s_next = ecc_cfg->strength - 1; ++ } ++ } ++ ++ mtd_set_ooblayout(mtd, &mtk_snand_ooblayout); ++ ++ conf->step_size = snf->caps->sector_size; ++ conf->strength = ecc_cfg->strength; ++ ++ if (ecc_cfg->strength < strength) ++ dev_warn(snf->dev, "unable to fulfill ECC of %u bits.\n", ++ strength); ++ dev_info(snf->dev, "ECC strength: %u bits per %u bytes\n", ++ ecc_cfg->strength, snf->caps->sector_size); ++ ++ return 0; ++} ++ ++static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand) ++{ ++ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); ++ ++ kfree(ecc_cfg); ++} ++ ++static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand, ++ struct nand_page_io_req *req) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand); ++ int ret; ++ ++ ret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize, ++ nand->memorg.oobsize); ++ if (ret) ++ return ret; ++ snf->autofmt = true; ++ snf->ecc_cfg = ecc_cfg; ++ return 0; ++} ++ ++static int mtk_snand_ecc_finish_io_req(struct nand_device *nand, ++ struct nand_page_io_req *req) ++{ ++ struct mtk_snand *snf = nand_to_mtk_snand(nand); ++ struct mtd_info *mtd = nanddev_to_mtd(nand); ++ ++ snf->ecc_cfg = NULL; ++ snf->autofmt = false; ++ if ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ)) ++ return 0; ++ ++ if (snf->ecc_stats.failed) ++ mtd->ecc_stats.failed += snf->ecc_stats.failed; ++ mtd->ecc_stats.corrected += snf->ecc_stats.corrected; ++ return snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips; ++} ++ ++static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = { ++ .init_ctx = mtk_snand_ecc_init_ctx, ++ .cleanup_ctx = mtk_snand_ecc_cleanup_ctx, ++ .prepare_io_req = mtk_snand_ecc_prepare_io_req, ++ .finish_io_req = mtk_snand_ecc_finish_io_req, ++}; ++ ++static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf) ++{ ++ u32 vall, valm; ++ u8 *oobptr = buf; ++ int i, j; ++ ++ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { ++ vall = nfi_read32(snf, NFI_FDML(i)); ++ valm = nfi_read32(snf, NFI_FDMM(i)); ++ ++ for (j = 0; j < snf->caps->fdm_size; j++) ++ oobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8); ++ ++ oobptr += snf->caps->fdm_size; ++ } ++} ++ ++static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf) ++{ ++ u32 fdm_size = snf->caps->fdm_size; ++ const u8 *oobptr = buf; ++ u32 vall, valm; ++ int i, j; ++ ++ for (i = 0; i < snf->nfi_cfg.nsectors; i++) { ++ vall = 0; ++ valm = 0; ++ ++ for (j = 0; j < 8; j++) { ++ if (j < 4) ++ vall |= (j < fdm_size ? oobptr[j] : 0xff) ++ << (j * 8); ++ else ++ valm |= (j < fdm_size ? oobptr[j] : 0xff) ++ << ((j - 4) * 8); ++ } ++ ++ nfi_write32(snf, NFI_FDML(i), vall); ++ nfi_write32(snf, NFI_FDMM(i), valm); ++ ++ oobptr += fdm_size; ++ } ++} ++ ++static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf) ++{ ++ u32 buf_bbm_pos, fdm_bbm_pos; ++ ++ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) ++ return; ++ ++ // swap [pagesize] byte on nand with the first fdm byte ++ // in the last sector. ++ buf_bbm_pos = snf->nfi_cfg.page_size - ++ (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size; ++ fdm_bbm_pos = snf->nfi_cfg.page_size + ++ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; ++ ++ swap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]); ++} ++ ++static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf) ++{ ++ u32 fdm_bbm_pos1, fdm_bbm_pos2; ++ ++ if (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1) ++ return; ++ ++ // swap the first fdm byte in the first and the last sector. ++ fdm_bbm_pos1 = snf->nfi_cfg.page_size; ++ fdm_bbm_pos2 = snf->nfi_cfg.page_size + ++ (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size; ++ swap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]); ++} ++ ++static int mtk_snand_read_page_cache(struct mtk_snand *snf, ++ const struct spi_mem_op *op) ++{ ++ u8 *buf = snf->buf; ++ u8 *buf_fdm = buf + snf->nfi_cfg.page_size; ++ // the address part to be sent by the controller ++ u32 op_addr = op->addr.val; ++ // where to start copying data from bounce buffer ++ u32 rd_offset = 0; ++ u32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth); ++ u32 op_mode = 0; ++ u32 dma_len = snf->buf_len; ++ int ret = 0; ++ u32 rd_mode, rd_bytes, val; ++ dma_addr_t buf_dma; ++ ++ if (snf->autofmt) { ++ u32 last_bit; ++ u32 mask; ++ ++ dma_len = snf->nfi_cfg.page_size; ++ op_mode = CNFG_AUTO_FMT_EN; ++ if (op->data.ecc) ++ op_mode |= CNFG_HW_ECC_EN; ++ // extract the plane bit: ++ // Find the highest bit set in (pagesize+oobsize). ++ // Bits higher than that in op->addr are kept and sent over SPI ++ // Lower bits are used as an offset for copying data from DMA ++ // bounce buffer. ++ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); ++ mask = (1 << last_bit) - 1; ++ rd_offset = op_addr & mask; ++ op_addr &= ~mask; ++ ++ // check if we can dma to the caller memory ++ if (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size) ++ buf = op->data.buf.in; ++ } ++ mtk_snand_mac_reset(snf); ++ mtk_nfi_reset(snf); ++ ++ // command and dummy cycles ++ nfi_write32(snf, SNF_RD_CTL2, ++ (dummy_clk << DATA_READ_DUMMY_S) | ++ (op->cmd.opcode << DATA_READ_CMD_S)); ++ ++ // read address ++ nfi_write32(snf, SNF_RD_CTL3, op_addr); ++ ++ // Set read op_mode ++ if (op->data.buswidth == 4) ++ rd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD : ++ DATA_READ_MODE_X4; ++ else if (op->data.buswidth == 2) ++ rd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL : ++ DATA_READ_MODE_X2; ++ else ++ rd_mode = DATA_READ_MODE_X1; ++ rd_mode <<= DATA_READ_MODE_S; ++ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, ++ rd_mode | DATARD_CUSTOM_EN); ++ ++ // Set bytes to read ++ rd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * ++ snf->nfi_cfg.nsectors; ++ nfi_write32(snf, SNF_MISC_CTL2, ++ (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes); ++ ++ // NFI read prepare ++ nfi_write16(snf, NFI_CNFG, ++ (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN | ++ CNFG_READ_MODE | CNFG_DMA_MODE | op_mode); ++ ++ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); ++ ++ buf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE); ++ if (dma_mapping_error(snf->dev, buf_dma)) { ++ dev_err(snf->dev, "DMA mapping failed.\n"); ++ goto cleanup; ++ } ++ nfi_write32(snf, NFI_STRADDR, buf_dma); ++ if (op->data.ecc) { ++ snf->ecc_cfg->op = ECC_DECODE; ++ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); ++ if (ret) ++ goto cleanup_dma; ++ } ++ // Prepare for custom read interrupt ++ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ); ++ reinit_completion(&snf->op_done); ++ ++ // Trigger NFI into custom mode ++ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ); ++ ++ // Start DMA read ++ nfi_rmw32(snf, NFI_CON, 0, CON_BRD); ++ nfi_write16(snf, NFI_STRDATA, STR_DATA); ++ ++ if (!wait_for_completion_timeout( ++ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { ++ dev_err(snf->dev, "DMA timed out for reading from cache.\n"); ++ ret = -ETIMEDOUT; ++ goto cleanup; ++ } ++ ++ // Wait for BUS_SEC_CNTR returning expected value ++ ret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, ++ BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for BUS_SEC_CNTR\n"); ++ goto cleanup2; ++ } ++ ++ // Wait for bus becoming idle ++ ret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->caps->mastersta_mask), 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) { ++ dev_err(snf->dev, "Timed out waiting for bus becoming idle\n"); ++ goto cleanup2; ++ } ++ ++ if (op->data.ecc) { ++ ret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE); ++ if (ret) { ++ dev_err(snf->dev, "wait ecc done timeout\n"); ++ goto cleanup2; ++ } ++ // save status before disabling ecc ++ mtk_ecc_get_stats(snf->ecc, &snf->ecc_stats, ++ snf->nfi_cfg.nsectors); ++ } ++ ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); ++ ++ if (snf->autofmt) { ++ mtk_snand_read_fdm(snf, buf_fdm); ++ if (snf->caps->bbm_swap) { ++ mtk_snand_bm_swap(snf, buf); ++ mtk_snand_fdm_bm_swap(snf); ++ } ++ } ++ ++ // copy data back ++ if (nfi_read32(snf, NFI_STA) & READ_EMPTY) { ++ memset(op->data.buf.in, 0xff, op->data.nbytes); ++ snf->ecc_stats.bitflips = 0; ++ snf->ecc_stats.failed = 0; ++ snf->ecc_stats.corrected = 0; ++ } else { ++ if (buf == op->data.buf.in) { ++ u32 cap_len = snf->buf_len - snf->nfi_cfg.page_size; ++ u32 req_left = op->data.nbytes - snf->nfi_cfg.page_size; ++ ++ if (req_left) ++ memcpy(op->data.buf.in + snf->nfi_cfg.page_size, ++ buf_fdm, ++ cap_len < req_left ? cap_len : req_left); ++ } else if (rd_offset < snf->buf_len) { ++ u32 cap_len = snf->buf_len - rd_offset; ++ ++ if (op->data.nbytes < cap_len) ++ cap_len = op->data.nbytes; ++ memcpy(op->data.buf.in, snf->buf + rd_offset, cap_len); ++ } ++ } ++cleanup2: ++ if (op->data.ecc) ++ mtk_ecc_disable(snf->ecc); ++cleanup_dma: ++ // unmap dma only if any error happens. (otherwise it's done before ++ // data copying) ++ if (ret) ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE); ++cleanup: ++ // Stop read ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); ++ ++ // Clear SNF done flag ++ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); ++ nfi_write32(snf, SNF_STA_CTL1, 0); ++ ++ // Disable interrupt ++ nfi_read32(snf, NFI_INTR_STA); ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); ++ return ret; ++} ++ ++static int mtk_snand_write_page_cache(struct mtk_snand *snf, ++ const struct spi_mem_op *op) ++{ ++ // the address part to be sent by the controller ++ u32 op_addr = op->addr.val; ++ // where to start copying data from bounce buffer ++ u32 wr_offset = 0; ++ u32 op_mode = 0; ++ int ret = 0; ++ u32 wr_mode = 0; ++ u32 dma_len = snf->buf_len; ++ u32 wr_bytes, val; ++ size_t cap_len; ++ dma_addr_t buf_dma; ++ ++ if (snf->autofmt) { ++ u32 last_bit; ++ u32 mask; ++ ++ dma_len = snf->nfi_cfg.page_size; ++ op_mode = CNFG_AUTO_FMT_EN; ++ if (op->data.ecc) ++ op_mode |= CNFG_HW_ECC_EN; ++ ++ last_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size); ++ mask = (1 << last_bit) - 1; ++ wr_offset = op_addr & mask; ++ op_addr &= ~mask; ++ } ++ mtk_snand_mac_reset(snf); ++ mtk_nfi_reset(snf); ++ ++ if (wr_offset) ++ memset(snf->buf, 0xff, wr_offset); ++ ++ cap_len = snf->buf_len - wr_offset; ++ if (op->data.nbytes < cap_len) ++ cap_len = op->data.nbytes; ++ memcpy(snf->buf + wr_offset, op->data.buf.out, cap_len); ++ if (snf->autofmt) { ++ if (snf->caps->bbm_swap) { ++ mtk_snand_fdm_bm_swap(snf); ++ mtk_snand_bm_swap(snf, snf->buf); ++ } ++ mtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size); ++ } ++ ++ // Command ++ nfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S)); ++ ++ // write address ++ nfi_write32(snf, SNF_PG_CTL2, op_addr); ++ ++ // Set read op_mode ++ if (op->data.buswidth == 4) ++ wr_mode = PG_LOAD_X4_EN; ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, ++ wr_mode | PG_LOAD_CUSTOM_EN); ++ ++ // Set bytes to write ++ wr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) * ++ snf->nfi_cfg.nsectors; ++ nfi_write32(snf, SNF_MISC_CTL2, ++ (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes); ++ ++ // NFI write prepare ++ nfi_write16(snf, NFI_CNFG, ++ (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) | ++ CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode); ++ ++ nfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S)); ++ buf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE); ++ if (dma_mapping_error(snf->dev, buf_dma)) { ++ dev_err(snf->dev, "DMA mapping failed.\n"); ++ goto cleanup; ++ } ++ nfi_write32(snf, NFI_STRADDR, buf_dma); ++ if (op->data.ecc) { ++ snf->ecc_cfg->op = ECC_ENCODE; ++ ret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg); ++ if (ret) ++ goto cleanup_dma; ++ } ++ // Prepare for custom write interrupt ++ nfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG); ++ reinit_completion(&snf->op_done); ++ ; ++ ++ // Trigger NFI into custom mode ++ nfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE); ++ ++ // Start DMA write ++ nfi_rmw32(snf, NFI_CON, 0, CON_BWR); ++ nfi_write16(snf, NFI_STRDATA, STR_DATA); ++ ++ if (!wait_for_completion_timeout( ++ &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) { ++ dev_err(snf->dev, "DMA timed out for program load.\n"); ++ ret = -ETIMEDOUT; ++ goto cleanup_ecc; ++ } ++ ++ // Wait for NFI_SEC_CNTR returning expected value ++ ret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, ++ NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0, ++ SNFI_POLL_INTERVAL); ++ if (ret) ++ dev_err(snf->dev, "Timed out waiting for NFI_SEC_CNTR\n"); ++ ++cleanup_ecc: ++ if (op->data.ecc) ++ mtk_ecc_disable(snf->ecc); ++cleanup_dma: ++ dma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE); ++cleanup: ++ // Stop write ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); ++ ++ // Clear SNF done flag ++ nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); ++ nfi_write32(snf, SNF_STA_CTL1, 0); ++ ++ // Disable interrupt ++ nfi_read32(snf, NFI_INTR_STA); ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ ++ nfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0); ++ ++ return ret; ++} ++ ++/** ++ * mtk_snand_is_page_ops() - check if the op is a controller supported page op. ++ * @op spi-mem op to check ++ * ++ * Check whether op can be executed with read_from_cache or program_load ++ * mode in the controller. ++ * This controller can execute typical Read From Cache and Program Load ++ * instructions found on SPI-NAND with 2-byte address. ++ * DTR and cmd buswidth & nbytes should be checked before calling this. ++ * ++ * Return: true if the op matches the instruction template ++ */ ++static bool mtk_snand_is_page_ops(const struct spi_mem_op *op) ++{ ++ if (op->addr.nbytes != 2) ++ return false; ++ ++ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && ++ op->addr.buswidth != 4) ++ return false; ++ ++ // match read from page instructions ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ // check dummy cycle first ++ if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > ++ DATA_READ_MAX_DUMMY) ++ return false; ++ // quad io / quad out ++ if ((op->addr.buswidth == 4 || op->addr.buswidth == 1) && ++ op->data.buswidth == 4) ++ return true; ++ ++ // dual io / dual out ++ if ((op->addr.buswidth == 2 || op->addr.buswidth == 1) && ++ op->data.buswidth == 2) ++ return true; ++ ++ // standard spi ++ if (op->addr.buswidth == 1 && op->data.buswidth == 1) ++ return true; ++ } else if (op->data.dir == SPI_MEM_DATA_OUT) { ++ // check dummy cycle first ++ if (op->dummy.nbytes) ++ return false; ++ // program load quad out ++ if (op->addr.buswidth == 1 && op->data.buswidth == 4) ++ return true; ++ // standard spi ++ if (op->addr.buswidth == 1 && op->data.buswidth == 1) ++ return true; ++ } ++ return false; ++} ++ ++static bool mtk_snand_supports_op(struct spi_mem *mem, ++ const struct spi_mem_op *op) ++{ ++ if (!spi_mem_default_supports_op(mem, op)) ++ return false; ++ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) ++ return false; ++ if (mtk_snand_is_page_ops(op)) ++ return true; ++ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) && ++ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) && ++ (op->data.nbytes == 0 || op->data.buswidth == 1)); ++} ++ ++static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) ++{ ++ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); ++ // page ops transfer size must be exactly ((sector_size + spare_size) * ++ // nsectors). Limit the op size if the caller requests more than that. ++ // exec_op will read more than needed and discard the leftover if the ++ // caller requests less data. ++ if (mtk_snand_is_page_ops(op)) { ++ size_t l; ++ // skip adjust_op_size for page ops ++ if (ms->autofmt) ++ return 0; ++ l = ms->caps->sector_size + ms->nfi_cfg.spare_size; ++ l *= ms->nfi_cfg.nsectors; ++ if (op->data.nbytes > l) ++ op->data.nbytes = l; ++ } else { ++ size_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; ++ ++ if (hl >= SNF_GPRAM_SIZE) ++ return -EOPNOTSUPP; ++ if (op->data.nbytes > SNF_GPRAM_SIZE - hl) ++ op->data.nbytes = SNF_GPRAM_SIZE - hl; ++ } ++ return 0; ++} ++ ++static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) ++{ ++ struct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master); ++ ++ dev_dbg(ms->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, ++ op->addr.val, op->addr.buswidth, op->addr.nbytes, ++ op->data.buswidth, op->data.nbytes); ++ if (mtk_snand_is_page_ops(op)) { ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ return mtk_snand_read_page_cache(ms, op); ++ else ++ return mtk_snand_write_page_cache(ms, op); ++ } else { ++ return mtk_snand_mac_io(ms, op); ++ } ++} ++ ++static const struct spi_controller_mem_ops mtk_snand_mem_ops = { ++ .adjust_op_size = mtk_snand_adjust_op_size, ++ .supports_op = mtk_snand_supports_op, ++ .exec_op = mtk_snand_exec_op, ++}; ++ ++static const struct spi_controller_mem_caps mtk_snand_mem_caps = { ++ .ecc = true, ++}; ++ ++static irqreturn_t mtk_snand_irq(int irq, void *id) ++{ ++ struct mtk_snand *snf = id; ++ u32 sta, ien; ++ ++ sta = nfi_read32(snf, NFI_INTR_STA); ++ ien = nfi_read32(snf, NFI_INTR_EN); ++ ++ if (!(sta & ien)) ++ return IRQ_NONE; ++ ++ nfi_write32(snf, NFI_INTR_EN, 0); ++ complete(&snf->op_done); ++ return IRQ_HANDLED; ++} ++ ++static const struct of_device_id mtk_snand_ids[] = { ++ { .compatible = "mediatek,mt7622-snand", .data = &mt7622_snand_caps }, ++ { .compatible = "mediatek,mt7629-snand", .data = &mt7629_snand_caps }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, mtk_snand_ids); ++ ++static int mtk_snand_enable_clk(struct mtk_snand *ms) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(ms->nfi_clk); ++ if (ret) { ++ dev_err(ms->dev, "unable to enable nfi clk\n"); ++ return ret; ++ } ++ ret = clk_prepare_enable(ms->pad_clk); ++ if (ret) { ++ dev_err(ms->dev, "unable to enable pad clk\n"); ++ goto err1; ++ } ++ return 0; ++err1: ++ clk_disable_unprepare(ms->nfi_clk); ++ return ret; ++} ++ ++static void mtk_snand_disable_clk(struct mtk_snand *ms) ++{ ++ clk_disable_unprepare(ms->pad_clk); ++ clk_disable_unprepare(ms->nfi_clk); ++} ++ ++static int mtk_snand_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ const struct of_device_id *dev_id; ++ struct spi_controller *ctlr; ++ struct mtk_snand *ms; ++ int ret; ++ ++ dev_id = of_match_node(mtk_snand_ids, np); ++ if (!dev_id) ++ return -EINVAL; ++ ++ ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms)); ++ if (!ctlr) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, ctlr); ++ ++ ms = spi_controller_get_devdata(ctlr); ++ ++ ms->ctlr = ctlr; ++ ms->caps = dev_id->data; ++ ++ ms->ecc = of_mtk_ecc_get(np); ++ if (IS_ERR(ms->ecc)) ++ return PTR_ERR(ms->ecc); ++ else if (!ms->ecc) ++ return -ENODEV; ++ ++ ms->nfi_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(ms->nfi_base)) { ++ ret = PTR_ERR(ms->nfi_base); ++ goto release_ecc; ++ } ++ ++ ms->dev = &pdev->dev; ++ ++ ms->nfi_clk = devm_clk_get(&pdev->dev, "nfi_clk"); ++ if (IS_ERR(ms->nfi_clk)) { ++ ret = PTR_ERR(ms->nfi_clk); ++ dev_err(&pdev->dev, "unable to get nfi_clk, err = %d\n", ret); ++ goto release_ecc; ++ } ++ ++ ms->pad_clk = devm_clk_get(&pdev->dev, "pad_clk"); ++ if (IS_ERR(ms->pad_clk)) { ++ ret = PTR_ERR(ms->pad_clk); ++ dev_err(&pdev->dev, "unable to get pad_clk, err = %d\n", ret); ++ goto release_ecc; ++ } ++ ++ ret = mtk_snand_enable_clk(ms); ++ if (ret) ++ goto release_ecc; ++ ++ init_completion(&ms->op_done); ++ ++ ms->irq = platform_get_irq(pdev, 0); ++ if (ms->irq < 0) { ++ ret = ms->irq; ++ goto disable_clk; ++ } ++ ret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0, ++ "mtk-snand", ms); ++ if (ret) { ++ dev_err(ms->dev, "failed to request snfi irq\n"); ++ goto disable_clk; ++ } ++ ++ ret = dma_set_mask(ms->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(ms->dev, "failed to set dma mask\n"); ++ goto disable_clk; ++ } ++ ++ // switch to SNFI mode ++ nfi_write32(ms, SNF_CFG, SPI_MODE); ++ ++ // setup an initial page format for ops matching page_cache_op template ++ // before ECC is called. ++ ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, ++ ms->caps->spare_sizes[0]); ++ if (ret) { ++ dev_err(ms->dev, "failed to set initial page format\n"); ++ goto disable_clk; ++ } ++ ++ // setup ECC engine ++ ms->ecc_eng.dev = &pdev->dev; ++ ms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; ++ ms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops; ++ ms->ecc_eng.priv = ms; ++ ++ ret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register ecc engine.\n"); ++ goto disable_clk; ++ } ++ ++ ctlr->num_chipselect = 1; ++ ctlr->mem_ops = &mtk_snand_mem_ops; ++ ctlr->mem_caps = &mtk_snand_mem_caps; ++ ctlr->bits_per_word_mask = SPI_BPW_MASK(8); ++ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ++ ctlr->dev.of_node = pdev->dev.of_node; ++ ret = spi_register_controller(ctlr); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_register_controller failed.\n"); ++ goto disable_clk; ++ } ++ ++ return 0; ++disable_clk: ++ mtk_snand_disable_clk(ms); ++release_ecc: ++ mtk_ecc_release(ms->ecc); ++ return ret; ++} ++ ++static int mtk_snand_remove(struct platform_device *pdev) ++{ ++ struct spi_controller *ctlr = platform_get_drvdata(pdev); ++ struct mtk_snand *ms = spi_controller_get_devdata(ctlr); ++ ++ spi_unregister_controller(ctlr); ++ mtk_snand_disable_clk(ms); ++ mtk_ecc_release(ms->ecc); ++ kfree(ms->buf); ++ return 0; ++} ++ ++static struct platform_driver mtk_snand_driver = { ++ .probe = mtk_snand_probe, ++ .remove = mtk_snand_remove, ++ .driver = { ++ .name = "mtk-snand", ++ .of_match_table = mtk_snand_ids, ++ }, ++}; ++ ++module_platform_driver(mtk_snand_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Chuanhong Guo "); ++MODULE_DESCRIPTION("MeidaTek SPI-NAND Flash Controller Driver"); diff --git a/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch b/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch new file mode 100644 index 000000000..01d9d1208 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-13-v5.19-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch @@ -0,0 +1,30 @@ +From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Mon, 4 Apr 2022 00:05:38 +0800 +Subject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if + available + +The recently added ECC engine support introduced a generic property +named nand-ecc-engine for ecc engine phandle. This patch adds support +for this new property. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54) +--- + drivers/mtd/nand/ecc-mtk.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/nand/ecc-mtk.c ++++ b/drivers/mtd/nand/ecc-mtk.c +@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de + struct mtk_ecc *ecc = NULL; + struct device_node *np; + +- np = of_parse_phandle(of_node, "ecc-engine", 0); ++ np = of_parse_phandle(of_node, "nand-ecc-engine", 0); ++ /* for backward compatibility */ ++ if (!np) ++ np = of_parse_phandle(of_node, "ecc-engine", 0); + if (np) { + ecc = mtk_ecc_get(np); + of_node_put(np); diff --git a/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch new file mode 100644 index 000000000..d5285676f --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-14-v5.19-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch @@ -0,0 +1,35 @@ +From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo +Date: Sun, 3 Apr 2022 10:19:29 +0800 +Subject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622 + +This patch adds a device-tree node for the MTK SPI-NAND Flash Interface +for MT7622 device tree. + +Signed-off-by: Chuanhong Guo +(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af) +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -552,6 +552,18 @@ + status = "disabled"; + }; + ++ snfi: spi@1100d000 { ++ compatible = "mediatek,mt7622-snand"; ++ reg = <0 0x1100d000 0 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + bch: ecc@1100e000 { + compatible = "mediatek,mt7622-ecc"; + reg = <0 0x1100e000 0 0x1000>; diff --git a/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch new file mode 100644 index 000000000..770a7ff9b --- /dev/null +++ b/target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch @@ -0,0 +1,20 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -714,7 +714,7 @@ static int spinand_mtd_write(struct mtd_ + static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) + { + struct spinand_device *spinand = nand_to_spinand(nand); +- u8 marker[2] = { }; ++ u8 marker[1] = { }; + struct nand_page_io_req req = { + .pos = *pos, + .ooblen = sizeof(marker), +@@ -725,7 +725,7 @@ static bool spinand_isbad(struct nand_de + + spinand_select_target(spinand, pos->target); + spinand_read_page(spinand, &req); +- if (marker[0] != 0xff || marker[1] != 0xff) ++ if (marker[0] != 0xff) + return true; + + return false; diff --git a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch index e7c5d9b16..be0018a38 100644 --- a/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch @@ -11,63 +11,80 @@ Signed-off-by: Xiangsheng Hou --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,22 @@ +@@ -272,6 +272,27 @@ status = "disabled"; }; -+ snand: snfi@1100d000 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; ++ snfi: spi@1100d000 { + compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>, <0x1100e000 0x1000>; -+ reg-names = "nfi", "ecc"; ++ reg = <0x1100d000 0x1000>; + interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; ++ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; ++ clock-names = "nfi_clk", "pad_clk"; ++ nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; ++ ++ bch: ecc@1100e000 { ++ compatible = "mediatek,mt7622-ecc"; ++ reg = <0x1100e000 0x1000>; ++ interrupts = ; ++ clocks = <&pericfg CLK_PERI_NFIECC_PD>; ++ clock-names = "nfiecc_clk"; ++ status = "disabled"; ++ }; + spi: spi@1100a000 { compatible = "mediatek,mt7629-spi", "mediatek,mt7622-spi"; --- a/arch/arm/boot/dts/mt7629-rfb.dts +++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -254,6 +254,38 @@ +@@ -254,6 +254,50 @@ }; }; -+&snand { ++&bch { + status = "okay"; -+ mediatek,quad-spi; ++}; + -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; ++&snfi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&serial_nand_pins>; ++ status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; + -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; + -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; ++ partition@0 { ++ label = "Bootloader"; ++ reg = <0x00000 0x0100000>; ++ read-only; ++ }; + -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; ++ partition@100000 { ++ label = "Config"; ++ reg = <0x100000 0x0040000>; ++ }; + -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; ++ partition@140000 { ++ label = "factory"; ++ reg = <0x140000 0x0080000>; ++ }; ++ ++ partition@1c0000 { ++ label = "firmware"; ++ reg = <0x1c0000 0x1000000>; ++ }; + }; + }; +}; diff --git a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch index b8050b359..134e5997e 100644 --- a/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch +++ b/target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch @@ -1,77 +1,64 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -561,6 +561,20 @@ - status = "disabled"; - }; - -+ snand: snfi@1100d000 { -+ compatible = "mediatek,mt7622-snand"; -+ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>; -+ reg-names = "nfi", "ecc"; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, -+ <&pericfg CLK_PERI_SNFI_PD>, -+ <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfi_clk", "pad_clk", "ecc_clk"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - nor_flash: spi@11014000 { - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -539,6 +539,55 @@ +@@ -539,6 +539,65 @@ status = "disabled"; }; -+&snand { -+ mediatek,quad-spi; ++&bch { ++ status = "okay"; ++}; ++ ++&snfi { + pinctrl-names = "default"; + pinctrl-0 = <&serial_nand_pins>; + status = "okay"; ++ flash@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ nand-ecc-engine = <&snfi>; + -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; + -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; ++ partition@0 { ++ label = "Preloader"; ++ reg = <0x00000 0x0080000>; ++ read-only; ++ }; + -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; ++ partition@80000 { ++ label = "ATF"; ++ reg = <0x80000 0x0040000>; ++ }; + -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; ++ partition@c0000 { ++ label = "Bootloader"; ++ reg = <0xc0000 0x0080000>; ++ }; + -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; ++ partition@140000 { ++ label = "Config"; ++ reg = <0x140000 0x0080000>; ++ }; + -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; ++ partition@1c0000 { ++ label = "Factory"; ++ reg = <0x1c0000 0x0100000>; ++ }; + -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; ++ partition@200000 { ++ label = "firmware"; ++ reg = <0x2c0000 0x2000000>; ++ }; + -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; ++ partition@2200000 { ++ label = "User_data"; ++ reg = <0x22c0000 0x4000000>; ++ }; + }; + }; +}; diff --git a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch index b65c4a280..8e6935b43 100644 --- a/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ b/target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch @@ -1,15 +1,15 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -571,7 +571,7 @@ - reg = <0x140000 0x0080000>; - }; +@@ -580,7 +580,7 @@ + reg = <0x140000 0x0080000>; + }; -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -631,5 +631,6 @@ +- partition@1c0000 { ++ factory: partition@1c0000 { + label = "Factory"; + reg = <0x1c0000 0x0100000>; + }; +@@ -641,5 +641,6 @@ &wmac { pinctrl-names = "default"; pinctrl-0 = <&wmac_pins>; diff --git a/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch new file mode 100644 index 000000000..39a9770d9 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch @@ -0,0 +1,106 @@ +From patchwork Tue Apr 26 19:51:36 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Daniel Golle +X-Patchwork-Id: 12827872 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF + for ; 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Tue, 26 Apr 2022 19:51:57 +0000 +Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71]) + by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) + id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000 +Received: from local + by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) + (Exim 4.94.2) (envelope-from ) + id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200 +Date: Tue, 26 Apr 2022 20:51:36 +0100 +From: Daniel Golle +To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, + linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org +Cc: Rob Herring , + Krzysztof Kozlowski , + Matthias Brugger +Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range +Message-ID: +MIME-Version: 1.0 +Content-Disposition: inline +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C +X-CRM114-Status: GOOD ( 12.45 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +With the current range specified for the CPU interface there is an +error message at boot: + +GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set + +Setting irqchip.gicv2_force_probe=1 in bootargs results in: + +GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB +GIC: Adjusting CPU interface base to 0x000000001032f000 +GIC: Using split EOI/Deactivate mode + +Using the adjusted CPU interface base and 8K size results in only the +final line remaining and fully working system as well as /proc/interrupts +showing additional IPI3,4,5,6: + +IPI3: 0 0 CPU stop (for crash dump) interrupts +IPI4: 0 0 Timer broadcast interrupts +IPI5: 0 0 IRQ work interrupts +IPI6: 0 0 CPU wake-up interrupts + +Signed-off-by: Daniel Golle +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -339,7 +339,7 @@ + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10310000 0 0x1000>, +- <0 0x10320000 0 0x1000>, ++ <0 0x1032f000 0 0x2000>, + <0 0x10340000 0 0x2000>, + <0 0x10360000 0 0x2000>; + }; diff --git a/target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch b/target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch new file mode 100644 index 000000000..8851fefbb --- /dev/null +++ b/target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch @@ -0,0 +1,132 @@ +From patchwork Thu Apr 28 22:57:55 2022 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Rui Salvaterra +X-Patchwork-Id: 12831311 +Return-Path: + +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF + for ; 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+ Thu, 28 Apr 2022 15:58:06 -0700 (PDT) +From: Rui Salvaterra +To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org +Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, + Rui Salvaterra +Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology +Date: Thu, 28 Apr 2022 23:57:55 +0100 +Message-Id: <20220428225755.785153-1-rsalvaterra@gmail.com> +X-Mailer: git-send-email 2.36.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220428_155811_895571_B63D2806 +X-CRM114-Status: GOOD ( 10.27 ) +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +On an MT7622 system, the kernel complains of not being able to detect the cache +hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in +order to fix this. + +Signed-off-by: Rui Salvaterra +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -80,6 +80,7 @@ + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; ++ next-level-cache = <&L2>; + }; + + cpu1: cpu@1 { +@@ -94,6 +95,12 @@ + enable-method = "psci"; + clock-frequency = <1300000000>; + cci-control-port = <&cci_control2>; ++ next-level-cache = <&L2>; ++ }; ++ ++ L2: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; + }; + }; + diff --git a/target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch b/target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch new file mode 100644 index 000000000..905d84d31 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch @@ -0,0 +1,122 @@ +From patchwork Fri Apr 29 08:42:25 2022 +Content-Type: text/plain; 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+ Fri, 29 Apr 2022 01:42:32 -0700 (PDT) +Received: from crystalwell.adg.lan (a109-49-0-175.cpe.netcabo.pt. + [109.49.0.175]) by smtp.gmail.com with ESMTPSA id + el10-20020a170907284a00b006f3ef214e32sm429064ejc.152.2022.04.29.01.42.31 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Fri, 29 Apr 2022 01:42:31 -0700 (PDT) +From: Rui Salvaterra +To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, + linux-kernel@vger.kernel.org +Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org, + Rui Salvaterra +Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests +Date: Fri, 29 Apr 2022 09:42:25 +0100 +Message-Id: <20220429084225.298213-1-rsalvaterra@gmail.com> +X-Mailer: git-send-email 2.36.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20220429_014236_944696_097D1E73 +X-CRM114-Status: UNSURE ( 8.85 ) +X-CRM114-Notice: Please train this message. +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.34 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org + +The MT7622 device tree never bothered to specify the number of virtual DMA +channels for the HSDMA controller, always falling back to the default value of +3. Make this value explicit, in order to avoid the following dmesg notification: + +mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property + +Signed-off-by: Rui Salvaterra +--- + arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -941,6 +941,7 @@ + clock-names = "hsdma"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; + #dma-cells = <1>; ++ dma-requests = <3>; + }; + + pcie_mirror: pcie-mirror@10000400 { diff --git a/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support b/target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch similarity index 100% rename from target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support rename to target/linux/mediatek/patches-5.15/213-spi-mediatek-add-mt7986-spi-support.patch diff --git a/target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch b/target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch new file mode 100644 index 000000000..fa22ea82f --- /dev/null +++ b/target/linux/mediatek/patches-5.15/215-mtdblock-revert-warn-if-opened-on-NAND.patch @@ -0,0 +1,26 @@ +--- a/drivers/mtd/mtdblock.c ++++ b/drivers/mtd/mtdblock.c +@@ -257,10 +257,6 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd) + return 0; + } + +- if (mtd_type_is_nand(mbd->mtd)) +- pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", +- mbd->tr->name, mbd->mtd->name); +- + /* OK, it's not open. Create cache info for it */ + mtdblk->count = 1; + mutex_init(&mtdblk->cache_mutex); +--- a/drivers/mtd/mtdblock_ro.c ++++ b/drivers/mtd/mtdblock_ro.c +@@ -46,10 +46,6 @@ static void mtdblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd) + dev->tr = tr; + dev->readonly = 1; + +- if (mtd_type_is_nand(mtd)) +- pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", +- tr->name, mtd->name); +- + if (add_mtd_blktrans_dev(dev)) + kfree(dev); + } diff --git a/target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch deleted file mode 100644 index 318c8b287..000000000 --- a/target/linux/mediatek/patches-5.15/330-mtk-snand-bmt-support.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- a/drivers/mtd/mtk-snand/mtk-snand-mtd.c -+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -612,6 +613,8 @@ static int mtk_snand_probe(struct platfo - mtd->_block_isbad = mtk_snand_mtd_block_isbad; - mtd->_block_markbad = mtk_snand_mtd_block_markbad; - -+ mtk_bmt_attach(mtd); -+ - ret = mtd_device_register(mtd, NULL, 0); - if (ret) { - dev_err(msm->pdev.dev, "failed to register mtd partition\n"); -@@ -623,6 +626,7 @@ static int mtk_snand_probe(struct platfo - return 0; - - errout4: -+ mtk_bmt_detach(mtd); - devm_kfree(msm->pdev.dev, msm->page_cache); - - errout3: -@@ -650,6 +654,8 @@ static int mtk_snand_remove(struct platf - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); -+ - mtk_snand_cleanup(msm->snf); - - if (msm->irq >= 0) diff --git a/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch new file mode 100644 index 000000000..cd1745dd7 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch @@ -0,0 +1,34 @@ +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) + { +@@ -1333,6 +1334,7 @@ static int spinand_probe(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_attach(mtd); + ret = mtd_device_register(mtd, NULL, 0); + if (ret) + goto err_spinand_cleanup; +@@ -1340,6 +1342,7 @@ static int spinand_probe(struct spi_mem + return 0; + + err_spinand_cleanup: ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return ret; +@@ -1358,6 +1361,7 @@ static int spinand_remove(struct spi_mem + if (ret) + return ret; + ++ mtk_bmt_detach(mtd); + spinand_cleanup(spinand); + + return 0; diff --git a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch index 03c0771bc..9c1a8f284 100644 --- a/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch +++ b/target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch @@ -1,11 +1,10 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -545,6 +545,8 @@ - pinctrl-0 = <&serial_nand_pins>; - status = "okay"; +@@ -553,6 +553,7 @@ + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + nand-ecc-engine = <&snfi>; ++ mediatek,bmt-v2; -+ mediatek,bmt-v2; -+ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; + partitions { + compatible = "fixed-partitions"; diff --git a/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch new file mode 100644 index 000000000..4a5d814b3 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch @@ -0,0 +1,122 @@ +From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 +From: Davide Fioravanti +Date: Fri, 8 Jan 2021 15:35:24 +0100 +Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA + +Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf + +Signed-off-by: Davide Fioravanti +--- + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 1 + + drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spinand.h | 1 + + 4 files changed, 79 insertions(+), 1 deletion(-) + create mode 100644 drivers/mtd/nand/spi/fidelix.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 +-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o ++spinand-objs := core.o esmt.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -929,6 +929,7 @@ static const struct nand_ops spinand_ops + + static const struct spinand_manufacturer *spinand_manufacturers[] = { + &esmt_c8_spinand_manufacturer, ++ &fidelix_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/fidelix.c +@@ -0,0 +1,76 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Davide Fioravanti ++ */ ++ ++#include ++#include ++#include ++ ++#define SPINAND_MFR_FIDELIX 0xE5 ++#define FIDELIX_ECCSR_MASK 0x0F ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { ++ .ecc = fm35x1ga_ooblayout_ecc, ++ .free = fm35x1ga_ooblayout_free, ++}; ++ ++static const struct spinand_info fidelix_spinand_table[] = { ++ SPINAND_INFO("FM35X1GA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), ++}; ++ ++static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer fidelix_spinand_manufacturer = { ++ .id = SPINAND_MFR_FIDELIX, ++ .name = "Fidelix", ++ .chips = fidelix_spinand_table, ++ .nchips = ARRAY_SIZE(fidelix_spinand_table), ++ .ops = &fidelix_spinand_manuf_ops, ++}; +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -261,6 +261,7 @@ struct spinand_manufacturer { + + /* SPI NAND manufacturers */ + extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; ++extern const struct spinand_manufacturer fidelix_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch b/target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch deleted file mode 100644 index 149215c11..000000000 --- a/target/linux/mediatek/patches-5.15/360-mtd-add-mtk-snand-driver.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/mtd/Kconfig -+++ b/drivers/mtd/Kconfig -@@ -241,6 +241,8 @@ source "drivers/mtd/ubi/Kconfig" - - source "drivers/mtd/hyperbus/Kconfig" - -+source "drivers/mtd/mtk-snand/Kconfig" -+ - source "drivers/mtd/composite/Kconfig" - - endif # MTD ---- a/drivers/mtd/Makefile -+++ b/drivers/mtd/Makefile -@@ -34,5 +34,7 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ - obj-$(CONFIG_MTD_UBI) += ubi/ - obj-$(CONFIG_MTD_HYPERBUS) += hyperbus/ - -+obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ -+ - # Composite drivers must be loaded last - obj-y += composite/ diff --git a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch index aec8f327f..262df9d2c 100644 --- a/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch +++ b/target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch @@ -15,7 +15,7 @@ help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -93,6 +93,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o +@@ -95,6 +95,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff --git a/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch b/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch index a1f744f5d..cdcb8eefd 100644 --- a/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch +++ b/target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch @@ -138,7 +138,7 @@ Signed-off-by: Matthias Brugger --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -292,18 +292,16 @@ +@@ -302,18 +302,16 @@ }; }; @@ -194,7 +194,7 @@ Signed-off-by: Matthias Brugger &pio { --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -802,75 +802,83 @@ +@@ -808,75 +808,83 @@ #reset-cells = <1>; }; diff --git a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch index 25a5eb87c..0ecceeceb 100644 --- a/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ b/target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -842,6 +842,12 @@ +@@ -848,6 +848,12 @@ #address-cells = <0>; #interrupt-cells = <1>; }; @@ -13,7 +13,7 @@ }; pcie1: pcie@1a145000 { -@@ -880,6 +886,12 @@ +@@ -886,6 +892,12 @@ #address-cells = <0>; #interrupt-cells = <1>; }; diff --git a/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch b/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch index 8ce463835..252ef080f 100644 --- a/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch +++ b/target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch @@ -149,7 +149,7 @@ Signed-off-by: chuanjia.liu &pciephy1 { --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -377,16 +377,21 @@ +@@ -382,16 +382,21 @@ #reset-cells = <1>; }; @@ -177,7 +177,7 @@ Signed-off-by: chuanjia.liu clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, <&pciesys CLK_PCIE_P0_AHB_EN>, <&pciesys CLK_PCIE_P1_AUX_EN>, -@@ -407,21 +412,19 @@ +@@ -412,21 +417,19 @@ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>; diff --git a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch index 9689c1e79..4c4db9f04 100644 --- a/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ b/target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -830,6 +830,9 @@ +@@ -836,6 +836,9 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; status = "disabled"; @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; -@@ -874,6 +877,9 @@ +@@ -880,6 +883,9 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; status = "disabled"; diff --git a/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch b/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch new file mode 100644 index 000000000..52069496c --- /dev/null +++ b/target/linux/mediatek/patches-5.15/722-remove-300Hz-to-prevent-freeze.patch @@ -0,0 +1,25 @@ +--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi ++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi +@@ -23,11 +23,17 @@ + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; +- opp-300000000 { +- opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <950000>; +- }; +- ++ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low ++ * voltage condition that can cause a hang when rebooting the RT3200/E8450. ++ * ++ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 ++ * ++ * opp-300000000 { ++ * opp-hz = /bits/ 64 <300000000>; ++ * opp-microvolt = <950000>; ++ * }; ++ * ++ */ + opp-437500000 { + opp-hz = /bits/ 64 <437500000>; + opp-microvolt = <1000000>; diff --git a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch index 987513eb4..b15d04f8b 100644 --- a/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ b/target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -308,7 +308,7 @@ +@@ -318,7 +318,7 @@ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and * SATA functions. i.e. output-high: PCIe, output-low: SATA */ diff --git a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch index 72211af58..2a863aecf 100644 --- a/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ b/target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch @@ -1,6 +1,6 @@ --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -635,5 +635,28 @@ +@@ -645,5 +645,28 @@ }; &wmac {