diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index b92abee1f..d6c352b01 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2023.07 -PKG_RELEASE:=$(AUTORELEASE) +PKG_VERSION:=2024.10 +PKG_RELEASE:=1 -PKG_HASH:=12e921b466ae731cdbc355e6832b7f22bc90b01aeceef9886f98aaba7b394300 +PKG_HASH:=b28daf4ac17e43156363078bf510297584137f6df50fced9b12df34f61a92fb0 PKG_MAINTAINER:=Tobias Maedel @@ -201,37 +201,56 @@ define U-Boot/rk3568/Default TPL:=rk3568_ddr_1560MHz_v1.21.bin endef -define U-Boot/lyt-t68m-rk3568 +define U-Boot/bpi-r2-pro-rk3568 $(U-Boot/rk3568/Default) - NAME:=LYT T68M - BUILD_DEVICES:= lyt_t68m + NAME:=Bananapi-R2 Pro + BUILD_DEVICES:= \ + sinovoip_bpi-r2-pro endef -define U-Boot/mrkaio-m68s-rk3568 +define U-Boot/fastrhino-r66s-rk3568 $(U-Boot/rk3568/Default) - NAME:=Mrkaio M68S + NAME:=FastRhino R66S BUILD_DEVICES:= \ + fastrhino_r66s +endef + +define U-Boot/fastrhino-r68s-rk3568 + $(U-Boot/rk3568/Default) + NAME:=FastRhino R68S + BUILD_DEVICES:= \ + fastrhino_r68s +endef + +define U-Boot/generic-rk3568 + $(U-Boot/rk3568/Default) + NAME:=GENERIC RK3568 + BUILD_DEVICES:= \ + advantech_rsb4810 \ + armsom_sige3 \ ezpro_mrkaio-m68s \ - ezpro_mrkaio-m68s-plus + ezpro_mrkaio-m68s-plus \ + hinlink_opc-h66k \ + hinlink_opc-h68k \ + hinlink_opc-h69k \ + lyt_t68m \ + seewo_sv21 +endef + +define U-Boot/nanopi-r5c-rk3568 + $(U-Boot/rk3568/Default) + NAME:=NanoPi R5C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r5c endef define U-Boot/nanopi-r5s-rk3568 $(U-Boot/rk3568/Default) NAME:=NanoPi R5S BUILD_DEVICES:= \ - friendlyarm_nanopi-r5c \ friendlyarm_nanopi-r5s endef -define U-Boot/opc-h68k-rk3568 - $(U-Boot/rk3568/Default) - NAME:=OPC-H68K Board - BUILD_DEVICES:= \ - hinlink_opc-h66k \ - hinlink_opc-h68k \ - hinlink_opc-h69k -endef - define U-Boot/photonicat-rk3568 $(U-Boot/rk3568/Default) NAME:=Ariaboard Photonicat @@ -239,14 +258,6 @@ define U-Boot/photonicat-rk3568 ariaboard_photonicat endef -define U-Boot/r66s-rk3568 - $(U-Boot/rk3568/Default) - NAME:=R66S/R68S - BUILD_DEVICES:= \ - fastrhino_r66s \ - fastrhino_r68s -endef - define U-Boot/radxa-e25-rk3568 $(U-Boot/rk3568/Default) NAME:=Radxa E25 @@ -261,68 +272,88 @@ define U-Boot/rock-3a-rk3568 radxa_rock-3a endef -define U-Boot/rsb4810-rk3568 +define U-Boot/rock-3b-rk3568 $(U-Boot/rk3568/Default) - NAME:=Advantech RSB4810 + NAME:=ROCK 3B BUILD_DEVICES:= \ - advantech_rsb4810 -endef - -define U-Boot/seewo-sv21-rk3568 - $(U-Boot/rk3568/Default) - NAME:=seewo SV21 - BUILD_DEVICES:= \ - seewo_sv21 -endef - -define U-Boot/sige3-rk3568 - $(U-Boot/rk3568/Default) - NAME:=Sige3 - BUILD_DEVICES:= \ - armsom_sige3 + radxa_rock-3b endef define U-Boot/station-p2-rk3568 $(U-Boot/rk3568/Default) - NAME:=StationP2 + NAME:=Station P2 BUILD_DEVICES:= \ firefly_station-p2 endef # RK3588 boards -define U-Boot/Default/rk3588 +define U-Boot/rk3588/Default BUILD_SUBTARGET:=armv8 DEPENDS:=+PACKAGE_u-boot-$(1):rkbin-rk3588 ATF:=rk3588_bl31_v1.45.elf TPL:=rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin endef +define U-Boot/generic-rk3588 + $(U-Boot/rk3588/Default) + NAME:=Generic RK3588 + BUILD_DEVICES:= \ + hinlink_owl-h88k +endef + +define U-Boot/nanopc-t6-rk3588 + $(U-Boot/rk3588/Default) + NAME:=NanoPC T6 + BUILD_DEVICES:= \ + friendlyarm_nanopc-t6 +endef + define U-Boot/sige7-rk3588 - $(U-Boot/Default/rk3588) + $(U-Boot/rk3588/Default) NAME:=Sige7 BUILD_DEVICES:= \ armsom_sige7 endef +# RK3588S boards + +define U-Boot/nanopi-r6c-rk3588s + $(U-Boot/rk3588/Default) + NAME:=NanoPi R6C + BUILD_DEVICES:= \ + friendlyarm_nanopi-r6c +endef + +define U-Boot/nanopi-r6s-rk3588s + $(U-Boot/rk3588/Default) + NAME:=NanoPi R6S + BUILD_DEVICES:= \ + friendlyarm_nanopi-r6s +endef + UBOOT_TARGETS := \ panther-x2-rk3566 \ rock-3c-rk3566 \ - lyt-t68m-rk3568 \ - mrkaio-m68s-rk3568 \ + bpi-r2-pro-rk3568 \ + generic-rk3568 \ + fastrhino-r66s-rk3568 \ + fastrhino-r68s-rk3568 \ + nanopi-r5c-rk3568 \ nanopi-r5s-rk3568 \ - opc-h68k-rk3568 \ photonicat-rk3568 \ - r66s-rk3568 \ radxa-e25-rk3568 \ rock-3a-rk3568 \ - rsb4810-rk3568 \ - seewo-sv21-rk3568 \ - sige3-rk3568 \ + rock-3b-rk3568 \ station-p2-rk3568 \ + generic-rk3588 \ + nanopc-t6-rk3588 \ + sige7-rk3588 \ + nanopi-r6c-rk3588s \ + nanopi-r6s-rk3588s \ dlfr100-rk3399 \ - fine3399-rk3399 \ h3399pc-rk3399 \ + fine3399-rk3399 \ king3399-rk3399 \ mpc1903-rk3399 \ nanopc-t4-rk3399 \ @@ -336,8 +367,7 @@ UBOOT_TARGETS := \ nanopi-r2c-rk3328 \ nanopi-r2s-rk3328 \ orangepi-r1-plus-rk3328 \ - orangepi-r1-plus-lts-rk3328 \ - sige7-rk3588 + orangepi-r1-plus-lts-rk3328 UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes @@ -349,8 +379,8 @@ UBOOT_MAKE_FLAGS += \ define Build/Configure $(call Build/Configure/U-Boot) - $(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config + echo '# CONFIG_TOOLS_MKEFICAPSULE is not set' >> $(PKG_BUILD_DIR)/.config echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config endef diff --git a/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch b/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch deleted file mode 100644 index 86172d632..000000000 --- a/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch +++ /dev/null @@ -1,155 +0,0 @@ -From 872197ee382688701f85fc486a14dc02d2113811 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Tue, 31 May 2022 00:51:23 -0400 -Subject: [PATCH] uboot: add NanoPi R5S board - -Signed-off-by: Marty Jones ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 25 +++++ - arch/arm/dts/rk3568-nanopi-r5s.dts | 9 ++ - arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++ - board/friendlyelec/nanopi-r5s-rk3568/Kconfig | 15 +++ - board/friendlyelec/nanopi-r5s-rk3568/Makefile | 4 + - .../nanopi-r5s-rk3568/nanopi-r5s-rk3568.c | 4 + - configs/nanopi-r5s-rk3568_defconfig | 97 +++++++++++++++++++ - include/configs/nanopi-r5s-rk3568.h | 17 ++++ - 9 files changed, 178 insertions(+) - create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts - create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Kconfig - create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Makefile - create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c - create mode 100644 configs/nanopi-r5s-rk3568_defconfig - create mode 100644 include/configs/nanopi-r5s-rk3568.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -168,6 +168,7 @@ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3566-anbernic-rgxx3.dtb \ - rk3566-radxa-cm3-io.dtb \ -+ rk3568-nanopi-r5s.dtb \ - rk3568-evb.dtb \ - rk3568-rock-3a.dtb - ---- /dev/null -+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ bootph-pre-ram; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R5S"; -+ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; -+}; ---- /dev/null -+++ b/configs/nanopi-r5s-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch b/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch deleted file mode 100644 index df99a80b0..000000000 --- a/package/boot/uboot-rockchip/patches/020-update-rock-3a-defconfig.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/configs/rock-3a-rk3568_defconfig -+++ b/configs/rock-3a-rk3568_defconfig -@@ -25,7 +25,6 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 - CONFIG_DEBUG_UART=y - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y --CONFIG_SPL_FIT_SIGNATURE=y - CONFIG_SPL_LOAD_FIT=y - CONFIG_LEGACY_IMAGE_FORMAT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" diff --git a/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch b/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch deleted file mode 100644 index 224c14af9..000000000 --- a/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -113,7 +113,6 @@ dumpimage-mkimage-objs := aisimage.o \ - imximage.o \ - imx8image.o \ - imx8mimage.o \ -- kwbimage.o \ - lib/md5.o \ - lpc32xximage.o \ - mxsimage.o \ diff --git a/package/boot/uboot-rockchip/patches/110-force-pylibfdt-build.patch b/package/boot/uboot-rockchip/patches/110-force-pylibfdt-build.patch index d34ed6f2a..9aeb495c1 100644 --- a/package/boot/uboot-rockchip/patches/110-force-pylibfdt-build.patch +++ b/package/boot/uboot-rockchip/patches/110-force-pylibfdt-build.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -2000,26 +2000,7 @@ endif +@@ -2052,26 +2052,7 @@ endif # Check dtc and pylibfdt, if DTC is provided, else build them PHONY += scripts_dtc scripts_dtc: scripts_basic diff --git a/package/boot/uboot-rockchip/patches/111-fix-mkimage-host-build.patch b/package/boot/uboot-rockchip/patches/111-fix-mkimage-host-build.patch index cd65c1321..d04a61432 100644 --- a/package/boot/uboot-rockchip/patches/111-fix-mkimage-host-build.patch +++ b/package/boot/uboot-rockchip/patches/111-fix-mkimage-host-build.patch @@ -1,6 +1,6 @@ --- a/tools/image-host.c +++ b/tools/image-host.c -@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d +@@ -1162,6 +1162,7 @@ static int fit_config_add_verification_d * 2) get public key (X509_get_pubkey) * 3) provide der format (d2i_RSAPublicKey) */ @@ -8,7 +8,7 @@ static int read_pub_key(const char *keydir, const void *name, unsigned char **pubkey, int *pubkey_len) { -@@ -1178,6 +1179,13 @@ err_cert: +@@ -1215,6 +1216,13 @@ err_cert: fclose(f); return ret; } diff --git a/package/boot/uboot-rockchip/patches/200-radxa-e25-update-baudrate.patch b/package/boot/uboot-rockchip/patches/200-radxa-e25-update-baudrate.patch new file mode 100644 index 000000000..b93e7ab06 --- /dev/null +++ b/package/boot/uboot-rockchip/patches/200-radxa-e25-update-baudrate.patch @@ -0,0 +1,21 @@ +--- a/configs/radxa-e25-rk3568_defconfig ++++ b/configs/radxa-e25-rk3568_defconfig +@@ -62,6 +62,7 @@ CONFIG_REGULATOR_RK8XX=y + CONFIG_PWM_ROCKCHIP=y + CONFIG_SPL_RAM=y + CONFIG_SCSI=y ++CONFIG_BAUDRATE=1500000 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_SYS_NS16550_MEM32=y + CONFIG_SYSRESET=y +--- a/dts/upstream/src/arm64/rockchip/rk3568-radxa-cm3i.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3568-radxa-cm3i.dtsi +@@ -13,7 +13,7 @@ + }; + + chosen { +- stdout-path = "serial2:115200n8"; ++ stdout-path = "serial2:1500000n8"; + }; + + gpio-leds { diff --git a/package/boot/uboot-rockchip/patches/201-rk3568-generic-remove-spi-support.patch b/package/boot/uboot-rockchip/patches/201-rk3568-generic-remove-spi-support.patch new file mode 100644 index 000000000..e6378214b --- /dev/null +++ b/package/boot/uboot-rockchip/patches/201-rk3568-generic-remove-spi-support.patch @@ -0,0 +1,80 @@ +--- a/arch/arm/dts/rk3568-generic-u-boot.dtsi ++++ b/arch/arm/dts/rk3568-generic-u-boot.dtsi +@@ -1,10 +1,3 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + + #include "rk356x-u-boot.dtsi" +- +-&sfc { +- flash@0 { +- bootph-pre-ram; +- bootph-some-ram; +- }; +-}; +--- a/arch/arm/dts/rk3568-generic.dts ++++ b/arch/arm/dts/rk3568-generic.dts +@@ -43,18 +43,6 @@ + status = "okay"; + }; + +-&sfc { +- #address-cells = <1>; +- #size-cells = <0>; +- status = "okay"; +- +- flash@0 { +- compatible = "jedec,spi-nor"; +- reg = <0>; +- spi-max-frequency = <24000000>; +- }; +-}; +- + &uart2 { + status = "okay"; + }; +--- a/configs/generic-rk3568_defconfig ++++ b/configs/generic-rk3568_defconfig +@@ -5,12 +5,9 @@ CONFIG_ARCH_ROCKCHIP=y + CONFIG_SF_DEFAULT_SPEED=24000000 + CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" + CONFIG_ROCKCHIP_RK3568=y +-CONFIG_ROCKCHIP_SPI_IMAGE=y + CONFIG_SPL_SERIAL=y + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 +-CONFIG_SPL_SPI_FLASH_SUPPORT=y +-CONFIG_SPL_SPI=y + CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART=y + CONFIG_FIT=y +@@ -25,8 +22,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_MAX_SIZE=0x40000 + CONFIG_SPL_PAD_TO=0x7f8000 + # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +-CONFIG_SPL_SPI_LOAD=y +-CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 + CONFIG_SPL_ATF=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y +@@ -56,21 +51,12 @@ CONFIG_MMC_DW_ROCKCHIP=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_SDMA=y + CONFIG_MMC_SDHCI_ROCKCHIP=y +-CONFIG_SF_DEFAULT_BUS=4 +-CONFIG_SPI_FLASH_SFDP_SUPPORT=y +-CONFIG_SPI_FLASH_GIGADEVICE=y +-CONFIG_SPI_FLASH_MACRONIX=y +-CONFIG_SPI_FLASH_SILICONKAISER=y +-CONFIG_SPI_FLASH_WINBOND=y +-CONFIG_SPI_FLASH_XMC=y +-CONFIG_SPI_FLASH_XTX=y + CONFIG_PHY_ROCKCHIP_INNO_USB2=y + CONFIG_SPL_PINCTRL=y + CONFIG_SPL_RAM=y + CONFIG_BAUDRATE=1500000 + CONFIG_DEBUG_UART_SHIFT=2 + CONFIG_SYS_NS16550_MEM32=y +-CONFIG_ROCKCHIP_SFC=y + CONFIG_SYSRESET=y + CONFIG_SYSRESET_PSCI=y + CONFIG_USB=y diff --git a/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch b/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch deleted file mode 100644 index 37e50d175..000000000 --- a/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sun, 17 Jan 2021 15:26:09 -0500 -Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT - -On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3 -CONFIG_USE_PREBOOT was enabled on the RockPro64. - -When the board is booting, U-Boot hangs as soon as it disables the USB -controller. This is a workaround until a final solution is deployed -upstream. - -Signed-off-by: Marty Jones ---- - configs/rockpro64-rk3399_defconfig | 1 - - 1 file changed, 1 deletion(-) - ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -21,7 +21,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_DEBUG_UART=y - CONFIG_BOOTSTAGE=y - CONFIG_BOOTSTAGE_REPORT=y --CONFIG_USE_PREBOOT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" - CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_MISC_INIT_R=y diff --git a/package/boot/uboot-rockchip/patches/300-rockchip-rk3399-Add-support-for-sv901-eaio.patch b/package/boot/uboot-rockchip/patches/300-rockchip-rk3399-Add-support-for-sv901-eaio.patch index c605f948b..51ce2d398 100644 --- a/package/boot/uboot-rockchip/patches/300-rockchip-rk3399-Add-support-for-sv901-eaio.patch +++ b/package/boot/uboot-rockchip/patches/300-rockchip-rk3399-Add-support-for-sv901-eaio.patch @@ -17,7 +17,7 @@ +}; --- /dev/null +++ b/arch/arm/dts/rk3399-sv901-eaio.dts -@@ -0,0 +1,638 @@ +@@ -0,0 +1,640 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; @@ -519,6 +519,8 @@ +}; + +&sdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; @@ -658,22 +660,18 @@ +}; --- /dev/null +++ b/configs/sv901-eaio-rk3399_defconfig -@@ -0,0 +1,81 @@ +@@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -+CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-sv901-eaio" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 @@ -681,16 +679,10 @@ +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-sv901-eaio.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -700,34 +692,37 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y @@ -738,5 +733,8 @@ +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_SPL_TINY_MEMSET=y ++CONFIG_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch b/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch index a6a6c6a1a..5e034aec8 100644 --- a/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch +++ b/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch @@ -1,85 +1,4 @@ --- /dev/null -+++ b/configs/guangmiao-g4c-rk3399_defconfig -@@ -0,0 +1,78 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-guangmiao-g4c" -+CONFIG_DM_RESET=y -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x2e000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_ROCKCHIP_EFUSE=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_ROCKCHIP_LPDDR4=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y ---- /dev/null +++ b/arch/arm/dts/rk3399-guangmiao-g4c-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ @@ -749,3 +668,76 @@ +&vopl_mmu { + status = "okay"; +}; +--- /dev/null ++++ b/configs/guangmiao-g4c-rk3399_defconfig +@@ -0,0 +1,70 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SPL_GPIO=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_OFFSET=0x3F8000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-guangmiao-g4c" ++CONFIG_DM_RESET=y ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_EVB_RK3399=y ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0x800800 ++CONFIG_DEBUG_UART=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb" ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y ++CONFIG_TPL=y ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_ROCKCHIP_IODOMAIN=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM_ROCKCHIP_LPDDR4=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_KEYBOARD=y ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch b/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch deleted file mode 100644 index 60c2ec7a8..000000000 --- a/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch +++ /dev/null @@ -1,157 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ - rk3328-nanopi-r2s.dtb \ -+ rk3328-orangepi-r1-plus.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi -@@ -0,0 +1,1 @@ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus"; -+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+}; -+ -+&sys_led { -+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -+}; -+ -+&sys_led_pin { -+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+}; ---- /dev/null -+++ b/configs/orangepi-r1-plus-rk3328_defconfig -@@ -0,0 +1,112 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" -+CONFIG_DM_RESET=y -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x2000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C=y -+CONFIG_SPL_POWER=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSINFO=y -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/302-rockchip-rk3399-Add-support-for-rumu3f-fine3399.patch b/package/boot/uboot-rockchip/patches/302-rockchip-rk3399-Add-support-for-rumu3f-fine3399.patch index ac54b68cb..65da8842a 100644 --- a/package/boot/uboot-rockchip/patches/302-rockchip-rk3399-Add-support-for-rumu3f-fine3399.patch +++ b/package/boot/uboot-rockchip/patches/302-rockchip-rk3399-Add-support-for-rumu3f-fine3399.patch @@ -603,6 +603,8 @@ +}; + +&sdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; @@ -615,8 +617,6 @@ + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; -+ #address-cells = <1>; -+ #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { @@ -792,45 +792,31 @@ +}; --- /dev/null +++ b/configs/fine3399-rk3399_defconfig -@@ -0,0 +1,97 @@ +@@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-fine-3399" -+CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0x800800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set ++CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-fine-3399.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y -+CONFIG_SYS_PROMPT="Fine3399 => " +CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_GPT=y -+CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y @@ -838,40 +824,41 @@ +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_DFU_MMC=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME_PCI=y -+CONFIG_PCI=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_KEYBOARD=y @@ -880,13 +867,13 @@ +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y -+CONFIG_DM_VIDEO=y ++CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch b/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch deleted file mode 100644 index 5cbbffa07..000000000 --- a/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch +++ /dev/null @@ -1,152 +0,0 @@ -From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001 -From: baiywt -Date: Wed, 24 Nov 2021 19:59:38 +0800 -Subject: [PATCH] Add support for Orangepi R1 Plus LTS - ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 7 ++ - configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++ - 3 files changed, 106 insertions(+) - create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts - create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-orangepi-r1-plus.dtb \ -+ rk3328-orangepi-r1-plus-lts.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi -@@ -0,0 +1,1 @@ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3328-orangepi-r1-plus.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus LTS"; -+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -+}; ---- /dev/null -+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig -@@ -0,0 +1,112 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" -+CONFIG_DM_RESET=y -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x2000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C=y -+CONFIG_SPL_POWER=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_SYS_MMC_ENV_DEV=1 -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSINFO=y -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch index 3003ab92b..790a94dc2 100644 --- a/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -1,5 +1,5 @@ --- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4se.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi-r4se.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + @@ -31,30 +31,23 @@ +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-nanopi-r4se" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -63,31 +56,39 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM_ROCKCHIP_LPDDR4=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y @@ -98,5 +99,4 @@ +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch b/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch index 7fc41f41b..8fdee9f2e 100755 --- a/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch +++ b/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch @@ -1,34 +1,26 @@ --- /dev/null +++ b/configs/king3399-rk3399_defconfig -@@ -0,0 +1,73 @@ +@@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-evb" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -37,17 +29,21 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y @@ -59,9 +55,10 @@ +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y @@ -71,6 +68,6 @@ +CONFIG_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y ++CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 ++CONFIG_DISPLAY_ROCKCHIP_MIPI=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch b/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch index 8561276b3..46803180f 100644 --- a/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch +++ b/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch @@ -708,35 +708,28 @@ +}; --- /dev/null +++ b/configs/mpc1903-rk3399_defconfig -@@ -0,0 +1,72 @@ +@@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-mpc1903" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-mpc1903.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -745,30 +738,39 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y @@ -779,5 +781,4 @@ +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/308-rockchip-rk3399-Add-support-for-sharevdi-h3399pc.patch b/package/boot/uboot-rockchip/patches/308-rockchip-rk3399-Add-support-for-sharevdi-h3399pc.patch index 952aee094..5a9675c0b 100644 --- a/package/boot/uboot-rockchip/patches/308-rockchip-rk3399-Add-support-for-sharevdi-h3399pc.patch +++ b/package/boot/uboot-rockchip/patches/308-rockchip-rk3399-Add-support-for-sharevdi-h3399pc.patch @@ -848,35 +848,28 @@ +}; --- /dev/null +++ b/configs/h3399pc-rk3399_defconfig -@@ -0,0 +1,72 @@ +@@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-h3399pc" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-h3399pc.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -885,30 +878,39 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y @@ -919,5 +921,4 @@ +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch b/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch index 70731bee0..c2c2eaaa7 100644 --- a/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch +++ b/package/boot/uboot-rockchip/patches/309-rockchip-rk3399-Add-support-for-dilusense-dlfr100.patch @@ -697,35 +697,28 @@ +}; --- /dev/null +++ b/configs/dlfr100-rk3399_defconfig -@@ -0,0 +1,72 @@ +@@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-dlfr100" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-dlfr100.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -734,30 +727,39 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y @@ -768,5 +770,4 @@ +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/310-rockchip-rk3399-Add-support-for-xiaobao-nas-v1.patch b/package/boot/uboot-rockchip/patches/310-rockchip-rk3399-Add-support-for-xiaobao-nas-v1.patch index 54f8e32a5..5fd06e7af 100644 --- a/package/boot/uboot-rockchip/patches/310-rockchip-rk3399-Add-support-for-xiaobao-nas-v1.patch +++ b/package/boot/uboot-rockchip/patches/310-rockchip-rk3399-Add-support-for-xiaobao-nas-v1.patch @@ -793,35 +793,28 @@ +}; --- /dev/null +++ b/configs/xiaobao-nas-v1-rk3399_defconfig -@@ -0,0 +1,72 @@ +@@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00200000 ++CONFIG_SPL_GPIO=y +CONFIG_NR_DRAM_BANKS=1 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-xiaobao-nas-v1" ++CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-xiaobao-nas-v1.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x2e000 ++CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x400000 -+CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y @@ -830,30 +823,39 @@ +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++# CONFIG_OF_UPSTREAM is not set ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PMIC_RK8XX=y ++CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSINFO=y ++CONFIG_SYSINFO_SMBIOS=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y @@ -864,5 +866,4 @@ +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch b/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch deleted file mode 100644 index f3ac8489d..000000000 --- a/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch +++ /dev/null @@ -1,126 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3566-anbernic-rgxx3.dtb \ - rk3566-radxa-cm3-io.dtb \ -+ rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ - rk3568-evb.dtb \ - rk3568-rock-3a.dtb ---- /dev/null -+++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ bootph-pre-ram; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "EZPRO Mrkaio M68S"; -+ compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568"; -+}; ---- /dev/null -+++ b/configs/mrkaio-m68s-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-fastrhino-r6xs.patch b/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-fastrhino-r6xs.patch new file mode 100644 index 000000000..187bcfd2c --- /dev/null +++ b/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-fastrhino-r6xs.patch @@ -0,0 +1,377 @@ +--- /dev/null ++++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "rk356x-u-boot.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc0; ++ }; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ maximum-speed = "high-speed"; ++ phys = <&usb2phy0_otg>; ++ phy-names = "usb2-phy"; ++}; +--- /dev/null ++++ b/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "rk356x-u-boot.dtsi" ++ ++/ { ++ chosen { ++ u-boot,spl-boot-order = "same-as-spl", &sdhci; ++ }; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ maximum-speed = "high-speed"; ++ phys = <&usb2phy0_otg>; ++ phy-names = "usb2-phy"; ++}; +--- /dev/null ++++ b/configs/fastrhino-r66s-rk3568_defconfig +@@ -0,0 +1,75 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_SERIAL=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ERRNO_STR=y +--- /dev/null ++++ b/configs/fastrhino-r68s-rk3568_defconfig +@@ -0,0 +1,78 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r68s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_SERIAL=y ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r68s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_ROCKUSB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++# CONFIG_USB_FUNCTION_FASTBOOT is not set ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_USB_FUNCTION_ROCKUSB=y ++CONFIG_ERRNO_STR=y +--- a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dtsi +@@ -39,9 +39,9 @@ + }; + }; + +- dc_12v: dc-12v-regulator { ++ vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; +- regulator-name = "dc_12v"; ++ regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; +@@ -65,7 +65,7 @@ + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +- vin-supply = <&dc_12v>; ++ vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { +@@ -75,16 +75,7 @@ + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +- vin-supply = <&dc_12v>; +- }; +- +- vcc5v0_usb_host: vcc5v0-usb-host-regulator { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0_usb_host"; +- regulator-always-on; +- regulator-boot-on; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { +@@ -94,8 +85,9 @@ + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; +- regulator-always-on; +- regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; + }; + }; + +@@ -123,6 +115,10 @@ + cpu-supply = <&vdd_cpu>; + }; + ++&display_subsystem { ++ status = "disabled"; ++}; ++ + &gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +@@ -405,8 +401,8 @@ + &pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; +- vccio1-supply = <&vccio_acodec>; +- vccio3-supply = <&vccio_sd>; ++ vccio1-supply = <&vcc_3v3>; ++ vccio2-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; +@@ -429,28 +425,12 @@ + status = "okay"; + }; + +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- + &usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; + }; + +-&usb_host1_ehci { +- status = "okay"; +-}; +- +-&usb_host1_ohci { +- status = "okay"; +-}; +- + &usb_host1_xhci { + status = "okay"; + }; +@@ -460,7 +440,7 @@ + }; + + &usb2phy0_host { +- phy-supply = <&vcc5v0_usb_host>; ++ phy-supply = <&vcc5v0_sys>; + status = "okay"; + }; + +--- a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r66s.dts +@@ -11,6 +11,10 @@ + }; + }; + ++&pmu_io_domains { ++ vccio3-supply = <&vccio_sd>; ++}; ++ + &sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; +--- a/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r68s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3568-fastrhino-r68s.dts +@@ -39,7 +39,7 @@ + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; +- snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; ++ snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; +@@ -61,7 +61,7 @@ + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; +- snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; ++ snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; +@@ -71,18 +71,18 @@ + }; + + &mdio0 { +- rgmii_phy0: ethernet-phy@0 { ++ rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; ++ reg = <0x1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; + }; + + &mdio1 { +- rgmii_phy1: ethernet-phy@0 { ++ rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +- reg = <0>; ++ reg = <0x1>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; + }; +@@ -102,6 +102,10 @@ + }; + }; + ++&pmu_io_domains { ++ vccio3-supply = <&vcc_3v3>; ++}; ++ + &sdhci { + bus-width = <8>; + max-frequency = <200000000>; diff --git a/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch b/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch deleted file mode 100644 index 0d9c207e6..000000000 --- a/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch +++ /dev/null @@ -1,142 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3566-radxa-cm3-io.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ -+ rk3568-opc-h68k.dtb \ - rk3568-evb.dtb \ - rk3568-rock-3a.dtb - ---- /dev/null -+++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ bootph-pre-ram; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-opc-h68k.dts -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "HINLINK OPC-H68K Board"; -+ compatible = "hinlink,opc-h68k", "rockchip,rk3568"; -+}; -+ -+&usb2phy0_host { -+ phy-supply = <&vcc5v0_usb_otg>; -+}; -+ -+&usb2phy1_host { -+ phy-supply = <&vcc5v0_usb_otg>; -+}; -+ -+&usb2phy1_otg { -+ phy-supply = <&vcc5v0_usb_otg>; -+}; -+ -+&vcc5v0_usb_host { -+ status = "disabled"; -+}; ---- /dev/null -+++ b/configs/opc-h68k-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch b/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch deleted file mode 100644 index 7c2cee6ea..000000000 --- a/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch +++ /dev/null @@ -1,125 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-nanopi-r5s.dtb \ - rk3568-opc-h68k.dtb \ - rk3568-evb.dtb \ -+ rk3568-r66s.dtb \ - rk3568-rock-3a.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3588) += \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-r66s-u-boot.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ bootph-all; -+ clock-frequency = <24000000>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-r66s.dts -@@ -0,0 +1,2 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3568-evb.dts" ---- /dev/null -+++ b/configs/r66s-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-r66s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-r66s.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-station-p2.patch b/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-station-p2.patch index 65196c4ad..b18384a09 100644 --- a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-station-p2.patch +++ b/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-station-p2.patch @@ -10,42 +10,29 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 --- /dev/null +++ b/configs/station-p2-rk3568_defconfig -@@ -0,0 +1,83 @@ +@@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-roc-pc" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-roc-pc.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y @@ -59,6 +46,7 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y @@ -71,8 +59,9 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y @@ -87,10 +76,10 @@ Subject: [PATCH] rockchip: rk3568: Add support for Station P2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch b/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-photonicat.patch similarity index 68% rename from package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch rename to package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-photonicat.patch index f8d3f50ff..33d1324e7 100644 --- a/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-photonicat.patch +++ b/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-photonicat.patch @@ -1,47 +1,20 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3566-radxa-cm3-io.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ -+ rk3568-photonicat.dtb \ - rk3568-opc-h68k.dtb \ - rk3568-evb.dtb \ - rk3568-r66s.dtb \ --- /dev/null +++ b/arch/arm/dts/rk3568-photonicat-u-boot.dtsi -@@ -0,0 +1,28 @@ +@@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ +&gpio0 { -+ bootph-all; -+}; -+ -+&pinctrl { -+ bootph-all; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; + bootph-pre-ram; -+ status = "okay"; +}; + +&vcc3v3_sd { -+ bootph-all; ++ bootph-pre-ram; +}; --- /dev/null +++ b/arch/arm/dts/rk3568-photonicat.dts -@@ -0,0 +1,54 @@ +@@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; @@ -53,7 +26,7 @@ + model = "Ariaboard Photonicat"; + compatible = "ariaboard,photonicat", "rockchip,rk3568"; + -+ chosen: chosen { ++ chosen { + stdout-path = "serial2:1500000n8"; + }; + @@ -61,7 +34,7 @@ + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_sd_h>; ++ pinctrl-0 = <&sdmmc0_pwren>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; @@ -70,26 +43,30 @@ +}; + +&pinctrl { -+ vcc_sd { -+ vcc_sd_h: vcc-sd-h { -+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; ++ sdmmc0 { ++ sdmmc0_pwren: sdmmc0-pwren { ++ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; -+ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; + non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { -+ max-frequency = <52000000>; -+ status = "okay"; -+}; -+ -+&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ disable-wp; ++ no-1-8-v; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + status = "okay"; +}; + @@ -98,29 +75,21 @@ +}; --- /dev/null +++ b/configs/photonicat-rk3568_defconfig -@@ -0,0 +1,83 @@ +@@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-photonicat" +CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-photonicat.dtb" @@ -128,12 +97,7 @@ +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y @@ -146,7 +110,9 @@ +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y ++# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y @@ -159,8 +125,9 @@ +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PHY_MOTORCOMM=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y @@ -175,10 +142,11 @@ +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch b/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch deleted file mode 100644 index 2ad62954f..000000000 --- a/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch +++ /dev/null @@ -1,128 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -177,7 +177,8 @@ rk3568-evb.dtb \ - rk3568-opc-h68k.dtb \ - rk3568-evb.dtb \ - rk3568-r66s.dtb \ -- rk3568-rock-3a.dtb -+ rk3568-rock-3a.dtb \ -+ rk3568-radxa-e25.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3588) += \ - rk3588-edgeble-neu6a-io.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ bootph-pre-ram; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-radxa-e25.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "Radxa E25"; -+ compatible = "radxa,e25", "rockchip,rk3568"; -+}; ---- /dev/null -+++ b/configs/radxa-e25-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch b/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch deleted file mode 100644 index 09eccc3d8..000000000 --- a/package/boot/uboot-rockchip/patches/316-rockchip-rk3568-Add-support-for-lyt_t68m.patch +++ /dev/null @@ -1,126 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -175,6 +175,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-nanopi-r5s.dtb \ - rk3568-photonicat.dtb \ - rk3568-opc-h68k.dtb \ -+ rk3568-lyt-t68m.dtb \ - rk3568-evb.dtb \ - rk3568-r66s.dtb \ - rk3568-rock-3a.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-lyt-t68m-u-boot.dtsi -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ bootph-pre-ram; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-lyt-t68m.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "LYT T68M"; -+ compatible = "lyt,t68m", "rockchip,rk3568"; -+}; ---- /dev/null -+++ b/configs/lyt-t68m-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-lyt-t68m" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lyt-t68m.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/317-rockchip-rk3566-Add-support-for-seewo-sv21-3568.patch b/package/boot/uboot-rockchip/patches/317-rockchip-rk3566-Add-support-for-seewo-sv21-3568.patch deleted file mode 100644 index 3a54cb9c3..000000000 --- a/package/boot/uboot-rockchip/patches/317-rockchip-rk3566-Add-support-for-seewo-sv21-3568.patch +++ /dev/null @@ -1,90 +0,0 @@ ---- /dev/null -+++ b/configs/seewo-sv21-rk3568_defconfig -@@ -0,0 +1,87 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_CMD_SETEXPR is not set -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_RESET_SCMI=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch b/package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch deleted file mode 100644 index 2d7d36ad4..000000000 --- a/package/boot/uboot-rockchip/patches/318-rockchip-rk3568-Add-support-for-advantech-rsb4810.patch +++ /dev/null @@ -1,146 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -184,7 +184,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-evb.dtb \ - rk3568-r66s.dtb \ - rk3568-rock-3a.dtb \ -- rk3568-radxa-e25.dtb -+ rk3568-radxa-e25.dtb \ -+ rk3568-rsb4810.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3588) += \ - rk3588-edgeble-neu6a-io.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-rsb4810.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include "rk3568.dtsi" -+ -+/ { -+ model = "Advantech RK3568 RSB4810 Board"; -+ compatible = "advantech-rsb4810", "rockchip,rk3568"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-rsb4810-u-boot.dtsi -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ status = "okay"; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ u-boot,dm-spl; -+ status = "okay"; -+}; ---- /dev/null -+++ b/configs/rsb4810-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rsb4810" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rsb4810.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/320-rockchip-rk3566-Add-support-for-rock3c.patch b/package/boot/uboot-rockchip/patches/320-rockchip-rk3566-Add-support-for-rock3c.patch deleted file mode 100644 index 3f96746bf..000000000 --- a/package/boot/uboot-rockchip/patches/320-rockchip-rk3566-Add-support-for-rock3c.patch +++ /dev/null @@ -1,126 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -185,6 +185,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-evb.dtb \ - rk3568-r66s.dtb \ - rk3568-rock-3a.dtb \ -+ rk3566-rock-3c.dtb \ - rk3568-radxa-e25.dtb \ - rk3568-rsb4810.dtb - ---- /dev/null -+++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi -@@ -0,0 +1,16 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ bootph-pre-ram; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3566-rock-3c.dts -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "Radxa ROCK 3C"; -+ compatible = "radxa,rock-3c", "rockchip,rk3566"; -+}; ---- /dev/null -+++ b/configs/rock-3c-rk3566_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3566-rock-3c" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y diff --git a/package/boot/uboot-rockchip/patches/321-rockchip-rk3568-Add-support-for-armsom-sige.patch b/package/boot/uboot-rockchip/patches/321-rockchip-rk3568-Add-support-for-armsom-sige.patch deleted file mode 100644 index 6cc271527..000000000 --- a/package/boot/uboot-rockchip/patches/321-rockchip-rk3568-Add-support-for-armsom-sige.patch +++ /dev/null @@ -1,157 +0,0 @@ ---- /dev/null -+++ b/configs/sige3-rk3568_defconfig -@@ -0,0 +1,83 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/configs/sige7-rk3588_defconfig -@@ -0,0 +1,68 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SPL_STACK=0x400000 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_BOARD_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -+CONFIG_SPL_BSS_START_ADDR=0x4000000 -+CONFIG_SPL_BSS_MAX_SIZE=0x4000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_ERRNO_STR=y