From 251f5643c93ab6312713831a09e9a091426e05ba Mon Sep 17 00:00:00 2001
From: imbrolla <33008627+imbrolla@users.noreply.github.com>
Date: Sun, 30 Sep 2018 04:41:06 +0800
Subject: [PATCH] Update 601-MIPS-ath79-add-more-register-defines.patch

---
 .../601-MIPS-ath79-add-more-register-defines.patch            | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/linux/ar71xx/patches-4.14/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.14/601-MIPS-ath79-add-more-register-defines.patch
index d0f5b7890..77a646378 100644
--- a/target/linux/ar71xx/patches-4.14/601-MIPS-ath79-add-more-register-defines.patch
+++ b/target/linux/ar71xx/patches-4.14/601-MIPS-ath79-add-more-register-defines.patch
@@ -217,7 +217,7 @@
  #define AR71XX_GPIO_COUNT		16
  #define AR7240_GPIO_COUNT		18
  #define AR7241_GPIO_COUNT		20
-@@ -570,4 +681,235 @@
+@@ -570,4 +681,237 @@
  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
  #define AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
  
@@ -433,6 +433,8 @@
 +#define QCA955X_GMAC_REG_ETH_CFG	0x00
 +
 +#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
++#define QCA955X_ETH_CFG_GE0_MII_EN	BIT(1)
++#define QCA955X_ETH_CFG_GE0_MII_SLAVE	BIT(4)
 +#define QCA955X_ETH_CFG_MII_GE0		BIT(1)
 +#define QCA955X_ETH_CFG_GMII_GE0	BIT(2)
 +#define QCA955X_ETH_CFG_MII_GE0_MASTER	BIT(3)