diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
index 77d511659..12ce6a781 100755
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@@ -27,19 +27,21 @@ rockchip_setup_interfaces()
 	fastrhino,r66s|\
 	firefly,rk3568-roc-pc|\
 	friendlyarm,nanopi-r5c|\
-	radxa,e25|\
-	seewo,sv21-rk3568)
+	seewo,sv21-rk3568|\
+	radxa,e25)
 		ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
 		;;
 	hinlink,opc-h68k|\
-	fastrhino,r68s|\
-	lyt,t68m)
+	fastrhino,r68s)
 		ucidef_set_interfaces_lan_wan 'eth0 eth2 eth3' 'eth1'
 		;;
 	hinlink,opc-h69k|\
 	friendlyarm,nanopi-r5s)
 		ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
 		;;
+	lyt,t68m)
+		ucidef_set_interfaces_lan_wan 'lan2 lan3 lan4' 'lan1'
+		;;
 	*)
 		ucidef_set_interface_lan 'eth0'
 		;;
diff --git a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-t68m.dts b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-t68m.dts
index 50e14f0a3..0db96e73a 100644
--- a/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-t68m.dts
+++ b/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-t68m.dts
@@ -214,6 +214,7 @@
 	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
 	assigned-clock-rates = <0>, <125000000>;
 	clock_in_out = "output";
+	label = "lan1";
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&gmac0_miim
@@ -236,6 +237,7 @@
 	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
 	assigned-clock-rates = <0>, <125000000>;
 	clock_in_out = "output";
+	label = "lan2";
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&gmac1m1_miim
@@ -553,6 +555,18 @@
 	reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x00100000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@10,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x000000 0 0 0 0>;
+			label = "lan4";
+		};
+	};
 };
 
 &pcie3x2 {
@@ -560,6 +574,18 @@
 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
+	
+	pcie@0,0 {
+		reg = <0x00200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		pcie-eth@20,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x000000 0 0 0 0>;
+			label = "lan3";
+		};
+	};
 };
 
 &pinctrl {