From 1fd443d852977d01c3fb0f57a3d182ec81d9391b Mon Sep 17 00:00:00 2001 From: oct-month <59117904+oct-month@users.noreply.github.com> Date: Sat, 26 Aug 2023 12:14:41 +0800 Subject: [PATCH] ip60xx: fix build issue (#11486) --- ...k-qcom-ipq6018-fix-networking-resets.patch | 60 ------------------- 1 file changed, 60 deletions(-) delete mode 100644 target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch diff --git a/target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch b/target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch deleted file mode 100644 index 53e227d1e..000000000 --- a/target/linux/ipq60xx/patches-5.15/0168-clk-qcom-ipq6018-fix-networking-resets.patch +++ /dev/null @@ -1,60 +0,0 @@ -From a9305e6356be71bdfee35913bdf78b52cdbeaf73 Mon Sep 17 00:00:00 2001 -From: Robert Marko -Date: Mon, 10 Oct 2022 23:24:15 +0200 -Subject: [PATCH] clk: qcom: ipq6018: fix networking resets - -Networking resets in IPQ6018 all use bitmask as they require multiple -bits to be set and cleared instead of a single bit. - -So, current networking resets have the same register and bit 0 set which -is clearly incorrect. - -Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") -Signed-off-by: Robert Marko ---- - drivers/clk/qcom/gcc-ipq6018.c | 32 ++++++++++++++++---------------- - 1 file changed, 16 insertions(+), 16 deletions(-) - ---- a/drivers/clk/qcom/gcc-ipq6018.c -+++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -4517,24 +4517,24 @@ static const struct qcom_reset_map gcc_i - [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, - [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, - [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, -- [GCC_PPE_FULL_RESET] = { 0x68014, 0 }, -- [GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 }, -+ [GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 }, -+ [GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 }, - [GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 }, -- [GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 }, -+ [GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 }, - [GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 }, -- [GCC_EDMA_HW_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT1_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT2_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT3_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT4_RESET] = { 0x68014, 0 }, -- [GCC_NSSPORT5_RESET] = { 0x68014, 0 }, -- [GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 }, -- [GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 }, -+ [GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 }, -+ [GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 }, -+ [GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c }, -+ [GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 }, -+ [GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 }, -+ [GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 }, -+ [GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 }, -+ [GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 }, -+ [GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 }, -+ [GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 }, -+ [GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 }, -+ [GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 }, -+ [GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 }, - [GCC_LPASS_BCR] = {0x1F000, 0}, - [GCC_UBI32_TBU_BCR] = {0x65000, 0}, - [GCC_LPASS_TBU_BCR] = {0x6C000, 0},